TWI279175B - Circuit board structure and method for fabricating the same - Google Patents

Circuit board structure and method for fabricating the same Download PDF

Info

Publication number
TWI279175B
TWI279175B TW094124650A TW94124650A TWI279175B TW I279175 B TWI279175 B TW I279175B TW 094124650 A TW094124650 A TW 094124650A TW 94124650 A TW94124650 A TW 94124650A TW I279175 B TWI279175 B TW I279175B
Authority
TW
Taiwan
Prior art keywords
layer
circuit
circuit board
conductive
block
Prior art date
Application number
TW094124650A
Other languages
Chinese (zh)
Other versions
TW200706085A (en
Inventor
Shing-Ru Wang
Hsien-Shou Wang
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW094124650A priority Critical patent/TWI279175B/en
Priority to US11/458,605 priority patent/US20070017815A1/en
Publication of TW200706085A publication Critical patent/TW200706085A/en
Application granted granted Critical
Publication of TWI279175B publication Critical patent/TWI279175B/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A circuit board structure and a method for fabricating the same are proposed. A plurality of conductive bumps and a first solder mask are formed on a carrier board, and the first solder mask is filled in the gaps between the conductive bumps and the conductive bumps are exposed. A first circuit layer and a first heat sink are formed on the first solder mask and the conductive bumps. A second heat sink is formed on the first heat sink, and a dielectric layer is formed on the first circuit layer and the first solder mask except the first and second heat sinks. A second circuit layer is formed on the dielectric layer and is electrically conducted to the first circuit layer. A third heat sink is formed on the second heat sink and a heat sink used for a chip mounting thereon is embedded in the dielectric layer. Therefore, the size of the circuit board is reduced and it is conformed to the size shrunk progress of electronic devices.

Description

1279175 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電路板結構及其製作方法，更詳 而口之係、有關於一種整合有散熱塊之電路板結構及其製 作方法。 •【先前技術】 - 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (Integration)以及微型化（Miniaturizati〇n)的封裝 而求k i、夕數主、被動元件及線路載接之電路板（C i『⑶h _ Board)亦逐漸由單層板演變成多層板（MuUi_layer Board) 〇 生惟因電路板的線路層數以及元件密度才是高，配合高度 積集化（Integration)半導體晶片運作產生的熱量亦會大 中田柘加，些熱1若不及時排除，將導致半導體封裝件 籲熱而嚴重威脅晶片壽命。 目丽於電路板底部貼附散熱片的方法為業界使用最 •多。例如習知之底穴置晶型球栅陣型式封裝結構 (Cavity—down ball grid array，CDBGA)，係為一種特殊 形態的球柵陣列式封裝結構10,如第1圖所示。主要係在 一電路板11形成有—開σ 113,並貼附有-散熱片12，以 將半導體晶片13接置於該散熱片12上且收納於該開口 13 ”中"玄政一件12的材質為一例如為銅之高導熱性材 料，且其係貼附於該電路板u的第一表面Ua;而該半導 5 18485 '1279175 脰日日片1 3具有主動面13a(Act i ve surf ace)和一非主動 面13b(Inactive surface)。於組裝過程中，係將半導體 晶片13接置於電路板u的開〇 113巾，並將其非電性^ 用面黏結至散熱件12、然後，進行—焊線製程，藉以利用 知線14將半導體晶片！ 3電性連接至該電路板^!第二表面1279175 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board structure and a method of fabricating the same, and more particularly to a circuit board structure incorporating a heat dissipation block and a method of fabricating the same. • [Prior Art] - With the booming electronics industry, electronic products are gradually entering the direction of multi-functional, high-performance research and development. In order to meet the high integration and integration of semiconductor packages, the circuit board for ki, the main and passive components, and the line-carrying (C i『(3)h _ Board) The single-layer board evolved into a multi-layer board (MuUi_layer Board). The number of circuit layers and component density of the board is high. The heat generated by the operation of the highly integrated semiconductor wafer will also increase. If the heat 1 is not removed in time, it will cause the semiconductor package to be hot and seriously threaten the life of the wafer. The method of attaching heat sinks to the bottom of the board is the most used in the industry. For example, a conventional Cavity-down ball grid array (CDBGA) is a special form of ball grid array package structure 10, as shown in FIG. Mainly, a circuit board 11 is formed with an opening σ 113, and a heat sink 12 is attached to connect the semiconductor wafer 13 to the heat sink 12 and is received in the opening 13 ” The material of 12 is a high thermal conductive material such as copper, and is attached to the first surface Ua of the circuit board u; and the semi-conductive 5 18485 '1279175 脰 Japanese film 13 has an active surface 13a (Act i ve surf ace) and a non-active surface 13b (Inactive surface). During the assembly process, the semiconductor wafer 13 is placed on the opening 113 of the circuit board u, and the non-electrical surface is bonded to the heat sink. And then, the wire bonding process is performed, whereby the semiconductor wafer is electrically connected to the circuit board by using the wire 14;

Ub之電性連接塾114,接著進行一封裝勝體製程，藉此而 形成封裝膠體15來完全包覆半導體晶片13和焊線Η，之 後，進行-植球程序，藉此而於電路板u㈣二表面爪 =置複數個焊球16。此即完成該底穴置 (CDBGA)封裝結構。 傅干〜式 問顆，"1 ㈣結構1G雖料以利用該散熱件12解決散熱 板，該焊球16配置高度必須大卜部印刷電路 配置同度，另一方面，由於半 極高，極易造成焊線14因不心：二3周圍之線弧密度 故增加打線作業的困難度；再者=產f短路m， 係將完成佈__ 13與料呈時， =二俾供—環氧樹脂(Ep。 而 用以包覆該半導體晶片13 U而形成 而，於實際製程中，該模且；^ 4之封裳膠體15,然 计，故其模穴尺寸與夾麼位置勢必有所差显 牛之設 密夾固等問題，俟注入樹脂材料時斤差f而造成無法緊 溢膠至該電路板表 ，致封裳膠體15 牛低料導體封裝件之表面平 18485 6 1279 ϊ 75 又”美觀@ h更可能〉讀該電路板上 16之烊塾位置，而影響該半導體封装件之電性連接Λ 、.以兀成+¥脰晶片13與電路板電性連接之導線產生 模流壓力，若注入速戶批在丨 、7產生 . 度才工制不§時，即會因該壓力衝擊導 線，使導線產生碰觸而發生短 @ 刀衡 封F件之U 口所U 嚴重影響該半導體 哀件之生產口口貝及產品信賴度。 '因而㈣耗將散^12㈣於該電路板表面， ^衣成品厚度增加，進而㈣於封裝成品尺寸之 …、因此此的提南’亦不符合電子產品微型化之發展趨勢。 盆f作方去如何提供一種具有良好散熱性之電路板結構及 板：=Γ 習知技術中由於將散熱“附於電路 起的封装成品尺寸無法縮小、電路板表面佈線 難度i日加寺缺失，實已成盎 1 【發明内容】、成A目别業界亟待解決之問題。 鑒於上述習知技術的缺點，本發明之主要 =料路板結構及其製作方法，藉以提供接置其上之t 又好放熱途徑，且得以縮小電路板尺寸。 八 =發k另目的在於提供—種電路板結構及其製 卞万法，糟以降低電路板表面佈線之難度。 為達上述目的，本發明接供—播命 法’係包括：於一承載板表面上；入：，構製作方 兮 面上I成多數導電凸塊，並於 ㈣成第1焊層’且令該第—防焊層填充 …寺h凸塊間之間隙中而露出該導電凸塊；於該第一 18485 7 1270175 及該導電凸塊表面形成一導電層，並於該導 开〔成弟-阻層，且令該第—阻層形成 ^ 分之該導電層；於該第一阻層開口中形成第一線路 一散埶挽·协兮外 风乐線路層及第 形成’第二阻層二散！塊、第一阻層及該第-線路層上 ^且令该第二阻層形成有開口以露出兮第一 ^ 散熱塊；於外露屮兮μ — n a μ弟一 •二散熱塊;移除該；：二:：之第一散熱塊上形成第 覆蓋之導電層，並；〜弟/且層及該第一阻層所 籲隹一細Α 對應於该弟一、弟二散熱塊位置外之誃 、、泉路層及第—防焊層上形成一 λ 層上形成第二線路肩，並於^ 層’以及於该介電 塊，且…：乐散熱塊上形成第三散熱 7 μ弟_、，泉路層得以電性連接至該第一線路層。 於該i':r結構之製作方法復包括移除該承載板：另可 成有門:ϊ層^成第二防焊層’且該第二防焊層中形 幵口以露出該第二線路層中作爲電性 可因應電性設計需求，以於該第二 _增層製程，㈣成乡I㈣結構。 持、、，進订線路 面及二m得之電路板結構係包括：-具有第-表 該散熱塊係外露於該介電層之第：“龙， 該介電声ώ弟—表面，且凸出於 外露於= 層，係嵌設於該介電層中且 ===表面;以及第二線路層，係形成於該 -二：! 令該第二線路層電性連接至該第 錢層。其巾該散熱塊之上下表面 —線路層齊平。 刀乃』舁。亥弟一及弟 18485 8 Ϊ279175 該電路板結構復包括··形成於該介電層第一表面之第 -防焊層，且該第-防焊層具多數開口以外部 一 線路層；形成於該第一防焊層開口中導带= 刀 χ Α T <蛉電凸塊；以及形 成於该第二線路層上之第二防焊層，且該第二防烊層具有 開口以露出該第二、線路層中作爲電性連接塾部分。 相較於習知技術，本發明之電路板結構及其製作方 法，主要係將散熱塊直接整合於佈設有第-線路層、介恭 ，ί二第：線路層Γ電路板中，從而可降低所形成的電路： 子又有利於封裝成品尺寸的縮小，藉以符合電子產品 型化之發展趨勢，而可適用於csp( 夕本逡邮酤罢^ 、cniP size package)級 免習知技術中將散熱片貼附於電路 引起的封裳產品厚度增加，封褒成品尺寸無法縮 同時，本發明係將散熱塊整合於電 習知技術中，散熱片貼附 /俾了避免 面佈線難度增加之缺失。表面所引起的電路板表 =’本發明於電路板中整合有散熱塊 =之:路板，以供後續將半導體晶片直接接置:該 :皁可藉由該散熱塊及導電凸塊以將該半導俨s 果。 …直接傳遞出去，提高電路板之散熱效 【實施方式】 由特定的具體實施例說明本發明之實施方 式U技藝之人士可由本說明書所揭示之内容輕易地 18485 9 Ϊ27 如 75 2解本發明之其他優點及功效。本發明亦可藉由I他 =體實施例加以施行或應用，本說明書中的各: I基於不同的觀點與應用，在不悖離本發明之 各種修飾與變更。 進仃 晴參閱第2A至2!圖，係詳細説明本發明之 構之製作方法第一實施例之剖面示意圖。 电、、、° 如第2A圖所示，首先提供—承載板2〇，並 板20上形成多數個導電凸塊 载 1形成-阻声（夫n s入— 於该承載板2〇上 下邻八之；it 層形成多數開口以露出爱 承載板，接著於該阻層開口中之承载板2。上形成 、屯凸塊21，亚移除該阻層，藉以 而供後續形成的恭玖钯έ士姐t 凸塊21 本實施例中t t凸1； 2? f子裝置電性導接。於 料所f成且由焊錫材料或其它金屬材 j h玄承載板20可為金屬板， 形成该導電凸塊21。 包圾万式 接著’於該承餘20上形成第-防 ==層22之材料填充於該等導電 ^ 中而外露出該等導電凸塊21。 Ί的間隙 。料第"防焊層22以及該導電凸塊 乂成‘電層23，該導電戶 屬材料所帝命、、 、曰 要作為後述電鍍金 層金屬芦所構：Ί广，其可由金屬、合金或沉積數 層23所構成’或可使用導電高分子材料以作為該導電 如第2C圖所示，接著於該導電層23上形成圖案化之 18485 10 127^175 第一阻層24，俾使該第一阻層μ霜芸社卹八 23。該第—阻層24可為一例如乾膜或液態:二導:： Γ:電二)面其:_ Μ包層23表面’再稭由曝光、顯影等製程加以圖宰化， 以使該第-阻層24僅覆蓋住部分之導電層23,而外露出 複數個欲電鍍形成線路與散熱塊之開口 24〇。 制。如第2D圖所示，接著，進行電錢⑻咖。_㈣ 衣私、’猎由料電層23具導電特性’俾在進行電鑛時可作 為電流傳導路徑，以在該等欲電㈣口 24{)中電鑛形成第 一線路層2 5及第一散熱塊2 51。 如第2E圖所示，於該第一散熱塊251、第一阻層％ 及該第一線路層25上形成第二阻層26，且該第二阻層26 中形成有開口 260以露出該第一線路層25中之第一散熱塊 251。 該第二阻層26可為一例如乾膜或液態光阻等光阻層 (Photoresist)，其係利用印刷、旋塗或貼合等方式形成於 名第阻層24及該第一線路層25表面，再藉由曝光、顯 影等製程加以圖案化以形成外露出該第一線路層25中之 第一散熱塊251。接著進行電鑛製程，以於外露出該第二 阻層26開口 260中之第一散熱塊251上形成第二散熱塊 252。 如第2F圖所示，移除該第二阻層26、該第一阻層24 以及該第一阻層24所覆蓋之導電層23。 如第2G圖所示，對應於該第一及第二散熱塊251，252 位置外之該第一線路層25及第一防焊層22上形成一介電 11 18485 127^175 層28，且於该介電層28中利用例如雷射鑽孔（丨aser drill)、電漿蝕孔或機械鑽孔方式形成盲孔28〇，以露出 其下部分之該第一線路層25。該介電層28係由即_4樹 脂、FR-5樹脂、環氧樹脂（Ep〇xy)、聚酯樹脂 (Polyesters)、氰脂（Cyanate ester)、聚乙醯胺 (Polyimide)、雙順丁烯二酸醯亞胺/三氮阱（訂，The electrical connection U114 of the Ub is followed by a package process, thereby forming the encapsulant 15 to completely encapsulate the semiconductor wafer 13 and the bonding wire, and then performing a ball implantation process, thereby on the circuit board u (4) Two surface claws = a plurality of solder balls 16 are placed. This completes the bottom hole placement (CDBGA) package structure. Fu Qian ~ type question, "1 (four) structure 1G is expected to use the heat sink 12 to solve the heat sink, the height of the solder ball 16 must be the same as the printed circuit configuration, on the other hand, due to the half-pole height, pole It is easy to cause the welding wire 14 to be unsatisfactory: the density of the arc around the 2 3 increases the difficulty of the wire-laying operation; the other is = the short-circuit m of the production f, the system will complete the cloth __ 13 and the material is presented, = 2 俾 supply - ring Oxygen resin (Ep. is used to cover the semiconductor wafer 13 U and formed, in the actual process, the mold and the sealant 15 of the mold, of course, so its cavity size and position is bound to have The problem is that the density of the cattle is tightly clamped, etc., when the resin material is injected into the resin material, the glue can not be glued to the circuit board, and the surface of the sealing material is low. 18485 6 1279 ϊ 75 and "beautiful @h more likely" read the position of the 16 on the circuit board, and affect the electrical connection of the semiconductor package ., the 导线 into + 脰 脰 wafer 13 and the circuit board electrically connected to the wire generated Molding pressure, if the injection speed of the batch is in the 丨, 7 is generated. If the system is not §, it will be due to the pressure Impacting the wire, causing the wire to touch and occur shortly. The U port of the F-piece is severely affected by the production mouth and product reliability of the semiconductor sorrow. 'Therefore (4) the consumption will be scattered ^12 (four) on the circuit board The surface, the thickness of the finished product is increased, and (4) the size of the finished product is packaged, so the mention of this is not in line with the development trend of miniaturization of electronic products. How to provide a circuit board structure with good heat dissipation And board: = Γ In the conventional technology, due to the heat dissipation, the size of the packaged product attached to the circuit cannot be reduced, and the surface of the circuit board is difficult to be replaced by the Japanese and Japanese temples. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main = material path structure of the present invention and the manufacturing method thereof, thereby providing a good heat release path for the connection of the above, and reducing the size of the circuit board. Another purpose is to provide a circuit board structure and its method of manufacturing, so as to reduce the difficulty of wiring the surface of the circuit board. To achieve the above purpose, the present invention includes: On the surface of the carrier plate; into: a plurality of conductive bumps are formed on the surface of the carrier, and are exposed in (4) into the first solder layer 'and the first solder mask layer is filled in the gap between the bumps of the temple h The conductive bump; forming a conductive layer on the surface of the first 18485 7 1270175 and the conductive bump, and forming the conductive layer on the conductive layer; and forming the conductive layer; Forming, in the first resistive layer opening, a first line, a bulk, a thin layer, and a second resist layer, a first resist layer, and the first circuit layer The second resistive layer is formed with an opening to expose the first heat dissipating block; the exposed 屮兮μ-na μdi one or two heat dissipating blocks; removing the second:: the first heat dissipating block forms a first covering The conductive layer, and the lower layer and the first resistive layer are corresponding to the 誃, the spring road layer and the first solder resist layer formed on the other side of the second heat sink block Forming a second line shoulder on a λ layer, and forming a third heat dissipation on the layer 'and the dielectric block, and ...: the heat sink block, the spring road layer Electrically connected to the first circuit layer. The manufacturing method of the i':r structure includes removing the carrier plate: another door may be formed: the second layer is formed into a second solder resist layer' and the second solder resist layer is shaped to expose the second layer In the circuit layer, electrical requirements can be made in response to the electrical design requirements, and the second _ layering process, (4) into the township I (four) structure. The circuit board structure of the circuit board and the second board includes: - having the first surface, the heat dissipating block is exposed on the dielectric layer: "Dragon, the dielectric sound brother - surface, and a second exposed circuit layer is electrically connected to the first money layer The layer has a lower surface of the heat sink block - the circuit layer is flush. Knife is 』 舁. Haidi 1 and brother 18485 8 Ϊ 279175 The circuit board structure includes · formed on the first surface of the dielectric layer - a solder layer, and the first solder mask has a plurality of openings to form an outer circuit layer; a conduction band formed in the opening of the first solder resist layer = a blade Α T < a 凸 electric bump; and a second line formed on the second line a second solder resist layer on the layer, and the second anti-corrugated layer has an opening to expose the second, circuit layer as an electrical connection portion. Compared with the prior art, the circuit board structure of the present invention and its fabrication The method mainly integrates the heat dissipating block directly into the circuit board provided with the first line layer, the second layer: the second layer: the circuit layer, The circuit can be reduced: the sub-product size is reduced, so as to conform to the development trend of the electronic product type, and can be applied to the csp (the 夕 逡 逡 酤 、 、 、 、 、 、 、 、 、 、 、 、 、 In the technology, the thickness of the sealing product caused by attaching the heat sink to the circuit is increased, and the size of the sealed product cannot be reduced. The present invention integrates the heat sink into the electric knowing technology, and the heat sink is attached/closed to avoid the difficulty of surface wiring. The lack of increase. The surface of the board caused by the surface = 'The present invention integrates a heat sink block in the circuit board =: the board, for subsequent subsequent connection of the semiconductor wafer: the: the soap can be used by the heat sink and conductive The bumps are directly transmitted to improve the heat dissipation effect of the circuit board. [Embodiment] The embodiment of the present invention will be described by a specific embodiment. 18485 9 Ϊ27, such as 75 2, to solve other advantages and effects of the present invention. The present invention can also be implemented or applied by the embodiment of the present invention, and each of the present specification: I is based on different viewpoints. The present invention is not limited to the various modifications and changes of the present invention. Referring to Figures 2A to 2!, a cross-sectional view showing a first embodiment of the manufacturing method of the present invention will be described in detail. As shown in Fig. 2A, the carrier plate 2 is first provided, and a plurality of conductive bumps are formed on the board 20 to form a sound-blocking sound (the ns are in--the upper and lower sides of the carrier board 2; the it layer forms a plurality of openings) To expose the love carrier board, and then to the carrier board 2 in the opening of the resist layer, the bumps 21 are formed thereon, and the resist layer is removed, thereby forming a constellation of palladium gentleman's t-bumps 21 In the embodiment, the tt convex 1; 2? f sub-device is electrically connected. The conductive bump 21 may be formed by a solder material or other metal material. The material of the layer 22 formed on the remainder 20 is filled in the conductive material to expose the conductive bumps 21. The gap between the cockroaches. The material "soldering layer 22 and the conductive bumps are formed into an 'electric layer 23', and the conductive household material is used as the metal layer of the electroplated gold layer, which is described later. The alloy or deposited layer 23 is formed 'or a conductive polymer material can be used as the conductive as shown in FIG. 2C, and then a patterned 18485 10 127^175 first resist layer 24 is formed on the conductive layer 23, Make the first resistance layer μ cream 芸 芸 八 23 23. The first resist layer 24 can be, for example, a dry film or a liquid: two-conductor:: Γ: electric two) surface: _ the surface of the enamel layer 23 is re-sowed by exposure, development, etc. The first-resist layer 24 covers only a portion of the conductive layer 23, and exposes a plurality of openings 24 to be plated to form a line and a heat sink. system. As shown in Fig. 2D, next, the electric money (8) coffee is carried out. _ (4) Clothing, 'hunting electrical conductivity 23 electrical properties' can be used as a current conduction path when conducting electric ore, to form the first circuit layer 2 5 and the first in the electric (4) port 24{) A heat sink block 2 51. As shown in FIG. 2E, a second resist layer 26 is formed on the first heat dissipation block 251, the first resist layer%, and the first circuit layer 25, and an opening 260 is formed in the second resist layer 26 to expose the The first heat dissipation block 251 in the first circuit layer 25. The second resist layer 26 can be a photoresist layer such as a dry film or a liquid photoresist, which is formed on the first resistive layer 24 and the first trace layer 25 by printing, spin coating or lamination. The surface is patterned by exposure, development, etc. to form a first heat dissipation block 251 exposed in the first circuit layer 25. Then, an electric ore processing is performed to form a second heat dissipation block 252 on the first heat dissipation block 251 which is exposed in the opening 260 of the second resistance layer 26. As shown in FIG. 2F, the second resist layer 26, the first resist layer 24, and the conductive layer 23 covered by the first resist layer 24 are removed. As shown in FIG. 2G, a dielectric 11 18485 127^175 layer 28 is formed on the first circuit layer 25 and the first solder resist layer 22 outside the first and second heat dissipation blocks 251, 252, and A blind via 28 is formed in the dielectric layer 28 by, for example, laser drilling, plasma etching, or mechanical drilling to expose the lower portion of the first wiring layer 25. The dielectric layer 28 is made of _4 resin, FR-5 resin, epoxy resin (Ep〇xy), polyester resin (Polyesters), cyanate ester, polyimide, polyshun. Butylenediamine/trinitrogen trap (scheduled,

B1Smaleimide triazine)或混合環氧樹脂、玻璃纖維 (Glass fiber)等絕緣性材料製成。 如第2H圖所示，於該介電層28、該第二散熱塊况 以及該盲孔280表面上形成一遙恭恳9〇斗、音 小珉钕包層29，該導電層29主 要作為後述電鍍金屬材料 刊7卞尸汀而之甩机傳導路徑，其可由金 屬、合金或沉積數層金屬 n &、·. 料而構成者。 θ所構成，或可輕電高分子材 該第三Ρ且層/9上形成圖案化之第三阻層30，俾使 ^ " 〇覆蓋住部分之該導電層29。哕第-卩且厗 可為一例如齡瞪汔、六〜 ％曰α 3弟二阻層30 利用印刷、旋卿— 藉由曝光、顯影等 形成複數欲電鑛形成 =^匕U使该弟三阻層30 -開口 300位置係對應於該；之開口 _，其中至少 如第21圖所示，/ —放熱塊252位置。 導電特性，俾在進〜兩仃電鍍製程，藉由該導電層29具 第三阻層開u 300】：：：可作為電流傳導路徑，以於該 2S〇I：；^IUM" 253 ^-^ "罘一、、泉路層31透過形成於該介 ]8485 ]2 1279175 =28中之導電盲孔280a與該第—線路層25進行電性 連接，之後移除該第三阻層30及其所覆蓋之導電層別。 層32H圖所^，於該第二線路層31上形成第二防焊 二 "弟一防干層32具有開口 32〇以露出該第三散 =塊253以及該第二線路層中作為電性連接墊311部分。 ㈣接塾311上形成一例如鎳/金層之金屬保 .未圖不)。之後移除該承載板2。，藉以形成 放熱塊之電路板結構。 名 :過本發明之電路板結構第—實施 :::rrr要係包括:-具有第-表一第二 之"书層28,禝數個堆疊散熱塊係嵌埋於該介電 層28中且凸出於該介電層28之第二表面挪；盆中，^ 複數堆疊散熱塊係包含有嵌埋於該介之^ 熱塊252及凸出於該介電層二面 4 28^^、、塊253 ’―嵌設於該介電層28中且與該介 1C入： …齊平之第一線路層25;以及-形成 二表面28b上且與第'線路層25電性連 二=:層中31;/中，該第一線路㈣ 層3卜θ +之¥電盲孔280&電性連接至該第二線路 上述該介電層28之第一表面28心私活——斤 層22,且該黛—，日， 表面Z8a，係覆盍有弟一防焊 ^ _ 11 方少干層22具多數開n 22a以外露出部分 :門口：路：25及第1熱塊251，另於該第-防焊層22 幵a中形成有導電凸塊2卜該導電凸塊21高度係 18485 13 Ϊ270175 與該第-防焊層22表面齊平，且其材質可為 屬材料。該介電層28之第二表面 第”、料或金 奴後盖有弟二防焊層32，且該第二防烊層⑵ 广上 以露出該第三散熱塊253及該 :4 口 320 接塾311部分。另L二：路層31中作為電性連 q…弟一線路層31上未被該第二防焊岸 復盍之部分以及該第三散熱塊253之表面 曰 金屬保護層，該金屬保護層係可為鎳/金層。^成有一 μ I閱第3A及第3B圖所示’係為本發明之 之製作方法第二實施例之剖面示意圖。於：、二 施例中’主要係可於前述第—實 = 表路4層製程，以形成所需電性設計之電路板。 -線:：23:圖：示，在第一實施例中所製備-已佈有第 、，泉路層25、弟二線路層3卜第一、第二 ⑸，252,咖、介電層28、第-防焊層22及多數— 請參閱第21圖所示)，對應在該第二線 _ 弗二放熱塊253上進行線路增層製程，以在該第 二線路層31上形成一線路增層結構34，並令該線路增層 ，構34電性連接至該第二線路層3卜同時持續堆高該散 熱塊之厚度’以於該第三散熱塊253上形成第四散熱塊 254。 “ 4線路增層結構34係包括：介電層，疊置於該介 電層340上之線路層342以及穿過該介電層34〇以電性連 接至該線路層342之導電盲孔342a，且該等多數個導電盲 孔342a得以電性連接至該第二線路層31。而在該線路增 14 18485 127^175 ^结構34之外表面之線路層上則形成有多數電性連接塾 如第3B圖所示，於該線路增層結構34之外 上及弟四散熱塊254上形成第二防谭層32，該第二^ 32係具有多數開口以外露出該外層線路層之電 曰 344及第四散熱塊254，藉以可供後續將半導體晶 示）接置於該第四散熱塊254上，並透過該散熱塊及導^ ，以逸散晶片運作時所產生之熱量。另可於該第二防二 2開口中之電性連㈣344上形成_例如錄/金金屬曰 屬保護層（未圖示）。之後即可移除該承載板2〇，藉以1 一埋設有散熱塊之電路板結構。 ㈢^ 因此’本發明之電路板結構及其製作方法， 供:表㈣成有多數導電㈣之承載板，且於該承载板^ =形成弟-防焊層’以使該第一防焊層材料填 導 電凸塊間之間隙中而露出該等導電凸塊；接著於^寺^ • SIS凸塊上形成第一線路層及第-散熱I: 遠弟-讀塊上形成第二散熱塊，並制於該第_ ' •散熱塊外之第一線路層及第一防焊層上形成： -於該介電層上形成第二線路層，且使該第二線路^導^ =電：連接至該第'線路層，藉以將散熱塊整 板中，俾可使電路板厚度降低，且有利於封裝成品尺3 =小及性能之提高，進而符合電子產品微型化之發=之 另]可避免習知技術中將散熱片貼附面 起的封裝產品厚度增力…★裝成品尺寸無法縮 18485 15 I279175 電路，本發明係於電路板中嵌設有散熱塊，無須佔據 面，佈線面積，因而有利於提升電路板表面佈線 面所引起=可避免習知技術中’散熱片貼附於電路板表 斤弓丨起的笔路板表面佈線難度增加之缺失。 且古本發明係將散熱塊整合於電路板中，藉以形成 該二:？之電路!反，以供後續將半導體晶片直接接置於 生的^旦亩’俾可猎由該散熱塊將該半導體晶片運作時產 、":'里接傳遞出去，提高電路板之散熱效果。 =及，於本發明之電路板結構之第二線路層上，復可 進仃線路增層製程，藉以在 後了 細線路之多層線路結構。弟—線路層上形成南密度及 上述貝施例僅為例示性說明本發明之原理及 限制本發明。任何熟習此項技藝之;; =不心本發明之精神及㈣下，對上述實施例進行修 改。因此本發明之權利彳早婼筋 " 圍所列。 ㈣保⑼圍’應如後述之申請專利範 【圖式簡單説明】 面示=圖係為習知底穴置晶型球拇陣型式封裝結構之剖 弟2A至U 、為本發明之電路板結構 一實施例之剖面示意圖；以及 衣作方法乐 弟3A及3B圖係為本發明之電路板結 二實施例之剖面示意圖。 衣忭万法罘 【主要元件符號說明】 18485 16 1279175 ίο 封裝結構 113 、 22a 、 240 、 260 、 300 、 320 開口 114、311、344 電性連接墊 11a 、 28a 第一表面 lib 、 28b 第二表面 11 電路板 12 散熱件 13a 主動面 13b 非主動面 13 半導體晶片 14 焊線 15 封裝膠體 16 焊球 20 承載板 21 導電凸塊 22 第一防焊層 23 > 29 導電層 24 第一阻層 251 第一散熱塊 252 第二散熱塊 253 第三散熱塊 254 第四散熱塊 25 第一線路層 26 第二阻層 17 18485 Ϊ279175 28、 340 介電層 280a 、342a 導電盲孔 280 盲孑L 30 第三阻層 31 第二線路層 32 第二防焊層 342 線路層 34 線路增層結構 18 18485B1Smaleimide triazine) or an insulating material such as a mixed epoxy resin or a glass fiber. As shown in FIG. 2H, a dielectric layer 9 and a small acoustic layer 29 are formed on the surface of the dielectric layer 28, the second heat dissipation block, and the blind hole 280. The conductive layer 29 is mainly used as the conductive layer 29. The electroplating metal material described later is a crucible conduction path, which can be composed of a metal, an alloy, or a plurality of layers of metal n & θ is formed, or the light-emitting polymer material can be formed on the third layer and the patterned third resist layer 30 is formed on the layer/9, so that the portion of the conductive layer 29 is covered by ^ "哕第卩 卩 and 厗 can be a 瞪汔 瞪汔 六 六 六 六 六 六 3 3 3 3 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用The three-resist layer 30-opening 300 position corresponds to the opening_, wherein at least as shown in Fig. 21, the position of the heat releasing block 252. Conductive characteristics, 俾 in the two ~ 仃 electroplating process, by the conductive layer 29 with a third resistive layer open u 300]::: can be used as a current conduction path for the 2S〇I:; ^IUM" 253 ^- ^ ", the spring layer 31 is electrically connected to the first wiring layer 25 through the conductive blind hole 280a formed in the dielectric 8848] 2 1279175 = 28, and then the third resist layer 30 is removed. And the conductive layer covered by it. The layer 32H is formed on the second circuit layer 31, and the second solder resist layer 32 has an opening 32〇 to expose the third bulk block 253 and the second circuit layer as electricity. Part of the connection pad 311. (4) Forming a metal such as a nickel/gold layer on the joint 311. Not shown). The carrier plate 2 is then removed. To form a circuit board structure of the heat release block. Name: The circuit board structure of the present invention - implementation:::rrr to include: - having the first - second and the "book layer 28", a plurality of stacked heat sink blocks embedded in the dielectric layer 28 And protruding from the second surface of the dielectric layer 28; in the basin, the plurality of stacked heat dissipating blocks comprise embedded in the dielectric block 252 and protruded from the dielectric layer on both sides of the dielectric layer 28 ^, block 253' - a first circuit layer 25 embedded in the dielectric layer 28 and flush with the dielectric layer; and - formed on the second surface 28b and electrically connected to the 'circuit layer 25 Two =: in the layer 31; /, the first line (four) layer 3 θ θ + electric blind hole 280 & electrically connected to the second line of the first surface 28 of the dielectric layer 28 is private -斤层22, and the 黛-, day, surface Z8a, the system is covered with a younger anti-welding ^ _ 11 square less dry layer 22 with a majority of open n 22a exposed part: door: road: 25 and the first thermal block 251, another A conductive bump 2 is formed in the first solder resist layer 22 幵a. The conductive bump 21 height 18485 13 Ϊ 270175 is flush with the surface of the first solder resist layer 22, and the material thereof can be a genus material. The second surface of the dielectric layer 28, the material or the Jinnu back cover has a second solder mask 32, and the second anti-mite layer (2) is wide to expose the third heat sink 253 and the: 4 port 320 Connected to Section 311. Another L: the layer of the circuit layer 31 as the electrical connection q...the portion of the circuit layer 31 that is not re-twisted by the second solder-proof shore and the surface of the third heat-dissipating block 253 The metal protective layer may be a nickel/gold layer. The first embodiment is a cross-sectional view of the second embodiment of the manufacturing method of the present invention. The 'mainly can be used in the above-mentioned first - real = table 4 layer process to form the circuit board of the required electrical design. - Line:: 23: Figure: shown, prepared in the first embodiment - has been clothed First, the spring road layer 25, the second circuit layer 3, the first, the second (5), 252, the coffee, the dielectric layer 28, the first solder mask 22 and the majority - see Figure 21, corresponding to A line build-up process is performed on the second line _ s 2 heat release block 253 to form a line build-up structure 34 on the second line layer 31, and the line is layered, and the structure 34 is electrically connected to The second circuit layer 3 continues to stack the thickness of the heat sink block at the same time to form a fourth heat dissipation block 254 on the third heat dissipation block 253. The "4 line build-up structure 34 includes: a dielectric layer stacked on the a circuit layer 342 on the dielectric layer 340 and a conductive via 342a electrically connected to the circuit layer 342 through the dielectric layer 34, and the plurality of conductive vias 342a are electrically connected to the second Circuit layer 31. On the circuit layer with 14 18485 127^175 ^ structure 34 on the external line, a plurality of electrical connections are formed, as shown in FIG. 3B, and the heat dissipation block is formed outside the line build-up structure 34. A second anti-tank layer 32 is formed on the 254, and the second layer 32 has a plurality of openings 142 and a fourth heat-dissipating block 254 exposing the outer-layer circuit layer, so that the semiconductor crystal can be subsequently placed on the second surface. The heat dissipating block 254 is passed through the heat dissipating block 254 to dissipate the heat generated when the wafer is operated. Further, for example, a recording/gold metal ruthenium protective layer (not shown) may be formed on the electrical connection (four) 344 of the second anti-two opening. The carrier board 2 can then be removed, whereby a circuit board structure in which a heat sink block is embedded is used. (3) ^ Therefore, the circuit board structure of the present invention and its manufacturing method are provided: Table (4) is a carrier plate having a plurality of conductive (four), and the carrier plate is formed with a solder-proof layer to make the first solder resist layer The material is filled in the gap between the conductive bumps to expose the conductive bumps; then the first circuit layer and the first heat dissipation I are formed on the SIS bumps: a second heat dissipation block is formed on the far-read block. And forming on the first circuit layer and the first solder resist layer outside the heat dissipation block: forming a second circuit layer on the dielectric layer, and causing the second circuit to be electrically: Connected to the 'the circuit layer, so that the heat sink block can be used in the whole board, the thickness of the circuit board can be reduced, and the package finished product 3 = small and the performance is improved, thereby complying with the miniaturization of the electronic product = another] It can avoid the thickness increase of the package product from the heat sink attachment surface in the prior art... ★ The finished product size cannot be reduced by 18485 15 I279175 circuit, the invention is embedded in the circuit board with the heat dissipation block, no need to occupy the surface, the wiring area Therefore, it is beneficial to raise the wiring surface of the board surface. The surface of the wiring increases the difficulty of deletion 'fins attached to the circuit board from Table pounds bow Shu pen board. And the invention of the invention integrates the heat sink block into the circuit board, thereby forming the second: The circuit is reversed for the subsequent connection of the semiconductor wafer directly to the raw material. The semiconductor chip can be produced by the heat sink block, and the ":" is transferred to improve the heat dissipation of the circuit board. effect. And, on the second circuit layer of the circuit board structure of the present invention, the circuit can be added to the line build-up process, whereby the multi-layer line structure of the fine line is followed. The formation of a south density on the circuit layer and the above-described bee examples are merely illustrative of the principles of the invention and the invention. Any of the skill in the art;; = the spirit of the present invention and (4), the above embodiment is modified. Therefore, the rights of the present invention are listed in the early days. (4) Bao (9) Wai' should apply for a patent model as described later [Simplified description of the drawing] Face = Figure is the schematic diagram of the well-formed hole-shaped crystal ball-shaped array type package structure 2A to U, which is the circuit board of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a second embodiment of a circuit board according to the present invention.衣忭万法罘 [Main component symbol description] 18485 16 1279175 ίο Package structure 113, 22a, 240, 260, 300, 320 Openings 114, 311, 344 Electrical connection pads 11a, 28a First surface lib, 28b Second surface 11 circuit board 12 heat sink 13a active surface 13b inactive surface 13 semiconductor wafer 14 bonding wire 15 encapsulant 16 solder ball 20 carrier plate 21 conductive bump 22 first solder mask 23 > 29 conductive layer 24 first resist layer 251 First heat sink block 252 second heat sink block 253 third heat sink block 254 fourth heat sink block 25 first circuit layer 26 second resist layer 17 18485 Ϊ 279175 28, 340 dielectric layer 280a, 342a conductive blind hole 280 blind 孑 L 30 Tri-resist layer 31 second circuit layer 32 second solder resist layer 342 circuit layer 34 line build-up structure 18 18485

Claims (1)

第94124650號專利申請案 申凊專利範圍修正本 1279175 一 （95年9月j曰） 種電路板結構之製作方法，係包括·· 於一承載板表面上形成多數導電凸塊與第一防焊 層，並令該第一防焊層填充於該等導電凸塊間之間隙中 、而露出該等導電凸塊； “ 於該第一防焊層及導電凸塊表面形成一導電層，並 • •於該V電層上形成第—阻層，且令該第一阻層形成有多 數開口以露出部分導電層； 於該第一阻層開口中形成第一線路層及第一散執 塊； … 〃於該第-散熱塊、第—阻層及該第—線路層上形成 第二阻層，且令該第二阻層形成有開口以露出該 熱塊； n % 於外露出該第 二散熱塊； 二阻層開口之第一散熱塊上形成第 移除該第二阻層、該第一阻層及該第一阻層所覆蓋 之導電層，並對應於該第一及第二散熱塊外之該第一線 路層及第一防焊層上形成一介電層；以及 ，於該第二散熱塊上形成第三散熱塊，且於該介電層 上形成第二線路層，並令該第二線路層#以電性連接^ 該第一線路層。 2·如申請專利^圍第丨項之電路板結構之製作方法，其 18485(修正本) 1279175 且該阻層形成複數個開 中，該導電凸塊之製程係為： 於該承載板上形成一阻層 口；以及 於該阻層開 3·如申請專利範圍 括移除該阻層。 口中形成導電凸塊。 第2項之電路板結構之製作方法 ，復包 4·=申請專利範圍第！項之電路板結構之製作方法，其 制成該導電凸塊係由焊錫材料及金屬材料之其中一者所 5.如申請2利範圍第丨項之電路板結構之製作方法其 中，S亥第二線路層之製程係為： 於該介電層中形成多數盲孔以露出其下部分之第 一線路層； 於該介電層、該第二散熱塊及該盲孔表面形成一 電層； 、於該導電層上形成一第三阻層，且該第三阻層中形 成複數開口；以及 於該第三阻層開口中電鍍形成第二線路層、導電盲 孔及第三散熱塊，該第二線路層係透過形成於該介電層 中之導電盲孔電性連接至該第一線路層，且該第三散熱 塊係對應形成於該第二散熱塊上。 •如申請專利範圍第5項之電路板結構之製作方法，復包 括移除該第三阻層及其所覆蓋之導電層。 •如申請專利範圍第1項之電路板結構之製作方法，復包 2 18485(修正本) -1279175 ‘括： 屛且二線路層上形成第二防焊層’且該第二防焊 =有開口以露出該第三散熱塊以及該第 作為電性連接塾部分；以及 路曰中 矛夕除該承載板。 =申請專利範圍第7項之f路板結構之製作方法，其 η亥電性連接墊表面形成有金屬保護層。 =申凊專利範圍第1項之電路板結構之製作方法，復包 於該第二線路層及第三散熱塊上進行線路增層製 轾以在該第二線路層上形成線路增層結構及堆高該散 熱塊厚度，該線路增層結構外表面之線路層上形成有多 數電性連接墊； 於該線路增層結構及散熱塊外表面形成第二防焊 曰且々该弟二防焊層形成開口以露出該電性連接塾及 散熱塊；以及 移除該承載板。 如申吻專利範圍第9項之電路板結構之製作方法，1 中’該電性連接墊表面形成有金屬保護層。 U· 一種電路板結構，係包括： 一具有第一表面及第二表面之介電層； 複數個堆疊散熱塊係嵌埋於該介電層中且凸出於 該介電層之第二表面； 一嵌設於該介電層中且與該介電層第一表面齊平 18485(修正本) 3 1279175 之第一線路層；以及 、一形成於該介電層第二表面上且與第一線路層電 f生連接之第一線路層；其中，該第一線路層係透過形成 於該f電層中之導電盲孔電性連接至該第二線路層。 12.如^請專利範圍第u項之電路板結構，其中，該複數 堆璺散熱塊係包括嵌埋於該介電層中之第一、第二散熱 塊及凸出於該介電層第二表面之第三散熱塊。 13·如申請專利範圍第u項之電路板結構，復包括： 覆蓋於該介電層第一表面及第一線路層上之第一 防焊層，且該第一防焊層具多數開口以外露出部分該第 一線路層；以及 形成於該第一防焊層之開口中之導電凸塊。 14·如申請專利範圍第13項之電路板結構，其中，該導電 凸塊之材質為焊錫材料及金屬材料之其中一者。 如申#專利範圍弟12項之電路板結構，復包括有形成 於該介電層之第二表面、第二線路層及第三散熱塊上之 第二防焊層，且該第二防焊層具有開口以露出該第三散 熱塊及该弟二線路層中作為電性連接塾部分。 16·如申請專利範圍第15項之電路板結構，其中，該電性 連接墊表面形成有金屬保護層。 17·如申請專利範圍第12項之電路板結構，其中，該介電 層第二表面及第二線路層上復形成有線路增層結構，且 該第三散熱塊上亦堆積有散熱塊。 18·如申請專利範圍第17項之電路板結構，其中，該線路 18485(修正本) 4 ,1279175 i * ，增層結構上復形成一防焊層，且該防焊層具有多數開口 以露出該線路增層結構外表面之線路層上之電性連接 墊。 11如申請專利範圍第18項之電路板結構，其中，該電性 連接墊表面係形成有金屬保護層。 5 18485(修正本)Patent Application No. 94,224,650, the entire disclosure of which is incorporated herein by reference. a layer, and the first solder resist layer is filled in the gap between the conductive bumps to expose the conductive bumps; “forming a conductive layer on the surface of the first solder resist layer and the conductive bumps, and Forming a first resist layer on the V-electrode layer, and forming a plurality of openings in the first resistive layer to expose a portion of the conductive layer; forming a first wiring layer and a first dissipation block in the first resistive layer opening; Forming a second resist layer on the first heat sink block, the first resist layer, and the first circuit layer, and forming the second resist layer with an opening to expose the heat block; n % exposing the second layer a heat dissipating block; a first heat dissipating block having a second resist layer opening, wherein the second resistive layer, the first resistive layer and the conductive layer covered by the first resistive layer are formed, and corresponding to the first and second heat dissipation Forming a dielectric layer on the first circuit layer and the first solder resist layer outside the block And forming a third heat dissipation block on the second heat dissipation block, and forming a second circuit layer on the dielectric layer, and electrically connecting the second circuit layer # to the first circuit layer. The manufacturing method of the circuit board structure of the patent application is as follows: 18485 (Revised) 1279175 and the resist layer forms a plurality of openings, and the manufacturing process of the conductive bump is: forming a resist layer on the carrier board And the barrier layer is opened. 3. If the patent application scope is removed, the conductive layer is formed. The conductive bump is formed in the mouth. The manufacturing method of the circuit board structure of the second item, the repacking 4·= the patent application scope item! The manufacturing method of the circuit board structure, wherein the conductive bump is made of one of a solder material and a metal material. 5. The manufacturing method of the circuit board structure of the second item of the application, wherein the second circuit of the S The process of the layer is: forming a plurality of blind vias in the dielectric layer to expose the first circuit layer of the lower portion; forming an electrical layer on the dielectric layer, the second heat dissipation block and the surface of the blind via; Forming a third resist layer on the conductive layer, and Forming a plurality of openings in the third resistive layer; and forming a second wiring layer, a conductive blind via and a third heat dissipating block in the third resistive layer opening, the second wiring layer transmitting the conductive layer formed in the dielectric layer The blind hole is electrically connected to the first circuit layer, and the third heat dissipation block is correspondingly formed on the second heat dissipation block. • The method for manufacturing the circuit board structure according to claim 5, including removing the The third resistive layer and the conductive layer covered by the same. • The manufacturing method of the circuit board structure according to the first application of the patent scope, the second package 2 18485 (amendment) -1279175 'includes: 屛 and the second circuit layer forms a second a solder resist layer 'and the second solder mask = an opening to expose the third heat sink block and the first portion as an electrical connection port; and the carrier in the road. = The method for fabricating the f-plate structure of claim 7 is to form a metal protective layer on the surface of the electrical connection pad. The manufacturing method of the circuit board structure of claim 1 is applied to the second circuit layer and the third heat dissipation block to form a line build-up system to form a line build-up structure on the second circuit layer and Stacking the thickness of the heat sink block, a plurality of electrical connection pads are formed on the circuit layer on the outer surface of the line build-up structure; forming a second solder mask on the line build-up structure and the outer surface of the heat sink block The layer forms an opening to expose the electrical connection port and the heat dissipation block; and remove the carrier plate. For example, in the manufacturing method of the circuit board structure of the ninth patent application scope, the surface of the electrical connection pad is formed with a metal protective layer. A circuit board structure comprising: a dielectric layer having a first surface and a second surface; a plurality of stacked heat dissipation blocks embedded in the dielectric layer and protruding from the second surface of the dielectric layer a first circuit layer embedded in the dielectric layer and flush with the first surface of the dielectric layer 18485 (Revised) 3 1279175; and a second surface formed on the dielectric layer and The first circuit layer is electrically connected to the second circuit layer through a conductive blind via formed in the electrical layer. 12. The circuit board structure of claim U, wherein the plurality of stacked heat sink blocks comprise first and second heat dissipating blocks embedded in the dielectric layer and protruding from the dielectric layer The third heat sink block on the two surfaces. 13. The circuit board structure of claim U, further comprising: a first solder resist layer covering the first surface of the dielectric layer and the first circuit layer, and the first solder resist layer has a plurality of openings Exposing a portion of the first wiring layer; and a conductive bump formed in the opening of the first solder resist layer. 14. The circuit board structure of claim 13, wherein the conductive bump is made of one of a solder material and a metal material. The circuit board structure of the 12th patent of the patent scope includes a second solder resist layer formed on the second surface of the dielectric layer, the second circuit layer and the third heat dissipation block, and the second solder mask The layer has an opening to expose the third heat dissipation block and the second circuit layer as an electrical connection portion. The circuit board structure of claim 15, wherein the surface of the electrical connection pad is formed with a metal protective layer. The circuit board structure of claim 12, wherein the second surface of the dielectric layer and the second circuit layer are further formed with a line build-up structure, and the heat dissipation block is also stacked on the third heat dissipation block. 18. The circuit board structure of claim 17, wherein the circuit 18485 (Revised) 4, 1279175 i*, the build-up structure is formed with a solder resist layer, and the solder resist layer has a plurality of openings to expose The circuit is electrically connected to the electrical connection pads on the outer layer of the outer surface of the structure. 11. The circuit board structure of claim 18, wherein the surface of the electrical connection pad is formed with a metal protective layer. 5 18485 (amendment)
TW094124650A 2005-07-21 2005-07-21 Circuit board structure and method for fabricating the same TWI279175B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094124650A TWI279175B (en) 2005-07-21 2005-07-21 Circuit board structure and method for fabricating the same
US11/458,605 US20070017815A1 (en) 2005-07-21 2006-07-19 Circuit board structure and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094124650A TWI279175B (en) 2005-07-21 2005-07-21 Circuit board structure and method for fabricating the same

Publications (2)

Publication Number Publication Date
TW200706085A TW200706085A (en) 2007-02-01
TWI279175B true TWI279175B (en) 2007-04-11

Family

ID=37678065

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094124650A TWI279175B (en) 2005-07-21 2005-07-21 Circuit board structure and method for fabricating the same

Country Status (2)

Country Link
US (1) US20070017815A1 (en)
TW (1) TWI279175B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200810043A (en) * 2006-08-04 2008-02-16 Phoenix Prec Technology Corp Circuit board structure with capacitor embedded therein and method for fabricating the same
US8269336B2 (en) * 2008-03-25 2012-09-18 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and signal post
TWI419272B (en) * 2009-12-19 2013-12-11 Bridge Semiconductor Corp Semiconductor chip assembly with post/base heat spreader and signal post
TWI419278B (en) * 2010-10-26 2013-12-11 Unimicron Technology Corp Package substrate and fabrication method thereof
US20160316573A1 (en) * 2015-04-22 2016-10-27 Dyi-chung Hu Solder mask first process
CN112492777B (en) * 2019-09-12 2022-05-27 宏启胜精密电子(秦皇岛)有限公司 Circuit board and manufacturing method thereof
CN111883431B (en) * 2020-06-15 2021-09-21 珠海越亚半导体股份有限公司 Packaging substrate with efficient heat dissipation structure and manufacturing method thereof
CN114828383A (en) * 2021-01-21 2022-07-29 欣兴电子股份有限公司 Circuit board structure and manufacturing method thereof
US20230197645A1 (en) * 2021-12-20 2023-06-22 Nxp Usa, Inc. Radio frequency packages containing multilevel power substrates and associated fabrication methods

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6156980A (en) * 1998-06-04 2000-12-05 Delco Electronics Corp. Flip chip on circuit board with enhanced heat dissipation and method therefor
SE513786C2 (en) * 1999-03-09 2000-11-06 Ericsson Telefon Ab L M Method for producing circuit boards and device for heat dissipation made according to the method
US6664617B2 (en) * 2000-12-19 2003-12-16 Convergence Technologies, Ltd. Semiconductor package
US20020079572A1 (en) * 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US6562656B1 (en) * 2001-06-25 2003-05-13 Thin Film Module, Inc. Cavity down flip chip BGA
US6657296B2 (en) * 2001-09-25 2003-12-02 Siliconware Precision Industries Co., Ltd. Semicondctor package

Also Published As

Publication number Publication date
TW200706085A (en) 2007-02-01
US20070017815A1 (en) 2007-01-25

Similar Documents

Publication Publication Date Title
TWI279175B (en) Circuit board structure and method for fabricating the same
TWI374531B (en) Inter-connecting structure for semiconductor device package and method of the same
TWI237885B (en) Semiconductor device having carrier embedded with chip and method for fabricating the same
US7656015B2 (en) Packaging substrate having heat-dissipating structure
TWI706519B (en) Semiconductor package having routable encapsulated conductive substrate and method
TWI279897B (en) Embedded semiconductor chip structure and method for fabricating the same
TWI249232B (en) Heat dissipating package structure and method for fabricating the same
TW200941659A (en) Thermally enhanced package with embedded metal slug and patterned circuitry
TW200832655A (en) Package structure with circuit directly connected to chip
TW201123374A (en) Package structure and fabrication method thereof
TWI321838B (en) Stacked type chip package, chip package and process thereof
CN101228625B (en) Semiconductor package with plated connection
TWI334202B (en) Carrier and manufacturing process thereof
TW201041103A (en) Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
TW200841442A (en) Stacked packing module
JP2008277570A (en) Semiconductor device and manufacturing method therefor
TW200828564A (en) Multi-chip package structure and method of forming the same
TW200910551A (en) Semiconductor package structure
TWI500130B (en) Package substrate, semiconductor package and methods of manufacturing the same
TW200839971A (en) Chip package module
TW201142998A (en) System-in-package
WO2021258706A1 (en) Semiconductor device packaging method and semiconductor device
TWI283055B (en) Superfine-circuit semiconductor package structure
TW200910561A (en) Packaging substrate structure with capacitor embedded therein and method for fabricating the same
TW201138043A (en) Circuit board structure, packaging structure and method for making the same