201142998 六、發明說明： 【發明所屬之技術領域】 本發明涉及半導體封裝技術，更具體地，涉及至少一種覆曰 _-ChiP)封裝及半導體晶片封裝，可應用於具有多個接腳㈣數目= 情形。 【先前技術】 在本領域中，為了將裸晶設置於基板上，可經由位於裸晶及基板 上之多個接合焊點來實現，在此過程中，可應用多種晶片封裝技術， 如球栅陣列(Ball Grid Array ’ BGA)、線結合、覆晶等。為了確保電子 產品或通信裝置之小型化及功能多樣化，半導體封裝需要尺寸小、多 接腳連接、高速率及多功能化。 輸入輸出(Input-Output ’ I/O)接腳數目之增加與高性能忙需求之 增加，促進了覆晶封裝技術之發展。覆晶技術使用位於晶片之多個接 ό火于塾上之夕個凸塊(bumps)與封裝媒體直接互連。晶片透過最短路徑 面向接合封裝媒體。該技術不僅可應用於單晶片封裝，也可應用於更 高整合位準之尺寸較大之封裝，以及可容納幾個晶片以形成較大功能 單元之更加精密之基板。覆晶技術使用區域陣列，具有實現與裳置之 互連密度最高與封裝之互連電感較低之優點。 第1圖所示為傳統晶片級覆晶封裝（Fijp_chip Chip Scale Package，以下簡稱FCCSP)之截面示意圖。如第1圖所示，FFCSp動 201142998 包含裸晶101，裸晶101倒置(face_down)於載體120之上表面(t〇p surface)並透過多個焊點凸塊(solderbump)l〇2連接至載體12〇。於載體 120之底面上提供多個焊錫球(solder ball) 122用以連接電路板。典型的 該封裝構造在區域陣列或週邊凸塊排佈中使用共晶錫/鉛覆晶互連 (eutectic tin/lead flip-chip interconnect)技術’以取代標準之線結合互 連。由於線結合迴路之消除，使與裸晶之連接電感較低，同時，走線 密度(routing density)之增加優化了臨界高頻信號線路之電氣路徑。 第2圖所示為傳統覆晶球柵陣列(Flip_Chip _ Gri(J如吵，以下 簡稱FCBGA)封裝之戴面示意圖。如第2圖所示，fcBGA封裝200 包含裸晶201，裸晶201倒置於晶片載體基板22〇之上表面並透過多 個悍點凸塊202連接晶片載體基板22G。底勝(underflli)2〇3填充裸晶 201與晶片載體基板22〇之頂面之間的空隙。晶片載體基板22〇可包 含多層走線(trace)，該多層走線之不同層透過盲孔(bUnd仏)222或埋孔 (bUriedvia)224互相連接在-起。例如，盲孔222可藉由雷射鑽孔以實 現較高密度。於晶 載體基板220之底面提供多個焊錫球226。fcbga 封裝200允許細封賴減之設計，對於#前或未來高速網路及數 位電視系統而言，高P㈣裝崎度是理想的。例如，為了轉信號完 整性，該縣具有低電感、齡電植及阻抗匹配之特點。 然而，傳統覆晶技術面臨基板上之凸塊間距限制的挑戰。另外， 高性能FCBGA封裝因昂貴的晶片載體基板（典型的晶片載體基板包 含1削層構建材料或更多層構建材料）而價格不菲。由於覆晶技術 201142998 之發展與凸塊間距縮小遠比裸晶縮小與接腳數目之增長慢得多，因 此基板之凸塊間距成為覆晶線路圖的瓶頸所在。即便未來裸晶縮小 將超越基板制之凸制轉減_小。為了歧雜術差距，石夕 中介層(silicon interposer)技術與石夕晶貫通穿孔(動喻別⑽他， TSV)技術是目前唯一且昂責的解決方案。因此，產業界強烈需求一種 改進型覆晶封裝技術’赠合成本效益鱗絲板上之凸制距限制。 【發明内容】 有鑑於此’特提供以下技術方案： 本發明實施例提供-種系統級封裝，包含··封裝載體，具有上表 面及下表面，第-轉體裸晶，包含裸晶面與裸晶邊緣，第—半 裸晶倒置於封賴體之上表面，其中，裸晶面上設議接合焊塾· 第二半導體稞晶’設置於與第―半導體裸晶相鄰之封輯體之上 佈線層結構，位於铸體裸晶與縣紐⑼，重 新佈局金屬層，其申，重新佑片冬凰恳忐 、，、口構13重 緣.以及W # / 至少—部分Μ於裸晶邊 緣，以及夕個凸塊，排佈於重佈線層結構之上，多 載體電性連接於㈣體裸晶。 關彳將封襄 本發明實施啦提供—_、統級封裝，包含：域龍， 表面及下絲；外—級裝置，包含設置於封域體之上表面f 第-半導體稞晶；第二半導體裸晶，設置於封 之 w卿’靖 間。或加以膠餅，用以包覆外擴晶圓級裝置。 之 201142998 本發明實施則提封裝，包含 =面;外擴晶圓級裝置，包含設置於封裝二 外擴明圓級裝置相鄰；以及賴，用吨覆外擴晶圓級裝置，以及膜 餅也用以填充封裝紐與賴晶®級裝置間之空隙。 乡 本發明實施例另提供一種系統級封裝，包含：第一半導 =裸=與稞晶邊緣，第一半導體裸晶倒置於封裝載體之上表二 體多個接合焊塾；第二半導體裸晶，設置於封裝載 裸曰盘與外擴級錢相鄰；重佈線層結構，位於半導體 =與封輯體之間，4佈線層結構包含麵佈局金屬層，其中，重 :==:::::裸晶_ 焊锡球，⑽基板之下表Γ紐·料導縣晶；以及多個 7树日柯有崎決職技射基紅之凸制距 碭，達到較佳之成本效益。 【實施方式】 的元利範圍當中使用了某些詞彙來指稱較 <〒八有通吊知識者應可理解，硬體製造商可能备用 的元件。本說明書及後續的申請專利範圍:不 異來作魏分树的方式，而糾元件在功能上的差異年 201142998 作為區分的準則。於通篇說明書及後續的請求項當中所提及的「包含」 係為一開放式的用語，故應解釋成「包含但不限定於」。另外，「耦接」 一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述 一第一裝置耦接於一第二裝置，則代表該第一裝置可直接電氣連接於 該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝 置。 ’ 本發明有關於應用於具有多個接腳數目之覆晶封裝，本發明提供 的覆b日封裝可包含晶圓級封裝(Wafer-Level Packaging，以下簡稱WLP) 技術。晶圓級封裝指於晶圓級別的封裝積體電路，不同於晶圓切割後 先將每個獨立單元封裝再進行組合之傳統處理。由於WLp最後的封裝 實際上與裸晶具有相同之尺寸’因此，WLp實質上係晶片級封裝 (Chip-ScalePackaging，CSP)技術。此外，晶圓級封裝為晶圓級製程整 合、封裝、測試及燒入作準備，並為從矽開始到客戶出貨之製程實現 最終流線化(streamlining)操作提供便利。 本發明利用WLCSP技術並於晶片上外擴小間距之接腳或凸塊， 以便外擴接合焊墊滿足當前之覆晶處理之最小間距需求。封裝载體用 以機械支持外擴重佈線層結構，該重佈線層結構具有超過三百個外擴 接合焊塾。 第3圖所示為依據本發明之一實施例之外擴WLp(fan_〇ut⑽知 level package) la之截面示意圖。如第3圖所示，該外擴^^ la包含 半導體裸晶10及膠體16，其中，膠體16包覆(encapsulate)半導體裸晶 201142998 ίο之一部分，例如，半導體裸晶10之整個表面，除形成接合焊墊u 之裸晶面外，均被膠體16所包覆。以及’直接於該裸晶面上及膠體 16之部分表面上提供重佈線層結構12。 重佈線層結構12包含一改道金屬層，該重新佈局金屬層重新分佈 位於半導體裸晶10之裸晶面上之多健合焊墊丨卜以形成位於絕緣 層上之多個外擴接合焊墊15。織，焊錫球14 _於多個接合焊塾 15。若第3圖之該外擴WLP丨禮用覆晶技術直接設置於印刷電路板 (Printed Circuit Board，PCB)上’例如，典型的 Fccsp 需要 〇 5職之 球間距_ piteh)P ’ _外擴WLP la之敎焊錫球數目限制在3〇〇 或更少。 第4圖所示為製造第3圖所示之外擴WLP la之典型步驟之流程 圖。外擴WLP la可經由如下幾個步驟製造： 王 步驟52 :晶圓切割與分離。 步驟54 :晶圓重新配置。 步驟56 :重新分佈。 步驟58 :植入球及封裝分離。 可以理解，外擴WLP la可經由其他方法來製造。使用重新分佈 技術之不同公概科同·及纽來製造外擴WLp。但是，所 現步驟大致相同。 而貫 與傳統晶1]製造處理概，重新分佈層及凸塊技術增加—個 的步驟’即在位於晶圓上之每個元件（例*晶片）上沉積(dep〇sit)多蜃 201142998 薄膜金屬重新佈局及互連系統。該額外步驟係在元件本身製造中使用 類似並兼各光刻(photoHth〇graphy)及薄膜沉積(thin dep〇siti〇n)技術 來實現的。互連之額外位準(additi〇nallevd)將每個晶片之週邊多個接 墊重新分佈至多個凸塊底墊(uncjerbump Metal，以下簡稱UBM) 焊墊之區域陣列。該多個凸塊底墊焊墊最終配置於晶片表面之上。多 個焊錫球或多個凸塊用於將晶片連接至應用電路板，實質上，該多個 烊錫球或多個凸塊位於這些凸塊底墊焊墊（例如外擴接合焊墊之 上。 舉例來說’覆蓋(put over)晶圓之第一層用來封裝該元件，該第一 層通常為基於苯並環丁烯(benzocyclobutane，以下簡稱BCB)之聚合物 電介質(polymerdielectric)，用以將元件電路與重佈線系統(例如，重佈 線層結構)相隔離。重佈線金屬層(rewiringmetamzati〇nla_通常為銅 (Cu)、紹(A1)或特別製造之合金，該重佈線金屬層沉積於該電介質上。 接著，該重佈線金屬層被另一 BCB電介質所覆蓋，該另一 BCB電介 質作為防焊緣漆(solder mask)。然後，凸塊底墊覆蓋實質上由多個焊錫 球占據之位置。當凸塊底墊附著該多個焊錫球後，使用覆晶技術將外 擴WLP設置於電路板上。 第5圖所示為依據本發明之另一實施例之覆晶封裝丨之截面示意 圖。如第5圖所示，覆晶封裝！包含半導體裸晶1〇，半導體裸晶ι〇 倒置於封裝載體20之上表面(chip side)20a。例如，封裝载體2〇為一 封裝基板，該封裝基板包含金屬佈線層22a和金屬佈線層22b，金屬 201142998 佈線層223和金屬佈線層22b分別排佈於上表面2〇a及下表面(opposite Side)2〇b。金屬佈線層和金屬佈線層細透過多個導通物綱 thr〇Ughh〇le)124彼此互連，依據本發明，多個導通孔124、經由機械式 鑽孔方法形成於封裝載體2时。此外，可以理解，域載體2〇可包 含多層金屬佈線層，例如四層或六層。在另—實施例中，封體加 可為導線架。 本發明之優點包含，相比雷射·封裝載體（如第2圖所示之晶 片載體基板22〇)，由於藉由應用機械式後之封輯體加，因此， 印刷電路板製作成本可大幅降低。另外，如第3圖所示之原始外擴 對I/O接腳數目有限制（一般情況下少於·個）。本實施例可 突破這個限制。 如第5圖所示，半導體裸晶1〇可以為重新分佈之多接腳數目晶 片，例如，具有超過30(Μ固！/〇接腳。藉由舉例之方式，覆晶封裝i 特別適用於至少5GG_接腳數目之晶片。典型地，對於這樣的多 =數_，咖㈣㈣基板與酬層構建材料㈣wu贼 ^的妙巾㈣之合併是何贱的。本㈣之該實麵可使得如此 叩貝的晶片載體基板與1+2+1層構建材料或昂責㈣中介層之消 曰”本實關細目關之-鱗徵在於，直接在半補^日1〇之裸 曰二上提供至少-織佈線騎構12，錢膠體16包覆半導體裸晶 1〇之-部分，例如，轉體裸晶10除形成多個接合焊塾u外之全雜 12 201142998 表面。依據本發明之實施例，重佈線層結構12包含絕緣層12a、重新 佈局金屬層12b及防焊層(solder resist iayer)12c。重新佈局金屬層 -之至少一部分（如數字標號13所指示）凸出了裸晶邊緣1〇a。也就是， 重新佈局金屬層12b橫向延伸出了膠體16之表面，膠體16實質上與 裸晶面10b共面，其中，多個接合焊塾^形成於裸晶面⑽之上。 重新佈局金屬層12b重新分佈設置於半導體裸晶1〇之裸晶面上之 多個接合焊塾U，以在絕緣層仏上形成多個外擴接合焊塾^，從而 突破基板上之凸塊間距限制。值得注意的是，多個外擴接合焊塾Μ 可具有不同類型與選擇，本發明之範圍並不以此為限。上述「在絕緣 層仏上」在此指多個外擴接合焊墊15排佈於絕緣層12a之表面以 及，例如，當絕緣層12a沉積後形成該多個結合焊墊15。 本發明之實施例可解決_晶尺寸小㈣致之p凸塊間距限制 之問題，這是由於重佈線層結構12於晶圓處理及製造期間形成，因 此’重佈線躲構12提供—更具彈性之間距尺度。相應地，由於重佈 線層結構12之外擴結構，增加了最大焊墊數目。 半導體裸晶10透過重新佈局金屬層12b及多個輝點凸塊μ電性 連接至封裝載體2〇,其中多個焊點凸塊14排佈於重佈線層結構^中 t之多個外擴接合焊墊15之上。焊點凸塊14可包含共晶（例如， 〇S〇. 7〇/〇Pb)^,〇L(,^,95〇^ .。g)成分。依據本發明之實施例，多個焊點凸塊Μ間之凸塊間 距P!大致為咖在下表面2Gb，多辦錫球％之球間距& 13 201142998 大致為0.4-1.0賺，例如，Fccsp使用之電路板。 覆晶凸塊有多種處理方法。以焊點凸塊為例，仙河經由蝕刻 (sputtering)、鑛詹(plating)或類似方式設置於接合焊墊之上。設置顶撾 之處理移除了接a 4墊上之保護氧化層(卩㈣㈣㈣⑽他㈣句，並定 義了焊錫_區域。接著，焊錫可經由適當之方法沉積於之上， 例如蒸心電鑛、電極網印或針孔沉積(needle-dep〇siting)等。 凸塊裸日日1〇經由焊點回焊(s〇ider ren〇w)附著於封裝載體2〇 ，上。此後’底膠30添加於重佈線層結構12與封裝載體2〇之間。底 膠30可為特別設計之環氧化物(ep〇xy)，用以填充重佈線層結構^盘 封裝載體20之間的空隙，並包覆多個焊點凸塊14。該設計用於控制 因半導體裸晶10與封裝載體2〇間之熱膨脹差而導致之焊接結合處之 壓力。-旦固化’則底膠3〇吸收壓力，從而降低多個焊點凸塊Μ上 之壓力，進而延長最終封裝之壽命。 ‘万面 ”U封裝（如覆晶封裝1)包含半導體裸晶1〇、 體16及重新分佈層（例如’重佈線層結構12)，其中於 晶^之裸晶面上具有多個接合焊㈣，雜16包覆半導體裸晶1〇 之4刀’以及重新分佈層覆蓋該裸晶面及膠體16之一部分 新分佈。該妹分佈層外擴多個接合 u。多個凸塊Μ於 =半導體晶片封裝更包含基板（如封裝載體= 基板包含金屬佈線層仏與金屬佈線層细 “ 佈線層辦難似㈣㈣面·。㈣咖4;= 201142998 表面2〇a之上。焊錫球24排佈於基板（如封裝載體2〇)之下表面娜。 -㈣2方面’半導體晶片封裝（如覆晶封裝υ包含雖载體2〇, 封裝载體20包含金屬佈線層22a與金屬佈線層创，金屬佈線層瓜 與金屬佈_ 22b分別排佈於封裝載體2〇之上表面2〇a與下曰表面 滿。外擴晶圓級裝置（例如，外擴WLpia)設置於封裝載㈣之上 表面20a。底膠30應用於封裝體在2〇與外擴晶圓級裝置之間。 對於多接腳數目之晶片，為了降低覆晶封裝方案之成本，本發明 =實施例錢具有成本競爭力之包含兩層金屬佈線層、機械式鑽孔之 基板（例如，封裝載體20)，來取代造價較高的方法，例如，多 數目晶片中使科貴_中介層。本發明之實施例之特徵包含於裸晶 面上直接提供重佈線層結構U。重佈線層結構^之重新佈局金屬層 ⑶重新分佈位於該裸晶面上之多個接合焊塾u，並形成多個外擴^ 合焊塾15，從而突破WLP中基板上之凸塊間距限制。 、 第6圖所示為依據本發明之另—實施例之覆晶封裝2之截面示音 圖’其中，_之數字標號代表類似之層、元件或區域。如第6圖戶^ 不’覆晶封裝2具有與第5騎示之覆晶封们極其相似之結構，所 不同之處包含經由移除膠體16之一部分，露出了與裸晶面⑽相對之 底^，使得膠體16之頂面16a與底祿齊平。於半導體裸晶1〇 ，路出之絲1〇C之上可設置外部散熱槽㈣_丨_雄。經由此 操作’提向了散熱效率。當然，如第6圇 — 輿" 千“、Μ 6圖所不之外部散熱槽2a僅用以 舉例.况明，鋪肋限林發明之變戦其他軸方法。也就是說， 15 201142998 之'、他類型之散熱襄置，也可應用於 玎適當設置於露出之底面i〇c 本實施例。 第7圖所示為依縣㈣之另—實施例之覆 立 圖’其中’ _街標嶋_導峨 :不=，=封裝3具有類似於第5圖所示之二之： 所不同之處包含露出了與裸晶面娜相對之底 由移除膠體16之一上半部分而#山& 坻面l〇c係經 上與底面1〇c齊二使得膠體16之頂面-實質 _ ^ a 3 (heat-spreading layer)3a > 3a 1〇c^16；^ =騎4錄本發明之另—實施例之覆晶封裝4之截面示意 -霜曰娜目同之數子標號代表類似之層、元件或區域。如第8圖所 不^：： 有類似於第5 _示之覆晶封裝1之結構，所不同 之編露出了與裸晶面相對之底錄。底面收係經由移除 或切除膠體16之-上半部分而露出，使得膠體16之頂面⑹實質上 與底面收齊平。於露出之底面收之上設置散熱遮罩師㈣邮 hd)302。當設置散熱遮罩3()2之前，可將散熱__hermai 神=置於露出之底錄之上。在另一實施例中，散熱遮罩3〇2 可直接與路出之底面10c相接觸。 第9圖所示為依據本發明之另-實施例之覆晶封裝5之截面示意 圖’其中’相同之數字標號代表類似之層、元件或區域。如第9圖所 201142998 ，，，5具有_於第5 _示之覆晶封裝】之結構，所不同 路出了與裸日日面1〇b相對之底面他。底面I%係經由移除 2除膠體16之-上半部分*露出，使得雜16之頂面⑹實質上 7底面_平。覆晶封裝5包含遮科導縣晶ω之—單體、血縫 =熱片㈣啊ade樣。同樣地，當設置散熱請之前 2層州應用於露出之底綠之上。在另一實 搬可直接與露出之絲1〇c相接觸。 此，、、迟罩 圖：:之截面示意 _覆曰目子標號代表類似之層、元件或區域。如第10圖所 不’覆晶封裝6具有類似於坌s圍& _ _ 之處包含露出了與裸晶面10b相對=1之結構，所不同 或切除鮮❹一 W 底面10c係經由移除 鱼广〆 半部分而露出’使得膠體16之頂面16a實質上 ^ 6 10 _ /斤7^ ’散熱片500包含支架观與遮罩5〇4兩部分。 面;〇c之熱二402之前’可將散熱膠層304應用於露出之底 接觸。 例中，遮罩5〇4可直接與露出之底面敗相 «, 1ίι ”相同之數子標號代表類似之層、元件或 =個::凸塊14之凸塊_大，因此，在丄= …目膠餅㈣mg刪p()und)_包覆外擴wLp以， s 17 201142998 並填充重佈線層結構I2與封裝載體2〇之上表面2〇a間之空隙⑽， 從而形成晶片、級無底膠覆晶封裝(moId_onlyflip_chipcsp)。、 第12圖所示為依據本個之另—實施例之覆晶封裝8之截面示音 圖，其中，相同之數字標號代表類似之層、元件或區域。如第η圖^ 不，為了露出與裸晶面1Gb相對之底面1Qe，移除或切除了膠餅_ 之上半部分與膠體16之上半部分。膠體16之頂面收實質上與底面 l〇c齊平。於底面l〇c之上設置外部散熱槽2a。 第13圖所示為依據本發明之另—實施例之系統級封裝 (SyStem_in_PaCkage ’以下簡稱為卿，之截面示意圖，其中，相同之 數字標號代表類似之層、元件或區域。如第13圖所示，灿ι，包含第 5圖中所不之外擴WLP la與半導體裸晶1()，，其皆為設置於封裝載體 20之上表面20a上之覆晶。根據本實施例’外擴驗&金半導體裸 晶職此水侧目置。細，射轉，於不麟本發鴨神之 情況下，，亦可細裸晶之其爾•卜舉例而言外擴wLp h可為設 置於與半導體裸晶10,相鄰之上表面2〇a上之覆晶，交錯排列但不必並 行排列。絲則於封裝鐘_外擴WLP la之間。底膠30,用於 封裝載體20與半導體裸晶1〇,之間。 外擴WUMa可包含第5圖中所示之所有特徵。舉例而言，外擴 剔&可_地包含轉體裸晶⑴，輸裸晶關_裝載體 +麗你二” 如封裝**體2(3為—封震基板，該封裝基板包含 金屬佈線層a和金屬佈線層既，金屬佈線層瓜和金屬佈線層现 201142998 分別排佈於上表面2Ga及下表面2Gb。金屬佈線層仏和金屬佈線層 22b透過多個導通孔m彼此互連，依據本發明，多個導通孔以經 由機械式鑽孔方法形成於封裝載體2〇中。此外，可以理解，封裝载體 20可包含錢金屬佈線層，例如四層或六層。半導體裸晶⑴可以為 重新分佈之多接腳數目晶片’例如，具有超過個PO接腳。 直接在半賴裸晶10之裸晶面上提供至少一個重佈線層結構 12 ’以及膠體16包覆半導體裸晶1〇之一部分，例如，半導體裸晶 上之接合焊塾間距小於（因此不符合）封裝載體2〇之上表面如&上要 求之凸塊間距删。舉辆言，半導體裸晶1G之裸晶面上之接合焊塾 間距11之接合焊墊間距可處於G 13_G 15醒⑽七⑴叫之範圍。依據 本發明之實施例，重佈線層結構u包含絕緣層以、重新佈局金屬詹 12b及防焊層以。重新佈局金屬層⑶之至少一部分（如數字標號 U所指示）凸出了裸晶邊緣收。也就是，重新佈局金屬層⑶橫向 延伸出了膠體16之表面，膠體16實質上與裸晶面共面，其中， 多個接合焊墊11形成於裸晶面l〇b之上。 ” _重新佈局金屬層12b重新分佈設置於半導體裸晶1〇之裸晶面上之 =個接合焊塾11 ’以在絕緣層12a上形成多個外擴接合焊塾丨5，從而 大皮基板上之凸塊間距限制。值得注意的是，多個外擴接合焊塾Μ 可具有不_型與選擇，本發明之範圍並不以此為限。上述「在絕緣 層12a上」在此指多個外擴接合焊墊15排佈於絕緣層12a之表面以 及例如，當絕緣層12a沉積後形成該多個結合焊塾Μ。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor packaging technology, and more particularly to at least one 曰-ChiP package and a semiconductor chip package, which can be applied to a plurality of pins (four) = situation. [Prior Art] In the art, in order to dispose the die on the substrate, it can be realized through a plurality of bonding pads located on the die and the substrate, in which various chip packaging technologies such as a ball grid can be applied. Grid (Ball Grid Array 'BGA), wire bonding, flip chip, etc. In order to ensure the miniaturization and versatility of electronic products or communication devices, semiconductor packages require small size, multiple pin connections, high speed, and versatility. The increase in the number of input-output (Input-Output ' I/O) pins and the increase in high-performance busy demand have contributed to the development of flip chip packaging technology. The flip chip technology is directly interconnected with the package media using a plurality of bumps located on the wafer. The wafer faces the packaged media through the shortest path. This technology can be applied not only to single-chip packages, but also to larger-sized packages with higher integrated levels and more sophisticated substrates that can accommodate several wafers to form larger functional units. The flip chip technology uses an area array that has the advantage of achieving the highest interconnect density with the package and the lower interconnect inductance of the package. FIG. 1 is a schematic cross-sectional view showing a conventional wafer level flip chip package (Fifp_chip Chip Scale Package, hereinafter referred to as FCCSP). As shown in FIG. 1, the FFCSp movement 201142998 includes a die 101, and the die 101 is face_down on the upper surface of the carrier 120 (t〇p surface) and is connected to the solder bump l〇2 through a plurality of solder bumps Vector 12〇. A plurality of solder balls 122 are provided on the bottom surface of the carrier 120 for connecting the circuit boards. Typically, the package construction uses a eutectic tin/lead flip-chip interconnect technique in a regional array or peripheral bump arrangement to replace the standard wire bond interconnect. Due to the elimination of the line bonding loop, the connection inductance to the bare crystal is low, and at the same time, the increase in routing density optimizes the electrical path of the critical high frequency signal line. Figure 2 shows a schematic diagram of a conventional flip-chip ball grid array (Flip_Chip _ Gri (hereinafter referred to as FCBGA) package. As shown in Figure 2, the fcBGA package 200 contains bare crystal 201, and the bare crystal 201 is inverted. The wafer carrier substrate 22G is connected to the upper surface of the wafer carrier substrate 22 through a plurality of defect bumps 202. The underflili 2〇3 fills the gap between the bare crystal 201 and the top surface of the wafer carrier substrate 22A. The wafer carrier substrate 22 can include a plurality of traces, and different layers of the plurality of traces are connected to each other through a blind via (bUnd) 222 or a buried via 224. For example, the blind via 222 can be used. Laser drilling to achieve higher density. A plurality of solder balls 226 are provided on the bottom surface of the crystal carrier substrate 220. The fcbga package 200 allows for a fine-grained design, for the #前前 or future high-speed network and digital television systems, High P (four) bulk is ideal. For example, for signal integrity, the county has the characteristics of low inductance, age electroplating, and impedance matching. However, traditional flip chip technology faces the challenge of bump spacing limitations on the substrate. , high performance FCBGA package due to expensive crystal The chip carrier substrate (a typical wafer carrier substrate contains 1 layer of building material or more layers of building materials) is expensive. Due to the development of flip chip technology 201142998 and the reduction of bump pitch is much smaller than the shrinking of the die and the number of pins. It is much slower, so the bump pitch of the substrate becomes the bottleneck of the flip-chip wiring diagram. Even if the shrinkage of the die in the future will exceed the convexity of the substrate, the _ small. For the difference of the dissimilarity, the silicon interposer Technology and Shi Xijing through-hole perforation (Metaphorus (10), TSV) technology is currently the only and blame solution. Therefore, the industry is strongly demanding an improved flip chip packaging technology 'gift synthetic benefit scale board The present invention provides a system-level package, including a package carrier having an upper surface and a lower surface, and a first-rotating body, Including the bare crystal surface and the bare crystal edge, the first-semi-naked crystal is placed on the upper surface of the sealing body, wherein the bonding surface is disposed on the bare crystal surface, and the second semiconductor twin crystal is disposed on the first semiconductor layer The wiring layer structure on the adjacent body of the bare body is located in the bare metal of the casting body and the county (9), re-laying the metal layer, and its application, re-save the winter phoenix, and the 13-edge of the mouth structure. W # / at least—partially adjacent to the edge of the bare crystal, and the bump of the outer layer, arranged on the structure of the redistribution layer, and the multi-carrier is electrically connected to the die of the (four) body. _, unified package, including: domain dragon, surface and underwire; external-level device, including surface f-semiconductor twin on the surface of the domain; second semiconductor die, set in the seal of the w' Jing or a rubber cake to cover the expanded wafer level device. 201142998 The present invention implements a package, including a surface; an externally expanded wafer level device, which is disposed adjacent to the encapsulation and expansion device of the encapsulation; and a device for coating the wafer level with a ton of overwrap and a film cake It is also used to fill the gap between the package and the Lai King® device. The embodiment of the present invention further provides a system-level package, comprising: a first semiconductor = bare = and a twinned edge, the first semiconductor die is placed on the package carrier, and the plurality of bonding pads are formed on the package carrier; the second semiconductor is bare The crystal is disposed adjacent to the packaged bare disk and the external expansion level; the redistribution layer structure is located between the semiconductor=and the package body, and the 4 wiring layer structure comprises the surface layout metal layer, wherein: weight:==:: :::Small crystal _ solder ball, (10) under the substrate, Γ ···························································· [Embodiment] Some vocabulary is used in the Yuanli range to refer to the components that the hardware manufacturer may reserve. The scope of this specification and the subsequent patent application: the method of Wei branching, and the difference in function in the year 201142998 as the criterion for differentiation. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Thus, if a first device is coupled to a second device, it is meant that the first device can be directly electrically coupled to the second device or indirectly electrically coupled to the second device through other devices or connection means. The present invention relates to a flip chip package having a plurality of pin numbers, and the b-day package provided by the present invention may comprise a Wafer-Level Packaging (WLP) technology. Wafer-level packaging refers to a package-level integrated circuit at the wafer level, which is different from the traditional processing of combining individual cells in a separate package after wafer dicing. Since the final package of WLp is actually the same size as the die, WLp is essentially a Chip-Scale Packaging (CSP) technology. In addition, wafer-level packaging prepares wafer level process integration, packaging, testing, and burn-in, and facilitates streamlining operations from start-up to customer shipment. The present invention utilizes WLCSP technology and externally spreads small pitch pins or bumps on the wafer so that the outer spread bond pads meet the minimum pitch requirements of current flip chip processing. The package carrier is used to mechanically support an outer expanded wiring layer structure having more than three hundred expanded joint pads. Figure 3 is a cross-sectional view showing the expansion of WLp (fan_〇ut(10) know level package) la according to an embodiment of the present invention. As shown in FIG. 3, the external expansion includes a semiconductor die 10 and a colloid 16, wherein the colloid 16 encapsulates a portion of the semiconductor die 201142998, for example, the entire surface of the semiconductor die 10, The outside of the bare crystal face forming the bonding pad u is covered by the colloid 16. And providing a redistribution layer structure 12 directly on the bare face and a portion of the surface of the colloid 16. The redistribution layer structure 12 includes a redirected metal layer that redistributes a plurality of bonding pads on the bare crystal face of the semiconductor die 10 to form a plurality of extended bonding pads on the insulating layer 15. Weaving, solder balls 14 _ for multiple bonding pads 15 . If the externally extended WLP 丨 ritual flip chip technology of Figure 3 is directly placed on a Printed Circuit Board (PCB) 'for example, a typical Fccsp requires a ball pitch of 5 positions _ piteh) P ' _ external expansion The number of solder balls in WLP la is limited to 3 inches or less. Figure 4 is a flow chart showing the typical steps for fabricating the WLP la as shown in Figure 3. The externally expanded WLP la can be fabricated through the following steps: King Step 52: Wafer cutting and separation. Step 54: Wafer reconfiguration. Step 56: Redistribution. Step 58: The implant ball and the package are separated. It will be appreciated that the flared WLP la can be fabricated via other methods. Use the different distributions of the redistribution technology to create a WLp. However, the steps are roughly the same. And the conventional crystal 1] manufacturing process, the redistribution layer and the bump technology add one step - that is, depositing (dep〇sit) more than 201142998 film on each component (eg * wafer) located on the wafer Metal re-layout and interconnection system. This additional step is accomplished using similar and photolithography and thin film deposition techniques in the fabrication of the component itself. The additional level of interconnection (additi〇nallevd) redistributes multiple pads around each wafer to an array of regions of uncjerbump metal (UBM) pads. The plurality of bump pad pads are ultimately disposed over the surface of the wafer. A plurality of solder balls or bumps are used to connect the wafer to the application circuit board. In essence, the plurality of solder balls or bumps are located on the bump pad pads (eg, over-extension bonding pads) For example, the first layer of the 'put over' wafer is used to encapsulate the element. The first layer is usually a polymer dielectric based on benzocyclobutane (BCB). To isolate the component circuit from the rewiring system (eg, the redistribution layer structure). The rewiring metal layer (rewiringmetamzati〇nla_ is usually copper (Cu), sho (A1) or specially manufactured alloy, the redistribution metal layer Deposited on the dielectric. Next, the redistributed metal layer is covered by another BCB dielectric as a solder mask. Then, the bump bottom pad covers substantially a plurality of solder balls When the bump bottom pad is attached to the plurality of solder balls, the epitaxial WLP is disposed on the circuit board by flip chip technology. FIG. 5 is a flip chip package according to another embodiment of the present invention. Schematic diagram of the cross section. 5, the flip chip package includes a semiconductor die 1 , and the semiconductor die 〇 is placed on the chip side 20a of the package carrier 20. For example, the package carrier 2 is a package substrate, and the package substrate The metal wiring layer 22a and the metal wiring layer 22b are included, and the metal layer 201142998 wiring layer 223 and the metal wiring layer 22b are respectively arranged on the upper surface 2a and the opposite side 2b. The metal wiring layer and the metal wiring layer are finely permeable. A plurality of vias thr〇Ughh〇) 124 are interconnected with each other. According to the present invention, a plurality of vias 124 are formed by the mechanical drilling method on the package carrier 2. Further, it can be understood that the domain carrier 2 can include A multilayer metal wiring layer, such as four or six layers. In another embodiment, the package may be a lead frame. Advantages of the present invention include, compared to a laser package carrier (such as the wafer carrier shown in FIG. 2) The substrate 22 〇), because the mechanical package is applied, the manufacturing cost of the printed circuit board can be greatly reduced. In addition, the original expansion as shown in Fig. 3 limits the number of I/O pins. (In general, less than one). This embodiment can overcome this limitation. As shown in FIG. 5, the semiconductor die 1 can be a redistributed multi-pin number of wafers, for example, having more than 30 (tamping!/〇 pins. By way of example The flip chip package i is particularly suitable for wafers having a number of pins of at least 5 GG_. Typically, for such a multi-number _, the combination of the coffee (four) (four) substrate and the layer construction material (four) wu thief ^ (four) is what. The solid surface of (4) can make the wafer carrier substrate of such a mussel and the 1+2+1 layer construction material or the dissatisfaction of the (4) intermediation layer. At least 1 woven wiring structure 12 is provided on the naked cymbal 2, and the carbon colloid 16 is coated with a portion of the semiconductor bare crystal. For example, the rotating bare crystal 10 is formed by a plurality of bonding dies. 12 201142998 Surface. According to an embodiment of the present invention, the redistribution layer structure 12 includes an insulating layer 12a, a redistribution metal layer 12b, and a solder resist iayer 12c. Re-layout of the metal layer - at least a portion (as indicated by numeral 13) protrudes from the bare edge 1〇a. That is, the rearranged metal layer 12b extends laterally beyond the surface of the colloid 16, and the colloid 16 is substantially coplanar with the bare face 10b, wherein a plurality of bond pads are formed over the bare face (10). The redistribution metal layer 12b redistributes a plurality of bonding pads U disposed on the bare surface of the semiconductor die 1 to form a plurality of external bonding pads on the insulating layer, thereby breaking the bumps on the substrate Spacing limit. It should be noted that a plurality of external expansion joints may have different types and options, and the scope of the present invention is not limited thereto. The above "on the insulating layer" herein means that a plurality of expanded bonding pads 15 are arranged on the surface of the insulating layer 12a and, for example, the plurality of bonding pads 15 are formed after the insulating layer 12a is deposited. Embodiments of the present invention address the problem of small p-block pitch limitations due to small crystal size, since the redistribution layer structure 12 is formed during wafer processing and fabrication, so the 'rewiring evasion 12 provides - more The distance between the elastic scales. Accordingly, the maximum number of pads is increased due to the expanded structure of the redistribution layer structure 12. The semiconductor die 10 is electrically connected to the package carrier 2 through the re-layout metal layer 12b and the plurality of bump bumps μ, wherein the plurality of solder bumps 14 are arranged in the rewiring layer structure. Bonded to the solder pad 15 above. Solder bumps 14 may comprise eutectic (eg, 〇S〇. 7〇/〇Pb)^, 〇L(,^, 95〇^.g) components. According to an embodiment of the present invention, the bump pitch P! between the plurality of pad bumps is substantially 2Gb on the lower surface, and the ball pitch of the ball is more than 0.4-1.0, for example, Fccsp The board used. There are many ways to treat flip chip bumps. Taking solder bumps as an example, the Xianhe is placed on the bonding pads via sputtering, plating, or the like. The treatment of the top Laos removes the protective oxide layer on the a 4 pad (卩(4)(4)(4)(10) he (4) sentence and defines the solder_region. Then, the solder can be deposited on the appropriate method, such as steam core, electrode Screen printing or needle-hole deposition (needle-dep〇siting), etc. The bumps are barely attached to the package carrier 2〇 by solder joint reflow (s〇ider ren〇w). Thereafter, the primer 30 is added. Between the redistribution layer structure 12 and the package carrier 2A. The primer 30 may be a specially designed epoxide (ep〇xy) for filling the gap between the redistribution layer structure and the package carrier 20, and Covering a plurality of solder bumps 14. The design is used to control the pressure at the solder joint due to the difference in thermal expansion between the semiconductor die 10 and the package carrier 2. When the curing is performed, the primer 3 〇 absorbs the pressure, thereby Reduces the stress on the bumps of multiple solder joints, thereby extending the life of the final package. 'Wan-faced' U packages (such as flip-chip package 1) contain semiconductor die 1 , body 16 and redistribution layers (eg 'rewiring Layer structure 12), wherein there are a plurality of bonding welds (4) on the bare crystal face of the crystal, 16 coated semiconductor bare die 1 ' 4 knife 'and redistribution layer covering the bare face and a part of the new distribution of the colloid 16 . The sister distribution layer is extended by a plurality of joints u. A plurality of bumps Μ = semiconductor wafer package It also includes a substrate (such as a package carrier = a substrate including a metal wiring layer and a metal wiring layer). The wiring layer is difficult to be (4) (four) surface. (4) Coffee 4; = 201142998 The surface is 2〇a. The solder balls 24 are arranged on the substrate ( For example, the package carrier 2 〇) under the surface Na. - (4) 2 aspects 'semiconductor chip package (such as flip chip package υ includes carrier 2 〇, package carrier 20 includes metal wiring layer 22a and metal wiring layer, metal wiring layer melon And the metal cloth _ 22b is respectively arranged on the surface 2〇a and the lower surface of the package carrier 2〇. The externally expanded wafer level device (for example, the externally expanded WLpia) is disposed on the upper surface 20a of the package carrier (4). 30 is applied between the package and the external wafer-level device. For a multi-pin number of wafers, in order to reduce the cost of the flip-chip packaging solution, the present invention is a cost-competitive two-layer metal. Wiring layer, mechanical drilling substrate ( For example, the package carrier 20) is substituted for a more expensive method, for example, a multi-number wafer is used to make a valuable layer. The features of embodiments of the present invention include directly providing a redistribution layer structure U on a bare crystal plane. The redistribution metal layer (3) of the wiring layer structure redistributes a plurality of bonding pads u on the bare surface, and forms a plurality of outer bonding pads 15, thereby breaking the bump spacing limitation on the substrate in the WLP. Figure 6 is a cross-sectional view of a flip chip package 2 according to another embodiment of the present invention. Wherein, the numeral number of _ represents a similar layer, element or region. The crystal package 2 has a structure very similar to that of the fifth crystal chip, except that a portion of the colloid 16 is removed, and the bottom surface opposite to the bare surface (10) is exposed, so that the top surface of the colloid 16 16a is flush with the bottom. In the semiconductor bare crystal 1 〇, the external heat sink (4) _ 丨 _ male can be set above the wire 1 〇 C. Through this operation, the heat dissipation efficiency is raised. Of course, the external heat sink 2a, as shown in the sixth 囵 舆 quot quot quot 图 图 图 图 图 图 图 图 图 图 图 图 图 图 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部 外部', his type of heat sink, can also be applied to the appropriate surface of the exposed surface i〇c this embodiment. Figure 7 shows the other example of the county (four) - the 'overlay'嶋 峨 峨 不 不 不 不 不 不 不 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装#山& 坻面 l〇c is connected to the bottom surface 1〇c to make the top surface of the colloid 16 - substantial _ ^ a 3 (heat-spreading layer) 3a > 3a 1〇c^16; ^ = riding 4 is a cross-sectional view of a flip chip package 4 of another embodiment of the present invention - the same number of sub-labels represent a similar layer, element or region. As shown in Fig. 8, there is no similar to the fifth _ shows the structure of the flip chip package 1, which is different from the bare crystal face. The bottom surface is exposed by removing or cutting the upper half of the colloid 16 so that The top surface (6) of the colloid 16 is substantially flush with the bottom surface. The heat-dissipating mask is placed on the exposed bottom surface (four) post hd) 302. When the heat-dissipating mask 3 () 2 is set, the heat dissipation __hermai God = It is placed on the exposed bottom. In another embodiment, the heat dissipation mask 3〇2 can be directly in contact with the bottom surface 10c of the road. Fig. 9 is a flip chip according to another embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a schematic view of a similar layer, element or region. As shown in FIG. 9 and 201142998, 5 has a structure of a flip chip package of the fifth embodiment. The bottom surface is opposite to the bare day surface 1〇b. The bottom surface I% is exposed by removing the upper portion of the colloid 16 from the upper portion*6, so that the top surface (6) of the impurity 16 is substantially 7 bottom surface_flat. 5 contains the occultation of the crystal ω - monomer, blood seam = hot film (four) ah like. Similarly, when the heat is set, please apply the two layers of state before the bottom of the exposed green. Contact with the exposed wire 1〇c. This,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Area. As shown in Fig. 10, the flip chip package 6 has a structure similar to 坌s circumference & _ _ including a structure that is opposite to the bare crystal surface 10b, and is different or cut off from the bottom surface 10c. Exposed by removing the half of the fish, the top surface 16a of the colloid 16 is substantially ^6 10 _ / kg 7 ^ 'The heat sink 500 comprises the bracket view and the cover 5 〇 4 two parts. Before the second 402, the heat-dissipating adhesive layer 304 can be applied to the exposed bottom contact. In the example, the mask 5〇4 can directly lose the same as the exposed bottom surface «, 1ίι ”, and the sub-numbers represent similar layers, components or = :: bumps of the bumps 14 _ large, therefore, in the 丄 = ... gelatin cake (four) mg delete p () und) _ wrap outer wLp to, s 17 201142998 and fill the redistribution layer structure I2 and package carrier 2 A gap (10) between the top surface 2〇a of the crucible is formed to form a wafer, graded bottomless flip chip package (moId_onlyflip_chipcsp). Figure 12 is a cross-sectional view of a flip chip package 8 in accordance with another embodiment of the present invention, wherein like numerals indicate like layers, elements or regions. As shown in the figure η, no, in order to expose the bottom surface 1Qe opposite to the bare crystal face 1Gb, the upper half of the cover _ and the upper half of the colloid 16 are removed or cut off. The top surface of the colloid 16 is substantially flush with the bottom surface l〇c. An external heat sink 2a is provided above the bottom surface l〇c. Figure 13 is a cross-sectional view of a system-in-package (SyStem_in_PaCkage', hereinafter referred to as "clear", in which the same reference numerals represent similar layers, elements or regions, as shown in Figure 13. In addition, the light bulb includes the WLP la and the semiconductor bare crystal 1 (), which are all flip-chips disposed on the upper surface 20a of the package carrier 20. According to the present embodiment The test & gold semiconductor bare crystal job this water side of the eye. Fine, shot, in the case of the non-Linben duck god, but also fine bare crystal of the er · b for example, the external expansion wLp h can be set With the semiconductor die 10, the flip-chips on the adjacent upper surface 2〇a are staggered but do not have to be arranged in parallel. The wires are between the package clock and the external WLP la. The underfill 30 is used to package the carrier 20 and the semiconductor. The bare cell 1 〇, the extended WUMa may include all the features shown in Figure 5. For example, the outer tapping & _ can include the rotating die (1), the bare die off _ load +丽你二", such as package ** body 2 (3 is - sealed substrate, the package substrate contains metal wiring layer a and metal wiring The metal wiring layer melon and the metal wiring layer are respectively arranged on the upper surface 2Ga and the lower surface 2Gb in 201142998. The metal wiring layer 金属 and the metal wiring layer 22b are interconnected with each other through the plurality of via holes m, and according to the present invention, a plurality of conduction lines are provided. The holes are formed in the package carrier 2 by mechanical drilling. Further, it can be understood that the package carrier 20 may comprise a money metal wiring layer, such as four or six layers. The semiconductor die (1) may be a redistributed multi-connection. The number of pads wafer 'e.g., has more than one PO pin. Directly providing at least one redistribution layer structure 12' directly on the bare crystal face of the bare die 10 and the colloid 16 overlying a portion of the semiconductor die 1 , for example, a semiconductor The pitch of the bonding pads on the bare crystal is less than (and therefore does not conform to) the surface of the package carrier 2, such as the bump spacing required on the &, in other words, the bonding pitch of the bare die on the semiconductor bare 1G The bonding pad pitch of 11 may be in the range of G 13_G 15 awake (10) seven (1). According to an embodiment of the present invention, the redistribution layer structure u includes an insulating layer to re-lay the metal 12b and the solder resist layer. At least a portion of the new layout metal layer (3) (as indicated by the numeral U) protrudes from the bare edge. That is, the re-layout metal layer (3) extends laterally beyond the surface of the colloid 16, and the colloid 16 is substantially coextensive with the bare surface. a plurality of bonding pads 11 are formed on the bare surface 10b." _Re-layout metal layer 12b is redistributed on the bare surface of the semiconductor die 1 = bonding pads 11' To form a plurality of over-expanding bonding pads 5 on the insulating layer 12a, thereby limiting the pitch of the bumps on the large-skin substrate. It is worth noting that a plurality of externally-expanded bonding pads may have a type and a selection, The scope of the invention is not limited thereto. The above "on the insulating layer 12a" herein means that a plurality of over-expanding bonding pads 15 are arranged on the surface of the insulating layer 12a and, for example, the plurality of bonding pads are formed after the insulating layer 12a is deposited.
S 19 201142998 、半導體裸晶ίο透過重新佈局金屬層12b及多個悍點凸塊μ電性 連接至龍載體20，其中多贿點凸塊14排佈於重佈線層結構^中 定義之多個外擴接合谭墊15之上。焊點凸塊14可包含共晶（例如， 63%Sn. 37〇/〇Pb). , 95〇/〇pb, 2.5〇/〇Ag, 9? 5〇/〇Sn, 2.5%Ag)成分。依據本發明之實施例，多個焊點凸塊μ間之凸塊間 距P1大致為’例如仏⑽職（跡遞m)。在下表面施多個焊 錫球Μ之球間距P2大致為⑷.0mm (5〇〇im)，例如，Fccsp使用 之電路板。 覆晶凸塊有多種處理方法。以焊點凸塊為例，經⑽刻、穿 ^或類似嫌賴娜m請Μ恤㈣了接辦 上之保4乳化層，並定義了焊錫附著區域。接著，焊锡可經由 =沉躲麵之上，例如，蒸發、紐、電娜卩或針孔沉積 專烊點凸塊稞晶10經由焊點回焊附著於封裝載體2〇之上。此後， 添加於重佈線層結構12與封裝載體2G之間，以及底膠30，添 ^半導舰H)，朗繼。_G娜料為特別 =十之環氧化物’用以填充重佈線層結構12與封裝倾Μ之間的空 ^並包覆多個焊點凸塊14。該設計用於控制因半_裸晶⑴盘封 軸體2〇狀觸縣而導狀焊接料紅壓力。—邮化，則底 膠30吸收壓力，從而降低多個焊 ' 封裝之壽命。 點凸塊14上之壓力，進而延長最終 依據本實施例，半導體裸晶1G (或主裸晶）具有超過·個⑽ 20 201142998 接腳。這些多接腳數目裸晶或晶片之範例不應僅限於基頻晶片、射頻 晶片或晶載晶片，而可由例如28nm技術之高級半導體製程製造。依 據本實施例，半導體裸晶10,（或次裸晶）具有小於3〇〇個1/〇接腳。 這些多接腳數目裸晶或晶片之範例不應僅限於電源管理積體電路 (power-management 1C ’ PMIC)。因半導體裸晶1〇,具有較少之J/Q接 腳數目’故應用於半導體裸晶10，與封裝載體2〇之間的凸塊間距p3 (大致上等於轉體裸晶1G，上之接合焊制距）相對較寬鬆。因此， 半導體裸aa 10不〶外擴依據本發明之實施例，凸塊間距Μ或半導 體裸晶10’之裸晶面上之接合焊塾間距可處於ai3 a4mm(跡伽 之範圍。 一立第Η 11所示為依據本發明之另一實施例之系統級封裝广之截面 示意圖’其中’補之數字標號代表類似之層、树或區域。如第Μ Γ，具有與第13圖所示之Sip Γ之所有特徵。第14圖之 f外擴圖之Slp Γ之間的區別在於，於第14圖中，膠餅600包 卜1a、+導體裸晶瓜、以及封裳載體20之部分上表面2η 膠餅6⑻圍繞外擴WLP la之膠體16。請注音Ρ心 可由不同材料製造。 思、膠餅_與膠體16 示音示為依據本發明之另一實施例之系統級咖，”之截面 "，、中，相同之數字標號代表類似之層、 底㈣與3丨。由於多轉點凸塊14之剛/^大=節省了 呢P1增大’因此節省S 19 201142998, the semiconductor bare crystal ίο is electrically connected to the dragon carrier 20 through the re-layout metal layer 12b and the plurality of bump bumps μ, wherein the plurality of brittle bumps 14 are arranged in the plurality of redistribution layer structures The outer expansion is joined to the top of the tan pad 15. Solder bumps 14 may comprise eutectic (e.g., 63% Sn. 37 〇 / 〇 Pb)., 95 〇 / 〇 pb, 2.5 〇 / 〇 Ag, 9 ? 5 〇 / 〇 Sn, 2.5% Ag) components. According to an embodiment of the present invention, the bump pitch P1 between the plurality of pad bumps μ is substantially ', for example, 仏(10) jobs (trace m). The ball pitch P2 of the plurality of solder balls on the lower surface is approximately (4).0 mm (5 〇〇 im), for example, a circuit board used by Fccsp. There are many ways to treat flip chip bumps. Take solder bumps as an example. After (10) engraving, wearing ^ or similar 赖 娜 m Μ ( 四 四 四 四 四 四 四 四 四 四 四 四 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化 乳化Then, the solder can be adhered to the package carrier 2 via solder joints, for example, by evaporation, neon, or neon or pinhole deposition. Thereafter, it is added between the redistribution layer structure 12 and the package carrier 2G, and the primer 30, which is added to the semi-conductor H). The _G nano material is a special = ten epoxide' to fill the space between the redistribution layer structure 12 and the package raking and to coat a plurality of solder bumps 14. This design is used to control the red pressure of the welded material due to the half-bare (1) disk seal shaft body 2. - For postalization, the primer 30 absorbs pressure, thereby reducing the life of multiple solder packages. The pressure on the bumps 14 is further extended. Finally, according to the present embodiment, the semiconductor bare 1G (or main die) has more than one (10) 20 201142998 pins. These examples of multiple pin counts or wafers should not be limited to baseband, RF, or wafer carriers, but can be fabricated by advanced semiconductor processes such as 28nm technology. According to this embodiment, the semiconductor die 10, (or sub-die) has less than 3 〇 1/〇 pins. Examples of these multiple pin counts or wafers should not be limited to power-management 1C 'PMICs. Due to the semiconductor die 1〇, with a small number of J/Q pins, the bump spacing p3 between the semiconductor die 10 and the package carrier 2〇 is substantially equal to the rotating die 1G. The joint welding distance is relatively loose. Therefore, the semiconductor bare aa 10 is not expanded. According to the embodiment of the present invention, the pitch of the bumps of the bumps or the bare pads of the semiconductor die 10' may be in the range of ai3 a4 mm (the range of the traces. Η11 is a schematic cross-sectional view of a system-in-package according to another embodiment of the present invention, wherein the 'numbers' indicate a similar layer, tree or region, such as Μ Γ, having the same as shown in FIG. All the features of Sip 。. The difference between Slp Γ of the f-extension diagram of Fig. 14 is that, in Fig. 14, the rubber cake 600 pack 1a, the + conductor bare crystal melon, and the part of the seal carrier 20 The surface 2η rubber cake 6 (8) surrounds the outer colloid 16 of the WLP la. The phonetic heart can be made of different materials. The idea, the rubber cake_ and the colloid 16 are shown as system level coffee according to another embodiment of the present invention," In the section ",, the same number indicates the similar layer, bottom (four) and 3丨. Since the multi-turn point bump 14 is just / ^ large = saves P1 increase 'so save
S 21 201142998 了底膠30與3〇、膠餅_包覆外擴 u與半導體裸晶⑴，，並填 充重佈線層結構12與封裝載體2〇之上表面2〇a間之空隙·、以及 半導體裸晶1〇’與封裝載體2〇之上表面2〇a間之空隙6〇2,。 第16圖所示為依據本發明之另_實施例之系統級封裝2,之截面 不心圖其中’相同之數字標號代表類似之層、元件或區域。如第Μ 圖所π ’ SiP 2,包含設置於封裝載體2〇之上表面2〇a上之外擴醫 la’。依據本實施例，外擴術la，為多晶片模組，其包含但不限於形 成於單-職之轉體裸晶職主裸晶)與半導體裸晶⑴，，(或連接裸 晶）。半導體裸晶10與半導體裸晶10，，每一者上之接合焊㈣或『 可通過半導體裸晶10與半導體裸晶1G，，之共面裸晶面上直接提供之重 佈線^結構12外擴，箱言，半導體裸晶1G可為基頻晶片或裸晶、 射頻晶片或晶載晶片，而半導體裸晶1〇，可為條晶片、·晶片、 GPS晶片或藍芽晶片。類似地’勝體16包覆半導體裸晶10之一部分， 例如除了接合焊墊U行程之裸晶_整絲面，錢包覆半導體裸晶 ίο”之-部分。重佈線層結構12具有與先前描述相同的結構。根據本 發月之實她例重佈線層結構12包含絕緣層仏、重新佈局金屬層⑶ ^防蟬層12C。重新佈局金屬詹⑶之至少—部分（如數字標號13所 心不）凸出了裸晶邊緣1〇3或耐，。也就是，重新佈局金屬層⑶橫 向延伸出了膠體16之表面，膠體16實質上與裸晶面1〇b與裸晶面應， 共面’其巾’多個接合焊塾u與u，，形成於裸晶面·之上。 重新佈局金屬層12b重新分佈設置於半導體裸晶10或1〇”之裸晶 22 201142998 =上之多個接合嬋墊η或u”，以在絕緣層12a上形成多個外擴接合 知塾15，從而突破基板上之凸塊間距限制。值得注意的是，多個外擴 接合焊塾可具有不同類型與選擇，本發明之範圍並不以此為限。上 述「在絕緣層l2a上」在此指多個外擴接合焊墊15排佈於絕緣層以 之表面以及，例如，當絕緣層12a沉積後形成該多個結合焊墊15。 半導體裸晶10透過重新佈局金屬屬12b及多個辉點凸塊Μ電性 連接至封裝載體2G ’其中多個焊點凸塊14排佈於重佈線層轉^中 定義之多個外擴接合 15之上。焊點凸塊14可包含共晶（例如， 63〇秦37%Pb)、高錯（例如’95%Pb，2.5%Ag)或無錯（例如，975〇备 2.5%Ag)成分。依據本發明之實施例，多個焊點凸塊μ間之凸塊間 距P1大致為0.13-0.4mm(130-400hn)。在下表面2〇b，多個焊錫球％ 之球間距P2大致為0.5mm(500im)，例如，Fccsp使用之電路板。 覆晶凸塊衫種處理方法。以焊點凸塊為例，腦^經㈣刻、鍵 層或類财式設置於接合雜之上。設置之歧㈣了接合焊 墊上之保4氧化層’並疋義了焊錫附著區域。接著，焊錫可經由適當 ，方法沉積於UBM之上，例如，蒸發、猶、電極網印或針孔沉積 等。焊點凸塊裸晶10經由焊點回焊附著於封装載體2〇之上。此後， 底膠30添加於重佈線層結構u與封裝載體2〇之間。絲3〇可為特 別設計之環氧化物，用以填充重佈線層結構12與封裝載體2〇之間的 空隙，並包覆多轉點凸塊14。封裝倾2G為—封裝基板，該封裝 基板包含金屬佈線層22a和金屬佈線層22b，金屬佈線層瓜和金屬 23 201142998 佈線層22b分別排佈於上表面2〇a及下表面2%。金屬佈線 金屬佈線層22b透過多個導通孔124彼此互連，依據本發日/ ^ 通孔124,經由機械式鑽孔方法形餘封褒載體2〇中。此外，可γ 封裝載體20可包含多層金屬佈線層，例如四層或六層。。Μ理解， 第17圖所示為依據本發明之另一實施例之系統級封装2 示意圖’其中，_之數字標號代表類似之層、元件或區域= 圖所示，SiP 2”具有與第16圖所示之灿2,之所有特徵。第/ η 灿2”與第16圖之SlP2，之間的區別在於，於第17圖中 _ =S 21 201142998 The primer 30 and 3 〇, the rubber cake _ cladding the expansion u and the semiconductor bare crystal (1), and fill the gap between the redistribution layer structure 12 and the surface 2〇a of the package carrier 2〇, and The gap between the semiconductor bare crystal 1〇' and the surface 2〇a of the package carrier 2〇 is 6〇2. Figure 16 is a cross-sectional view of a system-in-package 2 in accordance with another embodiment of the present invention, wherein like numerals indicate similar layers, elements or regions. As shown in Fig. π 'SiP 2, it is disposed on the surface 2〇a of the package carrier 2〇 and is expanded. According to this embodiment, the external expansion is a multi-wafer module, which includes, but is not limited to, a single-jointed bare-crystal die-die, and a semiconductor die (1), (or a bare die). The semiconductor die 10 and the semiconductor die 10, each of which is bonded (four) or "can pass through the semiconductor die 10 and the semiconductor die 1G, and the rewiring directly provided on the coplanar bare face ^ structure 12 Expanded, box, semiconductor bare crystal 1G can be a baseband wafer or bare crystal, RF wafer or crystal carrier wafer, and the semiconductor bare crystal can be a strip wafer, a wafer, a GPS wafer or a blue chip. Similarly, the 'body 16 is coated with a portion of the semiconductor die 10, for example, except for the bare die-finished surface of the bonding pad U-travel, the portion of the semiconductor-coated semiconductor die." The redistribution layer structure 12 has Describe the same structure. According to the present month, her example rewiring layer structure 12 includes an insulating layer 重新, a re-layout metal layer (3) ^ 蝉 layer 12C. Re-layout at least part of the metal (3) (such as the number 13 No) the bare edge is 1〇3 or resistant, that is, the re-layout metal layer (3) extends laterally beyond the surface of the colloid 16, and the colloid 16 substantially corresponds to the bare face 1b and the bare face. A plurality of bonding pads u and u are formed on the bare surface. The redistributed metal layer 12b is redistributed to the bare die of the semiconductor die 10 or 1" 201142998 = Bonding pads η or u" to form a plurality of outwardly-spreading joints 15 on the insulating layer 12a, thereby breaking the bump spacing limitation on the substrate. It is noted that the plurality of outer-welded joints may have different Type and selection, the scope of the invention is not limited thereto. The term "on the insulating layer 12a" herein means that a plurality of overextended bonding pads 15 are arranged on the surface of the insulating layer and, for example, the plurality of bonding pads 15 are formed after the insulating layer 12a is deposited. The semiconductor die 10 is electrically connected to the package carrier 2G through the re-layout metal 12b and the plurality of bump bumps. The plurality of solder bumps 14 are arranged in a plurality of external expansion joints defined in the redistribution layer. Above 15. Solder bumps 14 may comprise a eutectic (e.g., 63 〇 37% Pb), a high level (e.g., '95% Pb, 2.5% Ag) or a non-error (e.g., 975 2. 2.5% Ag) component. According to an embodiment of the present invention, the bump pitch P1 between the plurality of pad bumps μ is approximately 0.13-0.4 mm (130-400 hn). On the lower surface 2〇b, the ball pitch P2 of the plurality of solder balls% is approximately 0.5 mm (500 im), for example, a circuit board used by Fccsp. The method of processing the flip-chip bumps. Taking solder bumps as an example, the brain (4) engraved, key layer or financial type is placed on the bonding impurities. The difference between the settings (4) the bonding of the oxide layer on the pad 'and the solder adhesion area. Next, the solder can be deposited on the UBM via an appropriate method, such as evaporation, helium, electrode screen printing or pinhole deposition. Solder bump bump die 10 is attached to package carrier 2 via solder joint reflow. Thereafter, a primer 30 is added between the redistribution layer structure u and the package carrier 2A. The wire 3 can be a specially designed epoxide for filling the gap between the redistribution layer structure 12 and the package carrier 2 and covering the multi-turn bumps 14. The package tilt 2G is a package substrate including a metal wiring layer 22a and a metal wiring layer 22b, and the metal wiring layer melon and metal 23 201142998 wiring layer 22b are respectively arranged on the upper surface 2a and the lower surface 2%. Metal wiring The metal wiring layer 22b is interconnected with each other through a plurality of via holes 124, and is sealed in the carrier 2 via a mechanical drilling method in accordance with the present invention. Further, the gamma-encapsulated carrier 20 may comprise a plurality of layers of metal wiring, such as four or six layers. . ΜUnderstand, FIG. 17 is a schematic diagram of a system-in-package 2 according to another embodiment of the present invention, wherein the numeral _ represents a similar layer, component or region = Figure, SiP 2" has and 16th All the features of Can 2 shown in the figure. The difference between the / η 灿 2" and the S1P2 in Figure 16 is that in Figure 17 _ =
覆外擴WLP la以及封裝載體2〇之部分上表面加 音 L 與膠體16可由不同材料製造。 w >并600 第18圖所示為依據本發明之另一實施例之系統級封u 示意圖，其巾，相同讀字魏絲_之層、元件她 = 圖所示，鹏”，具有與第17圖所示之siP2”之所有特徵，除了節第 底膠30;於多個焊點凸塊14之凸塊間簡增大，因此節省了底膠 =WLP la㈣咖1G，，椒重佈細 構12與封裝載體20之上表面20a間之空隙602。 以上所述僅為本發狀難實關，軌熟悉本案之人士援 發明之精神所做之等效變化與修饰，㈣涵蓋於後附之申請專=範圍 【圖式簡單說明】 24 201142998 第1 ®所示為傳統FCCSP之截面示意圖。 第2圖所示為傳統FCBGA封裝之截面示意圖。 圖。第3圖所示為依據本發明之一實施例之外擴聊ia之戴面示意 圖。第4圖所不為製造第3圖所示之外擴WLp ^之典型步驟之流程 圖 第5圖所示為依據本發明之另一 實施例之覆晶封裝1之截面示意 圖 圖 圖 圖 圖 圖 圖 。圖所7^域本發明之另-實施例之覆晶封裝2之截面示意 。★圖所不為依據本發明之另—實施例之覆晶封裝3之截面示意 β第8圖所示為依據本發明之另—實施例之覆晶封裝4之截面示意 ，第9圖所㈣依據本㈣之另—實施例之覆晶餘5之截面示意 第10圖所示為依據本發明之另一實施例之覆晶雜6之截面示意 第Π圖所示為依據本判之另—實施例之覆晶封裝7之截面示意 第12圖所示為依據本發明之另-實施例之覆晶封裝8之截面示意 第13圖所示為依據本翻以-實_之純級封们，之截面The outer surface of the WLP la and the package carrier 2, the upper surface of the sound L and the colloid 16 can be made of different materials. w > and 600 Figure 18 is a schematic diagram of a system-level seal u according to another embodiment of the present invention, the towel, the same read word Wei _ layer, the component she = Figure, Peng", with All the features of the siP2" shown in Fig. 17 except for the base rubber 30; the simple increase between the bumps of the plurality of solder bumps 14, thereby saving the primer = WLP la (four) coffee 1G, A gap 602 between the microstructure 12 and the upper surface 20a of the package carrier 20. The above is only the difficulty of this issue, and the equivalent changes and modifications made by the people familiar with the case to the spirit of the invention, (4) are covered in the attached application = scope [simplified description] 24 201142998 1 ® shows a schematic cross-section of a conventional FCCSP. Figure 2 shows a schematic cross-sectional view of a conventional FCBGA package. Figure. Fig. 3 is a schematic view showing the wearing of the ia in addition to an embodiment of the present invention. FIG. 4 is a flow chart showing a typical step of expanding the WLp ^ shown in FIG. 3. FIG. 5 is a schematic cross-sectional view showing the flip chip package 1 according to another embodiment of the present invention. Figure. Figure 7 is a cross-sectional view of a flip chip package 2 of another embodiment of the present invention. The figure is not a cross-sectional view of the flip chip package 3 according to another embodiment of the present invention. FIG. 8 is a cross-sectional view of the flip chip package 4 according to another embodiment of the present invention, and FIG. 9(4) FIG. 10 is a cross-sectional view of a flip-chip 5 according to another embodiment of the present invention. FIG. 10 is a cross-sectional view of a flip-chip 6 according to another embodiment of the present invention. FIG. 12 is a cross-sectional view showing a flip chip package 7 according to another embodiment of the present invention. FIG. 13 is a view showing a pure level seal according to the present embodiment. Cross section
S 25 201142998 示意圖。 第14圖所示為依據本 示意圖。 另—實施例之系統級封裝Γ，之截面 第15圖所示為依據本發明之另 示意圖。 之系統級封裝1，，，之截面 例之系統級封裳2,之截面 不意圖。 第17圖所示為依據本發明之另一 示意圖。 第16圖所示為依據本發明之另一實 實％例之系統級封裝2，，之截面 不意圖 第I8圖所*為域本咖之另—實施例之系 統級封裝2”，之截面 【主要元件符號說明】S 25 201142998 Schematic. Figure 14 shows the schematic according to this. Further, a system-in-package of the embodiment, a cross section, Fig. 15 is a schematic view showing another embodiment according to the present invention. The system-level package 1, the section of the system-level package 2, the section is not intended. Figure 17 is a diagram showing another schematic view in accordance with the present invention. Figure 16 is a diagram showing a system-in-package 2 according to another embodiment of the present invention. The cross-section is not intended to be a system-in-package 2" of another embodiment of the present invention. [Main component symbol description]
100 FFCSP 101、 201 裸晶 102、 202焊點凸塊 120載體 122 ' 226 ' 14'24 焊錫球 200 FCBGA 封裝 203、30、30’ 底膠 220晶片載體基板 222 盲孔 224 埋孔 26 201142998100 FFCSP 101, 201 bare die 102, 202 solder bumps 120 carrier 122 ' 226 ' 14'24 solder ball 200 FCBGA package 203, 30, 30' primer 200 wafer carrier substrate 222 blind hole 224 buried hole 26 201142998
la、la’ 外擴 WLP 10、 10’半導體裸晶 11、 11’接合焊墊 12 重佈線層結構 12a絕緣層 12b 重新佈局金屬層 12c 防焊層 15外擴接合焊墊 16膠體 16a 頂面 52〜58 步驟 卜2、3、4、5、6、7、8覆晶封裝 1’、1”、Γ”、2’、2”、2”，系統級封裝 10a、10a”裸晶邊緣 10b、10b”裸晶面 10c 底面 13 重新佈局金屬層12b之至少一部分 124 導通孔 20封裝載體 20a 上表面 20b 下表面 22a、22b金屬佈線層 P、P2球間距La, la' externally expanded WLP 10, 10' semiconductor bare die 11, 11' bonding pad 12 redistribution layer structure 12a insulating layer 12b re-layout metal layer 12c solder resist layer 15 outer bonding bonding pad 16 colloid 16a top surface 52 ~58 Steps Bu 2, 3, 4, 5, 6, 7, 8 flip chip package 1', 1", Γ", 2', 2", 2", system-level package 10a, 10a" bare edge 10b, 10b" bare crystal face 10c bottom surface 13 re-arranged at least a portion of the metal layer 12b 124 via hole 20 package carrier 20a upper surface 20b lower surface 22a, 22b metal wiring layer P, P2 ball pitch
S 27 201142998S 27 201142998
Pi凸塊間距 2a外部散熱槽 3a散熱層 302散熱遮罩 304散熱膠層 402、500散熱片 502支架 504遮罩 600膠餅 602 空隙Pi bump spacing 2a external heat sink 3a heat sink 302 heat sink mask 304 heat sink layer 402, 500 heat sink 502 bracket 504 mask 600 rubber cake 602 void