CN102263074A - System-in-package With Fan-out Wlcsp - Google Patents
System-in-package With Fan-out Wlcsp Download PDFInfo
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- CN102263074A CN102263074A CN2011101193737A CN201110119373A CN102263074A CN 102263074 A CN102263074 A CN 102263074A CN 2011101193737 A CN2011101193737 A CN 2011101193737A CN 201110119373 A CN201110119373 A CN 201110119373A CN 102263074 A CN102263074 A CN 102263074A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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Abstract
A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier; a second semiconductor die mounted alongside of the first semiconductor die; a rewiring laminate structure comprising a re-routed metal layer between the first semiconductor die and the package carrier. At least a portion of the re-routed metal layer projects beyond the die edge. A plurality of bumps is arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.
Description
Technical field
The present invention relates to semiconductor packaging, more specifically, relate at least a flip-chip (flip-chip) encapsulation and semiconductor die package, can be applicable to have the situation of a plurality of pins (pin).
Background technology
In the art, for bare chip is arranged on the substrate, can realize by a plurality of joint solder joints that are positioned on bare chip and the substrate, in this process, can use the various chips encapsulation technology, as ball grid array (Ball Grid Array, BGA), toe-in closes, flip-chip etc.In order to ensure the miniaturization and the functional diversities of electronic product or communicator, semiconductor packages needs that size is little, the connection of many pins, two-forty and multifunction.
(Input-Output, I/O) increase of the increase of number of pins and high-performance IC demand has promoted the development of Flip-Chip Using technology in input and output.Flip chip technology (fct) uses a plurality of salient points (bumps) and encapsulation medium direct interconnection on a plurality of bond pads that are positioned at chip.Chip by shortest path towards the bond package medium.This technology not only can be applicable to single-chip package, also can be applicable to the larger-size encapsulation of higher integrative levels, and can hold several chips to form the accurate more substrate of big functional unit.Flip chip technology (fct) uses area array, has to realize the lower advantage of interconnection inductance the highest with the interconnection density that installs and encapsulation.
Figure 1 shows that the schematic cross-section of traditional die level flip chip encapsulation (Flip-Chip Chip Scale Package is hereinafter to be referred as FCCSP).As shown in Figure 1, FFCSP 100 comprises bare chip 101, and bare chip 101 is inverted (face-down) and also is connected to carrier 12 0 by a plurality of solder joint salient points (solder bump) 102 in the upper surface (top surface) of carrier 12 0.On the bottom surface of carrier 12 0, provide a plurality of soldered balls (solder ball) 122 in order to the connecting circuit plate.Typical this packaging structure uses eutectic tin/plumbous flip chip interconnects (eutectic tin/lead flip-chip interconnect) technology in area array or peripheral salient point are arranged, close interconnection with the toe-in of replacement standard.Because toe-in closes the elimination in loop, make with bare chip to be connected inductance lower, simultaneously, the electrical path of critical high-frequency signal circuit has been optimized in the increase of path density (routing density).
Figure 2 shows that the schematic cross-section of conventional flip chip ball grid array (Flip-Chip Ball Grid Array is hereinafter to be referred as FCBGA) encapsulation.As shown in Figure 2, FCBGA encapsulation 200 comprises bare chip 201, and bare chip 201 is inverted in the upper surface of chip carrier substrate 220 and connects chip carrier substrate 220 by a plurality of solder joint salient points 202.Space between the end face of primer (underfill) 203 filling bare chips 201 and chip carrier substrate 220.Chip carrier substrate 220 can comprise multilayer lead-in wire (trace), and the different layers of this multilayer lead-in wire is connected to each other together by blind hole (blind via) 222 or buried via hole (buried via) 224.For example, blind hole 222 can be by laser drill to realize higher density.A plurality of soldered balls 226 are provided in the bottom surface of chip carrier substrate 220.FCBGA encapsulation 200 allows the design of high-order encapsulation resolution, and for current or following express network and digital television system, high-order encapsulation resolution is desirable.For example, in order to keep signal integrity, this encapsulation has the characteristics of low inductance, low-dielectric loss and impedance matching.
Yet traditional flip chip techniques faces the challenge of the bump pitch restriction on the substrate.In addition, high-performance FCB GA encapsulation is expensive because of the chip carrier substrate (typical chip carrier substrate comprises 1+2+1 layer building material or more multi-layered structure material) of costliness.Since the development of flip chip technology (fct) and bump pitch dwindle more than bare chip dwindle with the growth of number of pins slowly many, therefore, the bump pitch of substrate becomes the bottleneck place of flip-chip line map.Even if dwindling, following bare chip will surmount the dwindling of bump pitch resolution of substrate carrier.In order to overcome this technological gap, (Through Silicon Via, TSV) technology is present unique and expensive solution for silicon intermediary layer (silicon interposer) technology and silicon chip clear opening technology.Therefore, a kind of modified model Flip-Chip Using of industrial circle tight demand technology limits with the bump pitch that meets cost benefit and solve on the substrate.
Summary of the invention
For solving above technical problem, the spy provides following technical scheme:
The embodiment of the invention provides a kind of system in package, comprises: package carrier has upper surface and lower surface; First semiconductor bare chip comprises the unilateral and bare chip edge of naked core, and first semiconductor bare chip is inverted in the upper surface of package carrier, wherein, on naked core is unilateral a plurality of bond pads is set; Second semiconductor bare chip is arranged on the package carrier adjacent with first semiconductor bare chip; Layer structure that reroute, between semiconductor bare chip and package carrier, layer structure that reroute comprises layout metal level again, and wherein, at least a portion in the layout metal level protrudes from the bare chip edge again; And a plurality of salient points, being arranged on layer structure that reroute, a plurality of salient points are in order to be electrically connected at semiconductor bare chip with package carrier.
The embodiment of the invention provides a kind of system in package in addition, comprises: package carrier has upper surface and lower surface; Extend out the wafer scale device, comprise first semiconductor bare chip on the upper surface that is arranged at package carrier; Second semiconductor bare chip is arranged on the upper surface of package carrier and with to extend out the wafer scale device adjacent; And primer, at package carrier and extend out between the wafer scale device.Or glue cake in addition, extend out the wafer scale device in order to coating.
The embodiment of the invention provides a kind of system in package in addition, comprises: package carrier has upper surface and lower surface; Extend out the wafer scale device, comprise first semiconductor bare chip on the upper surface that is arranged at package carrier; Second semiconductor bare chip is arranged on the upper surface of package carrier and with to extend out the wafer scale device adjacent; And the glue cake, extend out the wafer scale device in order to coating, and the glue cake is also in order to fill package carrier and to extend out space between the wafer scale device.
The embodiment of the invention provides a kind of system in package in addition, comprises: first semiconductor bare chip, comprise the unilateral and bare chip edge of naked core, and first semiconductor bare chip is inverted in the upper surface of package carrier, wherein, on naked core is unilateral a plurality of bond pads is set; Second semiconductor bare chip is arranged on the upper surface of package carrier and with to extend out the wafer scale device adjacent; Layer structure that reroute, between semiconductor bare chip and package carrier, layer structure that reroute comprises layout metal level again, and wherein, at least a portion in the layout metal level protrudes from the bare chip edge again; A plurality of salient points are arranged on layer structure that reroute, in order to package carrier is electrically connected at semiconductor bare chip; And a plurality of soldered balls, be positioned at the lower surface of substrate.
Utilize the present invention can effectively solve the problem of the restriction of the bump pitch on the substrate in the encapsulation technology, reach preferable cost benefit.
Description of drawings
Figure 1 shows that the schematic cross-section of traditional F CCSP.
Figure 2 shows that the schematic cross-section of traditional F CBGA encapsulation.
Figure 3 shows that the schematic cross-section that extends out WLP 1a according to one embodiment of the invention.
Figure 4 shows that the flow chart of making the exemplary steps that extends out WLP 1a shown in Figure 3.
Figure 5 shows that schematic cross-section according to the Flip-Chip Using 1 of another embodiment of the present invention.
Figure 6 shows that schematic cross-section according to the Flip-Chip Using 2 of another embodiment of the present invention.
Figure 7 shows that schematic cross-section according to the Flip-Chip Using 3 of another embodiment of the present invention.
Figure 8 shows that schematic cross-section according to the Flip-Chip Using 4 of another embodiment of the present invention.
Figure 9 shows that schematic cross-section according to the Flip-Chip Using 5 of another embodiment of the present invention.
Figure 10 shows that schematic cross-section according to the Flip-Chip Using 6 of another embodiment of the present invention.
Figure 11 shows that schematic cross-section according to the Flip-Chip Using 7 of another embodiment of the present invention.
Figure 12 shows that schematic cross-section according to the Flip-Chip Using 8 of another embodiment of the present invention.
Figure 13 shows that schematic cross-section according to the system in package 1 ' of another embodiment of the present invention.
Figure 14 shows that system in package 1 according to another embodiment of the present invention " schematic cross-section.
Figure 15 shows that system in package 1 ' according to another embodiment of the present invention " schematic cross-section.
Figure 16 shows that schematic cross-section according to the system in package 2 ' of another embodiment of the present invention.
Figure 17 shows that system in package 2 according to another embodiment of the present invention " schematic cross-section.
Figure 18 shows that system in package 2 ' according to another embodiment of the present invention " schematic cross-section.
Embodiment
In the middle of specification and claims, used some vocabulary to censure specific element.The person of ordinary skill in the field should understand, and hardware manufacturer may be called same element with different nouns.This specification and claims book not with the difference of title as the mode of distinguishing element, but with the difference of element on function as the criterion of distinguishing." comprising " mentioned in specification and claims is open term, therefore, should be construed to " comprise but be not limited to ".In addition, " couple " speech and comprise any indirect means that are electrically connected that directly reach here.Therefore, be coupled to second device, then represent first device can directly be electrically connected, or be connected electrically to second device indirectly by other device or connection means at second device if describe first device in the literary composition.
The present invention is relevant for the Flip-Chip Using that is applied to have a plurality of number of pins, and Flip-Chip Using provided by the invention can comprise wafer-level packaging (Wafer-Level Packaging is hereinafter to be referred as WLP) technology.Wafer-level packaging refers in other encapsulated integrated circuit of wafer scale, is different from the conventional process that make up each separate unit encapsulation earlier wafer cutting back again.Because in fact the last encapsulation of WLP has identical size with bare chip, therefore, WLP comes down to wafer-level package (Chip-Scale Packaging, CSP) technology.In addition, wafer-level packaging is wafer scale process conformity, encapsulation, test and burned preparing, and realizes that to the process of client's shipment finally streamlined (streamlining) operation facilitates for beginning from silicon.
The present invention utilizes the WLCSP technology and extend out closely spaced pin or salient point on chip, satisfies the minimum spacing demand that current flip-chip is handled so that extend out bond pad.Package carrier extends out layer structure that reroute in order to the machinery support, and this layer structure that reroute has and surpasses 300 and extend out bond pad.
Figure 3 shows that the schematic cross-section that extends out WLP 1a according to one embodiment of the invention.As shown in Figure 3, this extends out WLP 1a and comprises semiconductor bare chip 10 and colloid 16, wherein, colloid 16 coats the part of (encapsulate) semiconductor bare chip 10, for example, and the whole surface of semiconductor bare chip 10, except that the naked core that forms bond pad 11 is unilateral, all coated by colloid 16.And, directly provide layer structure 12 that reroute in unilateral the going up on the part surface that reaches colloid 16 of this naked core.
Figure 4 shows that the flow chart of making the exemplary steps that extends out WLP 1a shown in Figure 3.Extending out WLP 1a can be by following several steps manufacturing:
Step 52: wafer cuts and separates.
Step 54: wafer reconfigures.
Step 56: redistribution.
Step 58: implant ball and encapsulation separation.
Need to understand, extending out WLP 1a can make by other method.Use different company's use different materials of redistribution technology and handle to make and extend out WLP.But required performing step is roughly the same.
Compare with traditional wafer manufacturing processing, redistribution layer and Bumping Technology increase an extra step, promptly upward deposit (deposit) plural layers metal layout and interconnection system again at each assembly (for example chip) that is positioned on the wafer.This additional step uses similar and compatible photoetching (photolithography) and thin film deposition (thin film deposition) technology to realize in assembly itself is made.The extra level (additional level) of interconnection redistributes the extremely area array of a plurality of salient point heelpieces (Underbump Metal is hereinafter to be referred as UBM) pad with peripheral a plurality of bond pads of each chip.These a plurality of salient point heelpiece pads finally are disposed on the chip surface.A plurality of soldered balls or a plurality of salient point are used for chip is connected to application circuit board, and in fact, these a plurality of soldered balls or a plurality of salient point are positioned on these salient point heelpiece pads (for example extending out bond pad 15).
For instance, the ground floor that covers (put over) wafer is used for encapsulating this assembly, this ground floor is generally based on benzocyclobutene (benzocyclobutane, hereinafter to be referred as BCB) polymeric dielectric (polymer dielectric), in order to assembly circuit is isolated with the system's (for example, reroute a layer structure) that reroutes.The metal level (rewiring metallization layer) that reroutes is generally copper (Cu), aluminium (Al) or specially-made alloy, and this reroutes layer metal deposition on this dielectric.Then, this metal level that reroutes is covered by another BCB dielectric, and this another BCB dielectric is as anti-solder flux (solder mask).Then, the salient point heelpiece covers the position that is occupied by a plurality of soldered balls in fact.After the salient point heelpiece adheres to these a plurality of soldered balls, use flip chip technology (fct) will extend out WLP and be arranged on the circuit board.
Figure 5 shows that schematic cross-section according to the Flip-Chip Using 1 of another embodiment of the present invention.As shown in Figure 5, Flip-Chip Using 1 comprises semiconductor bare chip 10, and semiconductor bare chip 10 is inverted in upper surface (chip side) 20a of package carrier 20.For example, package carrier 20 is a base plate for packaging, and this base plate for packaging comprises metal wiring layer 22a and metal wiring layer 22b, and metal wiring layer 22a and metal wiring layer 22b are arranged in upper surface 20a and lower surface (opposite side) 20b respectively.Metal wiring layer 22a and metal wiring layer 22b interconnect each other by a plurality of plated-through-holes (plated through hole) 124, and according to the present invention, a plurality of plated-through-holes 124 are formed in the package carrier 20 by the mechanical type boring method.In addition, need to understand, package carrier 20 can comprise the multi-layer metal wiring layer, for example four layers or six layers.In another embodiment, package carrier 20 can be lead frame.
Advantage of the present invention comprises, and compares laser drill package carrier (chip carrier substrate 220 as shown in Figure 2), because by the package carrier 20 after the boring of application machine formula, therefore, the cost of Chip Packaging significantly reduces.In addition, the original WLP of extending out as shown in Figure 3 is to I/O number of pins restricted (being less than 300 generally speaking).Present embodiment can be broken through this restriction.
As shown in Figure 5, semiconductor bare chip 10 can be many number of pins chip of redistribution, for example, has 300 I/O pins of surpassing.By way of example, Flip-Chip Using 1 is specially adapted to the chip of at least 500 I/O number of pins.Typically, use for so many number of pins, the merging of the silicon intermediary layer of expensive chip carrier substrate and 1+2+1 layer building material (build up) or costliness is inevitable.This embodiment of the present invention can make the elimination of the chip carrier substrate of costliness like this and 1+2+1 layer building material or expensive silicon intermediary layer come true.
Be characterised in that with closely-related one of present embodiment, at least one layer structure 12 that reroute directly is provided on the naked core of semiconductor bare chip 10 is unilateral, and colloid 16 coats the part of semiconductor bare chip 10, for example, all surfaces of semiconductor bare chip 10 except that forming a plurality of bond pads 11.According to embodiments of the invention, layer structure 12 that reroute comprises insulating barrier 12a, layout metal level 12b and welding resisting layer (solder resist layer) 12c again.Again at least a portion of layout metal level 12b (word label 13 is indicated in full) has been given prominence to bare chip edge 10a.Just, layout metal level 12b has laterally extended the surface of colloid 16 again, colloid 16 in fact with the unilateral 10b coplane of naked core, wherein, a plurality of bond pads 11 are formed on the unilateral 10b of naked core.
Again layout metal level 12b redistribution is arranged at the naked core of the semiconductor bare chip 10 a plurality of bond pads 11 on unilateral, forming a plurality of bond pads 15 that extend out on insulating barrier 12a, thereby breaks through the bump pitch restriction on the substrate.It should be noted that a plurality of bond pads 15 that extend out can have dissimilar and selection, scope of the present invention is not as limit.Above-mentioned " on insulating barrier 12a " this refer to a plurality of extend out bond pad 15 be arranged in insulating barrier 12a the surface and, for example, when these a plurality of bond pads 15 of insulating barrier 12a deposition back formation.
Embodiments of the invention can solve the problem of another bump pitch restriction that causes because of the bare chip size is little, and this is that therefore, layer structure 12 that reroute provides one to have more flexible spacing yardstick because layer structure 12 that reroute forms in wafer-process and during making.Correspondingly, because the structure that extends out of layer structure 12 that reroute has increased the largest pads number.
Semiconductor bare chip 10 is electrically connected to package carrier 20 by layout metal level 12b and a plurality of solder joint salient point 14 again, and wherein a plurality of solder joint salient points 14 are arranged in a plurality of the extending out on the bond pad 15 of definition in layer structure 12 that reroute.Solder joint salient point 14 can comprise eutectic (for example, 63%Sn, 37%Pb), high plumbous (for example, 95%Pb, 2.5%Ag) or unleaded (for example, 97.5%Sn, 2.5%Ag) composition.According to embodiments of the invention, the bump pitch P that a plurality of solder joint salient points are 14
1Be roughly 0.15-0.3mm.At lower surface 20b, the sphere gap P of a plurality of soldered balls 24
2Be roughly 0.5mm, for example, the circuit board that FCCSP uses.
Flipchip-bumped has multiple processing method.With the solder joint salient point is example, and UBM is arranged on the bond pad by sputter (sputtering), coating (plating) or similar fashion.The processing that UBM is set has removed the protection oxide layer on the bond pad (passivating oxide layer), and has defined the scolding tin adhering zone.Then, scolding tin can be deposited on by suitable method on the UBM, for example, and evaporation, plating, silk screen printing or pin hole deposition (needle-depositing) etc.
Solder joint salient point bare chip 10 is attached on the package carrier 20 by solder joint soft heat (solder reflow).After this, primer 30 makes an addition between re-wiring layer structure 12 and the package carrier 20.Primer 30 can be specially designed epoxides (epoxy), in order to reroute space between layer structure 12 and the package carrier 20 of filling, and coats a plurality of solder joint salient points 14.This is designed for the pressure at the solder bond place that control causes because of the thermal expansion difference of 20 of semiconductor bare chip 10 and package carriers.In case solidify, primer 30 absorption pressure then, thus reduce pressure on a plurality of solder joint salient points 14, and then prolong the life-span of final encapsulation.
On the one hand, semiconductor die package (as Flip-Chip Using 1) (for example comprises semiconductor bare chip 10, colloid 16 and redistribution layer, layer structure 12 reroutes), wherein, on the naked core of semiconductor bare chip 10 is unilateral, have a plurality of bond pads 11, colloid 16 coats the part of semiconductor bare chip 10, and this naked core of redistribution layer covering is unilateral and the part of colloid 16, is used for redistribution.This redistribution layer extends out a plurality of bond pads 11.A plurality of salient points 14 are arranged on this redistribution layer.Semiconductor die package more comprises substrate (as package carrier 20), and this substrate comprises metal wiring layer 22a and metal wiring layer 22b, and metal wiring layer 22a and metal wiring layer 22b lay respectively at upper surface 20a and lower surface 20b.A plurality of salient points 14 are arranged on the upper surface 20a.Soldered ball 24 is arranged in the lower surface 20b of substrate (as package carrier 20).
On the other hand, semiconductor die package (as Flip-Chip Using 1) comprises package carrier 20, package carrier 20 comprises metal wiring layer 22a and metal wiring layer 22b, and metal wiring layer 22a and metal wiring layer 22b are arranged in the upper surface 20a and the lower surface 20b of package carrier 20 respectively.Extend out wafer scale device (for example, extending out WLP 1a) and be arranged at the upper surface 20a of package carrier 20.Primer 30 is applied to packaging body 20 and extend out between the wafer scale device.
Chip for many number of pins, in order to reduce the cost of Flip-Chip Using scheme, embodiments of the invention use have cost competitiveness the substrate that comprises double layer of metal wiring layer, mechanical type boring (for example, package carrier 20), replace the higher method of cost, for example, use expensive silicon intermediary layer in many number of pins chip.The feature of embodiments of the invention is contained in naked core and directly provides layer structure 12 that reroute on unilateral.Again the layout metal level 12b of layer structure 12 that reroute redistribution is positioned at a plurality of bond pads 11 of this naked core on unilateral, and forms a plurality of bond pads 15 that extend out, thereby breaks through the restriction of the bump pitch on the substrate among the WLP.
Figure 6 shows that the schematic cross-section according to the Flip-Chip Using 2 of another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in Figure 6, Flip-Chip Using 2 has the structure extremely similar to Flip-Chip Using shown in Figure 51, different locates to comprise by removing the part of colloid 16, has exposed and the unilateral 10b opposed bottom surface of naked core 10c, makes the end face 16a of colloid 16 flush with bottom surface 10c.Outside radiating groove (external heatsink) 2a can be set on the bottom surface 10c that exposes of semiconductor bare chip 10.By this operation, improved radiating efficiency.Certainly, outside radiating groove 2a as shown in Figure 6 is not in order to limit distortion of the present invention or other alternative method only in order to illustrate.That is to say, can suitably be arranged at the heat abstractor of other type on the bottom surface 10c that exposes, also can be applicable to present embodiment.
Figure 7 shows that the schematic cross-section according to the Flip-Chip Using 3 of another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in Figure 7, similarly, Flip-Chip Using 3 has the structure that is similar to Flip-Chip Using shown in Figure 51, and different locate to comprise has exposed and the unilateral 10b opposed bottom surface of naked core 10c.Bottom surface 10c exposes by the first half that removes colloid 16, makes the end face 16a of colloid 16 flush with bottom surface 10c in fact.Flip-Chip Using 3 more comprises heat dissipating layer (heat-spreading layer) 3a, and heat dissipating layer 3a is arranged on the end face 16a of the bottom surface 10c that exposes of semiconductor bare chip 10 and colloid 16.
Figure 8 shows that the schematic cross-section according to the Flip-Chip Using 4 of another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in Figure 8, Flip-Chip Using 4 has the structure that is similar to Flip-Chip Using shown in Figure 51, and different locate to comprise has exposed and the unilateral 10b opposed bottom surface of naked core 10c.Bottom surface 10c exposes by the first half that removes or excise colloid 16, makes the end face 16a of colloid 16 flush with bottom surface 10c in fact.Dissipating cover (heat-spreading lid) 302 is set on the bottom surface 10c that exposes.Before dissipating cover 302 is set, heat radiation glue-line (layer of thermal glue) 304 can be arranged on the bottom surface 10c that exposes.In another embodiment, dissipating cover 302 can directly contact with the bottom surface 10c that exposes.
Figure 9 shows that the schematic cross-section according to the Flip-Chip Using 5 of another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in Figure 9, Flip-Chip Using 5 has the structure that is similar to Flip-Chip Using shown in Figure 51, and different locate to comprise has exposed and the unilateral 10b opposed bottom surface of naked core 10c.Bottom surface 10c exposes by the first half that removes or excise colloid 16, makes the end face 16a of colloid 16 flush with bottom surface 10c in fact.Flip-Chip Using 5 comprises a monomer, the gapless fin (heat spreader) 402 of shielding semiconductor bare chip 10.Similarly, before fin 402 is set, on the bottom surface 10c that heat radiation glue-line 304 can be applied to expose.In another embodiment, dissipating cover 402 can directly contact with the bottom surface 10c that exposes.
Figure 10 shows that the schematic cross-section according to the Flip-Chip Using 6 of another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in figure 10, Flip-Chip Using 6 has the structure that is similar to Flip-Chip Using shown in Figure 51, and different locate to comprise has exposed and the unilateral 10b opposed bottom surface of naked core 10c.Bottom surface 10c exposes by the first half that removes or excise colloid 16, makes the end face 16a of colloid 16 flush with bottom surface 10c in fact.Flip-Chip Using 6 comprises a split type fin 500 of shielding semiconductor bare chip 10, and as shown in Figure 6, fin 500 comprises support 502 and shielding 504 two parts.Similarly, before fin 402 is set, on the bottom surface 10c that heat radiation glue-line 304 can be applied to expose.In another embodiment, shielding 504 can directly contact with the bottom surface 10c that exposes.
Figure 11 shows that the schematic cross-section according to the Flip-Chip Using 7 of another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in figure 11, because the bump pitch P of a plurality of solder joint salient points 14
1Increase, therefore, in some cases, saved primer.On the contrary, glue cake (molding compound) 600 coats and extends out WLP 1a, and fill space 602 between the upper surface 20a of reroute layer structure 12 and package carrier 20, thereby the formation chip-scale does not have primer Flip-Chip Using (mold-only flip-chip CSP).
Figure 12 shows that the schematic cross-section according to the Flip-Chip Using 8 of another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in figure 12, in order to expose and the unilateral 10b opposed bottom surface of naked core 10c, the first half of glue cake 600 and the first half of colloid 16 have been removed or have excised.The end face 16a of colloid 16 flushes with bottom surface 10c in fact.Outside radiating groove 2a is set on the 10c of bottom surface.
Figure 13 shows that the schematic cross-section of the system in package (system-in-package is designated hereinafter simply as SiP) 1 ' according to another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in figure 13, SiP 1 ' comprises and extends out WLP 1a and semiconductor bare chip 10 ' shown in Fig. 5, all is the flip-chip that is arranged on the upper surface 20a of package carrier 20.According to present embodiment, extend out WLP 1a and semiconductor bare chip 10 ' placed adjacent flatly each other.Yet, should understand, under the situation that does not break away from spirit of the present invention, also can use other arrangements of bare chip.For instance, extend out WLP 1a and can be the flip-chip that is arranged on the upper surface 20a adjacent, be staggered but needn't parallel arranged with semiconductor bare chip 10 '.Primer 30 is used for package carrier 20 and extends out between the WLP 1a.Primer 30 ' is used between package carrier 20 and the semiconductor bare chip 10 '.
Extend out WLP 1a and can comprise all features shown in Fig. 5.For instance, extend out WLP1a and can comprise semiconductor bare chip 10 similarly, semiconductor bare chip 10 is inverted in the upper surface 20a of package carrier 20.For example, package carrier 20 is a base plate for packaging, and this base plate for packaging comprises metal wiring layer 22a and metal wiring layer 22b, and metal wiring layer 22a and metal wiring layer 22b are arranged in upper surface 20a and lower surface 20b respectively.Metal wiring layer 22a and metal wiring layer 22b interconnect each other by a plurality of plated-through-holes 124, and according to the present invention, a plurality of plated-through-holes 124 are formed in the package carrier 20 by the mechanical type boring method.In addition, be appreciated that package carrier 20 can comprise the multi-layer metal wiring layer, for example four layers or six layers.Semiconductor bare chip 10 can be many number of pins chip of redistribution, for example, has 200 I/O pins of surpassing.
At least one layer structure 12 that reroute directly is provided on the naked core of semiconductor bare chip 10 is unilateral, and colloid 16 coats the part of semiconductor bare chip 10, for example, the bond pad spacing on the semiconductor bare chip 10 goes up the bump pitch rule that requires less than the upper surface 20a of (therefore not meeting) package carrier 20.For instance, the bond pad spacing of the bond pad spacing 11 of the naked core of semiconductor bare chip 10 on unilateral can be in the scope of 0.13-0.15mm (130-150 μ m).According to embodiments of the invention, layer structure 12 that reroute comprises insulating barrier 12a, layout metal level 12b and welding resisting layer 12c again.Again at least a portion of layout metal level 12b (word label 13 is indicated in full) has been protruded bare chip edge 10a.Just, layout metal level 12b has laterally extended the surface of colloid 16 again, colloid 16 in fact with the unilateral 10b coplane of naked core, wherein, a plurality of bond pads 11 are formed on the unilateral 10b of naked core.
Again layout metal level 12b redistribution is arranged at the naked core of the semiconductor bare chip 10 a plurality of bond pads 11 on unilateral, forming a plurality of bond pads 15 that extend out on insulating barrier 12a, thereby breaks through the bump pitch restriction on the substrate.It should be noted that a plurality of bond pads 15 that extend out can have dissimilar and selection, scope of the present invention is not as limit.Above-mentioned " on insulating barrier 12a " here refer to a plurality of extend out bond pad 15 be arranged in insulating barrier 12a the surface and, for example, when these a plurality of bond pads 15 of insulating barrier 12a deposition back formation.
Semiconductor bare chip 10 is electrically connected to package carrier 20 by layout metal level 12b and a plurality of solder joint salient point 14 again, and wherein a plurality of solder joint salient points 14 are arranged in a plurality of the extending out on the bond pad 15 of definition in layer structure 12 that reroute.Solder joint salient point 14 can comprise eutectic (for example, 63%Sn, 37%Pb), high plumbous (for example, 95%Pb, 2.5%Ag) or unleaded (for example, 97.5%Sn, 2.5%Ag) composition.According to embodiments of the invention, the bump pitch P1 that a plurality of solder joint salient points are 14 is roughly, for example 0.15-0.3mm (150-300 μ m).At lower surface 20b, the sphere gap P2 of a plurality of soldered balls 24 is roughly 0.4-1.0mm (500 μ m), for example, and the circuit board that FCCSP uses.
Flipchip-bumped has multiple processing method.With the solder joint salient point is example, and UBM is arranged on the bond pad by sputter, coating or similar fashion.The processing that UBM is set has removed the protection oxide layer on the bond pad, and has defined the scolding tin adhering zone.Then, scolding tin can be deposited on by suitable method on the UBM, for example, and evaporation, plating, electrode wire mark or pin hole deposition etc.Solder joint salient point bare chip 10 is attached on the package carrier 20 by the solder joint reflow.After this, primer 30 makes an addition to and reroutes between layer structure 12 and the package carrier 20, and primer 30 ' makes an addition between semiconductor bare chip 10 ' and the package carrier 20.Primer 30 or primer 30 ' can be specially designed epoxides, in order to reroute space between layer structure 12 and the package carrier 20 of filling, and coat a plurality of solder joint salient points 14.This is designed for the pressure at the solder bond place that control causes because of the thermal expansion difference of 20 of semiconductor bare chip 10 and package carriers.In case solidify, primer 30 absorption pressure then, thus reduce pressure on a plurality of solder joint salient points 14, and then prolong the life-span of final encapsulation.
According to present embodiment, semiconductor bare chip 10 (or main bare chip) has 200 I/O pins of surpassing.The example of these many number of pins bare chips or chip should not only limit to fundamental frequency chip, radio frequency chip or the brilliant chip that carries, and can be made by the advanced semiconductor process of for example 28nm technology.According to present embodiment, semiconductor bare chip 10 ' (or inferior bare chip) has less than 300 I/O pins.The example of these many number of pins bare chips or chip should not only limit to power management integrated circuit (power-management IC, PMIC).Because of semiconductor bare chip 10 ' has less I/O number of pins, so it is relative looser with bump pitch P3 (equaling the bond pad spacing on the semiconductor bare chip 10 ' haply) between the package carrier 20 to be applied to semiconductor bare chip 10 '.Therefore, semiconductor bare chip 10 ' need not extend out.According to embodiments of the invention, the bond pad spacing on the naked core of bump pitch P3 or semiconductor bare chip 10 ' is unilateral can be in the scope of 0.13-0.4mm (130-400 μ m).
Figure 14 shows that system in package 1 according to another embodiment of the present invention " schematic cross-section, wherein, the representative of identical number designation is layer, assembly or zone similarly.As shown in figure 14, SiP 1 " have all features with SiP 1 ' shown in Figure 13.The SiP 1 of Figure 14 " and the SiP 1 ' of Figure 13 between difference be that in Figure 14, glue cake 600 coats the part upper surface 20a that extends out WLP1a, semiconductor bare chip 10 ' and package carrier 20.Glue cake 600 is around the colloid 16 that extends out WLP 1a.Note that glue cake 600 and colloid 16 can be by the different materials manufacturings.
Figure 15 shows that system in package 1 ' according to another embodiment of the present invention " schematic cross-section, wherein, the representative of identical number designation is layer, assembly or zone similarly.As shown in figure 15, SiP 1 ' " have and SiP shown in Figure 14 1 " all features, except having saved primer 30 and 31.Because the bump pitch P1 of a plurality of solder joint salient points 14 increases, therefore saved primer 30 and 30 '.Glue cake 600 coats and extends out WLP 1a and semiconductor bare chip 10 ', and reroute space 602 ' between the upper surface 20a of space 602 between the upper surface 20a of layer structure 12 and package carrier 20 and semiconductor bare chip 10 ' and package carrier 20 of filling.
Figure 16 shows that the schematic cross-section according to the system in package 2 ' of another embodiment of the present invention, wherein, identical number designation representative is layer, assembly or zone similarly.As shown in figure 16, SiP 2 ' comprises and extends out WLP 1a ' on the upper surface 20a that is arranged at package carrier 20.According to present embodiment, extend out WLP 1a ' and be multi-chip modules, it is including but not limited to semiconductor bare chip 10 that is formed at single encapsulation (or main bare chip) and semiconductor bare chip 10 " (or being connected bare chip).Semiconductor bare chip 10 and semiconductor bare chip 10 " bond pad 11 or 11 on each " can be by semiconductor bare chip 10 and semiconductor bare chip 10 " and layer structure 12 that reroute that directly provide on unilateral of coplane naked core extend out.For instance, semiconductor bare chip 10 can be fundamental frequency chip or bare chip, radio frequency chip or brilliant year chip, and semiconductor bare chip 10 ' can be WiFi chip, FM chip, GPS chip or Bluetooth chip.Similarly, colloid 16 coats the part of semiconductor bare chips 10, the unilateral whole surface of naked core that forms except bond pad 11 for example, and coat semiconductor bare chip 10 " a part.Layer structure 12 that reroute has and the identical structure of previous description.According to embodiments of the invention, layer structure 12 that reroute comprises insulating barrier 12a, layout metal level 12b and welding resisting layer 12c again.Again at least a portion of layout metal level 12b (word label 13 is indicated in full) has been protruded bare chip edge 10a or 10a ".Just, layout metal level 12b has laterally extended the surface of colloid 16 again, colloid 16 in fact with unilateral 10b of naked core and the unilateral 10b ' coplane of naked core, wherein, a plurality of bond pads 11 and 11 " be formed on the unilateral 10b of naked core.
Again layout metal level 12b redistribution is arranged at semiconductor bare chip 10 or 10 " a plurality of bond pads 11 or 11 of naked core on unilateral ", on insulating barrier 12a, forming a plurality of bond pads 15 that extend out, thereby break through the bump pitch restriction on the substrate.It should be noted that a plurality of bond pads 15 that extend out can have dissimilar and selection, scope of the present invention is not as limit.Above-mentioned " on insulating barrier 12a " here refer to a plurality of extend out bond pad 15 be arranged in insulating barrier 12a the surface and, for example, when these a plurality of bond pads 15 of insulating barrier 12a deposition back formation.
Semiconductor bare chip 10 is electrically connected to package carrier 20 by layout metal level 12b and a plurality of solder joint salient point 14 again, and wherein a plurality of solder joint salient points 14 are arranged in a plurality of the extending out on the bond pad 15 of definition in layer structure 12 that reroute.Solder joint salient point 14 can comprise eutectic (for example, 63%Sn, 37%Pb), high plumbous (for example, 95%Pb, 2.5%Ag) or unleaded (for example, 97.5%Sn, 2.5%Ag) composition.According to embodiments of the invention, the bump pitch P 1 that a plurality of solder joint salient points are 14 is roughly 0.13-0.4mm (130-400 μ m).At lower surface 20b, the sphere gap P2 of a plurality of soldered balls 24 is roughly 0.5mm (500 μ m), for example, and the circuit board that FCC SP uses.
Flipchip-bumped has multiple processing method.With the solder joint salient point is example, and UBM is arranged on the bond pad by sputter, coating or similar fashion.The processing that UBM is set has removed the protection oxide layer on the bond pad, and has defined the scolding tin adhering zone.Then, scolding tin can be deposited on by suitable method on the UBM, for example, and evaporation, plating, electrode wire mark or pin hole deposition etc.Solder joint salient point bare chip 10 is attached on the package carrier 20 by the solder joint reflow.After this, primer 30 makes an addition to and reroutes between layer structure 12 and the package carrier 20.Primer 30 can be specially designed epoxides, in order to reroute space between layer structure 12 and the package carrier 20 of filling, and coats a plurality of solder joint salient points 14.Package carrier 20 is a base plate for packaging, and this base plate for packaging comprises metal wiring layer 22a and metal wiring layer 22b, and metal wiring layer 22a and metal wiring layer 22b are arranged in upper surface 20a and lower surface 20b respectively.Metal wiring layer 22a and metal wiring layer 22b interconnect each other by a plurality of plated-through-holes 124, and according to the present invention, a plurality of plated-through-holes 124 are formed in the package carrier 20 by the mechanical type boring method.In addition, be appreciated that package carrier 20 can comprise the multi-layer metal wiring layer, for example four layers or six layers.
Figure 17 shows that system in package 2 according to another embodiment of the present invention " schematic cross-section, wherein, the representative of identical number designation is layer, assembly or zone similarly.As shown in figure 17, SiP 2 " have all features with SiP 2 ' shown in Figure 16.The SiP 2 of Figure 17 " and the SiP 2 ' of Figure 16 between difference be that in Figure 17, glue cake 600 coats the part upper surface 20a that extends out WLP1a and package carrier 20.Note that glue cake 600 and colloid 16 can be by the different materials manufacturings.
Figure 18 shows that system in package 2 ' according to another embodiment of the present invention " schematic cross-section, wherein, the representative of identical number designation is layer, assembly or zone similarly.As shown in figure 18, SiP 2 ' " have and SiP shown in Figure 17 2 " all features, except having saved primer 30.Because the bump pitch P1 of a plurality of solder joint salient points 14 increases, therefore saved primer 30.Glue cake 600 coats and extends out WLP 1a and semiconductor bare chip 10 ', and reroute space 602 between the upper surface 20a of layer structure 12 and package carrier 20 of filling.
Though the present invention discloses as above with better embodiment; so it is not to be used to limit the present invention, and any the technical staff in the technical field is not in departing from the scope of the present invention; can do some and change, so protection scope of the present invention should be as the criterion with the scope that claim was defined.
Claims (28)
1. system in package comprises:
Package carrier has upper surface and lower surface;
First semiconductor bare chip comprises the unilateral and bare chip edge of naked core, and this first semiconductor bare chip is inverted in this upper surface of this package carrier, wherein, on this naked core is unilateral a plurality of bond pads is set;
Second semiconductor bare chip is arranged on this package carrier adjacent with this first semiconductor bare chip;
Layer structure that reroute, between this semiconductor bare chip and this package carrier, this layer structure that reroute comprises layout metal level again, wherein, this again at least a portion in the layout metal level protrude from this bare chip edge; And
A plurality of salient points are arranged on this layer structure that reroute, and these a plurality of salient points are in order to be electrically connected at this semiconductor bare chip with this package carrier.
2. the system as claimed in claim 1 level encapsulation more comprises primer, and this primer reroutes between layer structure and this package carrier at this.
3. the system as claimed in claim 1 level encapsulation, wherein, this package carrier is a substrate, and this substrate comprises two metal wiring layers, and this two metal wiring layer is arranged in this upper surface and this lower surface of this package carrier respectively.
4. system in package as claimed in claim 3, wherein, this two metal wiring layer electrically connects mutually by a plurality of metal piercings, and these a plurality of metal piercings are formed in this package carrier by the mechanical type boring method.
5. the system as claimed in claim 1 level encapsulation, wherein, this again layout metal level redistribution be positioned at this naked core of this semiconductor bare chip these a plurality of bond pads on unilateral, forming a plurality of bond pads that extend out, and these a plurality of salient points are arranged at this a plurality of extending out on the bond pad respectively.
6. the system as claimed in claim 1 level encapsulation, wherein, the bond pad spacing of this second semiconductor bare chip equals to be applied to the bump pitch between this second semiconductor bare chip and this package carrier haply.
7. the system as claimed in claim 1 level encapsulation, wherein, the bond pad spacing of this first semiconductor bare chip is less than the bond pad spacing of this second semiconductor bare chip.
8. the system as claimed in claim 1 level encapsulation more comprises colloid, and this colloid coats at least a portion of this first semiconductor bare chip.
9. the system as claimed in claim 1 level encapsulation more comprises primer, and this primer coats this first semiconductor bare chip and this second semiconductor bare chip.
10. system in package as claimed in claim 9, wherein, this primer is filled the space between this first semiconductor bare chip and this package carrier and this second semiconductor bare chip and this package carrier.
11. the encapsulation of the system as claimed in claim 1 level, wherein, this first semiconductor bare chip is fundamental frequency chip, radio frequency chip or the brilliant chip that carries.
12. the encapsulation of the system as claimed in claim 1 level, wherein, this second semiconductor bare chip is power management integrated circuit, WiFi chip, FM chip, GPS chip or Bluetooth chip.
13. a system in package comprises:
Package carrier has upper surface and lower surface;
Extend out the wafer scale device, comprise first semiconductor bare chip on this upper surface that is arranged at this package carrier;
Second semiconductor bare chip is arranged on the upper surface of this package carrier and to extend out the wafer scale device adjacent with this; And
Primer, this primer extends out between the wafer scale device at this package carrier and this.
14. system in package as claimed in claim 13, wherein, this extends out the wafer scale device and comprises:
Colloid is in order to coat at least a portion of this first semiconductor bare chip; And
The redistribution layer is in order to extend out a plurality of bond pads of this first semiconductor bare chip.
15. system in package as claimed in claim 13, wherein, this package carrier is a substrate, and this substrate comprises two metal wiring layers, and this two metal wiring layer is arranged in this upper surface and this lower surface of this package carrier respectively.
16. system in package as claimed in claim 13, wherein, the bond pad spacing of this second semiconductor bare chip equals to be applied to the bump pitch between this second semiconductor bare chip and this package carrier haply.
17. system in package as claimed in claim 13, wherein, this first semiconductor bare chip is fundamental frequency chip, radio frequency chip or the brilliant chip that carries.
18. system in package as claimed in claim 13, wherein, this second semiconductor bare chip is power management integrated circuit, WiFi chip, FM chip, GPS chip or Bluetooth chip.
19. a system in package comprises:
Package carrier has upper surface and lower surface;
Extend out the wafer scale device, comprise first semiconductor bare chip on this upper surface that is arranged at this package carrier;
Second semiconductor bare chip is arranged on the upper surface of this package carrier and to extend out the wafer scale device adjacent with this; And
The glue cake extends out the wafer scale device in order to coat this, and this glue cake also extends out space between the wafer scale device in order to fill this package carrier and this.
20. system in package as claimed in claim 19, wherein, this extends out the wafer scale device and comprises:
Colloid is in order to coat at least a portion of this first semiconductor bare chip; And
The redistribution layer is in order to extend out a plurality of bond pads of this first semiconductor bare chip.
21. system in package as claimed in claim 19, wherein, this package carrier is a substrate, and this substrate comprises two metal wiring layers, and this two metal wiring layer is arranged in this upper surface and this lower surface of this package carrier respectively.
22. system in package as claimed in claim 19, wherein, the bond pad spacing of this second semiconductor bare chip equals to be applied to the bump pitch between this second semiconductor bare chip and this package carrier haply.
23. system in package as claimed in claim 19, wherein, this first semiconductor bare chip is fundamental frequency chip, radio frequency chip or the brilliant chip that carries.
24. system in package as claimed in claim 19, wherein, this second semiconductor bare chip is power management integrated circuit, WiFi chip, FM chip, GPS chip or Bluetooth chip.
25. a system in package comprises:
First semiconductor bare chip comprises the unilateral and bare chip edge of naked core, and this first semiconductor bare chip is inverted in this upper surface of this package carrier, wherein, on this naked core is unilateral a plurality of bond pads is set;
Second semiconductor bare chip is arranged on the upper surface of this package carrier and to extend out the wafer scale device adjacent with this;
Layer structure that reroute, between this semiconductor bare chip and this package carrier, this layer structure that reroute comprises layout metal level again, wherein, this again at least a portion in the layout metal level protrude from this bare chip edge;
A plurality of salient points are arranged on this layer structure that reroute, and these a plurality of salient points are in order to be electrically connected at this semiconductor bare chip with this package carrier; And
A plurality of soldered balls are positioned at this lower surface of this substrate.
26. system in package as claimed in claim 25, wherein, this package carrier comprises two metal wiring layers, this two metal wiring layer is arranged in this upper surface and this lower surface of this package carrier respectively, and this two metal wiring layer electrically connects mutually by a plurality of metal piercings, and these a plurality of metal piercings are formed in this package carrier by the mechanical type boring method.
27. system in package as claimed in claim 25 more comprises primer, this primer reroutes between layer structure and this package carrier at this.
28. system in package as claimed in claim 25, wherein, the bond pad spacing of this second semiconductor bare chip equals to be applied to the bump pitch between this second semiconductor bare chip and this package carrier haply.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US34749410P | 2010-05-24 | 2010-05-24 | |
| US61/347,494 | 2010-05-24 | ||
| US12/905,095 US8093722B2 (en) | 2008-05-27 | 2010-10-15 | System-in-package with fan-out WLCSP |
| US12/905,095 | 2010-10-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102263074A true CN102263074A (en) | 2011-11-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101193737A Pending CN102263074A (en) | 2010-05-24 | 2011-05-10 | System-in-package With Fan-out Wlcsp |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102263074A (en) |
| TW (1) | TW201142998A (en) |
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|---|---|---|---|---|
| TWI514529B (en) * | 2013-07-01 | 2015-12-21 | 矽品精密工業股份有限公司 | Semiconductor package and its method of manufacture, semiconductor structure having semiconductor substrate and its method of manufacture |
| WO2017107174A1 (en) * | 2015-12-25 | 2017-06-29 | Intel Corporation | Flip-chip like integrated passive prepackage for sip device |
| US11107771B2 (en) * | 2019-12-26 | 2021-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Segregated power and ground design for yield improvement |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1505149A (en) * | 2002-12-02 | 2004-06-16 | 华泰电子股份有限公司 | Three-dimensional packaging apparatus of multichip integrated circuit |
| CN1835229A (en) * | 2005-03-16 | 2006-09-20 | 索尼株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| US7247932B1 (en) * | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
| CN101593734A (en) * | 2008-05-27 | 2009-12-02 | 联发科技股份有限公司 | Flip-Chip Using and semiconductor die package |
-
2011
- 2011-05-05 TW TW100115774A patent/TW201142998A/en unknown
- 2011-05-10 CN CN2011101193737A patent/CN102263074A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7247932B1 (en) * | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
| CN1505149A (en) * | 2002-12-02 | 2004-06-16 | 华泰电子股份有限公司 | Three-dimensional packaging apparatus of multichip integrated circuit |
| CN1835229A (en) * | 2005-03-16 | 2006-09-20 | 索尼株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| CN101593734A (en) * | 2008-05-27 | 2009-12-02 | 联发科技股份有限公司 | Flip-Chip Using and semiconductor die package |
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| CN103066068A (en) * | 2011-10-07 | 2013-04-24 | 联发科技股份有限公司 | Integrated circuit package structure |
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| CN103178047B (en) * | 2011-12-23 | 2018-11-02 | 新科金朋有限公司 | Semiconductor devices and preparation method thereof |
| CN103151341B (en) * | 2013-03-13 | 2015-05-13 | 华进半导体封装先导技术研发中心有限公司 | System-level packaging structure |
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| CN104078431B (en) * | 2014-06-27 | 2017-02-01 | 中国科学院上海微系统与信息技术研究所 | Packaging and interconnecting structure and method for copper protruded points filled up with double layers of underfill |
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| CN104465602A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Inverted PIP packaging structure achieving packaging and rewiring by utilizing frame and manufacturing method thereof |
| US10475741B2 (en) | 2015-04-14 | 2019-11-12 | Huawei Technologies Co., Ltd. | Chip |
| CN108140632A (en) * | 2015-04-14 | 2018-06-08 | 华为技术有限公司 | A kind of chip |
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| CN108140632B (en) * | 2015-04-14 | 2020-08-25 | 华为技术有限公司 | Chip |
| WO2017024680A1 (en) * | 2015-08-13 | 2017-02-16 | 陈明涵 | Aio package structure and packaging method |
| CN105047657A (en) * | 2015-08-13 | 2015-11-11 | 陈明涵 | AIO packaged structure and packaging method |
| CN107872924A (en) * | 2016-09-27 | 2018-04-03 | 瑞萨电子株式会社 | Semiconductor device, system in package and the system in package for vehicle |
| CN110534494A (en) * | 2019-09-06 | 2019-12-03 | 深圳市安信达存储技术有限公司 | A kind of secondary array packages method of bga chip pin and encapsulating structure |
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| CN114446910A (en) * | 2020-10-30 | 2022-05-06 | 京东方科技集团股份有限公司 | Chip structure, packaging structure, manufacturing method of chip structure and binding method |
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