CN105047657A - AIO packaged structure and packaging method - Google Patents
AIO packaged structure and packaging method Download PDFInfo
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- CN105047657A CN105047657A CN201510496691.3A CN201510496691A CN105047657A CN 105047657 A CN105047657 A CN 105047657A CN 201510496691 A CN201510496691 A CN 201510496691A CN 105047657 A CN105047657 A CN 105047657A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 340
- 229920003023 plastic Polymers 0.000 claims abstract description 66
- 238000012856 packing Methods 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 17
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses an AIO packaged structure and a packaging method. The AIO packaged structure includes a first packaged structure and a second packaged structure; the first packaged structure comprises a first substrate, a plurality of electronic components installed on the first substrate, and a first plastic packaging body which is located on the first substrate and packages the plurality of electronic components on the first substrate; the second packaged structure is located on the first packaging structure; the second packaged structure and the first substrate are packaged in a seamless manner through the first plastic packaging body; the second packaged structure includes a second substrate and a plurality of electronic components installed on the second substrate; and the second substrate and the first substrate are in electric conduction. According to an AIO obtained through adopting the packaging method, one or a plurality of second substrates are arranged on the first substrate, and adjacent substrates are packaged through plastic package techniques, and all the substrates are in electric conduction; each substrate is provided with the electronic components such as a capacitor, a resistor and a chip; an area occupied by the substrates can be decreased through stacked installation, and requirements for miniaturized chip package can be satisfied.
Description
Technical field
The present invention relates to IC encapsulation technology field, particularly relate to a kind of AIO encapsulating structure and method for packing.
Background technology
Along with the requirement of whole system power consumption, area, portability and function is more and more higher, together circuit integrated how by multiple difference in functionality, is proposed new requirement to the design of chip, manufacture and encapsulation.
System in package (SIP, SystemInPackage) refer to, by multiple, there is the active of difference in functionality and passive component, and such as other elements combinations such as MEMS (micro electro mechanical system) (MEMS), optics (Optics) element in same encapsulation, become the assembly of single the standard packaging that several functions can be provided, form a system or subsystem.Most integrated multiple chip, passive component etc. in system in package product, by the mode of wire bonding or flip-chip, the pad on the pad of chip and substrate is coupled together, connected the electrical connection realizing whole system again by the circuit line on substrate, finally utilize plastic packaging material technique that its plastic packaging is become an integral sealing product.
Along with the development of miniaturization, existing SIP encapsulating structure cannot meet the requirement of miniature chip encapsulation, in SIP encapsulating structure, each chip and element can only be packaged on one deck SIP substrate, can only from reducing chip and element number or reducing the miniature requirement that chip and element area realize chip, the miniaturization of chip then cannot be realized further when chip and element number and element area cannot be reduced.
Therefore, for above-mentioned technical problem, be necessary to provide a kind of new AIO encapsulating structure and method for packing.
Summary of the invention
The object of the present invention is to provide a kind of AIO encapsulating structure and method for packing.
To achieve these goals, the technical scheme that provides of the embodiment of the present invention is as follows:
A kind of AIO encapsulating structure, described AIO encapsulating structure comprises:
First encapsulating structure, comprises first substrate, is installed on the some electronic devices and components on first substrate and is positioned at above first substrate and the first plastic-sealed body of some electronic devices and components on plastic packaging first substrate;
Second encapsulating structure, described second encapsulating structure is positioned at above the first encapsulating structure, second encapsulating structure and first substrate are by the seamless plastic packaging of the first plastic-sealed body, second encapsulating structure comprises second substrate, the some electronic devices and components be installed on second substrate, and described second substrate and first substrate electrically conduct.
As a further improvement on the present invention, the second plastic-sealed body of some electronic devices and components on plastic packaging second substrate is formed above described second substrate.
As a further improvement on the present invention, described second encapsulating structure is stacked structures, by multiple second substrate with multiple second plastic-sealed body is mutual is stackingly formed, each second substrate is separately installed with electronic devices and components, and adjacent second substrate is by the seamless plastic packaging of the second plastic-sealed body.
As a further improvement on the present invention, in described second encapsulating structure each second substrate directly or indirectly and first substrate electrically conduct.
As a further improvement on the present invention, electrically conducted by metallic conduction post between described second substrate and first substrate or different second substrates.
As a further improvement on the present invention, cover plate is provided with at the top of the second encapsulating structure in described AIO encapsulating structure.
As a further improvement on the present invention, heat dissipating layer is provided with at the top of the second encapsulating structure in described AIO encapsulating structure.
As a further improvement on the present invention, described AIO encapsulating structure top and side is all or part of is provided with metal screen layer.
As a further improvement on the present invention, described electronic devices and components comprise electric capacity, resistance, inductance, positive cartridge chip, flip-chip.
Correspondingly, a kind of AIO method for packing, described method comprises:
First substrate is provided, some electronic devices and components are installed on the first substrate;
Second substrate is provided, second substrate and the first substrate being provided with some electronic devices and components is carried out seamless plastic packaging, forms the first plastic-sealed body between side and second substrate on the first substrate;
Electrically conduct second substrate and first substrate;
Second substrate is installed some electronic devices and components;
Cut above-mentioned encapsulating structure, obtain some AIO encapsulating structures.
As a further improvement on the present invention, also comprise after described " some electronic devices and components are installed on second substrate ":
Plastic packaging is carried out to second substrate, second substrate is formed second plastic-sealed body of plastic packaging on second substrate on some electronic devices and components.
As a further improvement on the present invention, also comprise after described " plastic packaging is carried out to second substrate ":
Second plastic-sealed body forms heat dissipating layer.
As a further improvement on the present invention, also comprise after described " some electronic devices and components are installed on second substrate ":
Cover plate and the second substrate being provided with some electronic devices and components are carried out plastic packaging, above second substrate and between cover plate, forms the second plastic-sealed body.
As a further improvement on the present invention, also comprise after described " some electronic devices and components are installed on second substrate ":
Another second substrate is provided, by this second substrate plastic packaging on original encapsulating structure, between second substrate, forms second plastic-sealed body of plastic packaging on second substrate on some electronic devices and components;
Electrically conduct the second substrate of the top and first substrate;
The second substrate of the top installs some electronic devices and components;
Repeat above-mentioned steps, form the second encapsulating structure of stack on the first substrate.
As a further improvement on the present invention, also comprise after described " some electronic devices and components are installed on second substrate ":
Another is provided to comprise the encapsulating structure of at least one second substrate, by this encapsulating structure plastic packaging on original encapsulating structure;
Electrically conduct two encapsulating structures;
Repeat above-mentioned steps, form some encapsulating structures of stack on the first substrate.
As a further improvement on the present invention, described " electrically conducting " is specially:
At second substrate and first substrate or get through hole between second substrate and second substrate, and pour into metallic conduction slurry in through-holes, form metallic conduction post after baking, described second substrate and first substrate are directly or indirectly electrically conducted by metallic conduction post.
As a further improvement on the present invention, described AIO method for packing also comprises:
First substrate in AIO encapsulating structure and all or part of region between second substrate form metal screen layer.
The invention has the beneficial effects as follows:
By arranging one or more second substrate on the first substrate, adjacent substrate carries out plastic packaging by plastic package process, and all substrates that electrically conducts, due to each substrate all can install the electronic devices and components such as electric capacity, resistance, chip, the area that can reduce shared by substrate is installed by stack, meets the requirement of miniature chip encapsulation;
Metallic conduction post can electrically conduct different substrates, and signal is being transmitted on different substrate by metallic conduction post, and compared to traditional encapsulating structure, the present invention can shorten the transmission range of signal, improves the speed of service of device;
This AIO encapsulating structure can carry out modular combination installation by the encapsulating structure identical or different with other, form Module part, can change when a certain encapsulating structure of device goes wrong, avoid the problem that conventional package carries out integral replacing, greatly reduce maintenance cost.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of AIO encapsulating structure in the embodiment of the present invention one.
Fig. 2 a ~ 2l is the encapsulation flow chart of AIO encapsulating structure in the embodiment of the present invention one.
Fig. 3 is the schematic diagram of AIO encapsulating structure in the embodiment of the present invention two.
Fig. 4 a-4c is the encapsulation flow chart of AIO encapsulating structure in the embodiment of the present invention two.
Fig. 5 a ~ 5d is the encapsulation flow chart of AIO encapsulating structure in the embodiment of the present invention four.
Fig. 6 is the schematic diagram of AIO encapsulating structure in the embodiment of the present invention five.
Fig. 7 a, 7b are the schematic diagram of AIO encapsulating structure in the embodiment of the present invention six.
Fig. 8 is the schematic diagram of AIO encapsulating structure in the embodiment of the present invention seven.
Fig. 9 a, 9b are the schematic diagram of AIO encapsulating structure in the embodiment of the present invention eight.
Figure 10 a, 10b are the schematic diagram of AIO encapsulating structure in the embodiment of the present invention nine.
Embodiment
Technical scheme in the present invention is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, should belong to the scope of protection of the invention.
Used herein such as " on ", " top ", D score, the representation space relative position such as " below " term be describe a unit as shown in the drawings or the feature relation relative to another unit or feature for the object being convenient to illustrate.The term of relative space position can be intended to comprise equipment in the different azimuth used or in work except orientation shown in figure.Such as, if by the structure upset in figure, be then described to be positioned at other unit or feature " below " or " under " unit will be positioned at other unit or feature " top ".Therefore, exemplary term " below " can include above and below these two kinds of orientation.Equipment can otherwise be directed (90-degree rotation or other towards), and correspondingly herein interpreted use with the description language of space correlation.
Further, although should be understood that first, second grade of term can be used to describe various element or structure in this article, these are described the restriction that object should not be subject to these terms.These terms are only for being distinguished from each other out these description objects.Such as, first substrate can be called as second substrate, and second substrate also can be called as first substrate similarly, and this does not deviate from the protection range of the application.
The invention discloses a kind of AIO (AllInOne) encapsulating structure, comprising:
First encapsulating structure, comprises first substrate, is installed on the some electronic devices and components on first substrate and is positioned at above first substrate and the first plastic-sealed body of some electronic devices and components on plastic packaging first substrate;
Second encapsulating structure, second encapsulating structure is positioned at above the first encapsulating structure, second encapsulating structure and first substrate are by the seamless plastic packaging of the first plastic-sealed body, and the second encapsulating structure comprises second substrate, the some electronic devices and components be installed on second substrate, and second substrate and first substrate electrically conduct.
Preferably, the second encapsulating structure is stacked structures, and by multiple second substrate with multiple second plastic-sealed body is mutual is stackingly formed, each second substrate is separately installed with electronic devices and components, and adjacent second substrate is by the seamless plastic packaging of the second plastic-sealed body.
The second encapsulating structure in the present invention comprises multiple second substrate, certainly, second encapsulating structure also can adopt other terms to be described, as the second encapsulating structure comprises second substrate, the 3rd substrate of stacking setting ..., the second plastic-sealed body in the present invention simultaneously also can adopt the second plastic-sealed body, the 3rd plastic-sealed body that set gradually ... mode be described.
The present invention is a kind of AIO method for packing also, comprising:
First substrate is provided, some electronic devices and components are installed on the first substrate;
Second substrate is provided, second substrate and the first substrate being provided with some electronic devices and components is carried out seamless plastic packaging, forms the first plastic-sealed body between side and second substrate on the first substrate;
Electrically conduct second substrate and first substrate;
Second substrate is installed some electronic devices and components;
Cut above-mentioned encapsulating structure, obtain some AIO encapsulating structures.
Below in conjunction with specific embodiment, the invention will be further described.In addition, label or the sign of repetition may be used in various embodiments.These repeat only clearly to describe the present invention in order to simple, do not represent between discussed different embodiment and/or structure and have any relevance.
Embodiment one:
Shown in ginseng Fig. 1, the AIO encapsulating structure in the embodiment of the present invention one comprises:
First encapsulating structure 10, it comprises first substrate 101, is installed on the some electronic devices and components 103 on first substrate 101 and is packaged in the first plastic-sealed body 102 on first substrate 101;
Second encapsulating structure 20, second encapsulating structure 20 is stack encapsulation structure, comprise two second substrates, be respectively second substrate 211 and second substrate 221, second substrate 211 and second substrate 221 are separately installed with some electronic devices and components 213 and 223, and on second substrate 211 and second substrate 221, plastic packaging is formed with the second plastic-sealed body 212 and 222 respectively;
Metallic conduction post, first encapsulating structure 10 and the second encapsulating structure 20 are electrically conducted by some metallic conduction posts, particularly, the present embodiment comprises the 3rd metallic conduction post 33 of the first metallic conduction post 31 of electrically conduct second substrate 211 and first substrate 101, the second metallic conduction post 32 of electrically conduct second substrate 221 and second substrate 211 and electrically conduct second substrate 221 and first substrate 101.
Second substrate 211 and 221 in the present invention all needs to electrically conduct with first substrate 101, should be understood that, electrically conduct as directly or indirectly electrically conducting in the present embodiment, first metallic conduction post 31 and the second metallic conduction post 32 or the first metallic conduction post 31 and the 3rd metallic conduction post 33 or the second metallic conduction post 32 and the 3rd metallic conduction post 33 also can be only set in other embodiments, two substrates not arranging metallic conduction post can be electrically conducted indirectly by other conductive poles, can realize the object electrically conducted equally.
First plastic-sealed body 102 and the second plastic-sealed body 212,222 lay respectively between adjacent two substrates, and the electronic devices and components in plastic packaging lower substrate, the substrate package being provided with electronic devices and components can be become an entirety by some plastic-sealed bodies, and encapsulating structure is stablized.
Electronic devices and components in the present invention comprise electric capacity, resistance, inductance, positive cartridge chip, flip-chip etc., and it can adopt formal dress to encapsulate or the mode of flip-chip packaged is installed on substrate.As in the present embodiment, electronic devices and components 103 and 213 are installed on first substrate 101 and second substrate 211 by the mode that formal dress encapsulates respectively, and electronic devices and components 103 and 213 are also respectively equipped with the gold thread (non-label) be electrically connected with first substrate 101 and second substrate 211; And electronic devices and components 223 are installed on second substrate 221 by the mode that formal dress encapsulates, it does not need to arrange gold thread.In other embodiments, other mounting means also can be adopted to install.
The method for packing of AIO encapsulating structure in the present embodiment is described in detail below in conjunction with accompanying drawing.
Shown in ginseng Fig. 2 a, 2b, first prepare first substrate 101, and substrate is carried out techniques such as toasting, dry;
By all kinds of electronic devices and components 103, as all kinds of small-sized, superminiature capacitor, resistance, inductance, chip etc. dip in scaling powder by automatic back flow brazier, Reflow Soldering is on first substrate 101;
Automatic rinser is finally adopted flux cleaning to be fallen.
Shown in ginseng Fig. 2 c, 2d, to needing the electronic devices and components of routing to carry out routing bonding, this step for as if the electronic devices and components of formal dress encapsulation, if the electronic devices and components of flip-chip packaged, this step can be omitted.
Before routing, plasma cleaning is carried out to first substrate 101 surface, then use gold thread, as alloy wire or copper cash etc. carry out routing bonding, electronic devices and components 103 are electrically connected on first substrate 101 by gold thread.
Shown in ginseng Fig. 2 e, provide second substrate 211, the first substrate 101 and second substrate 211 plastic package process that ground floor have been mounted all electronic devices and components are compression molded into one, obtain the packaging body shown in Fig. 2 f.
First the first substrate 101 being provided with electronic devices and components 103 is loaded automatic mold equipment, first substrate 103 is turned one's coat by automatic mold equipment, and absorption is buckled on patrix;
Second substrate 211 is loaded in automatic mold equipment, is specially: automatic mold equipment puts release film (not shown) on counterdie, and fixes by vacuum suction, is then located by second substrate 211, is placed on release film;
Second substrate 211 sprinkles graininess plastic packaging material equably, after plastic packaging material melts under mould high temperature, the upper die and lower die that automatic mold sets carry out matched moulds, complete plastic packaging under an increased pressure, and first substrate 101 and second substrate 211 are formed the first plastic-sealed body 102.
After die sinking, remove release film, first substrate 101 is with all electronic devices and components to be combined by the first plastic-sealed body 102 with second substrate 211.
Shown in ginseng Fig. 2 g, between second substrate 211 and first substrate 101, form some first metallic conduction posts 31, first substrate 101 and second substrate 211 can be electrically conducted by the first metallic conduction post 31.
Particularly, this technique is similar to substrate process: get through hole, fill with metallic conduction slurry (as copper slurry etc.), be communicated with first substrate 101 and second substrate 211.
Get through hole and can use various method, as mechanical punching, laser drilling etc., get through reserved first substrate 101 and the position, hole of second substrate 211.As first filled with copper slurry in the present embodiment, then toast, conducting first substrate 101 and second substrate 211.
Should be understood that, electrically conduct in other embodiments first substrate 101 and second substrate 211 can also adopt the methods such as electroplated metal layer conducting, metal sputtering to realize.
Shown in ginseng Fig. 2 h, 2i, then on second substrate 211, install some electronic devices and components 213, this mounting process is identical with the technique of installing electronic devices and components 103 on first substrate 101, no longer repeats at this.
Shown in ginseng Fig. 2 j, another second substrate 221 is provided, the second substrate 211 and second substrate 221 plastic package process that have mounted all electronic devices and components are compression molded into one, obtain the packaging body shown in Fig. 2 k, between second substrate 211 and second substrate 221, be formed with the second plastic-sealed body 212.This plastic package process is identical with the plastic package process of second substrate 211 with first substrate 101, no longer repeats at this.
Shown in ginseng Fig. 2 l, after having encapsulated second substrate 221, second substrate 221 and second substrate 211 form the second metallic conduction post 32, on second substrate 221 and first substrate 101, formed the 3rd metallic conduction post 33 simultaneously.This technique gets through hole with above-mentioned on second substrate 211 with first substrate 101, it is identical to fill with copper sizing process, no longer repeats at this.
Further, second substrate 221 is also provided with some electronic devices and components 223, and also can carries out plastic packaging by above-mentioned plastic package process, can cut above-mentioned packaging body after whole plastic packaging completes, obtain the some AIO encapsulating structures shown in Fig. 1.
Respectively by a step plastic packaging moulding process on first substrate 101 in the present embodiment, second substrate 211,221, first substrate 101, second substrate 211,221 are formed the first plastic-sealed body 102 and the second plastic-sealed body 212,222 respectively, and first substrate 101, first plastic-sealed body 102, second substrate 211, second plastic-sealed body 212, between second substrate 221 and the second plastic-sealed body 222, be seamless link, its plastic package process is simple and convenient, effectively improves stability and the reliability of AIO encapsulating structure.
Embodiment two:
Shown in ginseng Fig. 3, the AIO encapsulating structure in the embodiment of the present invention two comprises:
First encapsulating structure 10, it comprises first substrate 101, is installed on the some electronic devices and components 103 on first substrate 101 and is packaged in the first plastic-sealed body 102 on first substrate 101;
Second encapsulating structure 20, second encapsulating structure 20 is stack encapsulation structure, comprise three second substrates, be respectively second substrate 211, second substrate 221 and second substrate 231, second substrate 211, second substrate 221 and second substrate 231 are separately installed with some electronic devices and components 213,223 and 233, on second substrate 211, second substrate 221 and second substrate 231, plastic packaging is formed with the second plastic-sealed body 212,222 and 232 respectively;
Metallic conduction post, first encapsulating structure 10 and the second encapsulating structure 20 are electrically conducted by some metallic conduction posts, particularly, the present embodiment comprises the first metallic conduction post 31 of electrically conduct second substrate 211 and first substrate 101, electrically conduct the second metallic conduction post 32 of second substrate 221 and second substrate 211, electrically conduct the 3rd metallic conduction post 33 of second substrate 221 and first substrate 101, electrically conduct the 4th metallic conduction post 34 of second substrate 231 and first substrate 101, the five metals of second substrate 231 and second substrate 211 of electrically conducting belongs to conductive pole 35, and the 6th metallic conduction post 36 of electrically conduct second substrate 231 and second substrate 221.
Similarly, in the present embodiment, six metallic conduction posts also can not be set, and 3 metallic conduction posts are set as required, as only arranged the first, third and fourth metallic conduction post, or first, second and the 6th metallic conduction post etc., all can complete the object of all electrical property of substrate conductings, namely all second substrates and first substrate directly or indirectly electrically conduct.
Wherein, in the present embodiment, the second substrate 231 of the top is provided with heat dissipating layer 40, and the second overtime work 231 and heat dissipating layer 40 carry out plastic packaging by the second plastic-sealed body 232.This heat dissipating layer 40 can be metallic radiating layer, and when it is metallic radiating layer, the effect of signal shielding can also be played in the top of AIO encapsulating structure.
The method for packing of the encapsulating structure in the present embodiment can be similar with the method for packing in embodiment one, after having encapsulated second substrate 221, continue to adopt identical plastic package process plastic packaging second substrate 231 on second substrate 221, then punch on second substrate 231, fill with copper slurry, formation the 4th metallic conduction post 34, five metals belong to conductive pole 35 and the 6th metallic conduction post 36; And then on second substrate 231, electronic devices and components 233 are installed, and then whole packaging body is carried out plastic packaging in heat dissipating layer 40 by identical plastic package process, shown in ginseng Fig. 4 a ~ 4c, finally cutting forms the AIO encapsulating structure shown in Fig. 3 again.
Embodiment three:
AIO encapsulating structure in the present embodiment is identical with the AIO encapsulating structure in embodiment two, and difference is its method for packing, for the ease of understanding, only the encapsulation step of substrate is described in the present embodiment, and the steps such as electronic devices and components, punching, filling copper slurry are installed on substrate are not specifically described.
Encapsulate second substrate 211, second substrate 221, second substrate 231 and heat dissipating layer 40 successively on first substrate 101 in embodiment one, and on first substrate 101, encapsulate second substrate 211 in the present embodiment, second substrate 221 forms the first packaging body, on second substrate 231, package cooling layer 40 forms the second packaging body simultaneously, then the first packaging body and the second packaging body are carried out plastic packaging, obtain the encapsulating structure shown in Fig. 4 a.
Should be understood that, other encapsulation step can also be adopted in the present embodiment, the first packaging body is formed as encapsulated second substrate 211 on first substrate 101, simultaneously on second substrate 221, encapsulate second substrate 231 and heat dissipating layer 40 forms the second packaging body, then the first packaging body and the second packaging body are carried out plastic packaging, obtain the encapsulating structure shown in Fig. 4 a; Or on first substrate 101, encapsulate second substrate 211 form the first packaging body, on second substrate 221, encapsulate second substrate 231 forms the second packaging body simultaneously, then the first packaging body and the second packaging body are carried out plastic packaging, after completing, more whole packaging body and heat dissipating layer are carried out plastic packaging.
Embodiment four:
AIO encapsulating structure in the present embodiment and the encapsulating structure in embodiment two similar, difference is, shown in ginseng Fig. 5 d, the surrounding of each AIO encapsulating structure is provided with the metal screen layer 50 around AIO encapsulating structure, and heat dissipating layer 40 is provided with on the top of AIO encapsulating structure, this heat dissipating layer 40 is metallic radiating layer, and so five of this AIO encapsulating structure are covered shielding by metal completely.
Preferably, the earthed circuit with the intercommunication of AIO encapsulating structure can be directly designed when the design of bottom first substrate, the Bottom ground of whole first substrate can be shielded, like this, six faces of AIO encapsulating structure are except electric signal interface, can be covered by metal completely, thus extraneous signal can be shielded, avoid extraneous signal disturbing.
Shown in composition graphs 5a ~ 5d, after all substrates and heat dissipating layer plastic packaging complete, whole AIO packaging body is partly switched to first substrate, but ensures that first substrate is not cut off, AIO packaging body is formed some accepting grooves 51.Then in accepting groove 51, fill with copper starch and solidify, cut in the middle of accepting groove 51 after having solidified, the surrounding of the AIO encapsulating structure obtained just is distributed with metal screen layer 50.
Embodiment five:
Shown in ginseng Fig. 6, in another embodiment of the invention, AIO encapsulating structure is substantially identical with the structure in embodiment one, the surrounding interior section of AIO encapsulating structure in the present embodiment is provided with metal screen layer 50, and this metal screen layer 50 can shield the signal of telecommunication of AIO encapsulating structure inside.
In the present embodiment, the preparation technology of metal screen layer 50 is substantially identical with the technique in embodiment five, unlike,, after the complete second substrate 221 of plastic packaging, packaging body is partly switched to first substrate 101 in the present embodiment, form some accepting grooves, then in accepting groove, fill with copper starch and solidify, on this packaging body, proceed encapsulation after solidification, finally cut along accepting groove, the side of so cutting the AIO encapsulating structure obtained only has part to arrange metal screen layer again.
Should be understood that, be described for the signal of telecommunication shielded between second substrate 221 and first substrate 101 in the present embodiment, also such as accepting groove can be switched to second substrate 211 in other embodiments, then fill with copper in the accepting groove between second substrate 221 and second substrate 211 starch and solidify, finally cut the AIO encapsulating structure obtained and can shield the signal of telecommunication between second substrate 221 and second substrate 211, so optionally can design the region of metal screen layer according to actual needs.
Embodiment six:
In a specific embodiment of the present invention, shown in ginseng Fig. 7 a, this AIO encapsulating structure is light-electric mixed type AIO encapsulating structure, and second substrate 221 is provided with the optical communication chip 223 of some flip-chip packaged.
Further, shown in ginseng Fig. 7 b, optical communication chip 223 can also be provided with transparent plastic packaging material 222, and this transparent plastic packaging material 222 can be protected optical communication chip 223, does not affect the light extraction efficiency of optical communication chip simultaneously.
Embodiment seven:
In a specific embodiment of the present invention, shown in ginseng Fig. 8, this AIO encapsulating structure is light-electric mixed type AIO encapsulating structure, the top of AIO encapsulating structure is provided with heat dissipating layer 40, first substrate 101 is light-electric unitary substrate, first substrate 101 is provided with some optical communication chips 103, and the mode that this optical communication chip 103 adopts formal dress also to beat gold thread is installed, and this light-electric unitary substrate has some optical channels carrying out communicating for optical communication chip 103.Setting like this can not affect top and to generate heat the heat radiation of large chip, can significantly improve data simultaneously to come in and go out speed by optical communication.
Embodiment eight:
In another specific embodiment of the present invention, shown in ginseng Fig. 9 a, 9b, based on the AIO encapsulating structure of bio-identification, second substrate 221 is provided with fingerprint recognition chip 223, this fingerprint recognition chip 223 can be flip-chip mounted on second substrate 221 in Fig. 9 a, also also can be electrically connected with gold thread and second substrate 221 for formal dress in Fig. 9 b is arranged on second substrate 221.Second substrate 221 is formed cover plate 40, and cover plate can be glass, sapphire or other high-k cover plate, and between cover plate 40 and second substrate 221, plastic packaging is formed with the second plastic-sealed body 222.
Embodiment nine:
In another specific embodiment of the present invention, ginseng Figure 10 a, shown in 10b, based on the AIO encapsulating structure of imageing sensor, second substrate 221 is provided with image sensor chip 223, second substrate 221 is formed with the second plastic-sealed body 222 simultaneously, image sensor chip 223 exposes outside the second plastic-sealed body 222, Film-Mold(film die can be adopted) encapsulate, the top of imageing sensor installs micro lens additional, just can variable body camera, also can complete iris recognition chip in other embodiments simultaneously, face recognition chip, or other encapsulates with Image correlation matching method chip.
Wherein, in figure loa, image sensor chip 223 adopts gold thread and second substrate 221 to be electrically connected, and in figure 10b, image sensor chip 223 is provided with some TSV holes 2231, form TSV conductive pole (not shown) further in TSV hole 2231, the end face of image sensor chip 223 and the electric connection of second substrate 221 can be realized by TSV conductive pole.
Should be understood that, the connected mode of TSV conduction in the present embodiment also can be applied in other embodiments, and no longer citing illustrates one by one in other embodiments.
As can be seen from the above technical solutions, AIO encapsulating structure of the present invention and method for packing have the following advantages:
By arranging one or more second substrate on the first substrate, adjacent substrate carries out plastic packaging by plastic package process, and all substrates that electrically conducts, due to each substrate all can install the electronic devices and components such as electric capacity, resistance, chip, the area that can reduce shared by substrate is installed by stack, meets the requirement of miniature chip encapsulation;
Metallic conduction post can electrically conduct different substrates, and signal is being transmitted on different substrate by metallic conduction post, and compared to traditional encapsulating structure, the present invention can shorten the transmission range of signal, improves the speed of service of device;
This AIO encapsulating structure can carry out modular combination installation by the encapsulating structure identical or different with other, form Module part, can change when a certain encapsulating structure of device goes wrong, avoid the problem that conventional package carries out integral replacing, greatly reduce maintenance cost.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
Claims (17)
1. an AIO encapsulating structure, is characterized in that, described AIO encapsulating structure comprises:
First encapsulating structure, comprises first substrate, is installed on the some electronic devices and components on first substrate and is positioned at above first substrate and the first plastic-sealed body of some electronic devices and components on plastic packaging first substrate;
Second encapsulating structure, described second encapsulating structure is positioned at above the first encapsulating structure, second encapsulating structure and first substrate are by the seamless plastic packaging of the first plastic-sealed body, second encapsulating structure comprises second substrate, the some electronic devices and components be installed on second substrate, and described second substrate and first substrate electrically conduct.
2. AIO encapsulating structure according to claim 1, is characterized in that, is formed with the second plastic-sealed body of some electronic devices and components on plastic packaging second substrate above described second substrate.
3. AIO encapsulating structure according to claim 1, it is characterized in that, described second encapsulating structure is stacked structures, by multiple second substrate with multiple second plastic-sealed body is mutual is stackingly formed, each second substrate is separately installed with electronic devices and components, and adjacent second substrate is by the seamless plastic packaging of the second plastic-sealed body.
4. AIO encapsulating structure according to claim 3, is characterized in that, in described second encapsulating structure each second substrate directly or indirectly and first substrate electrically conduct.
5. AIO encapsulating structure according to claim 4, is characterized in that, is electrically conducted between described second substrate and first substrate or different second substrates by metallic conduction post.
6. AIO encapsulating structure according to claim 1, is characterized in that, is provided with cover plate in described AIO encapsulating structure at the top of the second encapsulating structure.
7. AIO encapsulating structure according to claim 1, is characterized in that, is provided with heat dissipating layer in described AIO encapsulating structure at the top of the second encapsulating structure.
8. AIO encapsulating structure according to claim 1, is characterized in that, the top of described AIO encapsulating structure and side is all or part of is provided with metal screen layer.
9. AIO encapsulating structure according to claim 1, is characterized in that, described electronic devices and components comprise electric capacity, resistance, inductance, positive cartridge chip, flip-chip.
10. an AIO method for packing, is characterized in that, described method comprises:
First substrate is provided, some electronic devices and components are installed on the first substrate;
Second substrate is provided, second substrate and the first substrate being provided with some electronic devices and components is carried out seamless plastic packaging, forms the first plastic-sealed body between side and second substrate on the first substrate;
Electrically conduct second substrate and first substrate;
Second substrate is installed some electronic devices and components;
Cut above-mentioned encapsulating structure, obtain some AIO encapsulating structures.
11. AIO method for packing according to claim 10, is characterized in that, also comprise after described " installing some electronic devices and components on second substrate ":
Plastic packaging is carried out to second substrate, second substrate is formed second plastic-sealed body of plastic packaging on second substrate on some electronic devices and components.
12. AIO method for packing according to claim 11, is characterized in that, also comprise after described " carrying out plastic packaging to second substrate ":
Second plastic-sealed body forms heat dissipating layer.
13. AIO method for packing according to claim 10, is characterized in that, also comprise after described " installing some electronic devices and components on second substrate ":
Cover plate and the second substrate being provided with some electronic devices and components are carried out plastic packaging, above second substrate and between cover plate, forms the second plastic-sealed body.
14. AIO method for packing according to claim 11, is characterized in that, also comprise after described " installing some electronic devices and components on second substrate ":
Another second substrate is provided, by this second substrate plastic packaging on original encapsulating structure, between second substrate, forms second plastic-sealed body of plastic packaging on second substrate on some electronic devices and components;
Electrically conduct the second substrate of the top and first substrate;
The second substrate of the top installs some electronic devices and components;
Repeat above-mentioned steps, form the second encapsulating structure of stack on the first substrate.
15. AIO method for packing according to claim 11, is characterized in that, also comprise after described " installing some electronic devices and components on second substrate ":
Another is provided to comprise the encapsulating structure of at least one second substrate, by this encapsulating structure plastic packaging on original encapsulating structure;
Electrically conduct two encapsulating structures;
Repeat above-mentioned steps, form some encapsulating structures of stack on the first substrate.
16. AIO method for packing according to claim 10,14,15, it is characterized in that, described " electrically conducting " is specially:
At second substrate and first substrate or get through hole between second substrate and second substrate, and pour into metallic conduction slurry in through-holes, form metallic conduction post after baking, described second substrate and first substrate are directly or indirectly electrically conducted by metallic conduction post.
17. AIO method for packing according to claim 10, is characterized in that, described AIO method for packing also comprises:
First substrate in AIO encapsulating structure and all or part of region between second substrate form metal screen layer.
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| CN201510496691.3A CN105047657A (en) | 2015-08-13 | 2015-08-13 | AIO packaged structure and packaging method |
| PCT/CN2015/094128 WO2017024680A1 (en) | 2015-08-13 | 2015-11-09 | Aio package structure and packaging method |
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