CN102176444B - High integration level system in package (SIP) structure - Google Patents

High integration level system in package (SIP) structure Download PDF

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Publication number
CN102176444B
CN102176444B CN2011100696669A CN201110069666A CN102176444B CN 102176444 B CN102176444 B CN 102176444B CN 2011100696669 A CN2011100696669 A CN 2011100696669A CN 201110069666 A CN201110069666 A CN 201110069666A CN 102176444 B CN102176444 B CN 102176444B
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China
Prior art keywords
layer
wiring
substrate
high integration
package structure
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CN2011100696669A
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CN102176444A (en
Inventor
陶玉娟
石磊
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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Priority to CN2011100696669A priority Critical patent/CN102176444B/en
Publication of CN102176444A publication Critical patent/CN102176444A/en
Priority to PCT/CN2012/072769 priority patent/WO2012126377A1/en
Application granted granted Critical
Publication of CN102176444B publication Critical patent/CN102176444B/en
Priority to US15/362,625 priority patent/US10741499B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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Abstract

The invention relates to a high integration level system in a package (SIP) structure. The structure comprises a substrate, at least a group of wiring packaging layers on the substrate, a top inverted packaging layer on the wiring packaging layers and connection balls arranged below the substrate, wherein the wiring packaging layers comprise erected surface-mount layers, material sealing layers and wiring layers which are arranged on the substrate in sequence; the top inverted packaging layer comprises an inverted surface-mount layer, bottom padding material and a material sealing layer which are arranged on the wiring packaging layers in sequence; and electrical interconnection between the adjacent packaging layers or spaced packaging layers is realized via the wiring layers. Compared with the prior art, the structure which the invention requests to protect has the following beneficial effects: the final packaged products having the functions of the whole system instead of the functions of the single chip can be formed; the interference factors among the resistors, inductors and chips in the system are reduced; and besides, the more complex multilayer interconnection structure can be formed and higher integration level wafer SIP can be realized.

Description

The high integration system-in-package structure
Technical field
The present invention relates to semiconductor technology, relate in particular to a kind of high integration system-in-package structure.
Background technology
Along with the continuous development of integrated circuit technique, electronic product more and more develops to miniaturization, intellectuality, high-performance and high reliability direction.And the integrated circuit encapsulation not only directly affects integrated circuit, electronic module and even machine performance, but also is restricting miniaturization, low cost and the reliability of whole electronic system.Progressively dwindle in the integrated circuit (IC) wafer size, under the situation that integrated level improves constantly, electronics industry has proposed more and more higher requirement to the integrated circuit encapsulation technology.
In being the Chinese patent of CN1747156C, notification number discloses a kind of base plate for packaging.Described base plate for packaging comprises: substrate, and described substrate comprises a surface; Be positioned at the pad of receiving on the described substrate surface; Be formed at the welding resisting layer on the described substrate surface, described welding resisting layer comprises at least one opening, and described opening exposes the described pad of receiving; Described base plate for packaging also comprises a pattern metal strengthening course, and described pattern metal strengthening course is formed on the described pad of receiving along the sidewall of described welding resisting layer opening.
The final products of packaged manufacturing only have single chip functions according to the method described above, yet, along with improving constantly of the compact trend of semiconductor product and product systems functional requirement, the integration that how further to improve system in package becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The technical problem that the present invention solves is: the high-density systems level encapsulation that how to realize having sandwich construction.
For solving the problems of the technologies described above, the invention provides the high integration system-in-package structure, comprising: substrate; Be positioned on the substrate at least one group wiring encapsulated layer, described wiring encapsulated layer comprises being positioned at successively and just mounts layer, the envelope bed of material, wiring layer on the substrate; Be positioned at the top flip-chip packaged layer on the wiring encapsulated layer, described top flip-chip packaged layer comprises that being positioned at losing money instead of making money on the wiring encapsulated layer successively adorns layer, underfill material, the envelope bed of material; Be arranged at the connection ball of substrate below; Wherein, see through wiring layer between the encapsulated layer and realize adjacent encapsulated layer or electric interconnected between encapsulated layer at interval.
Alternatively, described high integration system-in-package structure comprises the first wiring encapsulated layer, and the described first wiring encapsulated layer comprises that being positioned at first on the substrate is successively just mounting layer, the first envelope bed of material, first wiring layer.
Alternatively, described first just mounting that the function of each device faces up in the layer.
Alternatively, the described first envelope bed of material be filled in first just mounting the layer each device between, and expose described first just mounting the layer each device connector.
Alternatively, described wiring layer comprises that running through the place seals vertical wiring of the bed of material, is covered in the horizontal wiring that the place is sealed on the bed of material and is connected in described vertical wiring.
Alternatively, described function of losing money instead of making money each device in the dress layer faces down.
Alternatively, the envelope bed of material of described top flip-chip packaged layer is filled in to lose money instead of making money between each device of dress layer and will lose money instead of making money the dress layer and coats sealing.
Alternatively, described substrate is BT substrate or PCB substrate.
Alternatively, described just mounting comprises single or multiple chips in the layer, and described losing money instead of making money in the dress layer comprises single or multiple chips.
Alternatively, the described layer that just mounting also comprises passive device, and the described passive device that is just mounting layer is one or more in electric capacity, resistance or the inductance.
Compared with prior art, the high integration system-in-package structure that the present invention asks for protection, encapsulation in the lump again after chip and passive device integrated can form and comprises the total system function but not the final encapsulating products of single chip functions; Simultaneously, see through wiring layer between the multilayer encapsulated layer and realized that more the high-density systems of 3 D stereo angle is interconnected, compare the encapsulation of existing systems level, Miltilayer wiring structure has taken full advantage of the thickness of chip itself, satisfy that the compact trend of semiconductor packages requires and more complicated systemic-function integrate require in, reduced the disturbing factor of resistance, inductance and chip chamber in the system better, structural strength and product reliability are strengthened well.
Description of drawings
Fig. 1 is the schematic diagram of an embodiment of high integration system-in-package structure of the present invention.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
The invention provides a kind of high integration system-in-package structure, comprising: substrate; Be positioned on the substrate at least one group wiring encapsulated layer, described wiring encapsulated layer comprises being positioned at successively and just mounts layer, the envelope bed of material, wiring layer on the substrate; Be positioned at the top flip-chip packaged layer on the wiring encapsulated layer, described top flip-chip packaged layer comprises that being positioned at losing money instead of making money on the wiring encapsulated layer successively adorns layer, bottom filling, the envelope bed of material; Be arranged at the connection ball of substrate below; Wherein, see through wiring layer between the encapsulated layer and realize adjacent encapsulated layer or electric interconnected between encapsulated layer at interval.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
With reference to figure 1, show the schematic diagram of high integration system-in-package structure one execution mode of the present invention, in the present embodiment, described a kind of high integration system-in-package structure is example with two groups of wiring encapsulated layers and top flip-chip packaged layer, but the present invention does not limit therewith, and described a kind of high integration system-in-package structure comprises: substrate 101, be positioned at first on the substrate 101 wiring encapsulated layer, be positioned at the second wiring encapsulated layer on the first wiring encapsulated layer, be positioned at top flip-chip packaged layer on the second wiring encapsulated layer, be arranged at the connection ball 110 of substrate 101 belows.Wherein,
Substrate 101 is follow-up basis of piling up each package group, simultaneously, also is the basis of follow-up each layer encapsulated layer of carrying.Described substrate 101 comprises two function faces, wherein, the first surface of described substrate 101 is used for carrying out piling up of encapsulated layer, the second surface of described substrate 101 is used for planting ball (implant and connect ball), in the present embodiment, the upper surface of described substrate 101 is used for carrying out piling up of encapsulated layer, and the upper surface of described substrate 101 is provided with the pad that is electrically connected for realizing, the lower surface of described substrate 101 is used for implantation and connects ball.Particularly, described substrate 101 is generally BT(Bismaleimide Triazine) and substrate or printed circuit board (PCB) (Printed Circuit Board, PCB) etc., so that between the first surface of substrate 101 and second surface, carry out cabling.Described substrate 101 comprises the connection cabling that runs through described substrate 101, and described connection cabling can make pad and be connected ball realization electrical connection.
In order better to be fixed in encapsulation place on the substrate 101, preferably, described high integration system-in-package structure also comprises the cementing layer that is attached on the substrate 101, described cementing layer is used for just mounting layer 103 with first and is attached at substrate 101, the available material of described cementing layer has multiple, can be by methods such as some glue or printings when forming cementing layer on the substrate 101.Described method is well known to those skilled in the art in field of semiconductor manufacture, does not repeat them here.
Comprise in the first wiring encapsulated layer that being positioned at first on the substrate 101 is successively just mounting layer 102, the first envelope bed of material 103, first wiring layer 104.Wherein,
Described first is just mounting layer 102 comprises multiple semiconductor device, in the present embodiment, described first is just mounting layer 102 comprises chip and passive device, and be attached on the substrate 101 by cementing layer according to the supine mode of function, described first is just mounting layer 102 function face, refers to that first is just mounting chip in the layer 102 and the surface, pad place of passive device.
In a preferred embodiment of the present invention, be arranged at first on the substrate 101 just mounting the layer 102 and follow-up mention mount the layer can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices.These chips and passive device become the part of a system in package product separately, finish the one or more independent function that realizes in the system level function separately.
In a preferred embodiment of the present invention, first just mounting layer in 102 chip and the combination of passive device dispose according to systemic-function.Therefore, around one or a core assembly sheet, identical or different other one or a core assembly sheet may be arranged, perhaps identical or different passive devices such as electric capacity, resistance or inductance; Similarly, around a passive device, the passive device of identical or different other may be arranged, perhaps one or more identical or different chips.
The first envelope bed of material 103 is used for insulation and isolates first each device that is just mounting layer 102, simultaneously, also is used for insulation and isolates different encapsulated layers.The described first envelope bed of material 103 is filled in first and is just mounting between each device of layer 102, and, the part first envelope bed of material 103 is covered in described first and is just mounting on each device of layer 102, the described first envelope bed of material 103 expose described first just mounting the layer 102 each device connector, concrete, the bond pad surface of the described first envelope bed of material, 103 exposed chips and passive device group is so that electrically connect.
Because the first envelope bed of material 103 is filled in first and is just mounting between the device of layer 102, and expose the connector of each device, therefore just to mount layers 102 thickness suitable for the thickness and first of the first envelope bed of material 103, can reduce respectively to mount the stack thickness of layer, improve the integration of encapsulating structure to greatest extent.
First wiring layer 104 comprises the first vertically laterally wiring of wiring and first.Wherein, described first vertically wiring be used for realizing being electrically connected of the first wiring encapsulated layer and 101 of substrates for running through the lead (for example, plain conductor) of the described first envelope bed of material 103.
In actual applications, can in the envelope bed of material, form vertically wiring selectively according to design requirement, to realize respectively mounting between the layer or to mount electrical connection between layer and the substrate, because the envelope bed of material has good insulation performance, can avoid respectively mounting the interference between each device in the layer.
Described first laterally wiring for be covered on the described first envelope bed of material 103 lead (for example, plain conductor) and with first vertical wiring conducting link to each other, be used for to realize that first is just mounting the electrical connection between the device of layer 102, in the present embodiment, described first laterally connects up is used for realizing that first is just mounting the electrical connection between layer 102 chips and the passive device group, particularly, the described first horizontal wiring links to each other with the bond pad surface of chip and passive device.
The second wiring encapsulated layer is stacked on the first wiring encapsulated layer, particularly, comprising: be positioned at second on the first wiring encapsulated layer successively and just mounting layer 105, the second envelope bed of material 106 and second wiring layer 107.In the present embodiment, described second is just mounting layer 105 comprises chip and passive device, and is stacked on the first envelope bed of material 103 according to the supine mode of function.Described second is just mounting layer 105 and first is just mounting layers 102 similarly, can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices.
The second envelope bed of material 106 is used for insulation and isolates second each device that is just mounting layer 105, simultaneously, also is used for insulation and isolates different encapsulated layers.The described second envelope bed of material 106 is filled in second and is just mounting between each device of layer 105, and, the part second envelope bed of material 106 is covered in described second and is just mounting on each device of layer 105, the described second envelope bed of material 106 expose described second just mounting the layer 106 each device connector, concrete, the bond pad surface of the described second envelope bed of material, 106 exposed chips and passive device group is so that electrically connect.
Second wiring layer 107 comprises the second vertically laterally wiring of wiring and second.Wherein, described second vertical wiring is (for example to run through the lead of the described second envelope bed of material 106, plain conductor), be used for to realize being electrically connected between the second wiring encapsulated layer and other encapsulated layers, according to design requirement, described second vertically connects up also is used for realizing second electrical connection of connecting up between encapsulated layer and the substrate 101;
Described second laterally wiring for be covered on the described second envelope bed of material 106 lead (for example, plain conductor), described second laterally connects up is connected in the second vertically wiring, be used for to realize that second is just mounting the electrical connection between the device of layer 105, in the present embodiment, described second laterally connects up is used for realizing that second is just mounting the electrical connection between layer 105 chips and the passive device group.
Top flip-chip packaged layer comprises that being positioned at losing money instead of making money on the second wiring encapsulated layer successively adorns layer 108, bottom filling, the 3rd envelope bed of material 111.
The described dress layer 108 of losing money instead of making money is similar with the above-mentioned layer that mounts, and can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices.In the present embodiment, lose money instead of making money in the dress layer 108 and comprise chip, and be mounted on the second envelope bed of material 106 according to the ventricumbent mode of function, have solder bump 109 on the function face of chip, chip see through that its solder bump 109 has been realized and second wiring layer 107 second laterally the conducting between wiring is interconnected.
In a preferred embodiment of the present invention, can around flip-chip, dispose passive device according to the design needs, the mounting direction and can show the simplification technological process with the direction one that mounts of chip of passive device this moment, particularly, the function pads of passive device is mounted on the precalculated position of wiring layer and realizes that electricity is interconnected, the concrete steps that mount are well known to those skilled in the art, do not repeat them here.
Be provided with inserts 110 to constitute the bottom filling in the gap between the chip of losing money instead of making money dress layer 108 and the second wiring encapsulated layer.Fill described bottom is product reliability problem such as interior void in the envelope bed of material.Described inserts 110 can be macromolecule epoxy resin, and the good fluidity of this material can fully be filled the gap between flip-chip and the envelope bed of material.
The 3rd envelope bed of material 111 coats each device formation packaging body that dress layer 108 is lost money instead of making money in sealing, with pollution and the erosion of avoiding external environment.The material that forms the 3rd envelope bed of material 111 can be identical with the material that forms the first envelope bed of material 103 and the second envelope bed of material 106, namely adopts epoxy resin to form the 3rd envelope bed of material 111.
Described high integration system-in-package structure also comprises the connection ball 112 that is arranged at substrate 101 belows, and described connection ball 112 is arranged in substrate 101 and connects the corresponding position of cabling, links to each other with the pad of substrate 101 by the connection cabling in the substrate 101.
Comprise two groups of wiring encapsulated layers and top flip-chip packaged layer in above-described embodiment, but the present invention is not restricted to this, can also be one or more groups wiring encapsulated layer top encapsulation layer of arranging in pairs or groups, those skilled in the art can correspondingly be out of shape, revise and replace according to above-described embodiment.
High integration system-in-package structure of the present invention, realized adjacent by each wiring layer or the electrical connection between encapsulated layer of being separated by between each encapsulated layer, realized the integration of system again via the connection cabling arrangement of substrate 101 inside, the final connection ball 112 that passes through is exported function.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

Claims (10)

1. the high integration system-in-package structure is characterized in that, comprising:
Substrate; Be positioned on the substrate at least one group wiring encapsulated layer, described wiring encapsulated layer comprises being positioned at successively and just mounts layer, the envelope bed of material, wiring layer on the substrate; Be positioned at the top flip-chip packaged layer on the wiring encapsulated layer, described top flip-chip packaged layer comprises that being positioned at losing money instead of making money on the wiring encapsulated layer successively adorns layer, underfill material, the envelope bed of material; Be arranged at the connection ball of substrate below; Wherein, see through wiring layer between the encapsulated layer and realize adjacent encapsulated layer or electric interconnected between encapsulated layer at interval.
2. high integration system-in-package structure as claimed in claim 1, it is characterized in that, described high integration system-in-package structure comprises the first wiring encapsulated layer, and the described first wiring encapsulated layer comprises that being positioned at first on the substrate is successively just mounting layer, the first envelope bed of material, first wiring layer.
3. high integration system-in-package structure as claimed in claim 2 is characterized in that, described first is just mounting that the function of each device faces up in the layer.
4. high integration system-in-package structure as claimed in claim 2 is characterized in that, the described first envelope bed of material be filled in first just mounting the layer each device between, and expose described first just mounting the layer each device connector.
5. high integration system-in-package structure as claimed in claim 1 is characterized in that, described wiring layer comprises that running through the place seals vertical wiring of the bed of material, is covered in the horizontal wiring that the place is sealed on the bed of material and is connected in described vertical wiring.
6. high integration system-in-package structure as claimed in claim 1 is characterized in that, described function of losing money instead of making money each device in the dress layer faces down.
7. high integration system-in-package structure as claimed in claim 1 is characterized in that, the envelope bed of material of described top flip-chip packaged layer is filled in to lose money instead of making money between each device of dress layer and will lose money instead of making money the dress layer and coats sealing.
8. high integration system-in-package structure as claimed in claim 1, it is characterized in that: described substrate is BT substrate or PCB substrate.
9. as the described high integration system-in-package structure of any claim of claim 1 ~ 7, it is characterized in that: described just mounting comprises single or multiple chips in the layer, and described losing money instead of making money in the dress layer comprises single or multiple chips.
10. high integration system-in-package structure as claimed in claim 9 is characterized in that: the described layer that just mounting also comprises passive device, and the described passive device that is just mounting layer is one or more in electric capacity, resistance or the inductance.
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