CN102176446B - A kind of Three-dimensional high-integration system-in-package structure - Google Patents
A kind of Three-dimensional high-integration system-in-package structure Download PDFInfo
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- CN102176446B CN102176446B CN201110069846.7A CN201110069846A CN102176446B CN 102176446 B CN102176446 B CN 102176446B CN 201110069846 A CN201110069846 A CN 201110069846A CN 102176446 B CN102176446 B CN 102176446B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of Three-dimensional high-integration system-in-package structure, comprise circuit and arrange wafer; Be positioned at least one group of flip-chip packaged layer on circuit arrangement wafer; Be positioned at least one group of wiring encapsulated layer on flip-chip packaged layer; Be positioned at the top flip-chip packaged layer on end group wiring encapsulated layer; Be arranged at the connection ball below circuit arrangement wafer.Compared with prior art; a kind of Three-dimensional high-integration system-in-package structure of request protection of the present invention; can be formed and comprise total system function but not the final encapsulating products of single chip functions, reduce the disturbing factor of resistance in system, inductance and chip chamber.In addition, more complicated multiple level interconnect architecture can be formed, realize the system in package that packaging density is higher.
Description
Technical field
The present invention relates to semiconductor technology, particularly relate to a kind of Three-dimensional high-integration system-in-package structure.
Background technology
Along with the development of integrated circuit technique, electronic product is more and more to miniaturized, intellectuality, high-performance and high reliability future development.And integrated antenna package not only directly affects the performance of integrated circuit, electronic module and even complete machine, but also govern the miniaturization of whole electronic system, low cost and reliability.Progressively reduce in integrated circuit (IC) wafer size, when integrated level improves constantly, electronics industry proposes more and more higher requirement to integrated antenna package technology.
Be disclose a kind of encapsulation circuit in the Chinese patent of CN1747156C to arrange wafer at notification number.Described encapsulation circuit arranges wafer and comprises: circuit arranges wafer, and described circuit arranges wafer and comprises a surface; Be positioned at the pad of receiving on described circuit arrangement crystal column surface; Be formed at the welding resisting layer on described circuit arrangement crystal column surface, described welding resisting layer comprises at least one opening, pad of receiving described in described opening exposes; Described encapsulation circuit arranges wafer and also comprises a pattern metal strengthening course, receives on pad described in described pattern metal strengthening course is formed at along the sidewall of described welding resisting layer opening.
The packaged final products manufactured only have single chip functions according to the method described above, but, improving constantly of the trend compact along with semiconductor product and product systems functional requirement, the integration how improving system in package further becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The technical problem that the present invention solves is: the high-density systems level encapsulation how realizing having sandwich construction.
For solving the problems of the technologies described above, the invention provides a kind of Three-dimensional high-integration system-in-package structure, comprising: circuit arranges wafer; Be positioned at circuit and arrange at least one group of flip-chip packaged layer on wafer, described flip-chip packaged layer comprises and is positioned at circuit successively and arranges wafer losing money instead of making money dress layer, underfill, the envelope bed of material, wiring layer; Be positioned at least one group of wiring encapsulated layer on flip-chip packaged layer, described wiring encapsulated layer comprises the just attachment layer be positioned at successively on flip-chip packaged layer, the envelope bed of material, wiring layer; Be positioned at end group wiring encapsulated layer on top flip-chip packaged layer, described top flip-chip packaged layer comprise be positioned at successively end group wiring encapsulated layer on losing money instead of making money dress layer, underfill, the envelope bed of material; Be arranged at the connection ball below circuit arrangement wafer; Wherein, circuit arranges wafer, the electricity that realizes between adjacent package layer or interval encapsulated layer through wiring layer between each encapsulated layer is interconnected.
Alternatively, described a kind of Three-dimensional high-integration system-in-package structure comprises at least one group of flip-chip packaged layer, and described flip-chip packaged layer comprises: be positioned at first on circuit arrangement wafer successively and lose money instead of making money dress layer, the first underfill, the first encapsulated layer, the first wiring layer.
Alternatively, described first wiring layer comprises and runs through first of the first envelope bed of material and longitudinally connect up, be covered on the first envelope bed of material and connect up with described first the first transverse direction be connected that longitudinally connect up.
Alternatively, flip-chip packaged layer comprises at least one group of wiring encapsulated layer, described wiring encapsulated layer comprises: be positioned at first on flip-chip packaged layer successively and just mounting layer, the second envelope bed of material, the second wiring layer.
Alternatively, described second wiring layer comprises and runs through second of the second envelope bed of material and longitudinally connect up, be covered on the second envelope bed of material and connect up with described second the second transverse direction be connected that longitudinally connect up.
Alternatively, the solder bump in the flip-chip packaged layer of described top makes the attachment layer of top flip-chip packaged layer and end organize to be formed between the wiring layer that connects up in encapsulated layer electrically interconnected.
Alternatively, described circuit arranges wafer and is provided with upper and lower surface, and described upper and lower surface is provided with pad.
Alternatively, the solder pad space length of described circuit arrangement wafer upper surface is less than the solder pad space length of lower surface.
Alternatively, described attachment layer comprises chip, and described chip is single or many.
Alternatively, described attachment layer also comprises passive device, and described passive device is one or more in electric capacity, resistance or inductance.
Compared with prior art, a kind of Three-dimensional high-integration system-in-package structure of request protection of the present invention, encapsulates in the lump after chip and passive device being integrated again, can be formed and comprise total system function but not the final encapsulating products of single chip functions; Simultaneously, the high-density systems that multilayer encapsulation interlayer more achieves 3 D stereo angle through wiring layer is interconnected, compare existing system in package, Miltilayer wiring structure takes full advantage of the thickness of chip itself, while meeting the requirement of semiconductor packages compact trend and more complicated systemic-function integration requirement, reduce the disturbing factor of resistance in system, inductance and chip chamber better, structural strength and product reliability are strengthened well.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of Three-dimensional high-integration system-in-package structure one of the present invention embodiment.
Embodiment
Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when describing the embodiment of the present invention in detail, for ease of illustrating, described schematic diagram is example, and it should not limit the scope of protection of the invention at this.
The invention provides a kind of Three-dimensional high-integration system-in-package structure, comprising: circuit arranges wafer; Be positioned at circuit and arrange at least one group of flip-chip packaged layer on wafer, described flip-chip packaged layer comprises and is positioned at circuit successively and arranges wafer losing money instead of making money dress layer, underfill, the envelope bed of material, wiring layer; Be positioned at least one group of wiring encapsulated layer on flip-chip packaged layer, described wiring encapsulated layer comprises the just attachment layer be positioned at successively on flip-chip packaged layer, the envelope bed of material, wiring layer; Be positioned at end group wiring encapsulated layer on top flip-chip packaged layer, described top flip-chip packaged layer comprise be positioned at successively end group wiring encapsulated layer on losing money instead of making money dress layer, underfill, the envelope bed of material; Be arranged at the connection ball below circuit arrangement wafer; Wherein, circuit arranges wafer, the electricity that realizes between adjacent package layer or interval encapsulated layer through wiring layer between each encapsulated layer is interconnected.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
With reference to figure 1, show the schematic diagram of a kind of Three-dimensional high-integration system-in-package structure one of the present invention embodiment, in the present embodiment, described a kind of Three-dimensional high-integration system-in-package structure is with the first flip-chip packaged layer, first wiring encapsulated layer and top flip-chip packaged layer are example, but the present invention does not limit therewith, described a kind of Three-dimensional high-integration system-in-package structure comprises: circuit arranges wafer 101, be positioned at the first flip-chip packaged layer on circuit arrangement wafer 101, be positioned at the first wiring encapsulated layer on the first flip-chip packaged layer, be positioned at the top flip-chip packaged layer on the first wiring encapsulated layer, be arranged at the connection ball 110 below circuit arrangement wafer 101.Wherein,
Circuit arranges the basis that wafer 101 is follow-up stacking each encapsulated layers, simultaneously, also be the basis of carrying subsequent layers encapsulated layer, described circuit arranges wafer 101 and comprises two functional surfaces, wherein, described circuit arranges the first surface of wafer 101 for carrying out the stacking of encapsulated layer, the second surface that described circuit arranges wafer 101 is used for planting ball (implant and connect ball), in the present embodiment, described circuit arranges the upper surface of wafer 101 for carrying out the stacking of encapsulated layer, the lower surface that described circuit arranges wafer 101 is used for planting ball, described circuit arranges the upper of wafer 101, lower surface is provided with for realizing the pad be electrically connected, the connection cabling that the pad of upper and lower surface arranges wafer 101 inside by circuit realizes conducting, wherein, the solder pad space length of described circuit arrangement wafer 101 upper surface can be less than the solder pad space length of its lower surface, object is that the close pitch pad of upper surface is to comply with chip high accuracy, the technical requirement of high integration, the requirement that when the looser solder pad space length of lower surface is to adapt to final products SMT (surface mount), technology acuracy is relatively low, therefore, the wafer of circuit arrangement herein not only can carry out circuit arrangement to follow-up encapsulated layer, can also as the precision bridge between chip fabrication techniques and components and parts mounting technology.
First flip-chip packaged layer comprises and is positioned at circuit successively and arranges first on wafer 101 and lose money instead of making money dress layer 102, first underfill, the first envelope bed of material 103, first wiring layer 104.Wherein,
Described first loses money instead of making money dress layer 102 comprises multiple semiconductor device, in the present embodiment, described first loses money instead of making money dress layer 102 comprises chip and passive device, and be attached on circuit arrangement wafer 101 according to the ventricumbent mode of function, described first loses money instead of making money the functional surfaces filling layer 102, refers to that first loses money instead of making money the function solder joint of the chip in dress layer 102 and the surface, pad place of passive device.First loses money instead of making money the function solder joint of dress layer 102 chips, the pad of passive device and circuit, and to arrange the pad of wafer 101 upper surface interconnected.
In a preferred embodiment of the invention, be arranged at circuit to arrange first on wafer 101 and lose money instead of making money dress layer 102 and the follow-up attachment layer mentioned can comprise one or more identical or different chip, one or more identical or different passive device can also be comprised.These chips and passive device become a part for a system in package product separately, complete the one or more independent function realized in system level function separately.
In a preferred embodiment of the invention, first chip in dress layer 102 is lost money instead of making money and the combination of passive device configures according to systemic-function.Therefore, around one or a core assembly sheet, identical or different other one or a core assembly sheet may be had, or the passive device such as identical or different electric capacity, resistance or inductance; Similar, around a passive device, other identical or different passive device may be had, or one or more identical or different chip.
First loses money instead of making money in the gap that the dress chip of layer 102 and circuit arrange between wafer 101 and is provided with inserts to form the first underfill, and then to avoid in the follow-up envelope bed of material product reliability problems such as interior void.Described inserts can be the good fluidity of macromolecule epoxy resin, this material, fully can fill the gap between flip-chip and the envelope bed of material.
The first envelope bed of material 103 loses money instead of making money the coated sealing of each device of dress layer 102 to form fixing and protection by first, both can be used as the supporting body of subsequent technique, simultaneously also for insulating and isolating different encapsulated layer.Preferably, the material of the described first envelope bed of material 103 is epoxy resin, because the good seal performance of epoxy resin, plastotype is easy, be the preferred material of the formation first envelope bed of material 103, usually can adopt such as metaideophone, the method for compression or printing forms the first envelope bed of material 103.
First wiring layer 104 comprises the first longitudinally wiring and first laterally wiring.Wherein, the described first longitudinal wire (such as, plain conductor) of wiring for running through the described first envelope bed of material 103, arranges electrical connection between wafer 101 for realizing the first flip-chip packaged layer and circuit; Described first laterally connects up is covered on the first envelope bed of material 103 and is connected, for realizing the electrical connection between the first flip-chip packaged layer and follow-up encapsulated layer with the described first longitudinal wiring.In the present embodiment, described first longitudinally wiring and circuit to arrange the pad conducting of wafer 101 upper surface interconnected, first laterally wiring with first longitudinal connect up and the follow-up first second wiring layer conducting of connecting up in encapsulated layer interconnected.
First wiring encapsulated layer comprises and is positioned at first on the first flip-chip packaged layer successively and is just mounting layer 105, the second envelope bed of material 106, second wiring layer 107.
Described first is just mounting layer 105 also comprises multiple semiconductor device, in the present embodiment, described first is just mounting layer 105 comprises chip and passive device, and be attached on the first envelope bed of material 103 according to the supine mode of function, described first functional surfaces just mounting layer, refers to that first is just mounting the pad of the chip in layer 105 and the surface, pad place of passive device.Described first is just mounting layer 105 and first loses money instead of making money that to fill layer 102 similar, can comprise one or more identical or different chip, can also comprise one or more identical or different passive device.
Fixing and the protection first of the second envelope bed of material 106 is just mounting each device of layer 105; formed and make first just mounting the exposed packaging body of the pad of layer 105 chips and passive device, exposed chip and the pad of passive device are used for being formed the second envelope bed of material 106 in and between each encapsulated layer being electrically connected.The material forming the second envelope bed of material 106 can be identical with the material of the formation first envelope bed of material 103, namely adopts epoxy resin to form the second envelope bed of material 106.
Second wiring layer 107 comprises the second longitudinally wiring and second laterally wiring.Wherein, described second longitudinally connects up as running through the wire of the described second envelope bed of material 106 (such as, plain conductor), for realize and the first horizontal line of the first wiring layer 104 connect up between conducting interconnected, according to design requirement, described second longitudinally wiring also can be used for realizing and circuit arranges electrical connection between wafer 101; Described second laterally wiring for being covered in wire on the described second envelope bed of material 106 (such as, plain conductor), described second laterally connects up is connected to the second longitudinally wiring, for realizing the electrical connection between the first each device just mounting layer 105, in the present embodiment, particularly, described second laterally wiring and first just mounting layer 105 chips and be connected with the pad of passive device.
In practical application, selectively longitudinal wiring can be set in the envelope bed of material according to design requirement, with the electrical connection realizing between each encapsulated layer or between encapsulated layer and circuit arrangement wafer 101, because the envelope bed of material has good insulating properties, the interference between device in each encapsulated layer can be avoided.
Top flip-chip packaged layer comprises and is positioned at second on the first wiring encapsulated layer successively and loses money instead of making money dress layer 108, second underfill, the 3rd envelope bed of material 109.
Described second loses money instead of making money dress layer 108 and first loses money instead of making money that to fill layer 102 similar, can comprise one or more identical or different chip, can also comprise one or more identical or different passive device.In the present embodiment, the second attachment layer 108 chips achieve through its solder bump and the second wiring layer 107 second laterally connect up between conducting interconnected.
Second loses money instead of making money in the dress chip of layer 108 and the first gap of connecting up between encapsulated layer and is provided with inserts to form the second underfill.Similar to the first underfill, described second underfill is also the product reliability problem such as interior void in the envelope bed of material, and meanwhile, the materials and methods forming the second underfill can be identical with the first underfill.
Each device that dress layer 108 is lost money instead of making money in the coated sealing of the 3rd envelope bed of material 109 second forms packaging body, to avoid pollution and the erosion of external environment.The material forming the 3rd envelope bed of material 109 can be identical with the material of the second envelope bed of material 106 with the formation first envelope bed of material 103, namely adopts epoxy resin to form the 3rd envelope bed of material 109.
Described a kind of Three-dimensional high-integration system-in-package structure also comprises the connection ball 110 be arranged at below circuit arrangement wafer 101, and the pad that described connection ball 110 and circuit arrange wafer 101 lower surface is connected.The material forming described connection ball 110 can be the various metals such as metallic tin, ashbury metal.
A kind of Three-dimensional high-integration system-in-package structure of the present invention, circuit arranges wafer, it is adjacent to achieve between each encapsulated layer or it is interconnected to be separated by between encapsulated layer, the circuit arranging inside wafer via circuit again arranges and achieves the integration of system, eventually through connection ball by fuction output.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (6)
1. a Three-dimensional high-integration system-in-package structure, is characterized in that, comprising: circuit arranges wafer; Be positioned at circuit and arrange at least one group of flip-chip packaged layer on wafer, described flip-chip packaged layer comprises and is positioned at circuit successively and arranges first on wafer and lose money instead of making money dress layer, the first underfill, the first envelope bed of material, the first wiring layer; Be positioned at the wiring encapsulated layer more than two on flip-chip packaged layer, described wiring encapsulated layer comprises and is positioned at first on flip-chip packaged layer successively and is just mounting layer, the second envelope bed of material, the second wiring layer; Be positioned at end group wiring encapsulated layer on top flip-chip packaged layer, described top flip-chip packaged layer comprise be positioned at successively end group wiring encapsulated layer on second lose money instead of making money dress layer, the second underfill, the 3rd envelope bed of material; Be arranged at the connection ball below circuit arrangement wafer; Wherein, circuit arranges wafer, the electricity that realizes between adjacent package layer or interval encapsulated layer through wiring layer between each encapsulated layer is interconnected;
Described first wiring layer comprises and runs through first of the first envelope bed of material and longitudinally connect up, be covered on the first envelope bed of material and connect up with described first the first transverse direction be connected that longitudinally connect up;
The described second envelope bed of material is filled in described first and is just mounting between each semiconductor device of layer, the described second envelope bed of material of part is also covered in described first and is just mounting on the semiconductor device of layer, the upper surface of the described second envelope bed of material flushes with the top of the link of semiconductor device, to expose the link that described first is just mounting semiconductor device in layer; Often group attachment layer side is identical with the encapsulating material of end face;
Described second wiring layer comprises and runs through second of the second envelope bed of material and longitudinally connect up, be covered on the second envelope bed of material and connect up with described second the second transverse direction be connected that longitudinally connect up; In adjacent wire encapsulated layer second longitudinally wiring shifts to install.
2. a kind of Three-dimensional high-integration system-in-package structure as claimed in claim 1, is characterized in that, the solder bump in the flip-chip packaged layer of described top makes the attachment layer of top flip-chip packaged layer and end organize to be formed between the wiring layer that connects up in encapsulated layer electrically interconnected.
3. a kind of Three-dimensional high-integration system-in-package structure as described in claim as arbitrary in claim 1 ~ 2, is characterized in that: described circuit arranges wafer and is provided with upper and lower surface, and described upper and lower surface is provided with pad.
4. a kind of Three-dimensional high-integration system-in-package structure as claimed in claim 3, is characterized in that: the solder pad space length of described circuit arrangement wafer upper surface is less than the solder pad space length of lower surface.
5. a kind of Three-dimensional high-integration system-in-package structure as described in claim as arbitrary in claim 1 ~ 2, is characterized in that: described attachment layer comprises chip, and described chip is single or many.
6. a kind of Three-dimensional high-integration system-in-package structure as claimed in claim 5, is characterized in that: described attachment layer also comprises passive device, and described passive device is one or more in electric capacity, resistance or inductance.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110069846.7A CN102176446B (en) | 2011-03-22 | 2011-03-22 | A kind of Three-dimensional high-integration system-in-package structure |
| US13/984,876 US9595490B2 (en) | 2011-03-22 | 2012-03-22 | 3D system-level packaging methods and structures |
| PCT/CN2012/072765 WO2012126374A1 (en) | 2011-03-22 | 2012-03-22 | 3d system-level packaging methods and structures |
| US15/411,889 US10515883B2 (en) | 2011-03-22 | 2017-01-20 | 3D system-level packaging methods and structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110069846.7A CN102176446B (en) | 2011-03-22 | 2011-03-22 | A kind of Three-dimensional high-integration system-in-package structure |
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| Publication Number | Publication Date |
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| CN102176446A CN102176446A (en) | 2011-09-07 |
| CN102176446B true CN102176446B (en) | 2015-09-02 |
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| CN104810332A (en) * | 2015-05-05 | 2015-07-29 | 三星半导体(中国)研究开发有限公司 | Fan-out wafer level package part and manufacture method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2664198Y (en) * | 2003-08-18 | 2004-12-15 | 威盛电子股份有限公司 | Multi-chip packaging structure |
| US20070262436A1 (en) * | 2006-05-12 | 2007-11-15 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100914977B1 (en) * | 2007-06-18 | 2009-09-02 | 주식회사 하이닉스반도체 | Method for fabricating stack package |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2664198Y (en) * | 2003-08-18 | 2004-12-15 | 威盛电子股份有限公司 | Multi-chip packaging structure |
| US20070262436A1 (en) * | 2006-05-12 | 2007-11-15 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
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| CN102176446A (en) | 2011-09-07 |
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