CN201994292U - High-density system-level packaging structure - Google Patents

High-density system-level packaging structure Download PDF

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Publication number
CN201994292U
CN201994292U CN2011200776368U CN201120077636U CN201994292U CN 201994292 U CN201994292 U CN 201994292U CN 2011200776368 U CN2011200776368 U CN 2011200776368U CN 201120077636 U CN201120077636 U CN 201120077636U CN 201994292 U CN201994292 U CN 201994292U
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CN
China
Prior art keywords
wiring
layer
mounts
substrate
encapsulation structure
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Expired - Lifetime
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CN2011200776368U
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Chinese (zh)
Inventor
陶玉娟
石磊
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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Priority to CN2011200776368U priority Critical patent/CN201994292U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model relates to a high-density system-level packaging structure, which comprises a base plate, at least one group of wiring packaging layer positioned on the base plate, a wire bonding packaging layer positioned on the last group of wiring packaging layer, and a connecting ball arranged under the base plate, wherein the at least one group of wiring packaging layer comprises a wiring surface-mounting layer, a wiring packaging material layer and a wiring layer which are sequentially positioned on the base plate; the wire bonding packaging layer comprises a wire bonding surface-mounting layer, a metal wire, a top packaging material layer which are sequentially positioned on the last group of the wiring packaging layer; and between the packaging layers, and adjacent packaging layers or interval packaging layers are electrically connected through the wiring layer. Compared with the prior art, the high-density system-level packaging structure applied to be protected can form a final packaging product which contains the whole system functions instead of a single chip function, and reduces the resistance, inductance and interference factors among chips in a system. In addition, a more complex multi-layer interconnection structure can be formed, and a wafer system-level packaging with higher integration degree can be realized.

Description

The high-density systems class encapsulation structure
Technical field
The utility model relates to semiconductor technology, relates in particular to a kind of high-density systems class encapsulation structure.
Background technology
Along with the continuous development of integrated circuit technique, electronic product more and more develops to miniaturization, intellectuality, high-performance and high reliability direction.And the integrated circuit encapsulation not only directly affects integrated circuit, electronic module and even machine performance, but also is restricting miniaturization, low cost and the reliability of whole electronic system.Progressively dwindle in the integrated circuit (IC) wafer size, under the situation that integrated level improves constantly, electronics industry has proposed more and more higher requirement to the integrated circuit encapsulation technology.
In being the Chinese patent of CN1747156C, notification number discloses a kind of base plate for packaging.Described base plate for packaging comprises: substrate, and described substrate comprises a surface; Be positioned at the pad of receiving on the described substrate surface; Be formed at the welding resisting layer on the described substrate surface, described welding resisting layer comprises at least one opening, and described opening exposes the described pad of receiving; Described base plate for packaging also comprises a pattern metal strengthening course, and described pattern metal strengthening course is formed on the described pad of receiving along the sidewall of described welding resisting layer opening.
The final products of packaged manufacturing only have single chip functions according to the method described above, yet, along with improving constantly of compact trend of semiconductor product and product systems functional requirement, the integration that how further to improve system in package becomes those skilled in the art's problem demanding prompt solution.
The utility model content
The technical problem that the utility model solves is: the high-density systems level encapsulation that how to realize having sandwich construction.
For solving the problems of the technologies described above, the utility model provides the high-density systems class encapsulation structure, comprising: substrate; Be positioned at least one group of wiring encapsulated layer on the substrate, described wiring encapsulated layer comprises that the wiring that is positioned at successively on the substrate mounts layer, the wiring envelope bed of material, wiring layer; Be positioned at the wire bond package layer on the end group wiring encapsulated layer, described wire bond package layer comprises that the lead-in wire that is positioned at successively on the end group wiring encapsulated layer mounts layer, metal lead wire, the top envelope bed of material; Be arranged at the connection ball of substrate below; Wherein, see through wiring layer between the encapsulated layer and realize adjacent encapsulated layer or electric interconnected between encapsulated layer at interval.
Alternatively, described high-density systems class encapsulation structure comprises the first wiring encapsulated layer, and the described first wiring encapsulated layer comprises that being positioned at the wiring of first on the substrate successively mounts layer, the first wiring envelope bed of material, first wiring layer.
Alternatively, the described first wiring envelope bed of material is filled in first wiring and mounts in the layer between each device, and exposes the connector that described first wiring mounts each device in the layer.
Alternatively, described wiring layer comprises that running through the place seals vertical wiring of the bed of material, is covered in the horizontal wiring that the place is sealed on the bed of material and is connected in described vertical wiring.
Alternatively, described first wiring layer comprise run through the first wiring envelope bed of material and with the first vertically wiring of substrate conducting, and with described first vertically wiring is communicated with, is covered on the first wiring envelope bed of material and interconnected first wiring mounts first of device in the layer and laterally connects up.
Alternatively, described metal lead wire is interconnected with the wiring layer electricity in the end group wiring encapsulated layer with the device that lead-in wire mounts in the layer.
Alternatively, the described top envelope bed of material is filled in lead-in wire and mounts between each device of layer, and lead-in wire is mounted layer and metal lead wire coating sealing.
Alternatively, described substrate is BT substrate or PCB substrate.
Alternatively, it is characterized in that, describedly mount that the function of each device faces up in the layer.
Alternatively, described mounting comprises chip in the layer, and described chip is single or many.
Alternatively, the described layer that mounts comprises that also passive device, described passive device are one or more in electric capacity, resistance or the inductance.
Alternatively, the material of the described envelope bed of material is an epoxy resin.
Compared with prior art, the high-density systems class encapsulation structure that the utility model is asked for protection, encapsulation in the lump again after chip and passive device integrated can form and comprises the total system function but not the final encapsulating products of single chip functions; Simultaneously, see through wiring layer between the multilayer encapsulated layer and realized that more the high-density systems of 3 D stereo angle is interconnected, compare the encapsulation of existing systems level, Miltilayer wiring structure has made full use of the thickness of chip itself, satisfy that the compact trend of semiconductor packages requires and more complicated systemic-function integrate require in, reduced the disturbing factor of resistance, inductance and chip chamber in the system better, structural strength and product reliability are strengthened well.
Description of drawings
Fig. 1 is the schematic diagram of an embodiment of the utility model high-density systems class encapsulation structure.
Embodiment
A lot of details have been set forth in the following description so that fully understand the utility model.But the utility model can be implemented much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of the utility model intension, so the utility model is not subjected to the restriction of following public concrete enforcement.
Secondly, the utility model utilizes schematic diagram to be described in detail, and when the utility model embodiment was described in detail in detail, for ease of explanation, described schematic diagram was an example, and it should not limit the scope of the utility model protection at this.
The utility model provides a kind of high-density systems class encapsulation structure, comprising: substrate; Be positioned at least one group of wiring encapsulated layer on the substrate, described wiring encapsulated layer comprises that the wiring that is positioned at successively on the substrate mounts layer, the wiring envelope bed of material, wiring layer; Be positioned at the wire bond package layer on the end group wiring encapsulated layer, described wire bond package layer comprises that the lead-in wire that is positioned at successively on the end group wiring encapsulated layer mounts layer, metal lead wire, the top envelope bed of material; Be arranged at the connection ball of substrate below; Wherein, see through wiring layer between the encapsulated layer and realize adjacent encapsulated layer or electric interconnected between encapsulated layer at interval.
Below in conjunction with accompanying drawing embodiment of the present utility model is described in detail.
With reference to figure 1, show the schematic diagram of the utility model high-density systems class encapsulation structure one execution mode, in the present embodiment, described a kind of high-density systems class encapsulation structure is an example with two groups of wiring encapsulated layers and wire bond package layer, but the utility model does not limit therewith, and described a kind of high-density systems class encapsulation structure comprises: substrate 101, be positioned at first on the substrate 101 wiring encapsulated layer, be positioned at the second wiring encapsulated layer on the first wiring encapsulated layer, be positioned at wire bond package layer on the second wiring encapsulated layer, be arranged at the connection ball 110 of substrate 101 belows.Wherein,
Substrate 101 is follow-up basis of piling up each package group, simultaneously, also is the basis of follow-up each layer encapsulated layer of carrying.Described substrate 101 comprises two function faces, wherein, the first surface of described substrate 101 is used to carry out piling up of encapsulated layer, the second surface of described substrate 101 is used to plant ball (implant and connect ball), in the present embodiment, the upper surface of described substrate 101 is used to carry out piling up of encapsulated layer, and the upper surface of described substrate 101 is provided with and is used to realize that the pad that is electrically connected, the lower surface of described substrate 101 are used for implanting connects ball.Particularly, described substrate 101 be generally BT (Bismaleimide Triazine) substrate or printed circuit board (PCB) (Printed Circuit Board, PCB) etc. so that between the first surface of substrate 101 and second surface, carry out cabling.Described substrate 101 comprises the connection cabling that runs through described substrate 101, and described connection cabling can make pad and be connected ball realization electrical connection.
In order better to be fixed in encapsulation place on the substrate 101, preferably, described high-density systems class encapsulation structure also comprises the cementing layer that is attached on the substrate 101, described cementing layer is used for that first wiring is mounted layer 103 and is attached at substrate 101, the available material of described cementing layer has multiple, can be by methods such as some glue or printings when forming cementing layer on the substrate 101.Described method is well known to those skilled in the art in field of semiconductor manufacture, does not repeat them here.
Comprise in the first wiring encapsulated layer that being positioned at the wiring of first on the substrate 101 successively mounts layer 102, the first wiring envelope bed of material 103, first wiring layer 104.Wherein,
Described first wiring mounts layer 102 and comprises multiple semiconductor device, in the present embodiment, described first wiring mounts layer 102 and comprises chip and passive device, and be attached on the substrate 101 by cementing layer according to the supine mode of function, described first wiring mounts layer 102 function face, is meant that first wiring mounts the chip in the layer 102 and the surface, pad place of passive device.
In a preferred embodiment of the present utility model, be arranged at first on the substrate 101 wiring and mount layer 102 and follow-up mounting layer and can comprising one or more identical or different chips of mentioning, can also comprise one or more identical or different passive devices.These chips and passive device become the part of a system in package product separately, finish the one or more independent function that realizes in the system level function separately.
In a preferred embodiment of the present utility model, first wiring mount layer in 102 chip and the combination of passive device dispose according to systemic-function.Therefore, around one or a core assembly sheet, have identical or different other one or a core assembly sheet, passive devices such as perhaps identical or different electric capacity, resistance or inductance; Similarly, around a passive device, has the passive device of identical or different other, perhaps one or more identical or different chips.
The first wiring envelope bed of material 103 is used to insulate and isolate each device that first wiring mounts layer 102, simultaneously, also is used for insulation and isolates different encapsulated layers.The described first wiring envelope bed of material 103 is filled in first wiring and mounts between each device of layer 102, and, the part first wiring envelope bed of material 103 is covered in described first wiring and mounts on each device of layer 102, the described first wiring envelope bed of material 103 exposes the connector that described first wiring mounts layer 102 each device, concrete, the bond pad surface of the described first wiring envelope bed of material 103 exposed chips and passive device group is so that electrically connect.
Because the first wiring envelope bed of material 103 is filled in first wiring and mounts between the device of layer 102, and expose the connector of each device, therefore to mount layers 102 thickness suitable for the thickness of the first wiring envelope bed of material 103 and first wiring, can reduce respectively to mount the stack thickness of layer, improve the integration of encapsulating structure to greatest extent.
First wiring layer 104 comprises the first vertically laterally wiring of wiring and first.Wherein, described first vertically wiring be used to realize being electrically connected of the first wiring encapsulated layer and 101 of substrates for running through the lead (for example, plain conductor) of the described first wiring envelope bed of material 103.
In actual applications, can in the envelope bed of material, form vertically wiring selectively according to design requirement, to realize respectively mounting between the layer or to mount electrical connection between layer and the substrate,, can avoid respectively mounting the interference between each device in the layer because the envelope bed of material has good insulation performance.
Described first laterally wiring for be covered on the described first wiring envelope bed of material 103 lead (for example, plain conductor) and with first vertical wiring conducting link to each other, be used to realize first electrical connection of connecting up between the device that mounts layer 102, in the present embodiment, described first laterally connects up is used to realize that first wiring mounts the electrical connection between layer 102 chips and the passive device, particularly, the described first horizontal wiring links to each other with the bond pad surface of chip and passive device.
The second wiring encapsulated layer is stacked on the first wiring encapsulated layer, particularly, comprising: second wiring that is positioned at successively on the first wiring encapsulated layer mounts layer 105, the second wiring envelope bed of material 106 and second wiring layer 107.In the present embodiment, described second wiring mounts layer 105 and comprises chip and passive device, and is stacked on the first wiring envelope bed of material 103 according to the supine mode of function.Described second wiring mounts layer 105 and first wiring and mounts layers 102 similarly, can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices.
The second wiring envelope bed of material 106 is used to insulate and isolate each device that second wiring mounts layer 105, simultaneously, also is used for insulation and isolates different encapsulated layers.The described second wiring envelope bed of material 106 is filled in second wiring and mounts between each device of layer 105, and, the part second wiring envelope bed of material 106 is covered in described second wiring and mounts on each device of layer 105, the described second wiring envelope bed of material 106 exposes the connector that described second wiring mounts layer 106 each device, concrete, the bond pad surface of the described second wiring envelope bed of material 106 exposed chips and passive device group is so that electrically connect.
Second wiring layer 107 comprises the second vertically laterally wiring of wiring and second.Wherein, described second vertical wiring is (for example to run through the lead of the described second wiring envelope bed of material 106, plain conductor), be used to realize being electrically connected between the second wiring encapsulated layer and other encapsulated layers, according to design requirement, described second vertical wiring also is used to realize second electrical connection of connecting up between encapsulated layer and the substrate 101;
Described second laterally wiring for be covered on the described second wiring envelope bed of material 106 lead (for example, plain conductor), described second laterally connects up is connected in the second vertically wiring, be used to realize second electrical connection of connecting up between the device that mounts layer 105, in the present embodiment, described second laterally connects up is used to realize that second wiring mounts the electrical connection between layer 105 chips and the passive device group, and particularly, the described second horizontal wiring links to each other with the bond pad surface of chip and passive device.
The wire bond package layer comprises that the lead-in wire that is positioned at successively on the second wiring encapsulated layer mounts layer 108, metal lead wire 109, the top envelope bed of material 110.
It is similar with the above-mentioned layer that mounts that described lead-in wire mounts layer 108, can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices.In the present embodiment, lead-in wire mounts in the layer 108 and comprises chip, and is mounted on the second wiring envelope bed of material 106 according to the supine mode of function.
It is electrically interconnected that metal lead wire 109 in the described wire bond package layer mounts layer 108 and second wiring layer 107 formation at lead-in wire.In the present embodiment, particularly, it is interconnected that described metal lead wire 109 mounts the conducting of laterally connecting up of the chip bonding pad of layer in 109 and second of second wiring layer 107 with lead-in wire.
The top envelope bed of material 110 coats each device and the metal lead wire 109 formation packaging bodies that sealing wire mounts layer 108, with pollution and the erosion of avoiding external environment.The material that forms the top envelope bed of material 110 can be identical with the material that forms the first wiring envelope bed of material 103 and the second wiring envelope bed of material 106, promptly adopts epoxy resin to form the top envelope bed of material 110.
Described high-density systems class encapsulation structure also comprises the connection ball 111 that is arranged at substrate 101 belows, and described connection ball 111 is arranged in substrate 101 and connects the corresponding position of cabling, links to each other with the pad of substrate 101 by the connection cabling in the substrate 101.
Comprise two groups of wiring encapsulated layers and wire bond package layer in the foregoing description, but the utility model is not restricted to this, can also be one or more groups wiring encapsulated layer top encapsulation layer of arranging in pairs or groups, those skilled in the art can correspondingly be out of shape, revise and replace according to the foregoing description.
The utility model high-density systems class encapsulation structure, realized adjacent by each wiring layer or the electrical connection between encapsulated layer of being separated by between each encapsulated layer, realized the integration of system again via the connection cabling arrangement of substrate 101 inside, the final connection ball 111 that passes through is exported function.
Though the utility model discloses as above with preferred embodiment, the utility model is not to be defined in this.Any those skilled in the art in not breaking away from spirit and scope of the present utility model, all can do various changes and modification, and therefore protection range of the present utility model should be as the criterion with claim institute restricted portion.

Claims (12)

1. the high-density systems class encapsulation structure is characterized in that, comprising:
Substrate; Be positioned at least one group of wiring encapsulated layer on the substrate, described wiring encapsulated layer comprises that the wiring that is positioned at successively on the substrate mounts layer, the wiring envelope bed of material, wiring layer; Be positioned at the wire bond package layer on the end group wiring encapsulated layer, described wire bond package layer comprises that the lead-in wire that is positioned at successively on the end group wiring encapsulated layer mounts layer, metal lead wire, the top envelope bed of material; Be arranged at the connection ball of substrate below; Wherein, see through wiring layer between the encapsulated layer and realize adjacent encapsulated layer or electric interconnected between encapsulated layer at interval.
2. high-density systems class encapsulation structure as claimed in claim 1, it is characterized in that, described high-density systems class encapsulation structure comprises the first wiring encapsulated layer, and the described first wiring encapsulated layer comprises that being positioned at the wiring of first on the substrate successively mounts layer, the first wiring envelope bed of material, first wiring layer.
3. high-density systems class encapsulation structure as claimed in claim 2 is characterized in that, the described first wiring envelope bed of material is filled in first wiring and mounts in the layer between each device, and exposes the connector that described first wiring mounts each device in the layer.
4. high-density systems class encapsulation structure as claimed in claim 1 is characterized in that, described wiring layer comprises that running through the place seals vertical wiring of the bed of material, is covered in the horizontal wiring that the place is sealed on the bed of material and is connected in described vertical wiring.
5. high-density systems class encapsulation structure as claimed in claim 2, it is characterized in that, described first wiring layer comprise run through the first wiring envelope bed of material and with the first vertically wiring of substrate conducting, and with described first vertically wiring is communicated with, is covered on the first wiring envelope bed of material and interconnected first wiring mounts first of device in the layer and laterally connects up.
6. high-density systems class encapsulation structure as claimed in claim 1 is characterized in that, described metal lead wire is interconnected with the wiring layer electricity in the end group wiring encapsulated layer with the device that lead-in wire mounts in the layer.
7. high-density systems class encapsulation structure as claimed in claim 1 is characterized in that, the described top envelope bed of material is filled in lead-in wire and mounts between each device of layer, and lead-in wire is mounted layer and metal lead wire coating sealing.
8. high-density systems class encapsulation structure as claimed in claim 1 is characterized in that: described substrate is BT substrate or PCB substrate.
9. as the described high-density systems class encapsulation structure of the arbitrary claim of claim 1～7, it is characterized in that, describedly mount that the function of each device faces up in the layer.
10. as the described high-density systems class encapsulation structure of the arbitrary claim of claim 1～7, it is characterized in that: described mounting comprises chip in the layer, described chip is single or many.
11. high-density systems class encapsulation structure as claimed in claim 10 is characterized in that: the described layer that mounts comprises that also passive device, described passive device are one or more in electric capacity, resistance or the inductance.
12. as the described high-density systems class encapsulation structure of the arbitrary claim of claim 1～7, it is characterized in that: the material of the described envelope bed of material is an epoxy resin.
CN2011200776368U 2011-03-22 2011-03-22 High-density system-level packaging structure Expired - Lifetime CN201994292U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102157502A (en) * 2011-03-23 2011-08-17 南通富士通微电子股份有限公司 System-in-package structure
WO2012126379A1 (en) * 2011-03-23 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. Three-dimensional system-level packaging methods and structures
CN108431952A (en) * 2015-10-12 2018-08-21 英帆萨斯公司 Embedded wire bonding line

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102157502A (en) * 2011-03-23 2011-08-17 南通富士通微电子股份有限公司 System-in-package structure
WO2012126379A1 (en) * 2011-03-23 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. Three-dimensional system-level packaging methods and structures
CN102157502B (en) * 2011-03-23 2014-05-07 南通富士通微电子股份有限公司 System-in-package structure
CN108431952A (en) * 2015-10-12 2018-08-21 英帆萨斯公司 Embedded wire bonding line

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