CN100559582C - Chip stack package structure and manufacture method thereof - Google Patents
Chip stack package structure and manufacture method thereof Download PDFInfo
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- CN100559582C CN100559582C CNB2007101058298A CN200710105829A CN100559582C CN 100559582 C CN100559582 C CN 100559582C CN B2007101058298 A CNB2007101058298 A CN B2007101058298A CN 200710105829 A CN200710105829 A CN 200710105829A CN 100559582 C CN100559582 C CN 100559582C
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 121
- 239000011347 resin Substances 0.000 claims description 15
- 229920005989 resin Polymers 0.000 claims description 15
- 238000007789 sealing Methods 0.000 claims description 15
- 239000000853 adhesive Substances 0.000 claims description 2
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- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 18
- 239000000758 substrate Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 6
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- 230000015572 biosynthetic process Effects 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention provides a kind of chip stack package structure and manufacture method thereof, this encapsulating structure comprises: base material, first chip, circuit base plate and second chip.Wherein this base material has first surface and opposing second surface, and first chip is positioned at the first surface of base material, and first chip has first active surface and the first relative brilliant back of the body, and electrically connects with flip chip bonding encapsulation juncture with base material.Be formed at the circuit base plate of the first brilliant back, comprise the dielectric layer that is disposed at the first brilliant back, and be formed at the patterned line layer on the dielectric layer, and make patterned line layer and base material electrically connect by routing.Second chip is positioned on the patterned line layer, has second active surface and is disposed at least one second weld pad on second active surface, and wherein weld pad and patterned line layer electrically connect, again via routing and base material electric connection.
Description
Technical field
The present invention relates to a kind of semiconductor package, and relate in particular to a kind of stack package structure and manufacture method thereof.
Background technology
Along with the rapid increase of electronic product function and demands of applications, encapsulation technology also develops to the direction of three dimension scale to the encapsulation of multicore sheet, two-dimentional yardstick towards high density microminiaturization, single-chip package.A kind of preferred approach of integrating different circuit function chips of wherein systematization encapsulation technology (System In Package) is utilized surface adhering (Surface Mount Technology; SMT) technology is integrated in different chip stacks on the same substrate, so as to effective reduction package area.Have that volume is little, high frequency, at a high speed, with short production cycle and advantage cheaply.
Please refer to Fig. 4, the section of structure of Fig. 4 for being illustrated according to an existing chip stack package structure 400.Chip stack package structure 400 comprises substrate 410, first chip 420, second chip 430 and many routings 440 and 450.Wherein first chip 420 is fixedly arranged on the base material 410, and electrically connects by routing 440 and base material 410.Second chip 430 is stacked on first chip 420, and electrically connects by routing 450 and substrate 410.
Yet owing to stack on the chip on upper strata, for example second chip 430 must yield to routing (routing 440) configuration of lower floor's chip (first chip 420), so upper strata chip (second chip 430) size must be less than lower floor's chip.Therefore the quantity and the elasticity of chip stack have also been limited.Because the size of upper strata chip is less, must prolongs and make a call to 450 distribution length and enlarge its bank again, itself and base material 410 are electrically connected.When carrying out stamping technique, those routings that are extended are subjected to detrusion easily, and the phenomenon of short circuit occurs, influence the technology yield when follow-up.
Please refer to Fig. 5, the section of structure of Fig. 5 for being illustrated according to another kind of chip stack package structure 500.Chip stack package structure 500 comprise substrate 510, first chip 520, second chip 530, many routings 540 and 550 and be positioned at first chip 520 and second chip 530 between virtual chip 560.Wherein first chip 520 stacks on the substrate 510, and by routing 540 first weld pad 570 and base material 510 is electrically connected; Virtual chip 560 stacks on first chip 520; Second chip then stacks on the virtual chip 560, and by routing 550 second weld pad 580 and base material 510 is electrically connected.By the setting of size less than the virtual chip 560 of first chip 520, not only can be between first chip 520 and second chip 530, enough wiring space and bank height are provided, holding routing 540, and can not limit the upper strata chip storehouse size of (second chip 530).Therefore the size essence of second chip 530 equals the size of first chip 520.
Yet the setting of virtual chip not only can increase the thickness of chip stack, and increase the technology cost on foot, has more limited assembling structure microminiaturization and highdensity trend.
Therefore, have and a kind of yield height need be provided, technology is cheap and can not limits the chip stack package structure of packaging density.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of chip stack package structure bag to solve the problem that routing distribution length is long and bank is excessive that electrically connects upper strata chip and base material in the existent technique, seals and the not high problem of packaging density thereby solve prior art chip stack package structure yield.
For achieving the above object, this chip stack package structure comprises: base material, first chip, circuit base plate, second chip and sealing resin (molding compound).Wherein this base material has first surface and opposing second surface, and first chip is positioned at the first surface of base material, first chip has first active surface and the relative first brilliant back of the body, the first active surface faces substrate, and electrically connect with flip chip bonding encapsulation juncture with base material.The circuit base plate that is positioned at the first brilliant back comprises the dielectric layer that is disposed at the first brilliant back, and is formed at the patterned line layer on the dielectric layer, and makes patterned line layer and base material electrically connect by routing.Second chip is positioned on the patterned line layer, has second active surface and is disposed at least one second weld pad on second active surface, and wherein second weld pad and patterned line layer electrically connect, again via routing and base material electric connection.The sealing resin then is filled between base material, first chip, circuit base plate and second chip, last forms a plurality of outside terminals in the second surface of base material again, and these outside terminals are preferable can be, for example the tin ball.By these outside terminals, get so that chip stack package structure is electrically connected to other external circuit.
Another purpose of the present invention is providing a kind of manufacture method of chip stack package structure, to solve the problem that routing distribution length is long and bank is excessive that electrically connects upper strata chip and base material in the existent technique, seal and the not high problem of packaging density thereby solve prior art chip stack package structure yield.
For achieving the above object, the manufacture method of this chip stack package structure, comprise the steps: at first to provide a base material, wherein this base material has first surface and opposing second surface, first surface in base material disposes first chip, and first active surface of the first chip faces substrate and base material are electrically connected with the flip chip bonding packaged type.Then, in the first brilliant back formation circuit base plate of first chip with respect to first active surface, circuit base plate is comprised be positioned at the dielectric layer of brilliant back, and be formed at patterned line layer on the dielectric layer, wherein patterned line layer comprises at least one lead, electrically mates with at least one second weld pad of desiring to be stacked over second chip on the patterned line layer.Then, form at least one routing, so as to electrically connect patterned line layer and base material.Configuration second chip on patterned line layer again, and make the weld pad of second chip be electrically connected to the lead of patterned line layer, again via routing and base material electric connection.Then, use adhesive body encapsulation base material, first chip, circuit base plate and second chip, form a plurality of outside terminals in the second surface of base material more at last, these outside terminals are preferable can be, for example the tin ball.By these outside terminals, get so that chip stack package structure is electrically connected to other external circuit.
According to above-described embodiment, technical characterictic of the present invention forms a patterned line layer at the brilliant back of lower floor's chip of flip chip bonding encapsulation storehouse, and the wiring of patterned line layer and the weld pad of follow-up storehouse upper strata chip are thereon electrically mated.Then, again flip-chip encapsulation in upper strata is stacked on the patterned line layer.By the wiring of patterned line layer, the routing position of the weld pad of upper strata chip is redistributed, make its edge that is dispersed to the upper strata chip, by routing patterned line layer and base material are electrically connected again.Whereby, solve in the prior art, electrically connect the problem that routing distribution length is long and bank is excessive of upper strata chip and base material.
Therefore, by technical advantage provided by the present invention, can solve existing chip stack package structure yield envelope and the not high problem of packaging density.
Description of drawings
State with other purpose, feature, advantage and embodiment and can become apparent on the present invention for allowing, being described in detail as follows of appended accompanying drawing:
The generalized section of the chip stack package structure 100 that Fig. 1 is illustrated for first preferred embodiment according to the present invention;
The generalized section of the chip stack package structure 200 that Fig. 2 is illustrated for second preferred embodiment according to the present invention;
The generalized section of the chip stack package structure 300 that Fig. 3 is illustrated for the 3rd preferred embodiment according to the present invention;
The section of structure of Fig. 4 for being illustrated according to a known chip stack package structure 400;
The section of structure of Fig. 5 for being illustrated according to another kind of chip stack package structure 500.
Wherein, Reference numeral:
100: chip stack package structure 101: base material
103: the first active surfaces of 102: the first chips
104: the first brilliant back ofs the body 105: patterned line layer
105a: lead 105b: lead
106: 107: the second chips of routing
109: the second weld pads of 108: the second active surfaces
110: projection 111: external connection terminals
113: projection
114: 115: the first weld pads of primer
116: base material first surface 117: the base material second surface
120: sealing resin 123: circuit base plate
124: the routing tie point
200: chip stack package structure 201: base material
203: the first active surfaces of 202: the first chips
204: the first brilliant back ofs the body 205: patterned line layer
205a: lead 205b: lead
206: 207: the second chips of routing
210: projection 211: external connection terminals
213: projection 214: primer
215: weld pad 216: radiating fin
217: run through opening 218: the base material first surface
219: base material second surface 220: the sealing resin
223: circuit base plate 224: the routing tie point
300: chip stack package structure
301: 302: the first chips of base material
304: the first brilliant back ofs the body of 303: the first active surfaces
305: patterned line layer 305a: lead
305b: lead 306: routing
308: the second active surfaces of 307: the second chips
309: weld pad 310: projection
311: external connection terminals 313: projection
314: primer 315: weld pad
316: base material first surface 317: run through opening
318: routing 319: the base material second surface
320: sealing resin 323: circuit base plate
324: routing tie point 400: chip stack package structure 410: substrate
430: the second chips of 420: the first chips
440: routing 450: routing
510: 520: the first chips of substrate
550: routing 560: virtual chip
570: weld pad 580: weld pad
Embodiment
State with other purpose, feature, advantage and embodiment and can become apparent on the present invention for allowing, the spy provides several chip stack package structures to further specify as preferred embodiment.
Please refer to Fig. 1, the generalized section of the chip stack package structure 100 that Fig. 1 is illustrated for first preferred embodiment according to the present invention.
Chip stack package structure 100 comprises: base material 101 first chips 102, circuit base plate 123, second chip 107 and sealing resin 120.
One base material 101 at first is provided, and this base material has a first surface 116 and opposing second surface 117.Among preferred embodiment of the present invention, base material 101 is made of lead frame (Lead Frame), printed circuit board (PCB) (Printing Circuit Board) or crystal grain carrier (Carrier).And among present embodiment, base material 101 is a printed circuit board (PCB), and its material for example is BT or FR4 circuit board or other flexible circuit board.
Then the encapsulation of first chip, 102 flip chip bondings is engaged in the first surface of base material 101, first active surface 103 of first chip, 102 faces substrate 101 and base material 101 are electrically connected.Among present embodiment, first chip 102 has the first brilliant back of the body 104 relative with first active surface 103 in addition, and first active surface 103 has a plurality of first weld pads 115, and by a plurality of projections 113, these first weld pads 115 and base material 101 is electrically connected.In addition, after first chip 102 is stacked on the first surface of base material 101, also comprise and use a primer 114 that projection is coated, and so as to first active surface 103 being fixed in the first surface 118 of base material 101.
Then, on the first brilliant back of the body 104 of first chip 102, form a circuit base plate 123.Wherein circuit base plate 123 comprises the dielectric layer 120 that is positioned on the first brilliant back of the body 104, and is formed at the patterned line layer 105 on the dielectric layer 120, and makes patterned line layer 105 and base material 101 electrically connects by at least one routing 106.Therefore, as shown in Figure 1, routing 106 has routing tie point 124 with patterned line layer 105.Patterned line layer 105 is a rerouting line layer (Redistribution-Layer, RDL), and patterned line layer 105 comprises many leads, for example lead 105a and 105b, one end of each bar lead (for example lead 105a), one second weld pad 109 that designs in second chip 107 that is used for and is about to stacking on the patterned line layer 105 electrically mates, and the other end then extends toward other position of the first brilliant back of the body 104, and for example the edge of the past brilliant back of the body extends.
Then, second chip 107 is electrically connected at patterned line layer 105 with flip chip bonding encapsulation juncture.Second chip 107 has second active surface 108 and is disposed at second weld pad 109 on second active surface 108, and wherein each second weld pad 109 is by tin ball or conductive projection 110, electrically connects with the lead 105a or the 105b of patterned line layer 105.Among other embodiment, patterned line layer 105 can cooperate the weld pad configuration change Wiring pattern of different chips.As shown in Figure 1, because 107 chip bondings of second chip are on patterned line layer 105, and second weld pad 109 on second active surface 108 of second chip 107 sees through projection 110 and electrically connects with patterned line layer 105, therefore the routing tie point 124 on the patterned line layer 105 be positioned at second chip 107 second active surface 108 under.
Afterwards, use sealing resin 120 to encapsulate base material 101, first chip 102, circuit base plate 223 and second chip 107, sealing resin 120 is filled between base material 101, first chip 102, circuit base plate 223 and second chip 107.Last form a plurality of external connection terminals 111 in the second surface 117 of base material 101 again, these outside terminals 111 are preferable can be, for example the tin ball.By these external connection terminals 111, get so that chip stack package structure 100 is electrically connected to other external circuit.
Because at least one second weld pad 109 meetings of second chip 107 and wherein lead of patterned line layer 105, for example lead 105a or 105b electrically mate, therefore, when having with the mutual storehouse of second chip 107 of first chip, 102 same sizes and first chip 102, the lead of patterned line layer 105 can be with original second weld pad, 109 rewirings near second chip, 107 centers, make it be dispersed to other position of second chip 107, for example be dispersed to the edge of second chip 107, make second weld pad 109 and base material 101 electrically connects via routing 106 again.
Please refer to Fig. 2, the generalized section of the chip stack package structure 200 that Fig. 2 is illustrated for second preferred embodiment according to the present invention.
Chip stack package structure 200 comprises: base material 201, first chip 202, circuit base plate 223, second chip 207, sealing resin 220.
At first provide base material 201, and this base material 201 has first surface 218 and with respect to the second surface 219 of first surface 218.Among preferred embodiment of the present invention, base material 201 is preferable to be made of lead frame, printed circuit board (PCB) or crystal grain carrier.And among present embodiment, base material 201 is a crystal grain carrier, and its material for example is BT or FR4 circuit board or other flexible circuit board.
Then on base material 201, form one and run through opening 217.Again the encapsulation of first chip, 202 flip chip bondings is engaged in the first surface 218 of base material 201, first active surface 203 of first chip, 202 faces substrate 201 and base material 201 are electrically connected.In the present embodiment, first chip 202 has the first brilliant back of the body 204 relative with first active surface 203 in addition, and first active surface 203 has a plurality of first weld pads 215, and these first weld pads 215 then electrically connect by a plurality of projections 213 and base material 201.In addition, among present embodiment, after the encapsulation of first chip, 202 flip chip bondings is engaged in the first surface 218 of base material 201, also comprise and use primer 214 that a plurality of projections 213 are coated, and so as to first active surface 203 is fixed on the first surface 218 of base material 201.
Because first active surface 203 of some can come out by the opening 217 that runs through of base material 201.Therefore among present embodiment, also be included in and form a radiating fin 216 on first active surface 203, make it and run through opening 217 to stretch out, increase the radiating effect of chip stack package structure 200 whereby via this.
Then, on the first brilliant back of the body 204 of first chip 202, form a circuit base plate 223.Wherein circuit base plate 223 comprises the dielectric layer 220 that is positioned on the first brilliant back of the body 204, and is formed at the patterned line layer 205 on the dielectric layer 220, and makes patterned line layer 205 and base material electrically connect by at least one routing 206.Therefore, as shown in Figure 2, routing 206 has routing tie point 224 with patterned line layer 205.Patterned line layer 205 1 rerouting line layers.And patterned line layer 205 comprises many leads, for example lead 205a and 205b, an and end of each bar lead (for example lead 205a), second chip, 207 one of them second weld pad 209 that design is used for and is about to stacking on the patterned line layer 205 electrically mate, the other end then extends toward other position of the first brilliant back of the body 204, and for example the edge toward the first brilliant back of the body 204 extends.
Again second chip 207 is electrically connected at patterned line layer 205 with flip chip bonding encapsulation juncture.Second chip 207 has second active surface 208 and is disposed at second weld pad 209 on second active surface 208, and wherein at least one second weld pad 209 electrically connects by tin ball or conductive projection 210 lead 205a or the 205b with patterned line layer 205.Among other embodiment, patterned line layer 205 can cooperate the weld pad configuration change Wiring pattern of different chips.As shown in Figure 2, because 207 chip bondings of second chip are on patterned line layer 205, and second weld pad 209 on second active surface 208 of second chip 207 sees through projection 210 and electrically connects with patterned line layer 205, therefore the routing tie point 224 on the patterned line layer 205 be positioned at second chip 207 second active surface 208 under.
Afterwards, use sealing resin 220 to encapsulate base material 201, first chip 202, circuit base plate 223 and second chip 207, sealing resin 220 is filled between base material 201, first chip 202, circuit base plate 223 and second chip 207.Last again in a plurality of outside terminals 211 of second surface 219 formation of base material 201, these outside terminals are preferable can be, for example the tin ball.By these outside terminals 211, get so that chip stack package structure 200 is electrically connected to other external circuit.
Because at least one second weld pad, 209 meeting of second chip 207 and wherein lead of patterned line layer 205, for example lead 205a or 205b electrically mate, therefore, when having with the mutual storehouse of second chip 207 of first chip, 202 same sizes and first chip 202, the lead of patterned line layer 205 can be with original second weld pad, 209 rewirings near second chip, 207 centers, make it be dispersed to other position of second chip 207, for example be dispersed to the edge of second chip 207, make second weld pad 209 and base material 201 electrically connects via routing 206 again.
Please refer to Fig. 3, the generalized section of the chip stack package structure 300 that Fig. 3 the 3rd preferred embodiment according to the present invention is illustrated.
Chip stack package structure 300 comprises: base material 301, first chip 302, circuit base plate 323, second chip 307, sealing resin 320.
Then on base material 301, form one and run through opening 317.Again the encapsulation of first chip, 302 flip chip bondings is engaged in the first surface 316 of base material 301, first active surface 303 of first chip, 302 faces substrate 301 and base material 301 are electrically connected.
Among present embodiment, first active surface 303 also has the first brilliant back of the body 304 relative with first active surface 303, and the run through opening 317 of first active surface 303 of a part by base material 301 comes out.First chip 302 has a plurality of first weld pad, 309 first weld pads 309, is arranged in first active surface 303 by running through the zone that opening 317 comes out.These first weld pad, 309 first weld pads 309 then by passing the routing 318 that runs through opening 317, electrically connect with base material 301.
Then, on the first brilliant back of the body 304 of first chip 302, form a circuit base plate 323.Wherein circuit base plate 323 comprises the dielectric layer 320 that is positioned on the first brilliant back of the body 304, and is formed at the patterned line layer 305 on the dielectric layer 320, and makes patterned line layer 305 and base material 301 electrically connects by at least one routing 306.Therefore, as shown in Figure 3, routing 306 has routing tie point 324 with patterned line layer 305.Patterned line layer 305 is a rerouting line layer.And patterned line layer 305 comprises many leads, for example lead 305a and 305b, and one second weld pad 309 that an end of each bar lead (for example lead 305a) design is used for and is about to stacking in second chip 307 on the patterned line layer 305 electrically mate, and the other end for example is the first brilliant back of the body edge extension toward other position of the first brilliant back of the body 304 then.
Again second chip 307 is electrically connected at patterned line layer 305 with flip chip bonding encapsulation juncture.Second chip 307 has second active surface 308 and is disposed at second weld pad 309 on second active surface 308, and wherein at least one second weld pad 309 electrically connects by tin ball or conductive projection 310 lead 305a or the 305b with patterned line layer 305.Among other embodiment, patterned line layer 305 can cooperate the weld pad configuration change Wiring pattern of different chips.As shown in Figure 3, because 307 chip bondings of second chip are on patterned line layer 305, and second weld pad 309 on second active surface 308 of second chip 307 sees through projection 310 and electrically connects with patterned line layer 305, therefore the routing tie point 324 on the patterned line layer 305 be positioned at second chip 307 second active surface 308 under.Afterwards, use sealing resin 320 to encapsulate base material 301, first chip 302, circuit base plate 323 and second chip 307, sealing resin 320 is filled between base material 301, first chip 302, circuit base plate 323 and second chip 307, last again in a plurality of outside terminals 311 of second surface 319 formation of base material 301, these outside terminals are preferable can be, for example the tin ball.And by these outside terminals 311, chip stack package structure 300 can be electrically connected to other external circuit.
Because each second weld pad, 309 meeting of second chip 307 and wherein lead of patterned line layer 305, for example lead 305a or 305b mate, therefore when having with the mutual storehouse of second chip 307 of first chip, 302 same sizes and first chip 102, the lead of patterned line layer 305 can be with original second weld pad, 309 rewirings near second chip, 307 centers, make it be dispersed to other position of second chip 307, for example be dispersed to the edge of second chip 307, make second weld pad 309 and base material electrically connect via routing 306 again.
Not only shorten length of wire bonding and the bank be used between electrically connect upper strata chip and the base material whereby, can also cooperate the weld pad design of upper layer chip not to change wiring in the electrical pattern line layer, to improve the process flexibility of storehouse encapsulation.Owing to need not to use virtual chip, also can significantly reduce storehouse thickness degree and technology cost, improve packaging density simultaneously.
According to above-described embodiment, technical characterictic of the present invention is the brilliant back at lower floor's chip of flip chip bonding encapsulation storehouse, form a circuit base plate, make the wiring of patterned line layer and the weld pad coupling of follow-up storehouse upper strata chip thereon with patterned line layer.Then, again flip-chip encapsulation in upper strata is stacked on the patterned line layer.By the wiring of patterned line layer, the routing position of the weld pad of upper strata chip is redistributed, make its edge that is dispersed to the upper strata chip, by routing patterned line layer and base material are electrically connected again.
Therefore, by technical advantage provided by the present invention, can solve chip stack package structure yield envelope and the not high problem of packaging density that existing ponding spreads.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; being familiar with those of ordinary skill in the art ought can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (10)
1. a chip stack package structure is characterized in that, comprising:
One base material, this base material has a first surface and opposing second surface;
One first chip is positioned at the first surface of this base material, and this first chip has one first active surface, the first brilliant back of the body and at least one first weld pad relative with, and wherein this first active surface is in the face of this base material, and this first weld pad and the electric connection of this base material;
One circuit base plate is positioned at this first brilliant back, and this circuit base plate comprises:
One dielectric layer is disposed at the first brilliant back; And
One patterned line layer is formed on this dielectric layer, and by a routing and this base material electrically connect;
One second chip, be positioned on this patterned line layer, has one second active surface, and be disposed at least one second weld pad on this second active surface, wherein this second weld pad electrically connects with this patterned line layer by a plurality of first projections, electrically connect via this routing and this base material again, wherein this first chip and this second chip have same size, one bank height of this routing is lower than those first projections, and this routing and this patterned line layer have a routing tie point, and this routing tie point be positioned at this second active surface under; And
One sealing resin is filled between this base material, this first chip, this circuit base plate and this second chip.
2. stack package structure according to claim 1 is characterized in that, this first active surface has a plurality of first weld pads, and by a plurality of second projections, those first weld pads is electrically connected at this base material.
3. stack package structure according to claim 2, it is characterized in that this base material has one and runs through opening, this first active surface of the part of this first chip is come out, and dispose a radiating fin on this first active surface, and run through opening via this and stretch out.
4. stack package structure according to claim 1, it is characterized in that, this base material has one and runs through opening, this first active surface of the part of this first chip is come out, and this first active surface has a plurality of first weld pads, and is electrically connected to this base material by passing this at least one routing that runs through opening.
5. stack package structure according to claim 1 is characterized in that this patterned line layer comprises many leads, and an end of each those lead, and with the couplings and the electric connection of those second weld pads, the other end then extends toward the edge of this dielectric layer.
6. the manufacture method of a chip stack package structure is characterized in that, comprising:
One base material is provided, and this base material has a first surface and opposing second surface;
First surface in this base material disposes one first chip, and this first chip is electrically connected in the face of one first active surface and this base material of this base material;
Form a circuit base plate in this first chip with respect to one first brilliant back of this first active surface, this circuit base plate comprises a dielectric layer that is positioned at this crystalline substance back, and be formed at a patterned line layer on this dielectric layer, this patterned line layer comprises at least one lead, electrically mates with at least one second weld pad of desiring to be stacked over one second chip on this patterned line layer;
Form a dozen lines at least, so as to this patterned line layer of electrically connect and this base material;
This second chip of configuration on this patterned line layer, and make this second weld pad electrically connect this lead by a plurality of first projections, electrically connect via this routing and this base material again, wherein this first chip and this second chip have same size, one bank height of this routing is lower than those first projections, and this routing and this patterned line layer have a routing tie point, and this routing tie point be positioned at this second active surface under; And
Use an adhesive body to encapsulate this base material, this first chip, this circuit base plate and this second chip.
7. the manufacture method of stack package structure according to claim 6 is characterized in that, the step of this first chip of configuration on this base material comprises:
Form a plurality of second projections, will be positioned at a plurality of first weld pads of this first active surface, be electrically connected at this base material; And
Adopt a primer to be coated on those second projections.
8. the manufacture method of stack package structure according to claim 6 is characterized in that, provides the step of this base material also to comprise: form one and run through opening in this base material, come out in order to this first active surface with a part.
9. the manufacture method of stack package structure according to claim 8 is characterized in that, the step of this first chip of configuration comprises on this base material:
Form a plurality of second projections, will be positioned at a plurality of first weld pads of this first active surface, be electrically connected at this base material;
Adopt a primer be coated on those second projections and
Configuration one radiating fin on this first active surface, and run through opening via this and stretch out.
10. the manufacture method of stack package structure according to claim 8 is characterized in that, the step of this first chip of configuration comprises on this base material:
This first chip is fixedly arranged on the first surface of this base material, and makes a plurality of first weld pads that are positioned at this first active surface, run through opening by this and come out; And
On at least one first weld pad, form a dozen lines at least, pass this and run through opening, to be electrically connected to this base material.
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CN103179787B (en) * | 2011-12-21 | 2016-02-24 | 美新半导体(无锡)有限公司 | The encapsulating structure of three-axis sensor and method for packing thereof |
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