KR101070913B1 - Stacked die package - Google Patents

Stacked die package Download PDF

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Publication number
KR101070913B1
KR101070913B1 KR1020050042172A KR20050042172A KR101070913B1 KR 101070913 B1 KR101070913 B1 KR 101070913B1 KR 1020050042172 A KR1020050042172 A KR 1020050042172A KR 20050042172 A KR20050042172 A KR 20050042172A KR 101070913 B1 KR101070913 B1 KR 101070913B1
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South Korea
Prior art keywords
semiconductor chip
chip
formed
substrate
pad
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KR1020050042172A
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Korean (ko)
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KR20060120365A (en
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장창수
Original Assignee
삼성테크윈 주식회사
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Priority to KR1020050042172A priority Critical patent/KR101070913B1/en
Publication of KR20060120365A publication Critical patent/KR20060120365A/en
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Publication of KR101070913B1 publication Critical patent/KR101070913B1/en

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    • HELECTRICITY
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    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract

The present invention relates to a semiconductor chip stack package implemented by stacking two or more semiconductor chips including a center pad type semiconductor chip. The semiconductor chip stack package according to the present invention is formed by stacking two or more semiconductor chips including a center pad type semiconductor chip in which a chip pad is formed at a central portion of one surface thereof; A substrate on which device holes are formed, first layer semiconductor chips spaced apart from each other in a horizontal direction on the substrate, and having chip pads positioned in the device holes, and at least one second layer semiconductor chip stacked on the semiconductor chips. Equipped; The device hole and the chip pad portion are filled with an insulating material.

Description

Stacked die package

1 is a cross-sectional view showing an example of a laminated package according to the prior art.

Figure 2 is a cross-sectional view showing a chip stacked ball grid array package according to the prior art.

3 is a cross-sectional view schematically showing a semiconductor chip stack package in which center pad semiconductor chips are stacked in two layers, according to an embodiment of the present invention.

4 is a cross-sectional view schematically illustrating an example in which the size of the second layer semiconductor chip is smaller than the area occupied by the first layer semiconductor chip of the semiconductor chip stack package of FIG. 3.

FIG. 5 is a cross-sectional view schematically illustrating a semiconductor chip stack package in which a center pad semiconductor chip is stacked in two layers and a peripheral pad semiconductor chip is stacked thereon in another preferred embodiment according to the present invention.

6 is a plan view illustrating a substrate in the semiconductor chip stack package of FIGS. 3 to 5.

FIG. 7 is a schematic cross-sectional view of a semiconductor chip stack package in which a peripheral pad semiconductor chip is stacked in two layers on a center pad semiconductor chip according to another exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view schematically illustrating an example in which the size of the second layer semiconductor chip is smaller than the area occupied by the first layer semiconductor chip of the semiconductor chip stack package of FIG. 7.

FIG. 9 is a cross-sectional view schematically illustrating a semiconductor chip stack package in which peripheral pad semiconductor chips are stacked in two layers on center pad semiconductor chips according to another exemplary embodiment of the present invention.

FIG. 10 is a plan view illustrating a substrate in the semiconductor chip stack package of FIGS. 7 to 9.

<Explanation of symbols for the main parts of the drawings>

100, 200, 300, 400, 500, 600: semiconductor chip stack package,

110, 410: substrate, 111, 112, 411: device hole,

120, 130, 230, 380, 430, 530, 680: semiconductor chip,

141, 142, 343, 442, 542, 643: bonding wire,

150: package mold, 160: solder ball,

170: adhesive layer.

The present invention relates to a semiconductor package, and more particularly, to a semiconductor chip stack package implemented by stacking two or more semiconductor chips including a center pad type semiconductor chip.

Packaging technology for integrated circuit chips in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability. In addition, as the performance of electronic products increases, efforts are being made to mount a larger number of semiconductor packages on a limited size substrate. As part of this effort, what has been proposed is a stack package.

Stacked packages are designed to increase memory capacity by stacking memory chips of the same size and function, or to assemble different types of semiconductor chips of different sizes and functions into one package to maximize product performance and efficiency. . There are many types of laminated packages depending on the product to be applied and the manufacturing company. One example of a laminated package according to the prior art is shown in FIG. 1.

The stacked package 10 shown in FIG. 1 is a package stacked type in which individual packages 11 and 12 are stacked, and is a type of thin small outline package (TSOP). In the stacked package 10 of FIG. 1, each individual package 11, 12 contains one semiconductor chip 13 and uses a lead-on-chip lead frame. The inner lead 14 of the lead frame is bonded to the top surface of the semiconductor chip 13 with an adhesive tape 15 and electrically connected by the gold wire 16. The stacked individual packages 11, 12 are electrically connected to each other using separate connecting leads 17. At this time, the connection lead 17 is joined to the external lead 18 of each lead frame, and becomes the external connection terminal of the laminated package 10.

However, this type of stacked package 10 is difficult to be applied to a system such as an information and communication device that requires a small and thin because the package mounting area and height is high. In addition, the use of the lead frames 14, 17, and 18 is not suitable for high-speed device products, and the semiconductor chip 14 of the upper package 12 is more than the path from the mounting point to the semiconductor chip 13 of the lower package 11. Because of the long path to), the electrical characteristics are different.

Therefore, a ball grid array (BGA) package that uses solder balls as external connection terminals for the purpose of minimizing the surface mount area of the semiconductor package and minimizing the electrical connection length to improve electrical characteristics. Proposed. A so-called 'chip stacked ball grid array package' in which semiconductor chips are stacked in a package while basically following a ball grid array package is illustrated in FIG. 2.

As shown in FIG. 2, the chip stacked ball grid array package 20 is a chip stacked type in which individual semiconductor chips 23 and 24 are stacked inside a package mold 27, and instead of a lead frame, a printed circuit board 21 is used. ) And a solder ball 28 are used. The lower semiconductor chip 23 is adhered to the printed circuit board 21 on which the wiring 22 is formed using the adhesive 25, and the upper semiconductor chip 24 is adhered to the lower semiconductor chip 23. Each of the semiconductor chips 23 and 24 is electrically connected to the wiring 22 of the printed circuit board 21 by the gold wire 26, and solder balls 28 are formed on the bottom surface of the printed circuit board 21 to form the wiring. It is electrically connected to 22 and becomes an external connection terminal of the package 20.

However, this type of chip stacked ball grid array package 20 can only be used as a so-called 'peripheral pad type semiconductor chip'. On the active surface of the semiconductor chip such as DRAM, a plurality of chip pads 23a and 24a are formed to perform input and output to the outside, and the chip pads 23a and 24a are chip active. Peripheral pad-type semiconductor chips 23 and 24 are formed at the edge of the surface.

On the other hand, recently, the so-called 'center pad type semiconductor chip', in which chip pads are formed along the center of the chip active surface, is more popular because it is more advantageous for the implementation of a high-speed device. (20) has the disadvantage that such a center pad type semiconductor chip cannot be used due to the difficulty of chip stacking and the length of the gold wire.

In addition, in this type of package 20, thermal stress may be concentrated toward the top of the package, causing package warpage. Therefore, in the related art, a ball grid array package is implemented using only one center pad type semiconductor chip.

An object of the present invention is to provide a semiconductor chip stack package implemented by stacking two or more semiconductor chips including a center pad type semiconductor chip.

The semiconductor chip stack package according to the present invention for achieving the above object is formed by stacking two or more semiconductor chips including a center pad-type semiconductor chip chip chip is formed in the central portion of one surface; A substrate in which device holes are formed, first layer semiconductor chips spaced apart from each other in a horizontal direction on the substrate, and having chip pads positioned in the device holes, and at least one second layer semiconductor chip stacked on the semiconductor chips Having; The device hole and the chip pad portion are filled with an insulating material.

It is preferable that the said 2nd layer semiconductor chip is a center pad type semiconductor chip in which a chip pad is formed in the center part of one surface.

Preferably, the second layer semiconductor chip is locked so that the surface on which the chip pad of the second layer semiconductor chip is formed faces the substrate and the chip pad is positioned over the device hole formed in the substrate.

According to the present invention, a semiconductor chip stack package may be implemented by stacking two or more semiconductor chips including a center pad type semiconductor chip.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view schematically showing a semiconductor chip stack package in which center pad semiconductor chips are stacked in two layers, according to an embodiment of the present invention. 6 is a plan view illustrating a substrate in the semiconductor chip stack package of FIG. 3.

Referring to the drawings, the semiconductor chip stack package 100 according to the present invention stacks two or more semiconductor chips 120 and 130 including a center pad type semiconductor chip in which chip pads 121 and 131 are formed at the center of one surface thereof. To be formed, the substrate 110; First layer semiconductor chips 120; And a second layer semiconductor chip 130.

At least one device hole 111 and 112 is formed in the substrate 110. The first layer semiconductor chips 120 may be spaced apart from each other in a horizontal direction on the substrate 110, and the chip pads may be positioned on the device holes 111. The second layer semiconductor chip 130 is stacked on the first layer semiconductor chips 120.

Since the semiconductor chips are stacked on one surface of the substrate 110, there is no need to fold them, and thus the semiconductor chip stack package according to the present invention may be applied to a conventional planar type substrate, and thus may be implemented by a conventional process. There is no need to develop new equipment. Therefore, the application is simple and an advantageous effect can be obtained even at its cost.

The first layer semiconductor chips 120 are electrically connected to the substrate 110 and the bonding wire 141 through the chip pad 121. That is, the first layer semiconductor chips 120 and the substrate 110 are preferably connected by wire bonding. As the bonding wire 141 used herein, gold wire having excellent workability and electrical characteristics may be applied. However, the bonding wire in the present invention is not limited thereto, and various kinds of wires may be applied.

A package mold 150 is formed to surround the semiconductor chips 120 and 130 and the bonding wires to protect the semiconductor chips 120 and 130 and the bonding wires. In this case, the device hole 111 and the chip pad part 121 are filled with an insulating material.

Solder balls 160 are formed on the bottom surface of the substrate 110 to be electrically connected to the wirings formed on the substrate 110. That is, in the multilayer semiconductor package 100 of the present embodiment, a ball using a solder ball as an external connection terminal for the purpose of minimizing the surface mounting area of the semiconductor package and minimizing the length of the electrical connection to improve electrical characteristics. A ball grid array (BGA) type package is proposed.

Here, the multilayer semiconductor package 100 of the present embodiment will be described based on the solder ball type, but the present invention is not limited thereto, and the present invention is not limited thereto, and the present invention is also connected to the outside by a lead frame as shown in FIG. 1. The multilayer semiconductor package according to the invention can be applied.

An adhesive layer 170 is formed between the substrate 110 and the first layer semiconductor chips 120 and between the first layer semiconductor chips 120 and the second semiconductor chips 130. The second layer semiconductor chip 130 is preferably a center pad type semiconductor chip in which the chip pad 131 is formed at the center of one surface thereof.

In the second layer semiconductor chip 130, a surface on which the chip pad 131 of the second layer semiconductor chip 130 is formed faces the substrate 110, and a device hole in which the chip pad 131 is formed on the substrate 110. And lock to be positioned above 112. The second layer semiconductor chips 130 are electrically connected to the substrate 110 and the bonding wires 142 through the chip pads 131.

As such, even when the center pad type semiconductor chip is used as the second layer semiconductor chip 130 which is stretched horizontally with respect to the substrate 110 and stacked on the substrate 110, the device holes 112 are used. ), Sufficient wire bonding space can be secured.

In the present exemplary embodiment, a stacked semiconductor package in which semiconductor chips are stacked in two layers is illustrated, but the present invention is not limited thereto and may be stacked in three or more layers. To this end, the second layer semiconductor chip 130 may be formed by stacking two or more semiconductor chips.

The semiconductor chip stack package 100 according to the present invention can be applied to a center pad type memory device package, and a center pad type non-memory device as well as a stack package or a system in package (SIP) including a memory. It is applicable to a package and a laminated package or SIP to which such a device is applied.

4 illustrates a semiconductor chip stack package 200 as an embodiment in which the size of the second layer semiconductor chip 230 is smaller than the area occupied by the first layer semiconductor chip 120 with respect to the semiconductor chip stack package of FIG. 3. 6 illustrates one surface of the substrate 110 applied to the semiconductor chip stack package 200 of FIG. 4. In FIG. 4, the same reference numerals are used for the same components that perform the same functions as the components of the semiconductor chip stack package 100 illustrated in FIG. 3, and a detailed description thereof will be omitted.

In FIG. 5, as another preferred embodiment according to the present invention, the center pad semiconductor chips 120 and 130 are stacked in two layers, and the peripheral pad semiconductor chips 380 are stacked therein, and the semiconductor stacked in three layers. A chip stack package 300 is schematically illustrated, and FIG. 6 illustrates one surface of the substrate 110 applied to the semiconductor chip stack package 300 of FIG. 5.

In the present exemplary embodiment, the peripheral pad semiconductor chip 380 is stacked on the uppermost semiconductor chip 380 of the semiconductor chip stack package 300, a chip pad 381 is formed on the upper surface thereof, and the semiconductor chip 380 is a chip. It is electrically connected by the board | substrate 110 and the bonding wire 343 via the pad 381.

According to the semiconductor chip stack package according to the present invention, the center pad type semiconductor chip and the peripheral pad type semiconductor chip are efficiently applied according to the principles shown in FIGS. In addition, by stacking a semiconductor chip in three or more layers, a semiconductor chip stack package stacked in multiple layers may be formed.

FIG. 7 is a schematic cross-sectional view of a semiconductor chip stack package in which a peripheral pad semiconductor chip is stacked in two layers on a center pad semiconductor chip according to another exemplary embodiment of the present invention. FIG. 8 is a cross-sectional view schematically illustrating an example in which the size of the second layer semiconductor chip is smaller than the area occupied by the first layer semiconductor chip of the semiconductor chip stack package of FIG. 7. FIG. 9 is a cross-sectional view schematically illustrating a semiconductor chip stack package in which peripheral pad semiconductor chips are stacked in two layers on center pad semiconductor chips according to another exemplary embodiment of the present invention. FIG. 10 is a plan view illustrating a substrate in the semiconductor chip stack package of FIGS. 7 to 9.

7 to 10, the center pad type semiconductor chip is used as the first layer semiconductor chips 120, and the peripheral pad type is formed on the second or third layer semiconductor chips 430, 530, and 680 thereon. Shown are semiconductor chip stack packages 400, 500, and 600 formed by stacking semiconductor chips. As such, the center pad-type semiconductor chips and the peripheral pad-type semiconductor chips can be efficiently used, thereby making it easier to form a multilayer semiconductor chip stack package. However, in each embodiment, unlike in the embodiment shown in Figures 3 to 6 in the present embodiment, the space for the wire bonding for the semiconductor chips of the upper layer between the semiconductor chips forming the first layer separately Since it is not necessary, the space may be minimized or the space may be eliminated and each semiconductor chip forming the first layer may be in contact with each other.

In the semiconductor chip stack package 400 illustrated in FIGS. 7 to 10, the same or similar reference numerals are used for the same components that perform the same functions as the components illustrated in FIG. 3, and a detailed description thereof. Is omitted.

In the present exemplary embodiment, peripheral pad-type semiconductor chips are stacked on the second or third layer semiconductor chips 430, 530, and 680 of the semiconductor chip stack package 400, 500, and 600, and a chip pad 431 is disposed on an upper surface thereof. , 531, 381 are formed, and the semiconductor chip is electrically connected by the substrate 410 and the bonding wires 3442, 542, 643 through the chip pads 431, 531, 381.

According to the semiconductor chip stack package according to the present invention, a semiconductor chip stack package may be implemented by stacking two or more semiconductor chips including a center pad type semiconductor chip.

Moreover, in packaging two or more center pad type semiconductor chips, a wire bonding space can be ensured.

In addition, since it is easy to stack semiconductor chips in multiple layers, more semiconductor chips can be packaged in one semiconductor chip package taking up a certain space.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and those skilled in the art may realize various modifications and other equivalent embodiments therefrom. I can understand. Accordingly, the true scope of protection of the present invention should be determined only by the appended claims.

Claims (6)

  1. A chip pad formed by stacking two or more semiconductor chips including a center pad type semiconductor chip formed at a central portion of one surface thereof;
    A substrate on which device holes are formed, first layer semiconductor chips spaced apart from each other in a horizontal direction on the substrate, and having chip pads positioned in the device holes, and at least one second layer semiconductor chip stacked on the semiconductor chips. Equipped;
    The device hole and the chip pad part are filled with an insulating material;
    The second layer semiconductor chip is a center pad type semiconductor chip having a chip pad formed at a central portion of one surface thereof;
    And wherein the second layer semiconductor chip is disposed such that a surface on which the chip pad of the second layer semiconductor chip is formed faces the substrate and the chip pad is positioned over a device hole formed in the substrate.
  2. The method of claim 1,
    And the first layer semiconductor chips are electrically connected to the substrate and the bonding wires through the chip pads.
  3. The method of claim 1,
    Solder balls are formed on the lower surface of the substrate, the semiconductor chip stack package, characterized in that electrically connected with the wiring formed on the substrate.
  4. delete
  5. delete
  6. The method of claim 1,
    And a third layer semiconductor chip having a peripheral pad type formed at an edge of an upper surface of the chip pad stacked on the second layer semiconductor chip.
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