KR101070913B1 - Stacked die package - Google Patents

Stacked die package Download PDF

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Publication number
KR101070913B1
KR101070913B1 KR1020050042172A KR20050042172A KR101070913B1 KR 101070913 B1 KR101070913 B1 KR 101070913B1 KR 1020050042172 A KR1020050042172 A KR 1020050042172A KR 20050042172 A KR20050042172 A KR 20050042172A KR 101070913 B1 KR101070913 B1 KR 101070913B1
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South Korea
Prior art keywords
semiconductor chip
chip
layer
semiconductor
formed
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KR1020050042172A
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Korean (ko)
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KR20060120365A (en
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장창수
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삼성테크윈 주식회사
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Priority to KR1020050042172A priority Critical patent/KR101070913B1/en
Publication of KR20060120365A publication Critical patent/KR20060120365A/en
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Publication of KR101070913B1 publication Critical patent/KR101070913B1/en

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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/0657Stacked arrangements of devices
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    • H01L2924/181Encapsulation

Abstract

본 발명은 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩을 적층하여 구현된 반도체 칩 적층 패키지에 관한 것이다. The present invention relates to a semiconductor chip stack package implemented by laminating two or more semiconductor chips, including a center pad type semiconductor chip. 본 발명에 의한 반도체 칩 적층 패키지는, 칩 패드가 일 면의 중앙부에 형성되는 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩을 적층하여 형성되는 것으로; The semiconductor chip stack package according to the present invention, chip pads to be formed by laminating two or more semiconductor chips, including a center pad type semiconductor chip formed in a central portion of one surface; 디바이스 홀이 형성되는 기판, 상기 기판 위에 수평 방향으로 상호 이격되고, 상기 디바이스 홀에 칩 패드가 위치되도록 배치되는 제1층 반도체 칩들, 및 상기 반도체 칩들 위에 적층되는 적어도 하나 이상의 제2층 반도체 칩을 구비하고; Being spaced apart from each other in the horizontal direction on the substrate, the substrate on which the device hole is formed, the first layer semiconductor chips are arranged such that the chip pads are located in said device hole, and at least one second layer a semiconductor chip that is stacked on the semiconductor chips, and comprising; 상기 디바이스홀과 상기 칩 패드부가 절연물질로 충진된 것을 특징으로 한다. Characterized in that the filled holes in the device and the chip pad additional insulating material.

Description

반도체 칩 적층 패키지{Stacked die package} The semiconductor chip stack package Stacked die package {}

도 1은 종래기술에 따른 적층 패키지의 한 예를 나타내는 단면도이다. 1 is a cross-sectional view showing an example of a stacked package according to the prior art.

도 2는 종래기술에 따른 칩 적층 볼 그리드 어레이 패키지를 나타내는 단면도이다. Figure 2 is a cross-sectional view of a stacked chip ball grid array package according to the prior art.

도 3은 본 발명에 따른 바람직한 일 실시예로서, 센터 패드형 반도체 칩들을 2층으로 적층한 반도체 칩 적층 패키지를 개략적으로 도시한 단면도이다. Figure 3 is a preferred embodiment as a cross-sectional view schematically showing a semiconductor chip stack package stacking center pad type semiconductor chips in two layers according to the present invention.

도 4는 도 3의 반도체 칩 적층 패키지에 대하여, 제2층 반도체 칩의 크기가 제1층 반도체 칩이 차지하는 영역보다 작은 실시예를 개략적으로 도시한 단면도이다. 4 is a cross-sectional view schematically showing an embodiment of claim small than the area size occupied by the first layer semiconductor chip of the second layer semiconductor die to the semiconductor chip stack package of Fig.

도 5는 본 발명에 따른 바람직한 다른 실시예로서, 센터 패드형 반도체 칩들을 2층으로 적층하고, 그 위에 주변부 패드형 반도체 칩을 적층한 반도체 칩 적층 패키지를 개략적으로 도시한 단면도이다. 5 is preferred in other embodiments, cross-sectional view of the center pad stacked type semiconductor chips in two layers, and the views of the semiconductor chip stack package by laminating the peripheral pad type semiconductor chips thereon in accordance with the present invention.

도 6은 도 3 내지 도 5의 반도체 칩 적층 패키지에서, 기판을 도시한 평면도이다. 6 is laminated on the semiconductor chip package of FIG. 3 to FIG. 5, a top plan view of the substrate.

도 7은 본 발명에 따른 바람직한 다른 실시예로서, 센터 패드형 반도체 칩들 위에 주변부 패드형 반도체 칩을 2층으로 적층한 반도체 칩 적층 패키지를 개략적으로 도시한 단면도이다. 7 is preferred as another embodiment, a cross-sectional view schematically showing a semiconductor chip stack package stacking the peripheral pad on the semiconductor chip center pad type semiconductor chips in two layers according to the present invention.

도 8은 도 7의 반도체 칩 적층 패키지에 대하여, 제2층 반도체 칩의 크기가 제1층 반도체 칩이 차지하는 영역보다 작은 실시예를 개략적으로 도시한 단면도이다. 8 is a cross-sectional view schematically showing a small embodiment than the area size occupied by the first layer of the semiconductor chip, a second layer semiconductor die to the semiconductor chip stack package of Fig.

도 9는 본 발명에 따른 바람직한 다른 실시예로서, 센터 패드형 반도체 칩들 위에 주변부 패드형 반도체 칩들을 2층으로 적층한 반도체 칩 적층 패키지를 개략적으로 도시한 단면도이다. Figure 9 is a preferred another embodiment, cross-sectional view schematically showing a semiconductor chip stack package stacking the peripheral pad on the semiconductor chip center pad type semiconductor chips in two layers according to the present invention.

도 10은 도 7 내지 도 9의 반도체 칩 적층 패키지에서, 기판을 도시한 평면도이다. 10 is the semiconductor chip stack package in FIG. 7 to FIG. 9, a top view of a substrate.

<도면의 주요 부분에 대한 부호의 설명> <Description of the Related Art>

100, 200, 300, 400, 500, 600: 반도체 칩 적층 패키지, 100, 200, 300, 400, 500, 600: semiconductor chip stack package,

110, 410: 기판, 111, 112, 411: 디바이스 홀, 110, 410: substrate, 111, 112, 411: the device hole,

120, 130, 230, 380, 430, 530, 680: 반도체 칩, 120, 130, 230, 380, 430, 530, 680: semiconductor chip,

141, 142, 343, 442, 542, 643: 본딩 와이어, 141, 142, 343, 442, 542, 643: bonding wire,

150: 패키지 몰드, 160: 솔더 볼, 150: package mold, 160: solder ball,

170: 접착층. 170: adhesive layer.

본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩을 적층하여 구현된 반도체 칩 적층 패키지에 관한 것이다. The present invention relates to, and more particularly, the center pad by laminating two or more semiconductor chip including the semiconductor chip is implemented as a semiconductor chip stack package according to the semiconductor package.

반도체 산업에서 집적회로 칩에 대한 패키징(packaging) 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전하고 있다. In the semiconductor industry, packaging (packaging) technology for integrated circuit chips and continue to evolve in order to satisfy the demand for miniaturization and mounting reliability. 아울러, 전자 제품의 고성능화가 진행됨에 따라, 한정된 크기의 기판에 더 많은 수의 반도체 패키지를 실장하기 위한 노력들이 계속되고 있다. In addition, there is, continue their efforts to implement a greater number of semiconductor packages of the limited size of the board in accordance with the high performance of electronic products continues. 이러한 노력의 일환으로 제안된 것이 소위 적층 패키지(stack package)이다. It is proposed as part of this effort, a so-called laminate package (package stack).

적층 패키지는 동일한 크기 및 동일한 기능의 메모리 칩을 적층하여 메모리 용량을 증대시키거나, 서로 다른 크기와 기능을 가지는 여러 유형의 반도체 칩을 하나의 패키지에 조립하여 제품의 성능과 효율성을 최대화하기 위한 것이다. Laminated package to assemble different types of semiconductor chips having a either by stacking the memory chips of the same size and the same function increasing the memory capacity or of different sizes and functions in one package is to maximize the performance and efficiency of the product . 적층 패키지는 적용하고자 하는 제품, 제조 회사 등에 따라 그 종류가 매우 다양하다. Laminate package types that vary by product and manufacturer to apply. 종래기술에 따른 적층 패키지의 한가지 예가 도 1에 도시되어 있다. One example of a multilayer package, in accordance with the prior art is shown in Fig.

도 1에 도시된 적층 패키지(10)는 개별 패키지(11, 12)를 적층한 패키지 적층식으로서, TSOP(thin small outline package) 유형이다. The stacked package 10 shown in Figure 1 is an individual package (11, 12) as a package stack stacked, (thin small outline package), TSOP type. 도 1의 적층 패키지(10)에 있어서, 각각의 개별 패키지(11, 12)는 하나씩의 반도체 칩(13)을 내장하며 LOC(lead-on-chip) 리드 프레임(lead frame)을 사용한다. In the stacked package 10 of Figure 1, each individual package (11, 12) is built in one of the semiconductor chip 13, and uses the LOC (lead-on-chip), the lead frame (lead frame). 리드 프레임의 내부 리드(14)는 반도체 칩(13)의 상면에 접착 테이프(15)로 접착되고 금 와이어(16)에 의하여 전기적으로 연결된다. The inner leads of the lead frame 14 is adhered to the adhesive tape 15 to the upper surface of the semiconductor chip 13 is electrically connected to by a gold wire 16. 적층된 개별 패키지(11, 12)들은 별도의 연결용 리드(17)를 사용하여 서로 전기적으로 연결된다. The stacked individual packages (11, 12) are using a separate connecting leads (17) are each electrically connected. 이 때, 연결용 리드(17)는 각 리드 프레임의 외부 리드(18)와 접합되며, 적층 패키지(10)의 외부접속 단자가 된다. At this time, the lead 17 for connection is bonded to the outer lead 18 of each lead frame, and an external connection terminal of the stacked package 10. FIG.

하지만, 이러한 유형의 적층 패키지(10)는 패키지의 실장 면적이 넓고 높이 가 높아 소형화, 박형화를 요구하는 정보통신기기 등의 시스템에 적용하기가 곤란하다. However, the laminated package 10 of this type is difficult to apply to the system, such as miniaturization increases the wide mounting area of ​​the package height information and communication equipment requiring a reduction in thickness. 또한, 리드 프레임(14, 17, 18)을 이용하기 때문에 고속 소자 제품에 부적합하며, 실장 지점으로부터 하부 패키지(11)의 반도체 칩(13)까지의 경로보다 상부 패키지(12)의 반도체 칩(14)까지의 경로가 길기 때문에 전기적 특성의 차이를 보인다. Further, the lead frame (14, 17, 18) was used to due to high-speed devices, and not suitable for products, the semiconductor chips of the upper package 12 than the path from the semiconductor chip 13 of the lower package 11 from the mounting point (14 since) it is longer path to show a difference in electrical properties.

따라서, 반도체 패키지의 표면실장 면적을 최소화하고 또한 전기접속 길이를 최소화하여 전기적 특성을 향상시킬 목적으로 솔더 볼(solder ball)을 외부접속 단자로 사용하는 볼 그리드 어레이(ball grid array; BGA) 패키지가 제안되었다. Therefore, minimizing the surface mounting area of ​​the semiconductor package, and also see the solder in order to improve the electrical characteristics by minimizing the electrical connection length (solder ball) to the ball grid array for use as an external connection terminal (ball grid array; BGA) package It proposed. 기본적으로 볼 그리드 어레이 패키지의 형태를 따르면서 패키지 내부에 반도체 칩을 적층한 소위 '칩 적층 볼 그리드 어레이 패키지'가 도 2에 도시되어 있다. By default, the ball grid array package, while following the shape of the so-called laminated structure in the semiconductor chip inside the package, ball grid array chip stack package, is shown in FIG.

도 2에 도시된 바와 같이, 칩 적층 볼 그리드 어레이 패키지(20)는 패키지 몰드(27) 내부에 개별 반도체 칩(23, 24)들을 적층한 칩 적층식으로서, 리드 프레임 대신에 인쇄회로기판(21)과 솔더 볼(28)을 이용한다. The chip stacking ball grid array package 20 as shown in Figure 2 is a package mold 27 as a chip stacked stacking individual semiconductor chips (23, 24) therein, the printing in place of the lead frame circuit board (21 ) and uses a solder ball (28). 배선(22)이 형성된 인쇄회로기판(21) 위에 접착제(25)를 사용하여 하부 반도체 칩(23)이 접착되며, 하부 반도체 칩(23) 위에 상부 반도체 칩(24)이 접착된다. Wiring 22 with an adhesive 25 on the printed circuit board 21, the lower semiconductor chip 23 is bonded is formed, the lower semiconductor chip 23, the upper semiconductor chip 24 is bonded on. 각 반도체 칩(23, 24)은 금 와이어(26)에 의하여 인쇄회로기판(21)의 배선(22)과 전기적으로 연결되며, 인쇄회로기판(21) 하면에는 솔더 볼(28)들이 형성되어 배선(22)과 전기적으로 연결되며, 패키지(20)의 외부접속 단자가 된다. Each of the semiconductor chips 23 and 24 are wiring 22 and is electrically connected to a printed circuit board (28) (21) While in the solder ball of a printed circuit board 21 by the gold wire 26 are formed wire 22 and is electrically connected to, and the external connection terminals of the package 20.

하지만, 이러한 유형의 칩 적층 볼 그리드 어레이 패키지(20)는 소위 '주변부 패드(peripheral pad)형 반도체 칩' 밖에 사용할 수 없다. However, this type of stacked chip ball grid array package 20 can not be used outside the so-called "pad peripheral portion (peripheral pad) semiconductor chip. 디램(DRAM)과 같은 반도체 칩의 활성면(active surface)에는 외부와의 입출력을 담당하는 다수의 칩 패드(23a, 24a; chip pad)들이 형성되는데, 이 칩 패드(23a, 24a)들이 칩 활성면의 가장자리에 형성된 것이 바로 주변부 패드형 반도체 칩(23, 24)이다. The active surface of the semiconductor chip such as a dynamic random access memory (DRAM) (active surface) has a plurality of chip pads that is responsible for input-output with the outside (23a, 24a; chip pad) that are formed, the chip pads (23a, 24a) to chip active it is the peripheral pad-type semiconductor chips (23, 24) formed on the edge of the sheet.

한편, 최근에는 고속 소자의 구현에 보다 유리하기 때문에 칩 패드들이 칩 활성면의 중앙을 따라 형성된 소위 '센터 패드형 반도체 칩'이 보편화되어 있지만, 도 2에 도시된 종래의 칩 적층 볼 그리드 어레이 패키지(20)는 칩 적층의 곤란함과 금 와이어의 길이가 길어지는 문제 때문에 이러한 센터 패드형 반도체 칩을 사용할 수 없다는 단점을 안고 있다. Recently, because the advantage over the high-speed device implementing chip pads to the chip, but a so-called formed along the center of the active side is "center pad type semiconductor chip" is common, also see the conventional chip stack shown in a grid array package 20 may hold the disadvantage that it can use this center pad type semiconductor chip due to a problem that increases the difficulty and also the length of the gold wire of the chip stack.

또한, 이러한 패키지(20) 유형은 열응력이 패키지의 상부쪽으로 집중되어 패키지 뒤틀림(warpage) 현상이 발생할 수 있다. Further, this package 20 types are concentrated towards the top of the package, the thermal stress can cause package distortion (warpage) phenomenon. 따라서, 종래기술에서는 한 개의 센터 패드형 반도체 칩만을 이용하여 볼 그리드 어레이 패키지를 구현하고 있는 실정이다. Therefore, the situation that in the prior art implements a ball grid array package using only one center pad type semiconductor chip.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩을 적층하여 구현된 반도체 칩 적층 패키지를 제공하는 것을 목적으로 한다. The present invention intended to solve the above problems, an object of the present invention to provide a semiconductor chip stack package implemented by laminating two or more semiconductor chips, including a center pad type semiconductor chip.

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 칩 적층 패키지는, 칩 패드가 일 면의 중앙부에 형성되는 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩을 적층하여 형성되는 것으로; The semiconductor chip stack package according to the present invention for achieving the above object is, to which the chip pads are formed by laminating two or more semiconductor chips, including a center pad type semiconductor chip formed in a central portion of one surface; 디바이스 홀이 형성되는 기판, 상기 기 판 위에 수평 방향으로 상호 이격되고, 상기 디바이스 홀에 칩 패드가 위치되도록 배치되는 제1층 반도체 칩들, 및 상기 반도체 칩들 위에 적층되는 적어도 하나 이상의 제2층 반도체 칩을 구비하고; A first layer semiconductor chips, and at least one second layer a semiconductor chip stacked on the semiconductor chips are separated from each other in the horizontal direction on the substrate that the device hole is formed, the group board, which is arranged such that the chip pads are located in said device hole and a; 상기 디바이스홀과 상기 칩 패드부가 절연물질로 충진된 것을 특징으로 한다. Characterized in that the filled holes in the device and the chip pad additional insulating material.

상기 제2층 반도체 칩이, 칩 패드가 일 면의 중앙부에 형성되는 센터 패드형 반도체 칩인 것이 바람직하다. That the second layer is a semiconductor chip, a center pad type semiconductor chip, the chip pads are formed at the central portion of one surface is preferable.

상기 제2층 반도체 칩이, 상기 제2층 반도체 칩의 칩 패드가 형성된 면이 상기 기판을 향하고, 상기 칩 패드가 상기 기판에 형성된 디바이스 홀 위에 위치되도록 록 배치되는 것이 바람직하다. The second layer a semiconductor chip, it is preferred that the surface of the chip pads of the second semiconductor chip formed layer facing the substrate, wherein the chip pads are arranged to be located above the lock device hole formed in the substrate.

본 발명에 따르면, 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩을 적층하여 반도체 칩 적층 패키지를 구현할 수 있다. According to the invention, it is possible by laminating two or more semiconductor chips, including a center pad type semiconductor chips to implement a semiconductor chip stack package.

이하, 첨부된 도면을 참조하여 바람직한 실시예에 따른 본 발명을 상세히 설명하기로 한다. With reference to the accompanying drawings, a description of the invention according to the preferred embodiment in detail.

도 3은 본 발명에 따른 바람직한 일 실시예로서, 센터 패드형 반도체 칩들을 2층으로 적층한 반도체 칩 적층 패키지를 개략적으로 도시한 단면도이다. Figure 3 is a preferred embodiment as a cross-sectional view schematically showing a semiconductor chip stack package stacking center pad type semiconductor chips in two layers according to the present invention. 도 6은 도 3의 반도체 칩 적층 패키지에서, 기판을 도시한 평면도이다. Figure 6 is a plan view showing the substrate, the semiconductor chip stack package of Fig.

도면을 참조하면, 본 발명에 따른 반도체 칩 적층 패키지(100)는 칩 패드(121, 131)가 일 면의 중앙부에 형성되는 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩(120, 130)을 적층하여 형성되는 것으로, 기판(110); Referring to the drawings, the semiconductor chip stack package 100 includes a stack of chip pads (121, 131) the center paddle of two or more semiconductor chip including a semiconductor chip (120, 130) formed in a central portion of one surface to be formed, the substrate 110; 제1층 반도체 칩들(120); A first layer semiconductor chips 120; 및 제2층 반도체 칩(130)을 구비한다. And a second layer comprising a semiconductor chip (130).

상기 기판(110)에는 적어도 하나 이상의 디바이스 홀(111, 112)이 형성된다. The substrate 110 is formed with at least one device hole (111, 112). 상기 제1층 반도체 칩들(120)은 기판(110) 위에 수평 방향으로 상호 이격되고, 디바이스 홀(111) 위에 칩 패드가 위치되도록 배치된다. The first layer semiconductor chips 120 are separated from each other in the horizontal direction on the substrate 110, and is arranged such that the chip pads are located above the device hole (111). 상기 제2층 반도체 칩(130)은 상기 제1층 반도체 칩들(120) 위에 적층된다. It said second layer semiconductor die 130 is stacked on the first layer semiconductor chips (120).

상기 기판(110)의 한쪽 면 위에 반도체 칩들이 적층되므로 접힐 필요가 없어, 본 발명에 따른 반도체 칩 적층 패키지는 통상의 평면 타입의 기판에도 적용될 수 있으므로, 기존의 공정에 의하여 구현될 수 있어 이를 위한 새로운 장비의 개발이 필요 없다. The do not have to be folded, so the semiconductor chip on one side of the substrate 110 are stacked, since the semiconductor chip stack package according to the present invention may be applied to a substrate of a conventional flat-type, it can be implemented by a conventional process therefor eliminating the need for the development of new equipment. 따라서, 적용이 간단하고 그 비용에서도 유리한 효과를 얻을 수 있다. Therefore, the application may be simple, get a beneficial effect in those costs.

상기 제1층 반도체 칩들(120)이 칩 패드(121)를 통하여 기판(110)과 본딩 와이어(141)에 의하여 전기적으로 연결된다. The first layer semiconductor chips 120 are electrically connected to by the substrate 110 and the bonding wires 141 through the chip pad 121. 즉, 제1층 반도체 칩(120)들과 기판(110)은 와이어 본딩에 의하여 연결되는 것이 바람직한데, 이때 사용되는 본딩 와이어(141)로는 작업성 및 전기적 특성이 우수한 금 와이어가 적용될 수 있다. That is, the first layer semiconductor chip 120 and the substrate 110 is preferred to be connected by wire bonding, wherein roneun bonding wires 141 that are used can be applied to the gold wire is excellent in workability and electrical properties. 다만, 본 발명에서의 본딩 와이어는 이에 한정되지 아니하고, 다양한 종류의 와이어가 적용될 수 있다. However, the bonding wire in the present invention is not limited thereto and can be applied various kinds of wires.

상기 반도체 칩들(120, 130)과 상기 본딩 와이어를 감싸도록 패키지 몰드(150)가 형성되어, 반도체 칩들(120, 130)과 상기 본딩 와이어를 보호한다. The semiconductor chips package mold 150 to surround the 120, 130 and the bonding wires are formed to protect the semiconductor chips 120 and 130 and the bonding wires. 이때, 디바이스홀(111)과 칩 패드부(121)가 절연물질로 충진된다. At this time, the device hole 111 and the chip pads 121 are filled with an insulating material.

상기 기판(110)의 하면에는 솔더 볼(160)들이 형성되어 기판(110)에 형성된 배선과 전기적으로 연결된다. The lower surface of the substrate 110 has solder balls 160 are formed are electrically connected to the wiring formed on the substrate 110. 즉, 본 실시예의 적층 반도체 패키지(100)에서는 반 도체 패키지의 표면실장 면적을 최소화하고 또한 전기접속 길이를 최소화하여 전기적 특성을 향상시킬 목적으로 솔더 볼(solder ball)을 외부접속 단자로 사용하는 볼 그리드 어레이(ball grid array; BGA) 타입의 패키지가 제안된다. That is, to see that use of this embodiment lamination In the semiconductor package 100 minimize the surface mounting area of ​​the semiconductor package, and also the solder balls in order to improve the electrical characteristics by minimizing the electrical connection length (solder ball) to the external connection terminal grid array; a (ball grid array BGA) type package is proposed.

여기서, 본 실시예의 적층 반도체 패키지(100)는 솔더 볼 타입을 중심으로 기술되나, 본 발명은 이에 한정되지 아니하고 도 1에 도시된 경우에서와 같이 리드 프레임에 의하여 외부와 전기적으로 연결되는 경우에도 본 발명에 따른 적층 반도체 패키지가 적용될 수 있다. Here, the embodiment stacked semiconductor package 100 of this embodiment, but techniques around the solder ball type, the invention is present, even if electrically connected by the lead-frame and, as in the case shown in Figure 1 not limited thereto a multilayer semiconductor package according to the invention can be applied.

상기 기판(110)과 제1층 반도체 칩들(120) 사이 및 제1층 반도체 칩들(120)과 제2 반도체 칩들(130) 사이를 상호 접착시키는 접착층(170)이 형성된다. The adhesive layer 170 for mutual adhesion between the substrate 110 and the first layer semiconductor chips 120 and the first layer between the semiconductor chips 120 and the second semiconductor chips 130 are formed. 상기 제2층 반도체 칩(130)은, 칩 패드(131)가 일 면의 중앙부에 형성되는 센터 패드형 반도체 칩인 것이 바람직하다. It said second layer semiconductor die 130 is preferably a center pad type semiconductor chip formed in a central portion of the chip pad 131 is one.

상기 제2층 반도체 칩(130)은, 제2층 반도체 칩(130)의 칩 패드(131)가 형성된 면이 기판(110)을 향하고, 칩 패드(131)가 기판(110)에 형성된 디바이스 홀(112) 위에 위치되도록 록 배치된다. Said second layer a semiconductor chip 130, a second layer semiconductor This surface formed the chip pads 131 of the chip 130 faces the substrate 110, a device hole, the chip pads 131 formed on the substrate 110, 112 is disposed so as to be located above the rock. 상기 제2층 반도체 칩들(130)이 칩 패드(131)를 통하여 기판(110)과 본딩 와이어(142)에 의하여 전기적으로 연결된다. It said second layer semiconductor chips 130 are electrically connected by the substrate 110 and the bonding wires 142 through the chip pad 131.

이처럼, 제1층 반도체 칩(120)을 기판(110)을 기준으로 수평방향으로 늘여 놓아 그 위에 적층되는 제2층 반도체 칩(130)으로 센터 패드형 반도체 칩이 사용되는 경우에도 디바이스 홀(112)을 통하여 충분한 와이어 본딩 공간을 확보할 수 있다. As such, the device hole, even if the first layer semiconductor chip 120, a substrate 110, a second layer of a semiconductor chip 130, the center pad type semiconductor chip placed stretched in the horizontal direction reference which is stacked thereon to be used (112 ) it is possible to secure a sufficient space for wire bonding through.

본 실시예에는 반도체 칩들이 2층으로 적층된 적층 반도체 패키지가 도시되 었으나, 본 발명은 이에 한정되지 아니하고 3층 이상으로 적층될 수 있다. Eoteuna present embodiment, the semiconductor chips are stacked semiconductor packages stacked in two layers that are shown, the invention is not limited thereto can be stacked in three or more layers. 이를 위하여, 상기 제2층 반도체 칩(130)은, 2 이상의 반도체 칩들이 적층되어 이루어질 수 있다. To this end, the second layer semiconductor die 130, may be made is to stack two or more semiconductor chips.

본 발명에 다른 반도체 칩 적층 패키지(100)는 센터 패드형 메모리 디바이스 패키지에도 적용 가능하며, 메모리가 포함되는 적층 패키지 또는 시스템 인 패키지(system in package; SIP)뿐만 아니라, 센터 패드형의 비메모리 디바이스 패키지, 및 이러한 디바이스가 적용되는 적층 패키지 또는 SIP 등에 적용 가능하다. Other semiconductor chip stack package 100 in the present invention is also applicable to the center pad memory device package, and a package stack package, or system memory that includes (system in package; SIP), as well as non-memory device in the center pad package, and it can be applied to a laminated package or SIP that such devices apply.

도 4에는 도 3의 반도체 칩 적층 패키지에 대하여, 제2층 반도체 칩(230)의 크기가 제1층 반도체 칩(120)이 차지하는 영역보다 작은 실시예로서의 반도체 칩 적층 패키지(200)가 도시되어 있으며, 도 6에는 도 4의 반도체 칩 적층 패키지(200)에 적용되는 기판(110)의 일면이 도시되어 있다. With respect to the semiconductor chip stack package of Figure 4, Figure 3, the second layer, the size of the semiconductor chip 230, a first layer semiconductor chip 120 is smaller embodiment as an example the semiconductor chip stack package 200 than the area occupied is shown, and , Figure 6, there is shown the one side of the substrate 110 to be applied to the semiconductor chip stack package 200 of FIG. 도 4에는 도 3에 도시된 반도체 칩 적층 패키지(100)의 구성요소와 동일한 기능을 수행하는 동일한 구성요소에 대해서는 동일한 참조번호가 사용되고 그 자세한 설명은 생략된다. 4, the same reference numerals for the same elements performing the same function as the components of the semiconductor chip stack package 100 shown in Figure 3 used a detailed description thereof will be omitted.

도 5에는 본 발명에 따른 바람직한 다른 실시예로서, 센터 패드형 반도체 칩들(120, 130)이 2층으로 적층되고, 그 위에 주변부 패드형 반도체 칩(380)이 적층되어, 3층으로 적층된 반도체 칩 적층 패키지(300)가 개략적으로 도시되어 있으며, 도 6에는 도 5의 반도체 칩 적층 패키지(300)에 적용되는 기판(110)의 일면이 도시되어 있다. Figure 5 shows another preferred embodiment according to the present invention, the center pad is laminated to the semiconductor chips (120, 130) is the second floor, above the peripheral pad type semiconductor chips 380 are stacked, the stacked semiconductor of three layers, and a chip stack package 300 is shown schematically, FIG 6, there is shown the one side of the substrate 110 to be applied to the semiconductor chip stack package 300 of FIG.

본 실시예에서는 반도체 칩 적층 패키지(300)의 최상층 반도체 칩(380)으로 주변부 패드형 반도체 칩(380)이 적층되고, 그 상면에 칩 패드(381)가 형성되고, 반도체 칩(380)이 칩 패드(381)를 통하여 기판(110)과 본딩 와이어(343)에 의하여 전기적으로 접속된다. In this embodiment, the uppermost semiconductor chip 380 of the semiconductor chip stack package 300 periphery paddle semiconductor chips 380 are stacked, is formed in a chip pad 381 on the upper surface of the semiconductor chip 380. The chip via pad 381 it is electrically connected by the substrate 110 and the bonding wires (343).

본 발명에 따른 반도체 칩 적층 패키지에 의하면, 도 3 내지 도 5에 도시된 원리에 의하여 센터 패드형 반도체 칩과 주변부 패드형 반도체 칩이 효율적으로 적용되도록 하면서, 수평 및 수직 방향으로 배치하여, 2층뿐만 아니라 3층 이상으로 반도체 칩을 적층하여, 다층으로 적층된 반도체 칩 적층 패키지가 형성될 수 있을 것이다. According to the semiconductor chip stack package according to the present invention, and to Fig. 3 to the principles on by the center pad type semiconductor chip and the peripheral pad of the semiconductor chips shown in Figure 5 is effectively applied, and disposed in horizontal and vertical directions, two-layer in addition, by stacking a semiconductor chip with at least three layers, there will be a stacked multi-layer stacked semiconductor chip package can be formed.

도 7은 본 발명에 따른 바람직한 다른 실시예로서, 센터 패드형 반도체 칩들 위에 주변부 패드형 반도체 칩을 2층으로 적층한 반도체 칩 적층 패키지를 개략적으로 도시한 단면도이다. 7 is preferred as another embodiment, a cross-sectional view schematically showing a semiconductor chip stack package stacking the peripheral pad on the semiconductor chip center pad type semiconductor chips in two layers according to the present invention. 도 8은 도 7의 반도체 칩 적층 패키지에 대하여, 제2층 반도체 칩의 크기가 제1층 반도체 칩이 차지하는 영역보다 작은 실시예를 개략적으로 도시한 단면도이다. 8 is a cross-sectional view schematically showing a small embodiment than the area size occupied by the first layer of the semiconductor chip, a second layer semiconductor die to the semiconductor chip stack package of Fig. 도 9는 본 발명에 따른 바람직한 다른 실시예로서, 센터 패드형 반도체 칩들 위에 주변부 패드형 반도체 칩들을 2층으로 적층한 반도체 칩 적층 패키지를 개략적으로 도시한 단면도이다. Figure 9 is a preferred another embodiment, cross-sectional view schematically showing a semiconductor chip stack package stacking the peripheral pad on the semiconductor chip center pad type semiconductor chips in two layers according to the present invention. 도 10은 도 7 내지 도 9의 반도체 칩 적층 패키지에서, 기판을 도시한 평면도이다. 10 is the semiconductor chip stack package in FIG. 7 to FIG. 9, a top view of a substrate.

도 7 내지 도 10에 도시된 실시예에는 제1층 반도체 칩들(120)로는 센터 패드형 반도체 칩이 사용되고, 그 위에 제2층 또는 제3층 반도체 칩들(430, 530, 680)로 주변부 패드형 반도체 칩들이 적층되어 형성되는 반도체 칩 적층 패키지들(400, 500, 600)이 도시되어 있다. The embodiment shown in Figs. 7 to 10, the first layer semiconductor chips (120) includes a center pad type semiconductor chips are used, and that over a second layer or a third-layer semiconductor chips (430, 530, 680) periphery paddle the semiconductor chip stack package, which is the semiconductor chips are stacked to form (400, 500, 600) are shown. 이처럼, 센터 패드형 반도체 칩들과 주변부 패드형 반도체 칩들이 효율적으로 사용되어, 다층의 반도체 칩 적층 패키지 형성이 더욱 용이하게 될 수 있다. Thus, the center pad type semiconductor chips and the peripheral pad-type semiconductor chips are used efficiently, and the semiconductor chip package forming a multi-layer laminate can be made easier. 다만, 각각의 실시예에서, 본 실시예의 경우에는 도 3 내지 도 6에 도시된 실시예에서와는 달리 제1층을 형성하는 반도체 칩들 사이에 그 상층의 반도체 칩들을 위한 와어어 본딩을 위한 공간이 별도로 필요 없으므로, 그 공간을 최소화시키거나, 그 공간을 없애고 1층을 형성하는 각각의 반도체 칩들이 상호 접촉되도록 할 수도 있을 것이다. However, in each embodiment, the case of this embodiment, the space for waeo air bonding for the upper layer of the semiconductor chip between the embodiment than on different semiconductor chips to form a first layer shown in Figs. 3 to 6 additionally need not, to minimize the space, or could also be eliminated such that the space contacting each of the semiconductor chips to form a first layer mutually.

도 7 내지 도 10에 도시된 반도체 칩 적층 패키지(400)에서, 도 3에 도시된 구성요소와 동일한 기능을 수행하는 동일한 구성요소에 대해서는 동일한 참조번호 내지는 유사한 참조번호를 사용하고 이들에 대한 자세한 설명은 생략한다. In the semiconductor chip stack package 400 shown in Figs. 7 to 10, using like reference numerals naejineun same reference numerals for the same elements performing the same functions as the components shown in Figure 3, detailed description thereof It will be omitted.

본 실시예들에서는 반도체 칩 적층 패키지(400, 500, 600)의 제2층 또는 제3층 반도체 칩(430, 530, 680)으로 주변부 패드형 반도체 칩이 적층되고, 그 상면에 칩 패드(431, 531, 381)가 형성되고, 반도체 칩이 칩 패드(431, 531, 381)를 통하여 기판(410)과 본딩 와이어(3442, 542, 643)에 의하여 전기적으로 접속된다. In this embodiment, the second layer or the third layer semiconductor die (430, 530, 680) to the peripheral pad and a semiconductor chip is laminated, chip pad (431 in the upper surface of the semiconductor chip stack package (400, 500, 600) , 531, 381) are formed, the semiconductor chips are electrically connected to each other by the substrate 410 and the bonding wires (3442, 542, 643) through a chip pad (431, 531, 381).

본 발명에 따른 반도체 칩 적층 패키지에 의하면, 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩을 적층하여 반도체 칩 적층 패키지를 구현할 수 있다. According to the semiconductor chip stack package according to the present invention, by laminating two or more semiconductor chips, including a center pad type semiconductor chip can be realized a semiconductor chip stack package.

또한, 2 이상의 센터 패드형 반도체 칩을 패키징하는 데 있어서, 와이어 본딩 공간을 확보할 수 있다. Further, according to package two or more center pad type semiconductor chip, it is possible to secure the wire bonding area.

또한, 반도체 칩을 복수 층으로 적층하는 것이 용이하므로, 일정한 공간을 차지하는 하나의 반도체 칩 패키지 안에 더 많은 반도체 칩을 패키징할 수 있다. In addition, since it is easy to stack the semiconductor chips of a plurality of layers, it is possible to package more semiconductor chips in one semiconductor chip packages occupy a certain space.

본 발명은 첨부된 도면에 도시된 일 실시예를 참고로 설명되었으나, 이는 예 시적인 것에 불과하며, 당해 기술분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 수 있을 것이다. That the present invention is that been described in the embodiment illustrated in the accompanying drawings, an example as a reference, this example is merely to poetry, those skilled in the art from which the various modifications and equivalent other embodiments can be it will be appreciated. 따라서, 본 발명의 진정한 보호 범위는 첨부된 청구 범위에 의해서만 정해져야 할 것이다. Therefore, the true scope of the present invention as defined only by the appended claims.

Claims (6)

  1. 칩 패드가 일 면의 중앙부에 형성되는 센터 패드형 반도체 칩을 포함한 2 이상의 반도체 칩을 적층하여 형성되는 것으로; To which the chip pads are formed by laminating two or more semiconductor chips, including a center pad type semiconductor chip formed in a central portion of one surface;
    디바이스 홀이 형성되는 기판, 상기 기판 위에 수평 방향으로 상호 이격되고, 상기 디바이스 홀에 칩 패드가 위치되도록 배치되는 제1층 반도체 칩들, 및 상기 반도체 칩들 위에 적층되는 적어도 하나 이상의 제2층 반도체 칩을 구비하고; Being spaced apart from each other in the horizontal direction on the substrate, the substrate on which the device hole is formed, the first layer semiconductor chips are arranged such that the chip pads are located in said device hole, and at least one second layer a semiconductor chip that is stacked on the semiconductor chips, and comprising;
    상기 디바이스홀과 상기 칩 패드부가 절연물질로 충진된 것을 특징으로 하며; Characterized in that the filled holes in the device and the chip pads and the portion of insulating material;
    상기 제2층 반도체 칩이, 칩 패드가 일 면의 중앙부에 형성되는 센터 패드형 반도체 칩인 것을 특징으로 하며; The second layer a semiconductor chip, chip pad and the center pad type semiconductor chip, characterized in that formed at the central portion of the work surface;
    상기 제2층 반도체 칩이, 상기 제2층 반도체 칩의 칩 패드가 형성된 면이 상기 기판을 향하고, 상기 칩 패드가 상기 기판에 형성된 디바이스 홀 위에 위치되도록 배치되는 것을 특징으로 하는 반도체 칩 적층 패키지. Said second layer a semiconductor chip, said second layer is the chip pads are formed in the semiconductor chip facing the substrate, the semiconductor chip stack package, it characterized in that the chip pads are provided so as to be located above the device hole formed in the substrate.
  2. 제1항에 있어서, According to claim 1,
    상기 제1층 반도체 칩들이 상기 칩 패드를 통하여 상기 기판과 본딩 와이어에 의하여 전기적으로 연결되는 것을 특징으로 하는 반도체 칩 적층 패키지. The first layer semiconductor chip to a semiconductor chip stack package, characterized in that through the chip pad electrically connected to the substrate by bonding wires.
  3. 제1항에 있어서, According to claim 1,
    상기 기판의 하면에는 솔더 볼들이 형성되어 상기 기판에 형성된 배선과 전기적으로 연결되는 것을 특징으로 하는 반도체 칩 적층 패키지. When the substrate is a semiconductor chip stack package, it characterized in that the solder ball is formed to be connected to the wiring formed on the substrate and electrically.
  4. 삭제 delete
  5. 삭제 delete
  6. 제1항에 있어서, According to claim 1,
    상기 제2층 반도체 칩 위에 적층되는 칩 패드가 상면의 가장자리에 형성된 주변부 패드형인 제3층 반도체 칩을 더 구비하는 것을 특징으로 하는 반도체 칩 적층 패키지. The second layer type peripheral chip pads are stacked on a semiconductor chip is formed on the edge of the upper surface of the pad, the semiconductor chip stack package according to claim 1, further comprising a three-layer semiconductor chip.
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