CN102157394A - High-density system-in-a-package method - Google Patents
High-density system-in-a-package method Download PDFInfo
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- CN102157394A CN102157394A CN 201110069992 CN201110069992A CN102157394A CN 102157394 A CN102157394 A CN 102157394A CN 201110069992 CN201110069992 CN 201110069992 CN 201110069992 A CN201110069992 A CN 201110069992A CN 102157394 A CN102157394 A CN 102157394A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The invention relates to a high-density system-in-a-package method comprising the following steps of: supplying a base plate; forming at least one group of wiring packaging layers on the base plate, wherein the step of forming at least one group of wiring packaging layers includes the steps of sequentially forming an adhering layer, a packaging layer and a wiring layer on the base plate; forming lead bonding packaging layers on the tail group of wiring packaging layers, wherein the step of forming the lead bonding packaging layers includes the steps of sequentially forming an adhering layer, a metal lead bonding layer and the packaging layer; and bumping below the base plate. Compared with the prior art, by adopting the high-density system-in-a-package method disclosed by the invention, a final packaging product containing an integral system function but not a single chip function can be formed, the factor of the interference among the resistance, the inductance and the chip inside a system is reduced; and besides, by means of the high-density system-level packaging method, a more complicated multilayer interconnected structure can be formed, and the wafer system-in-a-package with higher integrated degree is realized.
Description
Technical field
The present invention relates to semiconductor technology, relate in particular to a kind of high-density systems level packaging methods.
Background technology
Along with the continuous development of integrated circuit technique, electronic product more and more develops to miniaturization, intellectuality, high-performance and high reliability direction.And the integrated circuit encapsulation not only directly affects integrated circuit, electronic module and even machine performance, but also is restricting miniaturization, low cost and the reliability of whole electronic system.Progressively dwindle in the integrated circuit (IC) wafer size, under the situation that integrated level improves constantly, electronics industry has proposed more and more higher requirement to the integrated circuit encapsulation technology.
In being the Chinese patent of CN1747156C, notification number discloses a kind of base plate for packaging.Described base plate for packaging comprises: substrate, and described substrate comprises a surface; Be positioned at the pad of receiving on the described substrate surface; Be formed at the welding resisting layer on the described substrate surface, described welding resisting layer comprises at least one opening, and described opening exposes the described pad of receiving; Described base plate for packaging also comprises a pattern metal strengthening course, and described pattern metal strengthening course is formed on the described pad of receiving along the sidewall of described welding resisting layer opening.
The final products of packaged manufacturing only have single chip functions according to the method described above, yet, along with improving constantly of compact trend of semiconductor product and product systems functional requirement, the integration that how further to improve system in package becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The technical problem that the present invention solves is: the high-density systems level encapsulation that how to realize having sandwich construction.
For solving the problems of the technologies described above, the invention provides the high-density systems level packaging methods, comprise step: provide substrate; On described substrate, form at least one group of wiring encapsulated layer, the step that forms described wiring encapsulated layer comprise on substrate, form successively mount layer, the envelope bed of material, wiring layer; Form the wire bond package layer on end group wiring encapsulated layer, the step that forms described wire bond package layer comprises that formation successively mounts layer, metal lead wire bonding, the envelope bed of material; Wherein, substrate, respectively organize between the encapsulated layer and to see through wiring layer and metal lead wire and realize adjacent encapsulated layer or electric interconnected between encapsulated layer at interval; Below substrate, plant ball.
Alternatively, the concrete steps of at least one group of wiring of formation encapsulated layer comprise on described substrate: attach first and mount layer on substrate; Form the first envelope bed of material with posting first one side that mounts layer on the substrate, first link that mounts layer is exposed; On the first envelope bed of material, form first wiring layer.
Alternatively, described link is first to mount the pad of layer chips and/or passive device.
Alternatively, comprise in the step that forms first wiring layer on the first envelope bed of material: form first micro through hole in the first envelope bed of material, filled conductive material in first micro through hole forms the first vertically wiring afterwards; On the first envelope bed of material, form and connect the described first vertically first laterally wiring of wiring, wherein, described first vertically wiring be used to realize being electrically connected between first encapsulated layer and substrate and other encapsulated layers, described first laterally connects up is used to realize electrical connection between each device of first encapsulated layer.
Alternatively, comprise in the concrete steps that form the wire bond package layer on the end group wiring encapsulated layer: on end group wiring encapsulated layer, form and mount layer; The described layer that mounts is realized that with metal lead wire electricity is interconnected with the wiring layer in the end group wiring encapsulated layer; On end group wiring encapsulated layer, form and cover the described envelope bed of material that mounts layer, describedly mount layer and metal lead wire is coated sealing by the plastic packaging material of the described envelope bed of material.
Alternatively, described substrate is BT substrate or PCB substrate.
Alternatively, described mounting comprises chip in the layer, and described chip is single or many.
Alternatively, the described layer that mounts comprises that also passive device, described passive device are one or more in electric capacity, resistance or the inductance.
Alternatively, the material of the envelope bed of material is an epoxy resin.
Alternatively, the envelope bed of material forms by the method for printing, compression or metaideophone.
Compared with prior art, the high-density systems level packaging methods that the present invention asks for protection, encapsulation in the lump again after chip and passive device integrated can form and comprises the total system function but not the final encapsulating products of single chip functions; Simultaneously, see through wiring layer between the multilayer encapsulated layer and realized that more the high-density systems of 3 D stereo angle is interconnected, compare the encapsulation of existing systems level, Miltilayer wiring structure has made full use of the thickness of chip itself, satisfy that the compact trend of semiconductor packages requires and more complicated systemic-function integrate require in, reduced the disturbing factor of resistance, inductance and chip chamber in the system better, structural strength and product reliability are strengthened well.
Description of drawings
Fig. 1 and Fig. 2 are one embodiment of the invention middle-high density system-in-a-package method flow chart;
Fig. 3 to Figure 10 is an encapsulating structure schematic diagram in the flow process illustrated in figures 1 and 2.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was an example, and it should not limit the scope of protection of the invention at this.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
With reference to figure 1, show the schematic flow sheet of high-density systems level packaging methods one execution mode of the present invention, described system-in-a-package method may further comprise the steps:
S101 provides substrate;
S102 forms at least one group of wiring encapsulated layer on substrate;
S103 forms the wire bond package layer on end group wiring encapsulated layer;
S104 plants ball below described substrate.
Below in conjunction with accompanying drawing each step is described further.
Execution in step S101 at first, as shown in Figure 3, substrate 101 is provided, substrate 101 is follow-up bases of piling up each encapsulated layer, simultaneously, it also is the basis of follow-up each layer encapsulated layer of carrying, described substrate 101 comprises two function faces, wherein, the first surface of described substrate 101 is used to carry out piling up of encapsulated layer, and the second surface of described substrate 101 is used to plant ball (implant and connect ball), in the present embodiment, the upper surface of described substrate 101 is used to carry out piling up of encapsulated layer, and the lower surface of described substrate 101 is used to plant ball, on the described substrate 101, lower surface is provided with and is used to realize the pad that is electrically connected.
Wherein, described substrate 101 is generally BT (Bismaleimide Triazine) substrate or PCB (PrintedCircuit Board) substrate etc., so that carry out cabling between the first surface of substrate 101 and second surface.
Execution in step S102 with reference to figure 2, shows the schematic flow sheet of step S102 one embodiment shown in Figure 1, be example on substrate, to form two groups of wiring encapsulated layers in the present embodiment, but the present invention is not restricted to this, and particularly, described step S102 comprises step by step following:
Step S1021 attaches first and mounts layer on substrate;
Step S1022 forms the first envelope bed of material with posting first one side that mounts layer on the substrate;
Step S1023 forms first wiring layer on the first envelope bed of material;
Step S1024 piles up second and mounts layer on the first envelope bed of material;
Step S1025 forms the second envelope bed of material that covering second mounts layer on the first envelope bed of material;
Step S1026 forms second wiring layer on the second envelope bed of material.
Execution in step S1021 as shown in Figure 4, is affixed on the relative one side of the function face of chip and passive device on the substrate 101, forms first and mounts layer 102.Described first mounts layer 102 function face, be meant first mount layer 102 in bonding pads and the surface, pad place of passive device.First position that mounts that mounts layer 102 chips and passive device is to set according to the overall routing scheme of design.
In a preferred embodiment of the present invention, fit in first on the substrate 101 mount the layer 102 and follow-up mention mount the layer can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices.These chips and passive device become the part of a system in package product separately, finish the one or more independent function that realizes in the system level function separately.
In a preferred embodiment of the present invention, first mount layer in 102 chip and the combination of passive device design according to systemic-function.Therefore, around one or a core assembly sheet, have identical or different other one or a core assembly sheet, passive devices such as perhaps identical or different electric capacity, resistance or inductance; Similarly, around a passive device, has the passive device of identical or different other, perhaps one or more identical or different chips.
Execution in step S1022, as shown in Figure 5, form the first envelope bed of material 103, first link that mounts layer 102 is exposed posting first one side that mounts layer 102 on the substrate 101, in the present embodiment, described link is first to mount layer 102 the bonding pads and the pad of passive device.In the subsequent technique process, the described first envelope bed of material 103 both can protect first to mount layer 102, can be used as the supporting body of subsequent technique again.
In one embodiment of the invention, the material of the described first envelope bed of material 103 is an epoxy resin.The good seal performance of epoxy resin, plastotype is easy, is the preferred materials that forms the first envelope bed of material 103.Particularly, the method that forms the first envelope bed of material 103 can adopt the method such as printing, metaideophone or compression.The concrete steps of these methods are well known to those skilled in the art, do not repeat them here.
Execution in step S1023, as shown in Figure 6, on the first envelope bed of material 103, form first wiring layer 104, particularly, described first wiring layer 104 comprises the first vertically laterally wiring of wiring and first, described first vertically wiring be used to realize between first encapsulated layer and the substrate 101 and first encapsulated layer and other encapsulated layers between be electrically connected, described first laterally connects up is used to realize electrical connection between each device of first encapsulated layer.The step of described formation first wiring layer 104 comprises:
Formed for first little the leading in the first envelope bed of material, filled conductive material in first micro through hole forms the first vertically wiring afterwards;
On the first envelope bed of material, form and connect the described first vertically first laterally wiring of wiring.
Particularly, form first micro through hole by the mode of holing on the first envelope bed of material 103, described first micro through hole runs through the described first envelope bed of material 103, and exposes the pad in the substrate 101, forms with substrate 101 and carries out interconnected passage; Filled conductive material in described first micro through hole, thus the first vertically wiring formed, make first vertical wiring interconnected with the pad conducting in the substrate 101; On the first envelope bed of material 103, form and connect the first vertically first laterally wiring of wiring, described first laterally is routed on the first envelope bed of material 103 and forms first and mount in the layer 102 interconnected between each device, particularly, the described first horizontal wiring links to each other with the bond pad surface of chip and passive device.Described electric conducting material can be a metal, for example copper etc.
In the practical application, can in the envelope bed of material, form vertically wiring selectively according to design requirement, to realize respectively mounting between the layer or to mount electrical connection between layer and the substrate,, can avoid respectively mounting the interference between each device in the layer because the envelope bed of material has good insulation performance.
So far, finished the manufacturing process that on substrate, forms the first wiring encapsulated layer.
Execution in step S1024 piles up second and mounts layer 105 on the first envelope bed of material 103, described piling up is meant to mount layer 105 pre-position that places on the first envelope bed of material 103 with second.
Need to prove, in the described stacking procedure, mount layer 105 according to the supine mode of function with second and be stacked on the first envelope bed of material 103.Described second mounts layer 105 and first mounts layers 102 similarly, can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices.
Execution in step S1025 then forms on the first envelope bed of material 103 and covers second and mount the second envelope bed of material 106 of layer 105, and making second, to mount the pad of the bonding pads of layer 105 and passive device exposed.The material that forms the second envelope bed of material 106 can be identical with the material that forms the first envelope bed of material 103, promptly adopts epoxy resin to form the second envelope bed of material 106.
Execution in step S1026, as shown in Figure 7, on the second envelope bed of material 106, form second wiring layer 107, particularly, described second wiring layer 107 comprises the second vertically laterally wiring of wiring and second, described second vertically wiring be used to realize being electrically connected between second encapsulated layer and other encapsulated layers, the substrate 101, described second laterally connects up is used to realize electrical connection between each device of second encapsulated layer.The step of described formation second wiring layer 107 comprises:
Form second micro through hole in the second envelope bed of material, filled conductive material in second micro through hole forms the second vertically wiring afterwards;
On the second envelope bed of material, form and connect the described second vertically second laterally wiring of wiring.
The method of the method for described formation second wiring layer 107 and formation first wiring layer 104 is similar, does not repeat them here.
So far finished the manufacturing process that on substrate 101, forms the first wiring encapsulated layer and the second wiring encapsulated layer successively, seen through wiring layer between substrate 101, the first wiring encapsulated layer and the second wiring encapsulated layer and realized system interconnect.
In the foregoing description with two groups the wiring encapsulated layers be example, but the present invention is not restricted to this, can also be at the encapsulated layer that forms on the substrate 101 more than a group or two groups, the manufacturing process of other encapsulated layers and the manufacturing process of above-mentioned encapsulated layer are similar, do not repeat them here.
Execution in step S103 forms the wire bond package layer on end group wiring encapsulated layer.Be example to form the wire bond package layer on the second wiring encapsulated layer in the present embodiment, particularly, the step of described formation wire bond package layer comprises:
On the second envelope bed of material 106, pile up the 3rd and mount layer 108, the described the 3rd mounts layer 108 and second mounts layer 105 and first and mounts layers 102 similar, can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices, chip and passive device are still according to the supine mode of function and mount;
The 3rd pad that mounts the layer pad of 108 chips or chip and passive device and second wiring layer, 107 usefulness metal lead wires 109 are realized electric interconnected, formation structure as shown in Figure 8;
On the second envelope bed of material 106, form the 3rd envelope bed of material 110 that covering the 3rd mounts layer 108, make the 3rd to mount layer 108 and metal lead wire 109 is coated sealing by the plastic packaging material of the 3rd envelope bed of material 110, form structure as shown in Figure 9, the material that forms the 3rd envelope bed of material 110 can be identical with the material that forms the first envelope bed of material 103 and the second envelope bed of material 110, promptly adopts epoxy resin to form the 3rd envelope bed of material 110.
So far finished the manufacturing process that on end group wiring encapsulated layer, forms the wire bond package layer.
Execution in step S104 then, as shown in figure 10, ball is planted in substrate 101 belows, forms to connect ball 111.Particularly, with substrate 101 in be connected the cabling corresponding position and plant ball, the metal of planting ball can adopt multiple metals such as metallic tin, ashbury metal to form described connection ball 111, the described ball technology of planting is same as the prior art, does not repeat them here.
So far, realized adjacent by wiring layer and metal lead wire or interconnected between encapsulated layer of being separated by between substrate 101, each encapsulated layer, realized the integration of system again via the circuit arrangement of substrate 101 inside, finally function has been exported by planting ball.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the high-density systems level packaging methods is characterized in that, comprises step:
Substrate is provided; On described substrate, form at least one group of wiring encapsulated layer, the step that forms described wiring encapsulated layer comprise on substrate, form successively mount layer, the envelope bed of material, wiring layer; Form the wire bond package layer on end group wiring encapsulated layer, the step that forms described wire bond package layer comprises that formation successively mounts layer, metal lead wire bonding, the envelope bed of material; Wherein, substrate, respectively organize between the encapsulated layer and to see through wiring layer and metal lead wire and realize adjacent encapsulated layer or electric interconnected between encapsulated layer at interval; Below substrate, plant ball.
2. high-density systems level packaging methods as claimed in claim 1 is characterized in that, the concrete steps that form at least one group of wiring encapsulated layer on described substrate comprise:
On substrate, attach first and mount layer; Form the first envelope bed of material with posting first one side that mounts layer on the substrate, first link that mounts layer is exposed; On the first envelope bed of material, form first wiring layer.
3. high-density systems level packaging methods as claimed in claim 2 is characterized in that, described link is first to mount the pad of layer chips and/or passive device.
4. high-density systems level packaging methods as claimed in claim 2 is characterized in that, the step that forms first wiring layer on the first envelope bed of material comprises:
Form first micro through hole in the first envelope bed of material, filled conductive material in first micro through hole forms the first vertically wiring afterwards; On the first envelope bed of material, form and connect the described first vertically first laterally wiring of wiring, wherein, described first vertically wiring be used to realize being electrically connected between first encapsulated layer and substrate and other encapsulated layers, described first laterally connects up is used to realize electrical connection between each device of first encapsulated layer.
5. high-density systems level packaging methods as claimed in claim 1 is characterized in that, the concrete steps that form the wire bond package layer on end group wiring encapsulated layer comprise:
On end group wiring encapsulated layer, form and mount layer; The described layer that mounts is realized that with metal lead wire electricity is interconnected with the wiring layer in the end group wiring encapsulated layer; On end group wiring encapsulated layer, form and cover the described envelope bed of material that mounts layer, describedly mount layer and metal lead wire is coated sealing by the plastic packaging material of the described envelope bed of material.
6. as the described high-density systems level packaging methods of any claim of claim 1～5, it is characterized in that: described substrate is BT substrate or PCB substrate.
7. as the described high-density systems level packaging methods of any claim of claim 1～5, it is characterized in that: described mounting comprises chip in the layer, described chip is single or many.
8. high-density systems level packaging methods as claimed in claim 7 is characterized in that: the described layer that mounts comprises that also passive device, described passive device are one or more in electric capacity, resistance or the inductance.
9. as the described high-density systems level packaging methods of any claim of claim 1～5, it is characterized in that: the material of the envelope bed of material is an epoxy resin.
10. as the described high-density systems level packaging methods of any claim of claim 1～5, it is characterized in that: the envelope bed of material forms by the method for printing, compression or metaideophone.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110069992 CN102157394A (en) | 2011-03-22 | 2011-03-22 | High-density system-in-a-package method |
| US13/984,929 US9543269B2 (en) | 2011-03-22 | 2012-03-22 | System-level packaging methods and structures |
| PCT/CN2012/072769 WO2012126377A1 (en) | 2011-03-22 | 2012-03-22 | System-level packaging methods and structures |
| US15/362,625 US10741499B2 (en) | 2011-03-22 | 2016-11-28 | System-level packaging structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110069992 CN102157394A (en) | 2011-03-22 | 2011-03-22 | High-density system-in-a-package method |
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| Publication Number | Publication Date |
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| CN102157394A true CN102157394A (en) | 2011-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201110069992 Pending CN102157394A (en) | 2011-03-22 | 2011-03-22 | High-density system-in-a-package method |
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| CN (1) | CN102157394A (en) |
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| WO2012126377A1 (en) * | 2011-03-22 | 2012-09-27 | Nantong Fujitsu Microelectronics Co., Ltd. | System-level packaging methods and structures |
| WO2012126379A1 (en) * | 2011-03-23 | 2012-09-27 | Nantong Fujitsu Microelectronics Co., Ltd. | Three-dimensional system-level packaging methods and structures |
| CN102790513A (en) * | 2012-07-30 | 2012-11-21 | 华为技术有限公司 | Power supply module and packaging method thereof |
| CN103165477A (en) * | 2011-12-14 | 2013-06-19 | 新科金朋有限公司 | Method for forming vertical interconnect structure and semiconductor device |
| WO2013170485A1 (en) * | 2012-05-18 | 2013-11-21 | 深南电路有限公司 | Packaging structure and packaging method thereof |
| CN103633076A (en) * | 2013-11-21 | 2014-03-12 | 三星半导体(中国)研究开发有限公司 | Chip type package on encapsulating piece |
| CN104332465A (en) * | 2014-09-03 | 2015-02-04 | 江苏长电科技股份有限公司 | 3D packaging structure and technological method thereof |
| CN109626319A (en) * | 2019-01-11 | 2019-04-16 | 清华大学 | A kind of built-in type device and its packaging method |
| US10475779B2 (en) | 2008-12-12 | 2019-11-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
| CN112466834A (en) * | 2019-09-06 | 2021-03-09 | 力成科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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| CN109626319A (en) * | 2019-01-11 | 2019-04-16 | 清华大学 | A kind of built-in type device and its packaging method |
| CN112466834A (en) * | 2019-09-06 | 2021-03-09 | 力成科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN112466834B (en) * | 2019-09-06 | 2023-04-07 | 力成科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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Application publication date: 20110817 |