CN201994290U - Fan-out high-density package structure - Google Patents

Fan-out high-density package structure Download PDF

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Publication number
CN201994290U
CN201994290U CN2011200775990U CN201120077599U CN201994290U CN 201994290 U CN201994290 U CN 201994290U CN 2011200775990 U CN2011200775990 U CN 2011200775990U CN 201120077599 U CN201120077599 U CN 201120077599U CN 201994290 U CN201994290 U CN 201994290U
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China
Prior art keywords
layer
wiring
fan
out high
protective layer
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Expired - Lifetime
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CN2011200775990U
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Chinese (zh)
Inventor
陶玉娟
石磊
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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Abstract

The utility model relates to a fan-out high-density package structure, which comprises a protective layer, a rewiring metal layer, at least one group of wiring package layers, a top package layer and connecting balls, wherein the rewiring metal layer is embedded in the protective layer; and the connecting balls are arranged below metal in an opening at the bottom of the protective layer. Compared with the prior art, the fan-out high-density package structure requested to be protected by the utility model can form a final package product comprising an overall system function but not a single chip function, so that interference factors among internal resistance and inductance of a system and between chips of the system can be reduced. In addition, a more complex multilayer interconnection structure can be formed, so that wafer system level package with higher integration can be realized.

Description

Fan-out high-density packaging structure
Technical Field
The utility model relates to a semiconductor technology especially relates to a fan-out high density packaging structure.
Background
With the continuous development of integrated circuit technology, electronic products are increasingly developing toward miniaturization, intellectualization, high performance and high reliability. The integrated circuit package not only directly affects the performance of the integrated circuit, the electronic module and even the complete machine, but also restricts the miniaturization, low cost and reliability of the whole electronic system. Under the conditions of the gradual reduction of the size of the integrated circuit wafer and the continuous improvement of the integration level, the electronic industry puts higher and higher requirements on the integrated circuit packaging technology.
A package carrier is disclosed in chinese patent No. CN 1747156C. The package carrier includes: a carrier comprising a surface; the ball receiving pad is positioned on the surface of the carrier plate; the solder mask layer is formed on the surface of the carrier plate and comprises at least one opening, and the ball receiving pad is exposed out of the opening; the packaging carrier plate further comprises a patterned metal reinforcing layer, and the patterned metal reinforcing layer is formed on the ball pad along the side wall of the welding-proof layer opening.
However, with the trend of light, thin, short and small semiconductor products and the increasing demand for system functions of products, how to further improve the integration of system-in-package is a problem to be solved by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
The utility model provides a technical problem be: how to implement a fan-out system-in-package with a multi-layer structure.
In order to solve the technical problem, the utility model provides a fan-out high density packaging structure, include: the protective layer comprises a bottom protective layer, a middle protective layer and an upper protective layer, wherein openings are formed in the bottom protective layer and the upper protective layer; the rewiring metal layer is embedded in the protective layer, wherein part of metal of the rewiring metal layer is arranged in the openings of the bottom protective layer and the upper protective layer; the wiring packaging layer is positioned on the upper protection layer and comprises a front mounting layer, a wiring packaging material layer and a wiring layer which are sequentially positioned on the upper protection layer; the top packaging layer is positioned on the wiring packaging layer and comprises a flip chip packaging layer, bottom filling and a top material sealing layer which are sequentially positioned on the wiring packaging layer; and the connecting balls are arranged below the metal in the openings of the bottom protective layer.
Optionally, the fan-out high-density package structure includes a first wiring package layer, where the first wiring package layer includes a first positive mounting layer, a first wiring package material layer, and a first wiring layer, which are sequentially located on the protection layer.
Optionally, the functional side of each device in the first positive mounting layer faces upward.
Optionally, the first wiring sealing material layer is filled between the devices of the first front mounting layer, and the connecting members of the devices of the first mounting layer are exposed.
Optionally, the first wiring layer includes a first longitudinal wiring penetrating through the first wiring sealing material layer and electrically connected to the metal in the opening of the upper protection layer, and a first transverse wiring connected to the first longitudinal wiring and covering the first wiring sealing material layer and interconnecting devices in the first positive mounting layer.
Optionally, the functional side of each device in the flip-chip layer faces downward.
Optionally, the top sealing material layer is filled between the devices of the flip chip packaging layer and encapsulates the flip chip packaging layer.
Optionally, the protective layer is polyimide or benzocyclobutene.
Optionally, the mounting layer includes chips, and the chips are single or multiple.
Optionally, the mounting layer further comprises a passive device, and the passive device is one or more of a capacitor, a resistor, or an inductor.
Compared with the prior art, the fan-out high-density packaging structure provided by the utility model integrates the chip and the passive device and then packages the integrated chip and the passive device together, so that a final packaging product containing the function of the whole system instead of the function of a single chip can be formed; meanwhile, the interconnection of a high-density system in a three-dimensional angle is realized through the wiring layers among the multilayer packaging layers, compared with the existing system-in-package, the multilayer wiring structure fully utilizes the thickness of the chip, meets the trend requirement of light, thin, short and small semiconductor packaging and the more complex system function integration requirement, and simultaneously better reduces the resistance, inductance and interference factors among the chips in the system, and the structural strength and the product reliability are well enhanced.
Drawings
Fig. 1 is a schematic diagram of an embodiment of a fan-out high-density package structure according to the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention can be implemented in many different ways than those herein described and one skilled in the art can do so without departing from the spirit and scope of the present invention, which is not limited to the specific implementations disclosed below.
Secondly, the present invention is described in detail by using schematic diagrams, and when the embodiments of the present invention are described in detail, for convenience of illustration, the schematic diagrams are only examples, and the present invention should not be limited herein.
The utility model provides a fan-out high density packaging structure, include: the protective layer comprises a bottom protective layer, a middle protective layer and an upper protective layer, wherein openings are formed in the bottom protective layer and the upper protective layer; the rewiring metal layer is embedded in the protective layer, wherein part of metal of the rewiring metal layer is arranged in the openings of the bottom protective layer and the upper protective layer; the wiring packaging layer is positioned on the upper protection layer and comprises a front mounting layer, a wiring packaging material layer and a wiring layer which are sequentially positioned on the upper protection layer; the top packaging layer is positioned on the wiring packaging layer and comprises a flip chip packaging layer, bottom filling and a top material sealing layer which are sequentially positioned on the wiring packaging layer; and the connecting balls are arranged below the metal in the openings of the bottom protective layer.
The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings.
Referring to fig. 1, a schematic diagram of an embodiment of the fan-out high density package structure of the present invention is shown, in this embodiment, the fan-out high density package structure uses a protection layer, a rewiring metal layer, two sets of wiring package layers and a top package layer as an example, but the present invention is not limited thereto, and the fan-out high density package structure includes: the package structure comprises a protective layer 101, a rewiring metal layer 102 embedded in the protective layer 101, a first wiring encapsulation layer located on the protective layer 101, a second wiring encapsulation layer located on the first wiring encapsulation layer, a top encapsulation layer located on the second wiring encapsulation layer, and a connecting ball 113 arranged below the protective layer 101. Wherein,
the protective layer 101 is pre-disposed on a carrier plate, which serves as a bearing foundation for the protective layer 101 and its upper layer structure. The carrier plate can be made of siliceous wafers or glass materials which are easy to peel off and strong in corrosion resistance and can be recycled. Specifically, a release film, which may be a UV glue, is disposed between the protective layer 101 and the carrier, and this material can firmly adhere the protective layer 101 to the carrier, and after the whole fan-out high-density package structure is formed, the UV glue is irradiated by ultraviolet rays and then the viscosity of the UV glue is reduced, so that the carrier can be peeled off from the structure.
The protective layer 101 includes a bottom protective layer, a middle protective layer, and an upper protective layer, wherein openings are provided in both the bottom protective layer and the upper protective layer. The protection layer 101 is made of polyimide or benzocyclobutene, and the like, and the material is characterized in that a pattern and a pattern opening which are designed as desired can be formed by a photoetching development technology.
The rewiring metal layer 102 is embedded in the passivation layer 101, wherein a part of metal of the rewiring metal layer 102 is disposed in openings of the bottom passivation layer and the upper passivation layer, the metal disposed in the opening of the bottom passivation layer is used as an output ball (an implanted connection ball 113) for system functions, the metal disposed in the opening of the upper passivation layer is used for conducting interconnection with the package layers, and the rewiring metal layer 102 is routed under the insulation protection of the middle passivation layer so as to form a system circuit arrangement for the whole package structure.
The first wiring encapsulation layer comprises a first positive mounting layer 103, a first wiring encapsulation layer 104 and a first wiring layer 105 which are sequentially arranged on the protection layer 101. Wherein,
the first positive mounting layer 103 includes a plurality of semiconductor devices, in this embodiment, the first positive mounting layer 103 includes a chip and a passive device, specifically, the chip and the passive device are attached to the upper protection layer of the protection layer 101 in a manner that the functional surface faces upward, and the functional surface of the first positive mounting layer 103 refers to the surface where the chip and the pad of the passive device in the first positive mounting layer 103 are located.
In a preferred embodiment of the present invention, the first positive mounting layer 103 and the subsequent mounting layers disposed on the protection layer 101 may include one or more same or different chips, and may further include one or more same or different passive devices. These chips and passive devices each become part of a system-in-package product, each performing one or more individual functions among the system-in-package functions.
In a preferred embodiment of the present invention, the combination of the chip and the passive device in the first positive mounting layer 103 is configured according to the system function. Therefore, around one or a group of chips, there may be another chip or group of chips, which may be the same or different, or passive devices such as capacitors, resistors or inductors, which may be the same or different; similarly, there may be other passive devices that are the same or different, or one or more of the same or different chips, around a passive device.
The first wiring encapsulant layer 104 serves to insulate and isolate the various devices of the first front mounting layer 103, while also serving to insulate and isolate the different encapsulation layers. The first wiring sealing material layer 104 is filled between the devices of the first positive mounting layer 103, and part of the first wiring sealing material layer 104 covers the devices of the first positive mounting layer 103, the first wiring sealing material layer 104 exposes the connecting pieces of the devices of the first positive mounting layer 103, and specifically, the first wiring sealing material layer 104 exposes the bonding pad surfaces of the chip and the passive device group, so as to facilitate electrical connection.
Since the first wiring encapsulation layer 104 is filled between the devices of the first positive mounting layer 103 and exposes the connectors of the devices, the thickness of the first wiring encapsulation layer 104 is equal to that of the first positive mounting layer 103, the stacking thickness of the mounting layers can be reduced, and the integration level of the package structure can be improved to the maximum extent.
The first wiring layer 105 includes a first vertical wiring and a first horizontal wiring. The first longitudinal wire is a wire (e.g., a metal wire) penetrating through the first wire encapsulation layer 104, and is used for realizing interconnection between the first wire encapsulation layer and the upper passivation layer opening metal, that is, electrical connection between the first wire encapsulation layer and the redistribution metal layer 102.
In practical application, longitudinal wiring can be selectively formed in the sealing material layer according to design requirements so as to realize electrical connection between the packaging layers or between the packaging layers and the rewiring metal layer 102, and because the sealing material layer has good insulation, interference between devices in the mounting layers can be avoided.
The first transverse wiring is a wire (e.g., a metal wire) covering the first wiring encapsulant layer 104 and is conductively connected to the first longitudinal wiring for electrical connection between devices of the first front mounting layer 103, in this embodiment, the first transverse wiring is used for electrical connection between a chip and a passive device group in the first front mounting layer 103, and specifically, the first transverse wiring is connected to pad surfaces of the chip and the passive device.
The second wiring encapsulation layer is stacked on the first wiring encapsulation layer, and specifically comprises: and the second positive mounting layer 106, the second wiring sealing material layer 107 and the second wiring layer 108 are sequentially positioned on the first wiring packaging layer. In this embodiment, the second front mounting layer 106 includes chips and passive devices, and is stacked on the first wiring encapsulant layer 104 with the functional surface facing up. The second front mounting layer 106, similar to the first front mounting layer 103, may include one or more same or different chips, and may further include one or more same or different passive devices.
The second wiring encapsulation layer 107 serves to insulate and isolate the various devices of the second front side mounting layer 106, as well as to insulate and isolate the different encapsulation layers. The second wiring sealing material layer 107 is filled between the devices of the second positive mounting layer 106, and part of the second wiring sealing material layer 107 covers the devices of the second positive mounting layer 106, the second wiring sealing material layer 107 exposes the connecting members of the devices of the second positive mounting layer 106, and specifically, the second wiring sealing material layer 107 exposes the bonding pad surfaces of the chip and the passive device group, so as to facilitate electrical connection.
The second wiring layer 108 includes a second vertical wiring and a second horizontal wiring. The second vertical wirings are wires (e.g., metal wires) penetrating through the second wiring encapsulation layer 107, and are used for realizing electrical connection between the second wiring encapsulation layer and other encapsulation layers, and according to design requirements, the second vertical wirings are also used for realizing electrical connection between the second wiring encapsulation layer and the rewiring metal layer 102;
the second transverse wiring is a wire (e.g., a metal wire) covered on the second wiring encapsulation layer 107, and the second transverse wiring is connected to the second longitudinal wiring for implementing electrical connection between devices of the second front mounting layer 106, in this embodiment, the second transverse wiring is used for implementing electrical connection between a chip and a passive device group in the second front mounting layer 106.
The top encapsulation layer includes a flip-chip packaging layer 109, an underfill, and a top encapsulation layer 112, which are sequentially located on the second wire encapsulation layer.
The flip-chip mounting layer 109, similar to the mounting layer described above, may contain one or more of the same or different chips, and may also include one or more of the same or different passive devices. In this embodiment, the flip-chip layer 109 includes a chip and is attached to the second wiring encapsulation layer 107 in a functional surface-down manner, the functional surface of the chip has solder bumps 110, and the chip is electrically connected to the second transverse wirings of the second wiring layer 108 through the solder bumps 110.
In a preferred embodiment of the present invention, the passive devices can be configured around the flip chip according to design requirements, and the mounting direction of the passive devices can be consistent with the mounting direction of the chip to simplify the process flow, specifically, the functional pads of the passive devices are mounted on the predetermined positions of the wiring layer to realize electrical interconnection, and the specific steps of mounting are well known to those skilled in the art and are not described herein again.
A filler 111 is provided in a gap between the chip of the flip chip package 109 and the second wiring encapsulation layer to constitute an underfill. The underfill is used for avoiding product reliability problems such as internal cavities in the sealant layer. The filler 111 may be a polymer epoxy resin, which has good fluidity and can fully fill the gap between the flip chip and the encapsulant layer.
The top encapsulant layer 112 encapsulates the devices of the flip chip package 109 to form a package body, so as to prevent the pollution and corrosion of the external environment. The material forming the top seal material layer 112 may be the same as the material forming the first wiring seal material layer 104 and the second wiring seal material layer 107, that is, an epoxy resin is used to form the top seal material layer 112.
The fan-out high-density packaging structure further comprises a connecting ball 113 arranged below the metal in the opening of the bottom protection layer, and the connecting ball 113 is made of tin, tin alloy and other metals or metal alloys.
The above embodiment includes two sets of wiring encapsulation layers and a top encapsulation layer, but the present invention is not limited thereto, and one or more sets of wiring encapsulation layers may be used to match the top encapsulation layer, and those skilled in the art may make corresponding modifications, alterations and replacements according to the above embodiment.
The utility model discloses fan-out high density packaging structure has realized adjacent or the electricity between the encapsulation layer of being separated by through each wiring layer between each encapsulation layer and has connected, has realized the integration of system via the circuit arrangement of metal level 102 of rewiring again, finally exports the function through connecting ball 113.
Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.

Claims (10)

1. Fan-out high density packaging structure, its characterized in that includes:
the protective layer comprises a bottom protective layer, a middle protective layer and an upper protective layer, wherein openings are formed in the bottom protective layer and the upper protective layer;
the rewiring metal layer is embedded in the protective layer, wherein part of metal of the rewiring metal layer is arranged in the openings of the bottom protective layer and the upper protective layer;
the wiring packaging layer is positioned on the upper protection layer and comprises a front mounting layer, a wiring packaging material layer and a wiring layer which are sequentially positioned on the upper protection layer;
the top packaging layer is positioned on the wiring packaging layer and comprises a flip chip packaging layer, bottom filling and a top material sealing layer which are sequentially positioned on the wiring packaging layer;
and the connecting balls are arranged below the metal in the openings of the bottom protective layer.
2. The fan-out high density package structure of claim 1, wherein the fan-out high density package structure comprises a first wire encapsulation layer comprising a first positive mounting layer, a first wire encapsulation layer, a first wire layer, in that order on a protective layer.
3. The fan-out high density package structure of claim 2, in which the functional side of each device in the first positive mounting layer is up.
4. The fan-out high density package structure of claim 2, wherein the first wiring encapsulant layer fills between the devices of the first positive mounting layer and exposes connectors of the devices of the first mounting layer.
5. The high-density system-in-package structure of claim 2, wherein the first wiring layer comprises a first vertical wiring penetrating the first wiring encapsulation layer and electrically connected to the metal in the opening of the upper passivation layer, and a first horizontal wiring connected to the first vertical wiring, covering the first wiring encapsulation layer, and interconnecting the devices in the first positive mounting layer.
6. The fan-out high density package structure of claim 1, in which the functional side of each device in the flip-chip is down.
7. The fan-out high density package structure of claim 1, wherein the top encapsulant layer fills between and encapsulates the flip chip devices.
8. The fan-out high density package structure of any of claims 1 to 5, wherein: the protective layer is polyimide or benzocyclobutene.
9. The fan-out high density package structure of any of claims 1 to 7, wherein: the mounting layer comprises a single chip or a plurality of chips.
10. The fan-out high density package structure of claim 9, wherein: the mounting layer further comprises a passive device, and the passive device is one or more of a capacitor, a resistor or an inductor.
CN2011200775990U 2011-03-22 2011-03-22 Fan-out high-density package structure Expired - Lifetime CN201994290U (en)

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