CN104078431A - Packaging and interconnecting structure and method for copper protruded points filled up with double layers of underfill - Google Patents
Packaging and interconnecting structure and method for copper protruded points filled up with double layers of underfill Download PDFInfo
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- CN104078431A CN104078431A CN201410300624.5A CN201410300624A CN104078431A CN 104078431 A CN104078431 A CN 104078431A CN 201410300624 A CN201410300624 A CN 201410300624A CN 104078431 A CN104078431 A CN 104078431A
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- glue
- layer
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- fill
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
The invention relates to a packaging and interconnecting structure and method for copper protruded points filled up with double layers of underfill. The packing and interconnecting structure is characterized in that the chip end is filled up with the first layer of underfill, the first layer of underfill is manufactured on a wafer through spin coating process, the substrate end is filled up with the second layer of underfill, the substrate end is filled through capillary effects after flip-chip welding is finished, the glass transition temperature and the Young modulus of the first layer of underfill are lower than those of the second layer of the underfill, a chip and a substrate are connected through the copper protruded points and tin-contained solder protruded points to achieve high-density connection, and the copper protruded points are manufactured in twice to guarantee that the first layer underfill is completely filled and the contact between the protruded points and the tin-contained solder is enough. The whole technological process is compatible with existing IC process and has higher vertical interconnection density, better electric connection characteristics and higher mechanical stability. Heating thermal circulation tests show that the service life of chips of the packaging structures is greatly prolonged.
Description
Technical field
The present invention relates to a kind of double bottom and fill copper bump packaging interconnection structure and the method that glue is filled, belong to Advanced Electronic Encapsulating field.
Background technology
In flip chip bonding, need to have salient point to connect chip and substrate, because the thermal coefficient of expansion between material differs larger, can produce very large thermal stress, in order to guarantee the integrality of salient point, need to fill the end and fill glue concentrated stress is disperseed.For traditional, containing tin solder and organic substrate, require the end to fill glue and there is higher vitrification point, larger Young's modulus and thermal coefficient of expansion.
Along with IC technique is to smaller szie high density future development more, late effect between interconnection line is more and more subject to people and pays close attention to, become the bottleneck that limited chip performance further improves, this just requires to adopt new interconnection material and connected medium layer (ILD, Interlayer Dielectric).Using copper alloy as interconnect material, and low-k (low-K) material can well improve device speed as connected medium layer, reduces power consumption.But compare with traditional dielectric layer, advanced low-k materials is generally all more crisp, has higher thermal coefficient of expansion and less modulus of elasticity, adopt advanced low-k materials to do after dielectric layer, can between chip and dielectric layer, produce larger thermal stress.Therefore the integrality of protection soldered ball is not only in the end effect of filling glue, also will protect chip and dielectric layer.Research shows that low Tg, low elastic modulus are conducive to strengthen the reliability of chip and dielectric layer, and higher vitrification point, higher modulus of elasticity are conducive to strengthen the reliability of soldered ball and substrate.
In addition, along with constantly advancing of Moore's Law, the characteristic size of silicon technology has broken through 28nm now, and this also requires encapsulating structure to have less bump size and salient point pitch.And adopt soldered ball to be directly connected with chip, substrate, have significant limitation, size is further dwindled and is faced larger difficulty.And adopt copper bump to connect, not only there is good electrical connection characteristic, and keep the distance between chip and substrate when reaching higher density, there is good application prospect.At present, copper bump technology has started progressively to promote the use of, but because copper has larger Young's modulus, can introduce larger stress in die terminals.At present, industry still uses conventional methods carries out the filling of filling glue in the end, can not make the stress of die terminals effectively be reduced, and the reliability that causes copper bump is not very desirable.Therefore, the present invention proposes a kind of double bottom and fills the structure that glue is filled, and can effectively carry out stresses re-distribution, improves the reliability of copper pillar bump.
Summary of the invention
The object of the present invention is to provide a kind of double bottom to fill copper bump packaging interconnection structure and method that glue is filled.In order to reduce the thermal stress in packaging interconnection structure, take into account chip, connected medium layer and substrate, scolder and filled to the different requirements of glue the end, the present invention proposes a kind of double bottom and fills glue fill method, wherein at the bottom of ground floor, fill glue in die terminals, have lower vitrification point (lower than 110 ℃), lower Young's modulus (is less than 7 * 10
9pa), adopt spin coating proceeding to fill, centre is electroplate with copper bump; At the bottom of the second layer, fill glue at edge of substrate, have higher vitrification point (higher than 110 ℃), higher Young's modulus (is greater than 7 * 10
9pa), chip, substrate, complete containing tin solder bonding after, by capillary effect, fill.This double bottom is filled the encapsulating structure that glue is filled, and has better realized the heavily distribution of thermal stress, has improved integrally-built reliability; This structure adopts copper bump and stanniferous solder bump as machinery and electrical connection simultaneously, can realize higher interconnection density, has good electric property.
The technical solution used in the present invention is: first utilize the upper electro-coppering salient point of electroplating technology metal (UBM) under salient point; Then at the bottom of spin coating ground floor, fill glue, solidify; Then carry out chemico-mechanical polishing and expose copper bump; Then carrying out copper bump for the second time electroplates; Then be diced into discrete chip.On substrate, make stanniferous solder bump, the chip pulling is attached on substrate, be welded to one, fill glue at the bottom of finally applying the second layer by capillary effect, solidify.(referring to embodiment).
Concrete technology step of the present invention is as follows:
A. electro-coppering salient point
(a) first the chip surface after rerouting is coated with thicker photoresist, photoresist thickness 10-30 μ m;
(b) by the good reticle of making, carry out photoetching, by sputtering at the Seed Layer that side wall deposition one deck is very thin.
(c) electro-coppering, removes photoresist.
B. at the bottom of applying ground floor, fill glue
(a) with spin-coating method, at the bottom of coating ground floor, fill glue, make the end fill the complete covering copper salient point of glue.
(b) at the bottom of curing ground floor, fill glue.
(c) with chemico-mechanical polishing, coated surface is processed, copper bump is come out.
C. electro-coppering salient point for the second time
(a) on the basis completing at step B, in the copper bump surface electro-coppering for the second time of exposing, this time thinner thickness carried out sputter clean to ground floor copper bump before electroplating, and it is exposed completely, and other techniques are identical with A.
(b) scribing.
D. at the bottom of chip and bonding and the filling second layer, fill glue
(a) on substrate, make stanniferous solder bump.Can pass through laser ball implanting or silk screen printing reflux technique.
(b) on the substrate of having made stanniferous solder bump, apply scaling powder.
(c) chip step C being completed carries out Flip chip with substrate and is connected.
(d) after bonding completes, by capillary effect, carry out the filling of filling glue at the bottom of the second layer, glue is filled in the end and be cured.
As can be seen here, processing step feature provided by the invention is:
1. the photoresist thickness described in steps A is 10-30 μ m;
2. steps A electro-coppering salient point pitch is 120 μ m, and I reaches 50 μ m, and even less, UBM opening diameter is 60 μ m;
3. the chip surface described in steps A exposes the copper bump diameter 20-60 μ m of UBM, and height is 10-30 μ m;
4. step B fills the complete covering copper salient point of glue at the bottom of applying ground floor, and it is Henkel Hysol FF2300 that glue model is filled at the end of employing, and its vitrification point is 81 ℃, and Young's modulus is 2.6 * 10
9pa;
5. step C for the second time in electro-coppering salient point electrodeposited coating thickness be 5-10 μ m;
6. at the bottom of the second layer of the coating described in step D, filling the end that glue adopts, to fill glue model be Henkel ABLEFILL UF8829, and its vitrification point is 122 ℃, and Young's modulus is greater than 7.47 * 10
9pa.
The feature that the double bottom being provided by above-mentioned manufacture craft is filled the copper bump packaging interconnection structure of glue filling is:
(1) double bottom is filled glue filling, and ground floor contacts with chip, adopts spin coating proceeding to make on disk, and it has relatively low vitrification point (being less than 110 ℃), less Young's modulus (is less than 7 * 10
9pa); The second layer is filled by capillary effect after flip chip bonding completes, and it has compared with high glass transition temperature (being greater than 110 ℃), larger Young's modulus and (is greater than 7 * 10
9pa).
Concrete structure is shown in that accompanying drawing 8. its chips 101 and being connected of substrate 108 are to consist of copper bump 105 and stanniferous solder bump 107 two parts, can realize high density and connect; In structure, fill glue and be divided into twice at the end, is to be formed by twice filling, fills glue 106 in die terminals at the bottom of ground floor, adopts spin coating proceeding to make on disk, at the bottom of this ground floor, fill glue and be vitrification point lower than 110 ℃, Young's modulus is less than 7 * 10
9glue is filled at the end of Pa; At the bottom of the second layer, fill glue 109 at edge of substrate, after flip chip bonding completes, by capillary effect, fill, at the bottom of this second layer, fill glue and be vitrifying higher than 110 ℃, Young's modulus is greater than 7 * 10
9glue is filled at the end of Pa.Corresponding copper bump 105 is also made at twice, both can guarantee the filling completely of filling glue at the bottom of ground floor, also can guarantee salient point and contain enough fully contacting of tin solder.
(2) chip is to consist of copper bump and stanniferous solder bump two parts with being connected of substrate, realizes high density process.
(3) copper bump is made at twice, both can guarantee the filling completely of filling glue at the bottom of ground floor, also can guarantee salient point and enough contacting containing tin solder.
In sum; the present invention proposes a kind of double bottom and fills wafer-level package structure and the method that glue is filled; fill glue and be filled between chip and substrate at the end that the present invention proposes two kinds of different qualities; when disperseing salient point concentrated stress, also can protect interconnected dielectric layer; and reduce the stress between connected medium layer and silicon chip, strengthened global reliability.Its chips and substrate are realized machinery and electrical connection by copper bump and stanniferous solder bump.The coating of filling glue realize ground floor on the basis of disk technique at the bottom of, after flip chip bonding, carry out filling glue coating at the bottom of the second layer, owing to filling glue and there is no characteristic in the two-layer end, meet respectively the requirement of different contact-making surfaces, can better realize stresses re-distribution, improve reliability and the thermal stability of whole system.And, at the contact-making surface of the copper bump of having electroplated and stanniferous solder bump, can first electroplate iron, nickel or layer of iron-nickel alloy that one deck is very thin, reduce contact resistance and issuable cavity, be conducive to improve Electric connection characteristic and mechanical stability.Whole technical process and existing IC process compatible, can realize higher perpendicular interconnection density, higher Electric connection characteristic and higher mechanical stability.It is even less that minimum pitch can reach 50 μ m, and owing to adopting copper bump, the more traditional tinbase salient point of resistance reduces by 40%～60%.In addition, by accelerating thermal cycle test, show, experience (40 ℃～125 ℃) after 1500 thermal cycles, the chip of encapsulating structure of the present invention still can works fine, so have higher reliability, has improved useful life.With respect to the advanced low-k materials of current employing, as interconnection line dielectric layer and requirement, glue is filled at the end that Young's modulus is less, fully demonstrates superiority.
Accompanying drawing explanation
Fig. 1 is at chip active face, applies the thicker photoresist of one deck.
Fig. 2 is the position exposure that metal under salient point (UBM) is corresponding, after development, in relevant position, exposes UBM.
Fig. 3 is the copper bump shape schematic diagram of electroplating in copper bump position, removing photoresist and form.
Fig. 4 fills glue at the bottom of spin coating ground floor after having plated copper bump, makes its covering copper salient point fully completely, solidifies.
Fig. 5 carries out chemico-mechanical polishing, and the copper bump of electroplating is come out.
Fig. 6 is the schematic diagram of electroplating after second layer copper bump.
Fig. 7 is that chip carries out back bonding with the substrate of having made stanniferous solder bump.
Fig. 8 fills glue at the bottom of utilizing capillary effect to fill the second layer, solidifies.
Marginal data:
101: chip; 106: at the bottom of ground floor, fill glue;
102: metal under salient point (UBM); 107: stanniferous solder bump;
103: passivation layer; 108: substrate;
104: photoresist; 109: at the bottom of the second layer, fill glue;
105: copper.
Embodiment
In order to make advantage of the present invention and good effect find full expression, below in conjunction with drawings and Examples, substantive distinguishing features of the present invention and significant progress are described further.
Fig. 1 is the active face at chip, applies the thicker photoresist 104 of one deck, and its bumps pitch is 120 μ m, and UBM opening diameter is about 60 μ m, and photoresist thickness is about 30 μ m.
Fig. 2 is in position exposure corresponding to UBM, after development, in relevant position, exposes UBM.
Fig. 3 is at copper bump position sputtering seed layer, the copper bump shape schematic diagram of then electroplating, removing photoresist and form.Copper bump diameter 60 μ m, high 30 μ m.
Fig. 4 fills glue at the bottom of spin coating ground floor after having plated copper bump, makes its covering copper salient point fully completely, solidifies.That at the bottom of this layer, fill that glue adopts is Henkel Hysol FF2300, has relatively low vitrification point (81 ℃), less Young's modulus (2.6 * 10
9pa).
Fig. 5 carries out chemico-mechanical polishing, and the copper bump of electroplating is come out.
Fig. 6 is the schematic diagram of electroplating after second layer copper bump, and electroplating thickness is about 10 μ m.
Fig. 7 is that chip carries out back bonding with the substrate of having made stanniferous solder bump.
Fig. 8 fills glue at the bottom of utilizing capillary effect to fill the second layer, solidifies.That at the bottom of this layer, fill that glue adopts is Henkel ABLEFILL UF8829, has higher vitrification point (122 ℃), larger Young's modulus (is greater than 7.47 * 10
9pa).
Claims (7)
1. double bottom is filled the copper bump packaging interconnection structure that glue is filled, and it is characterized in that:
(1) by double bottom, fill glue and fill, ground floor, in die terminals, adopts spin coating proceeding to make on disk; The second layer, at edge of substrate, is filled by capillary effect after flip chip bonding completes; At the bottom of ground floor, fill vitrification point and the Young's modulus of at the bottom of the vitrification point of glue and the lower second layer of Young's modulus, filling glue;
(2) chip is to consist of copper bump and stanniferous solder bump two parts with being connected of substrate, realizes high density and connects;
(3) copper bump is made at twice, to guarantee filling filling completely and guaranteeing salient point and enough contacting containing tin solder of glue at the bottom of ground floor.
2. by structure claimed in claim 1, it is characterized in that:
1. at the bottom of ground floor, filling glue model is Henkel Hysol FF2300, and vitrification point is 81 ℃, and Young's modulus is 2.6 * 10
9pa;
2. at the bottom of the second layer, filling glue model is Henkel AB LEFILL UF8829, and vitrification point is 122 ℃, and Young's modulus is greater than 7.47 * 10
9pa.
3. double bottom is filled the manufacture method of the copper bump packaging interconnection structure that glue fills, and it is characterized in that first utilizing electroplating technology electro-coppering salient point on metal UBM under salient point; Then at the bottom of spin coating ground floor, fill glue, solidify; Then carry out chemico-mechanical polishing and expose copper bump; Then carrying out copper bump for the second time electroplates; Be diced into subsequently discrete chip.Secondly, on substrate, apply containing tin solder and make salient point, the chip pulling is attached on substrate, be welded to one, fill glue at the bottom of finally applying the second layer by capillary effect, curing.
4. by method claimed in claim 3, it is characterized in that concrete technology step is:
A. electro-coppering salient point
(1) first on the surface of chip, be coated with thicker photoresist;
(2) by the good reticle of making, carry out photoetching, the UBM of chip surface is exposed, by sputtering at sidewall and the very thin Seed Layer of bottom deposition one deck;
(3) electro-coppering, removes photoresist;
B. at the bottom of applying ground floor, fill glue
(1) with spin-coating method, at the bottom of coating ground floor, fill glue, make the end fill the complete covering copper salient point of glue;
(2) at the bottom of curing ground floor, fill glue;
(3) with chemico-mechanical polishing, coated surface is processed, copper bump is come out;
C. electro-coppering salient point for the second time
(1) on the basis completing at step B, in the copper bump surface electro-coppering for the second time of exposing, before electroplating, ground floor copper bump is carried out to sputter clean, it is exposed completely, other techniques are identical with A;
(2) scribing;
D. at the bottom of chip and bonding and the filling second layer, fill glue
(1) on substrate, by laser ball implanting or silk screen printing reflux technique, make stanniferous solder bump;
(2) on the substrate of having made stanniferous solder bump, apply scaling powder;
(3) chip of step C being made carries out Flip chip with substrate and is connected, and makes copper bump and carries out bonding containing tin solder;
(4) after bonding completes, clean and remove remaining scaling powder, finally by capillary effect, carry out the filling of filling glue at the bottom of the second layer, solidify.
5. by method claimed in claim 4, it is characterized in that the stone that contacts with stanniferous solder bump at the copper bump of having electroplated, can first electroplate iron, nickel or iron-nickel alloy that one deck is thin, to reduce contact resistance.
6. by the method described in claim 3 or 4, it is characterized in that whole technical process and IC process compatible.
7. by method claimed in claim 4, it is characterized in that:
1. the photoresist thickness described in steps A is 10-30 μ m;
2. the copper bump pitch described in steps A is 50-120 μ m, and UBM opening diameter is 60 μ m;
3. the copper bump diameter 20-60 μ m described in steps A, height is 10-30 μ m;
4. in the salient point of electro-coppering for the second time described in step C, electrodeposited coating thickness is 5-10 μ m.
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| CN201410300624.5A CN104078431B (en) | 2014-06-27 | 2014-06-27 | Packaging and interconnecting structure and method for copper protruded points filled up with double layers of underfill |
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| CN201410300624.5A CN104078431B (en) | 2014-06-27 | 2014-06-27 | Packaging and interconnecting structure and method for copper protruded points filled up with double layers of underfill |
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| CN105575924A (en) * | 2014-10-15 | 2016-05-11 | 台达电子工业股份有限公司 | Power module |
| CN106252276A (en) * | 2016-08-08 | 2016-12-21 | 中国电子科技集团公司第五十四研究所 | Manufacture method based on TSV technology switch matrix radio frequency unit |
| CN107210269A (en) * | 2015-03-11 | 2017-09-26 | 英特尔公司 | Utilize the stretchable electronic device manufacturing method for straining redistribution layer |
| CN109103117A (en) * | 2017-06-20 | 2018-12-28 | 普罗科技有限公司 | In conjunction with the method for the equipment and combination semiconductor chip of semiconductor chip |
| CN109967747A (en) * | 2019-04-03 | 2019-07-05 | 深圳第三代半导体研究院 | A kind of metal multilayer film and preparation method thereof |
| CN111384003A (en) * | 2018-12-27 | 2020-07-07 | 财团法人工业技术研究院 | Electronic component packaging structure and manufacturing method thereof |
| CN116154609A (en) * | 2023-04-04 | 2023-05-23 | 深圳市光为光通信科技有限公司 | Photoelectric co-packaging method based on VCSEL (vertical cavity surface emitting laser) laser |
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| US10276522B2 (en) | 2014-10-15 | 2019-04-30 | Delta Electronics, Inc. | Power module |
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| CN109103117B (en) * | 2017-06-20 | 2022-05-17 | 普罗科技有限公司 | Apparatus for bonding semiconductor chips and method of bonding semiconductor chips |
| CN111384003A (en) * | 2018-12-27 | 2020-07-07 | 财团法人工业技术研究院 | Electronic component packaging structure and manufacturing method thereof |
| CN109967747A (en) * | 2019-04-03 | 2019-07-05 | 深圳第三代半导体研究院 | A kind of metal multilayer film and preparation method thereof |
| CN116154609A (en) * | 2023-04-04 | 2023-05-23 | 深圳市光为光通信科技有限公司 | Photoelectric co-packaging method based on VCSEL (vertical cavity surface emitting laser) laser |
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