CN109637985B - Packaging structure for fan-out of chip and manufacturing method thereof - Google Patents

Packaging structure for fan-out of chip and manufacturing method thereof Download PDF

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CN109637985B
CN109637985B CN201811540271.0A CN201811540271A CN109637985B CN 109637985 B CN109637985 B CN 109637985B CN 201811540271 A CN201811540271 A CN 201811540271A CN 109637985 B CN109637985 B CN 109637985B
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chip
fan
layer
carrier
chip carrier
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CN109637985A (en
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任玉龙
孙鹏
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a packaging structure of chip fan-out, comprising: a chip carrier having a first embedded groove; a chip disposed in the first insertion groove; a back metal disposed on a back side of the chip; the plastic sealing layer is partially filled in a gap between the chip and the embedded groove, and the plastic sealing layer realizes wafer reconstruction of the front surface of the chip and the chip carrier and leaks out of a welding structure of the chip; a re-layout wiring layer (RDL) that implements a fan-out function for the chip pins; and the external solder balls are arranged on the external bonding pads of the outermost redistribution layer (RDL).

Description

Packaging structure for fan-out of chip and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip fan-out packaging structure and a manufacturing method thereof.
Background
With the demand for light weight and miniaturization of electronic products, IC chip packages tend to be thin and miniaturized. At this time, the conventional plastic package IC chip is more likely to generate local thermal stress due to mismatch of Coefficient of Thermal Expansion (CTE) between each packaging material (especially between the chip and the plastic package material), so that the package is likely to generate surface warpage. The excessive warping not only increases the difficulty of subsequent processes (such as rib cutting, forming and the like) after plastic packaging, but also obviously increases the process reject ratio when the finished product of the plastic packaged IC chip is assembled by SMT, and is easy to generate serious device failure problems such as chip and packaging cracks and the like.
In the field of Fan-Out (Fan-Out) package technology (as shown in fig. 1, 101 is an IC chip and 102 is a molding layer in fig. 1), the problem of package warpage due to manual wafer reconfiguration of Fan-Out package is a significant challenge. Because the reconstituted wafer contains the plastic packaging material, silicon and the metal material, and the thermal expansion coefficient of the volume edge between the silicon and the plastic packaging material is different in X, Y, Z directions, the thermal expansion and cold contraction effects are generated due to heating and cooling in the processing technology, so that the warping behavior of the packaging body is influenced. In addition, the excessive epoxy resin not only influences the warping of the reconstituted wafer, but also greatly reduces the heat dissipation effect of the chip.
Aiming at the problems of poor warping and heat dissipation effect of a packaging body and the like in the existing Fan-Out (Fan-Out) packaging technology, the invention provides a novel chip Fan-Out packaging structure and a manufacturing method thereof, and at least part of the problems are overcome.
Disclosure of Invention
In order to solve the problems of warpage of a package body, poor heat dissipation effect and the like in the existing Fan-Out (Fan-Out) packaging technology, the invention provides a chip Fan-Out packaging structure according to one aspect of the invention, which comprises:
a chip carrier having a first embedded groove;
a chip disposed in the first insertion groove;
a back metal disposed on a back side of the chip;
the plastic packaging layer is partially filled in a gap between the chip and the embedded groove, the plastic packaging layer realizes wafer reconstruction of the front surface of the chip and the chip carrier, and exposes the welding structure of the chip;
a re-layout wiring layer (RDL) that implements a fan-out function for the chip pins; and
and the external solder balls are arranged on the external bonding pads of the outermost redistribution layer (RDL).
In one embodiment of the invention, the chip carrier is a silicon wafer or a glass wafer.
In an embodiment of the present invention, the package structure of fan-out of a chip further includes a chip mounting layer, and the chip mounting layer is disposed on the back surface of the chip near the edge.
In one embodiment of the present invention, the chip carrier further has a second insertion groove for receiving the soldering structure of the chip.
In an embodiment of the invention, the package structure of the fan-out of the chip further comprises a chip mounting layer, wherein the chip mounting layer is arranged on the front surface of the chip close to the edge position and fixes the chip to the chip carrier.
In one embodiment of the invention, the re-layout routing layer (RDL) has N layers of routing, where N ≧ 2.
In one embodiment of the invention, the package structure of the chip fan-out further comprises a passivation layer disposed between the two adjacent layers of the redistribution routing layer (RDL) and/or above the redistribution routing layer (RDL).
According to another embodiment of the present invention, there is provided a method of manufacturing a package structure of a chip fan-out, including:
providing a chip carrier, wherein a first embedded groove and a second embedded groove are preset in the front of the chip carrier;
flip-chip mounting is carried out on the chip to a first embedded groove of the chip carrier;
filling glue in a gap between the chip and the chip carrier to form a first plastic packaging layer;
forming a back metal layer on the back of the chip;
thinning the back of the chip carrier to expose the second embedded groove;
filling glue on the back surface of the chip carrier and the second embedded groove to form a second plastic packaging layer;
thinning the second plastic packaging layer and the back surface of the chip carrier to expose the welding structure of the chip;
making a re-layout wiring layer; and
and forming external solder balls.
In another embodiment of the present invention, the performing the redistribution layer fabrication implements a fan-out function for the chip pins.
According to another embodiment of the present invention, there is provided a method for manufacturing a package structure of a chip fan-out, including:
bonding the chip carrier with the embedded groove to the carrier plate;
the chip is positively mounted in a chip carrying sheet embedded groove, and the back surface of the chip is fixed with the carrier plate through a chip mounting layer;
carrying out whole-surface plastic package on the front surface of the chip carrier and a gap between the chip and the chip carrier to form a plastic package layer;
removing the bonding and the carrier plate;
forming a back metal layer on the back of the chip;
thinning the plastic packaging layer and the chip carrier to expose the welding structure of the chip;
making a re-layout wiring layer; and
and forming external solder balls.
The invention provides a chip fan-out packaging structure and a manufacturing method thereof.A preprocessed silicon chip or glass is used as a slide glass to carry out chip fan-out packaging, so that the use of epoxy resin in the packaging structure is greatly reduced, and the rigidity of a reconstructed wafer is increased; and meanwhile, the chip is subjected to back gold treatment, so that the heat dissipation effect of the chip is obviously improved. The packaging structure for fan-out of the chip and the manufacturing method thereof have the advantages that the warping of a fan-out packaging body is improved; the heat dissipation effect is improved; the manufacturing process flow of the packaging structure is simple; high product reliability and the like.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 is a cross-sectional view of a fan-out chip package 100 used in the prior art.
Fig. 2 illustrates a cross-sectional view of a package structure 200 for chip fan-out formed in accordance with an embodiment of the present invention.
Fig. 3A to 3I are schematic cross-sectional views illustrating a process of forming the package structure 200 of chip fan-out according to an embodiment of the invention.
Fig. 4 illustrates a flow diagram 400 for forming the package structure 200 for chip fan-out according to one embodiment of the invention.
Fig. 5 illustrates a cross-sectional view of a package structure 500 for chip fan-out formed in accordance with another embodiment of the present invention.
Fig. 6 illustrates a cross-sectional view of a package structure 600 for chip fan-out formed in accordance with yet another embodiment of the present invention.
Fig. 7 illustrates a flow diagram 700 for forming the package structure 600 of chip fan-out according to yet another embodiment of the present invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a chip fan-out packaging structure and a manufacturing method thereof.A preprocessed silicon chip or glass is used as a slide glass to carry out chip fan-out packaging, so that the use of epoxy resin in the packaging structure is greatly reduced, and the rigidity of a reconstructed wafer is increased; and meanwhile, the chip is subjected to back gold treatment, so that the heat dissipation effect of the chip is obviously improved. The packaging structure for fan-out of the chip and the manufacturing method thereof have the advantages that the warping of a fan-out packaging body is improved; the heat dissipation effect is improved; the manufacturing process flow of the packaging structure is simple; high product reliability and the like.
A chip fan-out package structure according to an embodiment of the invention is described in detail below with reference to fig. 2. Fig. 2 illustrates a cross-sectional view of a package structure 200 for chip fan-out formed in accordance with an embodiment of the present invention. As shown in fig. 2, the package structure 200 of the chip fan-out further includes a chip carrier 210, a chip 220, a chip layer 230, a first molding layer 240, a back metal 250, a second molding layer 260, a redistribution layer (RDL)270, a passivation layer 280, and external solder balls 290.
The chip die 210 acts as a fan-out structural support for the package structure 200 for the entire chip fan-out. The chip carrier 210 further includes a first insertion groove 211 for receiving a chip to be embedded and a second insertion groove 212 for receiving a chip bonding structure. In one embodiment of the present invention, the chip carrier sheet 210 is a silicon wafer or a glass sheet. However, one skilled in the art will appreciate that other materials having good structural rigidity may be used as the material for the carrier sheet 210.
The chip 220 is fixed to the bottom surface of the first insertion groove 211 of the chip 210 by the chip attach layer 230. The chip 220 may be a logic chip such as a cpu, a DSP, or an FPGA, or a memory chip such as a DRAM or a FLASH, or may be another type of chip, such as an SOC or an MEMS sensor. The patch layer 230 may be a solder material (e.g., solder) or a paste material (e.g., a patch paste).
The first molding compound 240 is disposed in a gap between the chip 220 and the chip carrier 210, and protects the chip 210. In one embodiment of the present invention, the first molding layer 240 is resin.
The back metal 250 is disposed on the back side of the chip 220 to improve heat dissipation. The back metal 250 may be a metal such as copper, nickel, aluminum, or combinations or compounds thereof.
The second molding compound layer 260 is disposed on the front surface of the chip and in the second embedded groove 212, so as to realize the wafer reconfiguration function of the package structure. Wherein the solder structures 221 of the chip 220 are exposed from the second molding layer 260. In one embodiment of the present invention, the material of the second molding layer 260 is the same as that of the first molding layer 240, and is also resin. In other embodiments of the present invention, the second molding layer 260 may be made of other molding materials that are the same as or different from the first molding layer 240.
A redistribution layer (RDL)270 is disposed on the outer drain surface of the second molding layer 260 and the corresponding surface of the chip carrier 210 to implement a pin fan-out function for the chip 210. In one embodiment of the invention, the re-layout routing layer (RDL)270 may be one or more layers, as determined by design requirements.
The passivation layer 280 is used for protection of the redistribution routing layer (RDL)270 or for insulation between the multiple layers of the redistribution routing layer (RDL) 270. The passivation layer 280 may be an organic material such as a curing paste, a semi-curing paste, a resin, PI, or the like, and may be an inorganic material such as silicon oxide, silicon nitride, or the like.
External solder balls 290 are disposed on the outermost external pads of the redistribution routing layer (RDL)270 to enable electrical and/or signal interconnection with external circuitry.
A process of forming the package structure 200 of the chip fan-out is described in detail below with reference to fig. 3A to 3I and fig. 4. Fig. 3A to 3I are schematic cross-sectional views illustrating a process of forming the package structure 200 of chip fan-out according to an embodiment of the invention; fig. 4 illustrates a flow diagram 400 for forming the package structure 200 for chip fan-out according to one embodiment of the invention.
First, at step 410, as shown in fig. 3A, a chip-slide 310 is provided. The front surface of the chip 310 is previously completed with the first and second insertion grooves 311 and 312 according to design. Wherein the first embedded groove 311 is used for embedding the chip; the second insertion groove 312 is used to receive a chip bonding structure. In one embodiment of the present invention, the chip carrier 310 is a silicon wafer, and the first insertion groove 311 and the second insertion groove 312 are sequentially formed through an etching process.
Next, at step 420, as shown in fig. 3B, the chip 320 is flip-chip mounted into the first insertion groove 311 of the chip carrier 310, and the chip carrier 310 is fixed by the mounting layer 330. In one embodiment of the present invention, the die attach layer 330 is a ring-shaped solder material. In yet another embodiment of the present invention, the patch layer 330 is a ring-shaped adhesive material. The front side of the chip 320 includes a solder structure 321.
Then, in step 430, as shown in fig. 3C, the gap between the chip 320 and the chip carrier 310 is filled with glue to form the first molding compound layer 340. The first molding compound layer 340 mainly fills the side surfaces of the chip 320 and a few of the upper and lower surfaces adjacent to the side surfaces.
Next, at step 440, as shown in fig. 3D, a back metal layer 350 is formed on the back surface of the chip 320. The back metal layer 350 serves to improve heat dissipation of the chip 320, and the back metal 350 may be a metal such as copper, nickel, aluminum, or a combination or compound thereof, and may be formed by electroplating, CVD deposition, or the like.
Then, at step 450, as shown in fig. 3E, thinning of the back surface of the chip 310 is performed to expose the second insertion groove 312. In one embodiment of the present invention, the back surface of the chip carrier 310 is thinned by grinding and/or Chemical Mechanical Polishing (CMP) process until the second embedded groove 312 is exposed, and then cleaned.
Next, at step 460, as shown in fig. 3F, glue is filled on the back surface of the chip carrier 310 and the second insertion groove 312 to form the second molding layer 360. The second molding layer 360 is formed to cover the back surface of the chip carrier 310 and to fill the second embedding groove 312. The second molding compound layer 360 plays a role in wafer reconfiguration of the package structure.
Then, in step 470, as shown in fig. 3G, the second molding layer 360 and the back surface of the chip carrier 310 are thinned to expose the bonding structures 321 on the front surface of the chip. The solder structures 321 may be pads, conductive copper pillars, bumps, etc.
Next, in step 480, as shown in fig. 3H, the wiring layer 370 is re-laid out. The re-layout wiring layer 370 is electrically connected to the die attach structure 321 and implements the pin fan-out function of the die 320. In one embodiment of the present invention, the re-layout wiring layer 370 may have one or more metal layers with a passivation layer 380 disposed between adjacent re-layout wiring layers 370 and/or overlying the outermost re-layout wiring layer 370 to provide insulation protection to the re-layout wiring layer 370 while exposing the external pads of the outermost re-layout wiring layer 370.
Finally, at step 490, as shown in FIG. 3I, external solder balls 390 are formed. The external solder balls 390 may be formed by plating or ball-planting.
Fig. 5 illustrates a cross-sectional view of a package structure 500 for chip fan-out formed in accordance with another embodiment of the present invention. As shown in fig. 5, the package structure 500 for chip fan-out further includes a chip carrier 510, a chip 520, a chip attach layer 530, a first molding compound layer 540, a back metal 550, a second molding compound layer 560, a redistribution layer (RDL)570, a passivation layer 580, and external solder balls 590. The difference between the chip fan-out package structure 500 and the chip fan-out package structure 200 is that the back surface of the chip carrier 510 is thinned to a greater extent, and the chip carrier does not have a second embedded groove, and other structures are completely the same, and are not described herein again.
Fig. 6 illustrates a cross-sectional view of a package structure 600 for chip fan-out formed in accordance with yet another embodiment of the present invention. As shown in fig. 6, the package structure 600 of chip fan-out further includes a chip carrier 610, a chip 620, a chip layer 630, a molding layer 640, a back metal 650, a redistribution layer (RDL)660, a passivation layer 670, and external solder balls 680. The difference between the package structure 600 for fan-out of chip and the package structure 500 for fan-out of chip is two points: the first point is that there is only one molding layer 640; the second point is that the patch layer 630 is located on the back side of the chip 620.
Fig. 7 shows a flowchart 700 of forming the package structure 600 for chip fan-out according to another embodiment of the present invention, and as shown in fig. 7, the package structure 600 for chip fan-out is formed by the following steps:
first, at step 710, a chip carrier is bonded to a carrier plate. The bonding mode can be completed by heating and laser detachable bonding glue. The chip carrier has an insertion groove for receiving the chip.
Next, in step 720, the chip is mounted to the insertion slot of the chip carrier, and the back surface of the chip is fixed to the carrier through the mounting layer.
Then, in step 730, the gap between the chip and the chip carrier and the front surface of the chip carrier are filled with glue to form a plastic package layer, so as to achieve the wafer reconfiguration function of the package structure.
Next, at step 740, the bond is removed and the carrier plate is removed. The carrier plate may be removed by heating, light irradiation, etc., depending on the properties of the bonding material.
Then, in step 750, a back metal layer is formed on the back side of the chip. The back metal layer is used for improving the heat dissipation of the chip, and the back metal can be copper, nickel, aluminum and other metals or a composition or compound thereof and can be formed by electroplating, CVD deposition and other processes.
Next, in step 760, the molding layer and the chip carrier are thinned to expose the chip bonding structure. The die bonding structures may be pads, conductive copper pillars, bumps, etc.
Next, in step 770, a re-layout wiring layer fabrication is performed. And the re-layout wiring layer is electrically connected with the chip welding structure, and the fan-out function of the pins of the chip is realized.
Finally, at step 780, external solder balls are formed. The external solder balls may be formed by electroplating or ball-planting processes.
According to the chip fan-out packaging structure and the manufacturing method thereof, the chip fan-out packaging is carried out by taking the preprocessed silicon wafer or glass as a slide glass, so that the use of epoxy resin in the packaging structure is greatly reduced, and the rigidity of a reconstructed wafer is increased; and meanwhile, the chip is subjected to back gold treatment, so that the heat dissipation effect of the chip is obviously improved. The packaging structure for fan-out of the chip and the manufacturing method thereof have the advantages that the warping of a fan-out packaging body is improved; the heat dissipation effect is improved; the manufacturing process flow of the packaging structure is simple; high product reliability and the like.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (7)

1. A package structure of a chip fan-out, comprising:
a chip carrier having a first embedded groove;
a chip disposed in the first insertion groove;
a back metal disposed on a back side of the chip;
the plastic packaging layer is partially filled in a gap between the chip and the embedded groove, the plastic packaging layer realizes wafer reconstruction of the front surface of the chip and the chip carrier, and exposes the welding structure of the chip;
a wiring layer RDL is re-laid, and the re-laid wiring layer RDL realizes the fan-out function of the chip pins; and
an external solder ball arranged on the external pad at the outermost layer of the redistribution routing layer RDL,
wherein the chip carrier further has a second insertion groove for accommodating the soldering structure of the chip.
2. The package structure of chip fan-out of claim 1, in which the chip carrier is a silicon wafer or a glass sheet.
3. The package structure of the chip fan-out of claim 1, further comprising a sticker sheet disposed on the front side of the chip proximate to an edge location to secure the chip to the chip carrier.
4. The package structure of chip fan-out of claim 1, in which the re-routing layer (RDL) has N layers of routing, where N ≧ 2.
5. The package structure of chip fan-out of claim 1 or 4, further comprising a passivation layer disposed between two adjacent layers in the re-layout wiring layer RDL and/or over the re-layout wiring layer RDL.
6. A manufacturing method of a packaging structure of chip fan-out comprises the following steps:
providing a chip carrier, wherein a first embedded groove and a second embedded groove are preset in the front of the chip carrier;
flip-chip mounting is carried out on the chip to a first embedded groove of the chip carrier;
filling glue in a gap between the chip and the chip carrier to form a first plastic packaging layer;
forming a back metal layer on the back of the chip;
thinning the back of the chip carrier to expose the second embedded groove;
filling glue on the back surface of the chip carrier and the second embedded groove to form a second plastic packaging layer;
thinning the second plastic packaging layer and the back surface of the chip carrier to expose the welding structure of the chip;
making a re-layout wiring layer; and
and forming external solder balls.
7. The method of claim 6, wherein said performing re-routing wiring layer fabrication implements a fan-out function for the chip pins.
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