CN111883521B - Multi-chip 3D packaging structure and manufacturing method thereof - Google Patents

Multi-chip 3D packaging structure and manufacturing method thereof Download PDF

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Publication number
CN111883521B
CN111883521B CN202010670966.1A CN202010670966A CN111883521B CN 111883521 B CN111883521 B CN 111883521B CN 202010670966 A CN202010670966 A CN 202010670966A CN 111883521 B CN111883521 B CN 111883521B
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layer
die
chip
conductive
redistribution
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CN111883521A (en
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霍炎
涂旭峰
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to PCT/CN2021/106025 priority patent/WO2022012538A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a multi-chip 3D packaging structure and a manufacturing method thereof, wherein in the packaging structure, a first bare chip, a second bare chip and a conductive column which are arranged back to back are packaged in a plastic packaging layer, the first bare chip comprises a plurality of first bonding pads positioned on an active surface, the active surface of the first bare chip is covered with a protective layer exposing the first bonding pads, and the second bare chip comprises a plurality of second bonding pads positioned on the active surface; the protective layer, the first bonding pads, the first ends of the conductive columns and the front surface of the plastic packaging layer are provided with first redistribution layers so as to perform circuit layout on each first bonding pad, and the first redistribution layers are led to the back surface of the plastic packaging layer through the conductive columns; and the active surface of the second bare chip, the second end of the conductive column and the back surface of the plastic packaging layer are provided with second re-wiring layers so as to perform circuit layout on each second bonding pad, the second re-wiring layers are electrically connected with the first re-wiring layers through the conductive columns, and the second re-wiring layers are provided with pins. The multi-chip 3D packaging structure has the advantages of more complex wiring, smaller volume and higher degree of freedom.

Description

Multi-chip 3D packaging structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of chip packaging, in particular to a multi-chip 3D packaging structure and a manufacturing method thereof.
Background
In recent years, with the continuous development of circuit integration technology, electronic products are increasingly developed toward miniaturization, intellectualization, high integration, high performance and high reliability. The packaging technique not only affects the performance of the product, but also restricts the miniaturization of the product.
In view of this, the present invention provides a multi-chip 3D package structure and a method for manufacturing the same, so as to meet the requirements of small size, compact structure and high integration level of the package structure.
Disclosure of Invention
The invention aims to provide a multi-chip 3D packaging structure and a manufacturing method thereof, so as to meet the requirements of small size, compact structure and high integration level of the packaging structure.
To achieve the above object, a first aspect of the present invention provides a multi-chip 3D package structure, including:
a first die and a second die, the first die including a number of first bonding pads, the first bonding pads being located on an active side of the first die, the second die including a number of second bonding pads, the second bonding pads being located on an active side of the second die; the first die and the second die are arranged back-to-back;
a protective layer covering an active side of the first die, the protective layer exposing the first pad;
conductive pillars located at sides of the first and second dies, the conductive pillars including opposing first and second ends;
a molding compound layer covering the first die, the second die and the conductive pillars, wherein the front surface of the molding compound layer exposes the protective layer, the first bonding pad and the first ends of the conductive pillars, and the back surface of the molding compound layer exposes the active surface of the second die and the second ends of the conductive pillars;
a first redistribution layer located on the protection layer, the first pads, the first ends of the conductive pillars, and the front surface of the plastic package layer, and configured to perform circuit layout on the first pads, where the first redistribution layer is led to the back surface of the plastic package layer through the conductive pillars;
a first dielectric layer embedding the first rewiring layer;
a second redistribution layer on the active surface of the second die, the second end of the conductive pillar, and the back surface of the molding layer, for performing circuit layout on each of the second pads, the second redistribution layer being electrically connected to the first redistribution layer through the conductive pillar;
a pin connected to the second rewiring layer;
and the second dielectric layer at least embeds the second rewiring layer, and the pins are exposed outside the second dielectric layer.
Optionally, the conductive pillars are distributed on a plurality of sides of the first die and the second die.
Optionally, the second die is a control die for controlling the first die.
Optionally, the area of the second die is larger than the area of the first die.
Optionally, the material of the protective layer is an insulating resin material or an inorganic material.
Optionally, the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
Optionally, the first redistribution layer includes two or more layers; and/or the second rewiring layer includes two or more layers.
The second aspect of the present invention provides a method for manufacturing a multi-chip 3D package structure, comprising:
providing a carrier and at least one group of to-be-packaged pieces loaded on the carrier, wherein each group of to-be-packaged pieces comprises: the semiconductor device comprises a conductive column, a first die and a second die, wherein the first die and the second die are arranged back to back, the first die comprises a plurality of first bonding pads, the first bonding pads are positioned on the active surface of the first die, the active surface of the first die is covered with a protective layer, the second die comprises a plurality of second bonding pads, and the second bonding pads are positioned on the active surface of the second die; the conductive post comprises a first end and a second end which are opposite; wherein the active surface of the second die and the second ends of the conductive pillars face the carrier board, and the conductive pillars are located at the sides of the first die and the second die;
forming a plastic packaging layer for embedding the to-be-packaged part on the surface of the carrier plate; thinning the plastic packaging layer until the protective layer and the first end of the conductive column are exposed;
forming an opening in the protective layer to expose the first pad; forming a first redistribution layer on the protection layer, the first pads, the first ends of the conductive pillars, and the front surface of the plastic package layer, wherein the first redistribution layer is used for performing circuit layout on the first pads, and the first redistribution layer is led to the back surface of the plastic package layer through the conductive pillars; forming a first dielectric layer embedding the first rewiring layer;
removing the carrier plate to expose the active surface of the second bare chip, the second ends of the conductive posts and the back surface of the plastic packaging layer; forming a second redistribution layer on the active surface of the second die, the second end of the conductive pillar, and the back surface of the molding layer, wherein the second redistribution layer is used for performing circuit layout on each second pad, and the second redistribution layer is electrically connected with the first redistribution layer through the conductive pillar;
and forming a pin on the second rewiring layer and a second dielectric layer at least embedding the second rewiring layer, wherein the pin is exposed outside the second dielectric layer.
Optionally, a group of packages to be packaged includes a plurality of the conductive pillars distributed at a plurality of sides of the first die and the second die.
Optionally, the packages to be packaged carried by the carrier board are in multiple groups, the first redistribution layer is used for performing circuit layout on each first pad of the first die in a group, and the first redistribution layer is led to the back surface of the molding layer through the conductive pillars in the group; the second redistribution layer is used for performing circuit layout on each second bonding pad of the second die in the group, and the second redistribution layer is electrically connected with the first redistribution layer through the conductive pillars in the group; and after the pins and the second dielectric layer are formed, cutting to form a plurality of multi-chip 3D packaging structures, wherein each multi-chip 3D packaging structure comprises a group of to-be-packaged parts.
Optionally, the material of the protective layer is an insulating resin material or an inorganic material.
Optionally, the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
Optionally, the first redistribution layer includes two or more layers; and/or the second rewiring layer includes two or more layers.
A third aspect of the present invention provides a multi-chip 3D package structure, comprising:
a first die and a second die, the first die including a number of first bonding pads, the first bonding pads being located on an active side of the first die, the second die including a number of second bonding pads, the second bonding pads being located on an active side of the second die; the first die and the second die are arranged back-to-back;
a protective layer covering an active side of the first die, the protective layer exposing the first pad;
the plastic package layer covers the first bare chip and the second bare chip, the front surface of the plastic package layer exposes the protective layer and the first bonding pad, the back surface of the plastic package layer exposes the active surface of the second bare chip, and a conductive plug is arranged in the plastic package layer and is positioned at the side edges of the first bare chip and the second bare chip;
the first rewiring layer is positioned on the protective layer, the first bonding pads, one end of the conductive plug and the front surface of the plastic packaging layer and used for carrying out circuit layout on each first bonding pad, and the first rewiring layer is led to the back surface of the plastic packaging layer through the conductive plug;
a first dielectric layer embedding the first rewiring layer;
a second redistribution layer located on an active surface of the second die, another end of the conductive plug, and a back surface of the molding layer, for performing circuit layout on each of the second pads, the second redistribution layer being electrically connected to the first redistribution layer through the conductive plug;
a pin connected to the second rewiring layer;
and the second dielectric layer at least embeds the second rewiring layer, and the pins are exposed outside the second dielectric layer.
Optionally, the conductive plugs are distributed on a plurality of sides of the first die and the second die.
Optionally, the second die is a control die for controlling the first die.
Optionally, the area of the second die is larger than the area of the first die.
Optionally, the material of the protective layer is an insulating resin material or an inorganic material.
Optionally, the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
Optionally, the first redistribution layer includes two or more layers; and/or the second rewiring layer includes two or more layers.
The fourth aspect of the present invention provides a method for manufacturing a multi-chip 3D package structure, comprising:
providing a carrier and at least one group of to-be-packaged pieces loaded on the carrier, wherein each group of to-be-packaged pieces comprises: the semiconductor device comprises a first die and a second die which are arranged back to back, wherein the first die comprises a plurality of first bonding pads, the first bonding pads are positioned on the active surface of the first die, the active surface of the first die is covered with a protective layer, the second die comprises a plurality of second bonding pads, and the second bonding pads are positioned on the active surface of the second die; wherein an active side of the second die faces the carrier plate;
forming a plastic packaging layer for embedding the to-be-packaged part on the surface of the carrier plate; thinning the plastic packaging layer until the protective layer is exposed;
forming an opening in the protective layer to expose the first pad; forming a first rewiring layer on the front surfaces of the protective layer, the first bonding pads and the plastic packaging layer, wherein the first rewiring layer is used for performing circuit layout on each first bonding pad; forming a first dielectric layer embedding the first rewiring layer;
removing the carrier plate, and exposing the active surface of the second bare chip and the back surface of the plastic packaging layer; forming a conductive plug in the plastic packaging layer through the back surface of the plastic packaging layer so as to lead the first rewiring layer to the back surface of the plastic packaging layer; forming a second redistribution layer on the active surface of the second die, the conductive plugs and the back surface of the plastic package layer, wherein the second redistribution layer is used for performing circuit layout on each second bonding pad, and the second redistribution layer is electrically connected with the first redistribution layer through the conductive plugs;
and forming a pin on the second rewiring layer and a second dielectric layer at least embedding the second rewiring layer, wherein the pin is exposed outside the second dielectric layer.
Optionally, a group of to-be-packaged components correspondingly form a plurality of the conductive plugs, and the conductive plugs are distributed on a plurality of sides of the first die and the second die.
Optionally, the packages to be packaged carried by the carrier board are in multiple groups, the first redistribution layer is used for performing circuit layout on each first pad of the first die in a group, and the first redistribution layer is led to the back surface of the molding layer through the conductive plugs in the group; the second redistribution layer is used for performing circuit layout on each second bonding pad of the second bare chip in the group, and the second redistribution layer is electrically connected with the first redistribution layer through the conductive plug in the group; and after the pins and the second dielectric layer are formed, cutting to form a plurality of multi-chip 3D packaging structures, wherein each multi-chip 3D packaging structure comprises a group of to-be-packaged parts.
Optionally, the material of the protective layer is an insulating resin material or an inorganic material.
Optionally, the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
Optionally, the first redistribution layer includes two or more layers; and/or the second rewiring layer includes two or more layers.
The inventor finds out in the development process that: the multi-chip 3D packaging structure can be realized by two methods: a plurality of die stacks within the package structure and a plurality of chip package structure stacks within the package structure.
A plurality of bare chips in the packaging structure are stacked, each bare chip is firstly arranged on a corresponding substrate in an inverted mode, the two sides of each substrate are provided with interconnection welding points, and the plurality of substrates can be stacked through the interconnection welding points to be electrically interconnected.
The stacking of the chip packaging structures in the packaging structure is to overlap small-scale packaging bodies of the same type and similar sizes, and to solder the same terminals of the overlapped small-scale packaging bodies together by utilizing the terminal arrangement of the original standard packaging bodies so as to realize the electric connection among the packaging bodies.
However, the multi-chip 3D package structure has a large size and a complicated packaging process.
Different from the two packaging modes, in the multi-chip 3D packaging structure, the first bare chip, the second bare chip and the conductive columns which are arranged back to back are packaged in the plastic packaging layer, the first bare chip comprises a plurality of first bonding pads, the first bonding pads are positioned on the active surface of the first bare chip, the active surface of the first bare chip is covered with a protective layer which exposes the first bonding pads, the second bare chip comprises a plurality of second bonding pads, and the second bonding pads are positioned on the active surface of the second bare chip; the protective layer, the first bonding pads, the first ends of the conductive columns and the front surface of the plastic packaging layer are provided with first redistribution layers so as to perform circuit layout on each first bonding pad of the first bare chip, and the first redistribution layers are led to the back surface of the plastic packaging layer through the conductive columns; and the active surface of the second bare chip, the second end of the conductive post and the back surface of the plastic packaging layer are provided with a second re-wiring layer so as to perform circuit layout on each second bonding pad of the second bare chip, the second re-wiring layer is electrically connected with the first re-wiring layer through the conductive post, and the second re-wiring layer is provided with a pin. The first rewiring layer is combined with the second rewiring layer, and through circuit layout on two surfaces, compared with the circuit layout on only one surface, the density of wiring can be improved, and a multi-chip 3D packaging structure with more complex wiring and smaller volume is formed. The multi-chip 3D packaging structure realizes external circuit connection through pins and has reliable performance. In addition, the layout modes of the conductive columns, the first redistribution layer and the second redistribution layer are free and flexible, and are not limited by the size of the substrate.
In addition, due to the existence of the protective layer, a first rewiring layer can be directly formed on the protective layer and the front surface of the plastic packaging layer after the plastic packaging process is finished, and a dielectric layer does not need to be formed on the whole panel; in panel packaging, the process difficulty of forming a dielectric layer on a large-area panel is high due to the large panel area, the dielectric layer is made of more materials, and the existence of the protective layer reduces the process difficulty and the cost of packaging.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a multi-chip 3D package structure according to a first embodiment of the present invention;
FIG. 2 is a flow chart of a method of fabricating the multi-chip 3D package structure of FIG. 1;
FIGS. 3-9 are schematic intermediate structures corresponding to the flow chart of FIG. 2;
FIG. 10 is a schematic cross-sectional view of a multi-chip 3D package structure according to a second embodiment of the invention;
FIG. 11 is a flow chart of a method of fabricating the multi-chip 3D package structure of FIG. 10;
fig. 12 to 18 are intermediate structural diagrams corresponding to the flow in fig. 11.
To facilitate an understanding of the invention, all reference numerals appearing in the invention are listed below:
first bare chip 11 of multi-chip 3D packaging structure 1, 2
First pads 111 the back side 11b of the first die
Active surface 11a of the first die the second die 12
Second pads 121 the back side 12b of the second die
Second die active surface 12a conductive post 13
First end 13a of the conductive post and second end 13b of the conductive post
Plastic-sealing layer 14 front surface 14a of plastic-sealing layer
Back surface 14b of plastic encapsulation layer first rewiring layer 15
First dielectric layer 16 second rewiring layer 17
Lead 18 second dielectric layer 19
Metal block 15a, 17a carrier plate 2
Opening 110a supporting plate 3
Conductive plug 20 conductive convex column 181
To-be-packaged piece 10, 10'
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic cross-sectional structure diagram of a multi-chip 3D package structure according to a first embodiment of the invention.
Referring to fig. 1, a multi-chip 3D package structure 1 includes:
a first die 11 and a second die 12, the first die 11 including a plurality of first bonding pads 111, the first bonding pads 111 being located on an active surface 11a of the first die 11, the second die 12 including a plurality of second bonding pads 121, the second bonding pads 121 being located on an active surface 12a of the second die 12; the first die 11 and the second die 12 are arranged back to back;
a protective layer 110 covering the active surface 11a of the first die 11, the protective layer 110 exposing the first pad 111;
a conductive pillar 13 located at a side of the first die 11 and the second die 12, the conductive pillar 13 including a first end 13a and a second end 13b opposite to each other;
a molding compound layer 14, which encapsulates the first die 11, the second die 12 and the conductive pillars 13, wherein a front surface 14a of the molding compound layer 14 exposes the protective layer 110, the first bonding pad 111 and the first ends 13a of the conductive pillars 13, and a back surface 14b of the molding compound layer 14 exposes the active surface 12a of the second die 12 and the second ends 13b of the conductive pillars 13;
a first redistribution layer 15 located on the protection layer 110, the first pads 111, the first ends 13a of the conductive pillars 13, and the front surface 14a of the molding layer 14, and configured to perform circuit layout on the respective first pads 111, where the first redistribution layer 15 is led to the back surface 14b of the molding layer 14 through the conductive pillars 13;
a first dielectric layer 16 embedding the first redistribution layer 15;
a second redistribution layer 17 located on the active surface 12a of the second die 12, the second end 13b of the conductive pillar 13, and the back surface 14b of the molding layer 14, and configured to perform circuit layout on each second pad 121, wherein the second redistribution layer 17 is electrically connected to the first redistribution layer 15 through the conductive pillar 13;
a pin 18 connected to the second rewiring layer 17;
a second dielectric layer 19 at least embedding the second redistribution layer 17, and the leads 18 exposed outside the second dielectric layer 19.
Referring to fig. 1, in the present embodiment, the area of the second die 12 is larger than that of the first die 11, so as to reduce the area of the multi-chip 3D package structure. In some embodiments, the area of the first die 11 may also be larger than the area of the second die 12.
The first DIE 11 may be a POWER DIE (POWER DIE), a MEMORY DIE (MEMORY DIE), a sensing DIE (SENSOR DIE), or a RADIO frequency DIE (RADIO frequency DIE). The second die 12 may be a control chip for controlling the first die 11. In other embodiments, the first die 11 and the second die 12 may be dies requiring electrical interconnection, having other functions. The invention does not limit the function of the first die 11 and the second die 12.
The first die 11 includes an active surface 11a and a back surface 11b opposite to each other. The first pad 111 is provided on the active surface 11 a. The first die 11 may include a variety of devices formed on a semiconductor substrate, and electrical interconnect structures electrically connected to the various devices. The first pads 111 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.
The second die 12 includes opposing active and backside surfaces 12a and 12 b. The second pad 121 is disposed on the active surface 12 a. The second die 12 may include a variety of devices formed on a semiconductor substrate, as well as electrical interconnect structures electrically connected to the various devices. The second pads 121 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.
The first die 11 and the second die 12 are disposed back-to-back, which means that: the back surface 11b of the first die 11 is bonded to the back surface 12b of the second die 12.
The protective layer 110 is an insulating material, and may be specifically an insulating resin material, or may be an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, abf (ajinomoto build file), pbo (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other organic materials having similar insulating properties. The inorganic material is, for example, at least one of silicon dioxide and silicon nitride.
The material of the conductive post 13 may be a metal having excellent conductivity, such as copper.
The number of the conductive pillars 13 may be one or more, and the number and the position of the conductive pillars 13 may be determined according to a predetermined circuit layout.
The material of the molding layer 14 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the molding layer 14 may also be various polymers or a composite of resin and polymer.
The molding layer 14 includes a front surface 14a and a back surface 14b opposite to each other. In this embodiment, the front surface 14a of the molding layer 14 exposes the protection layer 110 and the first ends 13a of the conductive pillars 13.
In the embodiment shown in fig. 1, the first redistribution layer 15 includes a plurality of metal blocks 15a having one layer. A part of the number of metal blocks 15a is selectively electrically connected to a number of first pads 111 to realize a circuit layout of the first pads 111; a partial number of metal blocks 15a are electrically connected to the first ends 13a of the conductive pillars 13 to enable electrical signals of the first die 11 to be routed to the back surface 14b of the molding layer 14. The layout of the first redistribution layer 15 may be determined according to a predetermined circuit layout.
In some embodiments, the first redistribution layer 15 may further include two or more layers, i.e., two or more layers of metal blocks 15 a.
The second rewiring layer 17 includes several metal blocks 17a, having one layer. A part of the number of metal blocks 17a is selectively electrically connected with a number of second pads 121 to realize a circuit layout of the second pads 121; a partial number of metal bumps 17a are electrically connected to the second ends 13b of the conductive pillars 13 to electrically connect the second redistribution layer 17 to the first redistribution layer 15. The layout of the second re-wiring layer 17 may be determined according to a predetermined circuit layout.
In some embodiments, the second re-wiring layer 17 may further include two or more layers, i.e., two or more layers of metal blocks 17 a.
The leads 18 on the second redistribution layer 17 may be metal posts.
The material of the first dielectric layer 16 and the second dielectric layer 19 may be an insulating resin material or an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, abf (ajinomoto build file), pbo (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other organic materials having similar insulating properties. The inorganic material is, for example, at least one of silicon dioxide and silicon nitride. Compared with inorganic materials, the insulating resin material has smaller tensile stress, and can prevent the surface of the multi-chip 3D packaging structure 1 from warping.
Referring to fig. 1, in the multi-chip 3D package structure 1 in the present embodiment, external circuit connection of multiple chips is realized through pins 18.
In the multi-chip 3D package structure 1, on the one hand, the first redistribution layer 15 implements a circuit layout on the front surface 14a of the molding layer 14, and on the other hand, the conductive posts 13 and the second redistribution layer 17 implement a circuit layout on the back surface 14b of the molding layer 14. Compared with the circuit layout on only one side, the two-side circuit layout mode of the embodiment can improve the density of wiring, and form the multi-chip 3D package structure 1 with more complex wiring and smaller volume.
In addition, the multi-chip 3D package structure 1 realizes external circuit connection through the pins 18, so that the performance of the multi-chip 3D package structure 1 is reliable. The conductive pillars 13, the first redistribution layer 15, and the second redistribution layer 17 are freely and flexibly laid out, and are not limited by the size of the substrate.
An embodiment of the invention provides a manufacturing method of the multi-chip 3D package structure 1 in fig. 1. Fig. 2 is a flow chart of a method of fabrication. Fig. 3 to 9 are intermediate schematic diagrams corresponding to the flow in fig. 2.
First, referring to step S1 in fig. 2, fig. 3 and fig. 4, a carrier 2 and a plurality of to-be-packaged devices 10 carried on the carrier 2 are provided, where each of the to-be-packaged devices 10 includes: the semiconductor package comprises a conductive column 13, and a first die 11 and a second die 12 arranged back to back, wherein the first die 11 comprises a plurality of first bonding pads 111, the first bonding pads 111 are located on an active surface 11a of the first die 11, the active surface 11a of the first die 11 is covered with a protective layer 110, the second die 12 comprises a plurality of second bonding pads 121, and the second bonding pads 121 are located on an active surface 12a of the second die 12; conductive post 13 includes opposing first and second ends 13a, 13 b; the active surface 12a of the second die 12 and the second ends 13b of the conductive pillars 13 face the carrier 2, and the conductive pillars 13 are located at the sides of the first die 11 and the second die 12. Fig. 3 is a top view of a carrier and a plurality of groups of packages to be packaged; fig. 4 is a sectional view taken along the AA line in fig. 3.
In this embodiment, the first DIE 11 may be a POWER DIE (POWER DIE), a MEMORY DIE (MEMORY DIE), a sensing DIE (SENSOR DIE), or a RADIO frequency DIE (RADIO frequency DIE). The second die 12 may be a control chip for controlling the first die 11. In other embodiments, the first die 11 and the second die 12 may be dies requiring electrical interconnection, having other functions. The invention does not limit the function of the first die 11 and the second die 12.
Referring to fig. 3, in the present embodiment, the area of the second die 12 is larger than that of the first die 11, so as to reduce the area of the multi-chip 3D package structure 1. In some embodiments, the area of the first die 11 may also be larger than the area of the second die 12.
The first die 11 includes an active surface 11a and a back surface 11b opposite to each other. The first die 11 may include a variety of devices formed on a semiconductor substrate, and electrical interconnect structures electrically connected to the various devices. The first pads 111 provided on the active surface 11a of the first die 11 are connected to an electrical interconnect structure for inputting/outputting electrical signals of the respective devices. The protective layer 110 covers the first pad 111 to protect the first pad 111 when thinning the molding layer.
The second die 12 includes opposing active and backside surfaces 12a and 12 b. The second pad 121 is disposed on the active surface 12 a. Also included within the second die 12 may be a variety of devices formed on a semiconductor substrate, as well as electrical interconnect structures electrically connecting the various devices. The second pads 121 disposed on the active surface 12a of the second die 12 are connected to electrical interconnect structures for inputting/outputting electrical signals of the respective devices.
The first die 11 and the second die 12 are both formed as a singulated wafer. Taking the first die 11 as an example, the wafer includes a wafer active surface and a wafer back surface, the wafer active surface is provided with the first bonding pad 111 and an insulating layer (not shown) protecting the first bonding pad 111. After the wafer dicing, the first die 11 is formed, and accordingly, the first die 11 includes an active surface 11a and a back surface 11b, and the die active surface 11a is provided with a first bonding pad 111 and an insulating layer electrically insulating the adjacent first bonding pad 111.
Applying the protective layer 110 on the active surface 11a of the first die 11, the applying process of the protective layer 110 may be: before the wafer is cut into the first dies 11, the protective layer 110 is applied on the active surface of the wafer, and the wafer with the protective layer 110 is cut to form the first dies 11 with the protective layer 110, which may also be: after the wafer is diced into the first dies 11, a protective layer 110 is applied on the active side 11a of the first dies 11.
Compared with the method that after a plurality of groups of packages 10 are subjected to plastic package, a dielectric layer is applied on the plastic package layer, and a protective layer 110 is applied on the first bare chip 11 before the plastic package, the dielectric layer can be prevented from being manufactured in a large area, so that material waste is avoided on one hand, and warping of a plastic package body can be avoided on the other hand.
The protective layer 110 is an insulating material, and may be specifically an insulating resin material, or may be an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, abf (ajinomoto build file), pbo (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other organic materials having similar insulating properties.
The insulating resin material may be a) laminated on the first pad 111 and the insulating layer between the adjacent first pads 111 through a lamination process, or b) coated or printed on the first pad 111 and the insulating layer between the adjacent first pads 111 first and then cured, or c) cured on the first pad 111 and the insulating layer between the adjacent first pads 111 through an injection molding process.
When the material of the protective layer 110 is an inorganic material such as silicon dioxide or silicon nitride, the protective layer may be formed on the first pads 111 and the insulating layer between adjacent first pads 111 through a deposition process.
The protective layer 110 may include one or more layers.
The wafer may be thinned from the back side prior to dicing to reduce the thickness of the first die 11 and/or the second die 12.
The carrier plate 2 is a rigid plate and may comprise a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.
When a plurality of to-be-packaged components 10 are disposed on the surface of the carrier 2, a plurality of first dies 11 may be disposed on the carrier 2 first. An adhesive layer may be disposed between the active surface 11a of the first die 11 and the carrier 2 to fix the two. Specifically, a full-surface bonding layer may be coated on the surface of the carrier 2, and the plurality of first dies 11 are disposed on the bonding layer.
A plurality of second dies 12 may be arranged on another carrier plate. An adhesive layer may also be disposed between the active surface 12a of the second die 12 and the carrier, so as to fix the two.
The back side 11b of the first die 11 and/or the back side 12b of the second die 12 may be provided with an adhesive layer.
Then, the two carrier boards are combined to bond the back surface 11b of the first bare chip 11 and the back surface 12b of the second bare chip 12 together. The carrier plate carrying the plurality of second dies 12 is then removed.
The adhesive layer between the first die 11 and the carrier 2 and the adhesive layer between the second die 12 and the carrier may be made of a material that is easily peelable to peel off the corresponding carrier, for example, a thermal release material that can be made to lose its adhesiveness by heating or a UV release material that can be made to lose its adhesiveness by ultraviolet irradiation.
Then, the second ends 13b of the conductive posts 13 are disposed on the adhesive layer on the surface of the carrier 2 according to a predetermined arrangement, so as to fix the conductive posts.
The height of the conductive pillar 13 is greater than the sum of the thicknesses of the first die 11 and the second die 12 arranged back to back.
A group of packages 10 to be packaged is located on an area of the surface of the carrier 2, which facilitates subsequent dicing. The surface of the carrier plate 2 is fixed with a plurality of groups of packages 10 to be packaged, so that a plurality of multi-chip 3D packaging structures 1 can be manufactured simultaneously, and batch production and cost reduction are facilitated. In some embodiments, a group of packages 10 to be packaged may also be fixed on the surface of the carrier 2.
Next, referring to step S2 in fig. 2 and fig. 5, a molding layer 14 embedding each group of to-be-packaged components 10 is formed on the surface of the carrier 2; referring to fig. 6, the molding compound layer 14 is thinned until the protection layer 110 on the active surface 11a of each first die and the first end 13a of each conductive pillar 13 are exposed.
The material of the molding layer 14 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the molding layer 14 may also be various polymers or a composite of resin and polymer. Correspondingly, the packaging may be performed by filling a liquid molding compound between the first bare chip 11 and the second bare chip 12 arranged back to back and each conductive pillar 13, and then curing the liquid molding compound at a high temperature by using a molding die. In some embodiments, the molding layer 14 may also be formed by plastic material molding such as hot press molding and transfer molding.
The molding layer 14 may include a front surface 14a and a back surface 14b opposite to each other.
Referring to fig. 6, the plastic sealing layer 14 is thinned from the front surface 14a by mechanical grinding, for example, grinding with a grinding wheel.
Specifically, when the molding compound layer 14 is thinned, the conductive posts 13 have been removed by a certain height when the passivation layer 110 disposed on the active surface 11a of each first die 11 is exposed, so as to ensure that the first ends 13a of the conductive posts 13 are exposed on the front surface 14a of the molding compound layer 14.
The protective layer 110 can prevent the first bonding pads 111, the electrical interconnection structures in the first die 11 and the second die 12, and the devices from being damaged during the process of forming the molding compound layer 14 and grinding the molding compound layer 14.
This step forms a molded body of the package to be packaged 10.
Next, referring to step S3 in fig. 2 and fig. 7, an opening 110a is formed in the protection layer 110 to expose the first pad 111; forming a first redistribution layer 15 on the protection layer 110, the first pads 111, the first ends 13a of the conductive pillars 13, and the front surface 14a of the molding layer 14, wherein the first redistribution layer 15 is used for performing circuit layout on the first pads 111 of the first dies 11 in the group, and the first redistribution layer 15 is led to the back surface 14b of the molding layer 14 through the conductive pillars 13 in the group; a first dielectric layer 16 embedding the first rewiring layer 15 is formed.
In this embodiment, the first rewiring layer 15 includes one layer. Forming the first rewiring layer 15 includes the following steps S31 to S38.
Step S31: a photoresist layer is formed on the protective layer 110 of each first die 11, the first end 13a of each conductive pillar 13, and the front surface 14a of the molding layer 14.
In this step S31, in an alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film may be peeled off from the adhesive tape and applied on the protective layer 110 of each first die 11, the first end 13a of each conductive pillar 13, and the front surface 14a of the molding layer 14. In other alternatives, the photoresist layer may be formed by first applying a liquid photoresist and then curing the liquid photoresist by heating.
Step S32: and exposing and developing the photoresist layer to form a patterned photoresist layer.
This step S32 patterns the photoresist layer. In other alternatives, other sacrificial materials that are easily removable may be used in place of the photoresist layer.
Step S33: with the patterned photoresist layer as a mask, the protective layer 110 is dry etched or wet etched to form a plurality of openings 110a to expose a portion of each first pad 111. One opening 110a may expose a partial region of one first pad 111. In other embodiments, one opening 110a may also expose partial areas of two or more first pads 111.
Step S34: and ashing to remove the residual photoresist layer.
Step S35: a photoresist layer is formed on the protective layer 110 of each first die 11, the first pad 111 exposed by the protective layer 110, the first end 13a of each conductive pillar 13, and the front surface 14a of the molding layer 14.
The method of forming the photoresist layer may refer to the method of forming the photoresist layer in step S31.
Step S36: the photoresist layer is exposed and developed, leaving the photoresist layer in a first predetermined area complementary to the area where the metal block 15a of the first rewiring layer 15 is to be formed.
Step S37: the complementary region of the first predetermined region is filled with a metal layer to form a metal block 15a of the first rewiring layer 15.
A part of the number of metal blocks 15a is positioned so as to be able to electrically connect several first pads 111 of the first die 11. A part of the number of metal blocks 15a is positioned so as to be electrically connected to the first ends 13a of the conductive pillars 13, so as to enable electrical signals of the first die 11 to be led to the back surface 14b of the molding layer 14.
The step S37 can be performed by an electroplating process. The process of electroplating copper or aluminum is mature.
Specifically, before forming the photoresist Layer in step S35, a Seed Layer (Seed Layer) may be formed on the passivation Layer 110 of each first die 11, the first pad 111 exposed by the passivation Layer 110, the first end 13a of each conductive pillar 13, and the front surface 14a of the molding Layer 14 by using a physical vapor deposition method or a chemical vapor deposition method. The seed layer may serve as a power supply layer for electroplating copper or aluminum.
The electroplating may comprise electrolytic plating or electroless plating. In the electrolytic plating, a member to be plated is used as a cathode, and an electrolytic solution is electrolyzed to form a layer of metal on the member to be plated. Electroless plating is a method of forming a metal layer by reducing and precipitating metal ions in a solution on an article to be plated. In some embodiments, the metal block 15a may also be formed by sputtering and etching.
Step S38: and ashing to remove the residual photoresist layer in the first preset area.
And after ashing, removing the seed crystal layer in the first preset area by dry etching or wet etching.
The metal blocks 15a of the first rewiring layer 15 may be planarized on the upper surface thereof by a polishing process, such as chemical mechanical polishing.
In step S3, the metal blocks 15a of the first redistribution layer 15 are arranged according to design requirements, and the distribution of the first redistribution layer 15 on each first die 11 in different groups of packages 10 may be the same or different.
In addition, in some embodiments, the first redistribution layer 15 may further include two or more layers, i.e., two or more layers of metal blocks 15 a.
In the step of forming the first dielectric layer 16, in order to prevent the molding layer 14 from being scratched by the process, the first dielectric layer 16 may be formed on the front surface 14a of the molding layer 14.
The first dielectric layer 16 is an insulating material, and may be specifically an insulating resin material or an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, abf (ajinomoto build file), pbo (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other organic materials having similar insulating properties.
The insulating resin material may be a) laminated on the first rewiring layer 15 and the front surface 14a of the molding layer 14 through a lamination process, or b) coated on the first rewiring layer 15 and the front surface 14a of the molding layer 14 first and then cured, or c) cured on the first rewiring layer 15 and the front surface 14a of the molding layer 14 through an injection molding process.
When the material of the first dielectric layer 16 is an inorganic material such as silicon dioxide or silicon nitride, the first dielectric layer may be formed on the first redistribution layer 15 and the front surface 14a of the molding layer 14 by a deposition process.
Compared with inorganic materials, the insulating resin material has smaller tensile stress, and can prevent the plastic package body from warping when the first dielectric layer 16 is formed in a large area.
The first dielectric layer 16 may include one or more layers.
Thereafter, referring to step S4 in fig. 2 and fig. 8, the carrier board 2 is removed, and the active surface 12a of each second die 12, the second ends 13b of each conductive pillar 13 and the back surface 14b of the molding layer 14 are exposed; a second redistribution layer 17 is formed on the active surface 12a of each second die 12, the second end 13b of each conductive pillar 13, and the back surface 14b of the molding layer 14, the second redistribution layer 17 is used for circuit layout of each second pad 121 of the second die 12 in the group, and the second redistribution layer 17 is electrically connected to the first redistribution layer 15 through the conductive pillar 13 in the group.
Referring to fig. 8, after removing the carrier plate 2, a support plate 3 may be disposed on the first dielectric layer 16.
The removal method of the carrier 2 may be laser lift-off, UV irradiation, or other conventional removal methods.
The supporting board 3 may serve as a support in the subsequent processes of forming the second re-wiring layer 17, and/or forming the leads 18, and/or forming the second dielectric layer 19.
The support plate 3 is a hard plate member and may include a glass plate, a ceramic plate, a metal plate, and the like.
The formation method of the metal block 17a in the second rewiring layer 17 may refer to the formation method of the metal block 15a in the first rewiring layer 15. The layout of the second re-wiring layer 17 may be determined according to a predetermined layout. The second rewiring layer 17 may include one layer, two layers, or more than two layers.
Next, referring to step S5 in fig. 2 and fig. 8, the leads 18 are formed on the second redistribution layer 17 and the second dielectric layer 19 at least embedding the second redistribution layer 17 is formed, and the leads 18 are exposed outside the second dielectric layer 19.
The present step S5 may include steps S51-S55.
Step S51: a photoresist layer is formed on the metal block 17a, the insulating layer, and the back surface 14b of the molding layer 14.
In this step S51, in an alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film can be peeled off from the tape and applied to the metal block 17a, the insulating layer, and the back surface 14b of the molding layer 14. In other alternatives, the photoresist layer may be formed by first applying a liquid photoresist and then curing the liquid photoresist by heating.
Step S52: and exposing and developing the photoresist layer to retain the photoresist in the second predetermined area. The second predetermined region is complementary to the region where the conductive stud 181 is to be formed.
This step S52 patterns the photoresist layer. In other alternatives, other sacrificial materials that are easily removable may be used in place of the photoresist layer.
Step S53: the complementary region of the second predetermined region is filled with a metal layer to form the conductive stud 181.
The step S53 can be performed by an electroplating process. The process of electroplating copper or aluminum is mature. Before electroplating copper or aluminum, a Seed Layer (Seed Layer) can be physically or chemically vapor deposited as a power supply Layer.
Step S54: and ashing to remove the residual photoresist layer in the second preset area.
The conductive posts 181 may have a flat upper surface by a polishing process, such as chemical mechanical polishing.
Step S55: referring to fig. 8, a second dielectric layer 19 is formed on the conductive stud 181, the metal block 17a, the insulating layer, and the back surface 14b of the molding layer 14; the second dielectric layer 19 is thinned until the conductive stud 181 is exposed.
In some embodiments, the second dielectric layer 19 embedding the second rewiring layer 17 may be formed first; thinning the second dielectric layer 19 until the uppermost metal block 17a of the second rewiring layer 17 is exposed; conductive studs 181 are then formed on the metal block 17 a.
The material and formation method of the second dielectric layer 19 can be referred to those of the first dielectric layer 16.
In the step of forming the second dielectric layer 19, in order to prevent the molding layer 14 from being scratched by the process, the second dielectric layer 19 may also be formed on the back surface 14b of the molding layer 14 between adjacent groups of packages 10 to be packaged.
The second dielectric layer 19 may comprise one or more layers.
After the conductive stud 181 is manufactured, in an alternative of a), as shown in fig. 8, the conductive stud 181 serves as the pin 18.
b) In an alternative embodiment, after the conductive pillar 181 is exposed, an anti-oxidation layer is further formed on the conductive pillar 181.
The oxidation resistant layer may include: b1) tin layer, or b2) nickel layer and gold layer stacked from bottom to top, or b3) nickel layer, palladium layer and gold layer stacked from bottom to top. The oxidation resistant layer may be formed using an electroplating process. The conductive pillar 181 may be made of copper, and the anti-oxidation layer may prevent oxidation of copper, thereby preventing deterioration of electrical connection performance due to oxidation of copper.
c) In an alternative, after the conductive stud 181 is exposed, a solder ball is further formed on the conductive stud 181 for flip-chip mounting of the multi-chip 3D package structure 1 (see fig. 1).
After forming the leads 18, the support plate 3 is removed as shown in fig. 9.
The support plate 3 may be removed by conventional methods such as laser lift-off and UV irradiation.
Thereafter, referring to step S6 in fig. 2, fig. 9 and fig. 1, a plurality of multi-chip 3D package structures 1 are formed by cutting, where each multi-chip 3D package structure 1 includes a group of packages 10 to be packaged.
Through the above steps, the first die 11 and the second die 12 in the group of packages 10 to be packaged can be connected through the pins 18 to realize external circuit connection, so that the performance of the multi-chip 3D package structure 1 is reliable. In addition, the conductive pillars 13, the first redistribution layer 15, and the second redistribution layer 17 are freely and flexibly laid out, and are not limited by the substrate size.
Fig. 10 is a schematic cross-sectional view of a multi-chip 3D package structure according to a second embodiment of the invention. Referring to fig. 10, the multi-chip 3D package structure 2 in the present embodiment includes:
a first die 11 and a second die 12, the first die 11 including a plurality of first bonding pads 111, the first bonding pads 111 being located on an active surface 11a of the first die 11, the second die 12 including a plurality of second bonding pads 121, the second bonding pads 121 being located on an active surface 12a of the second die 12; the first die 11 and the second die 12 are arranged back to back;
a protective layer 110 covering the active surface 11a of the first die 11, the protective layer 110 exposing the first pad 111;
a molding compound layer 14 for covering the first die 11 and the second die 12, wherein a front surface 14a of the molding compound layer 14 exposes the protective layer 110 and the first bonding pad 111, a back surface 14b of the molding compound layer 14 exposes an active surface 12a of the second die 12, a conductive plug 20 is arranged in the molding compound layer 14, and the conductive plug 20 is located at a side edge of the first die 11 and the second die 12;
a first rewiring layer 15, located on the protective layer 110, the first pads 111, one end of the conductive plugs 20 and the front surface 14a of the plastic package layer 14, for performing circuit layout on each first pad 111, wherein the first rewiring layer 15 is led to the back surface 14b of the plastic package layer 14 through the conductive plugs 20;
a first dielectric layer 16 embedding the first redistribution layer 15;
a second redistribution layer 17 located on the active surface 12a of the second die 12, the other end of the conductive plug 20, and the back surface 14b of the molding layer 14, for performing circuit layout on each second pad 121, the second redistribution layer 17 being electrically connected to the first redistribution layer 15 through the conductive plug 20;
a pin 18 connected to the second rewiring layer 17;
a second dielectric layer 19 at least embedding the second redistribution layer 17, and the leads 18 exposed outside the second dielectric layer 19.
It can be seen that the multi-chip 3D package structure 2 in the second embodiment is substantially the same as the multi-chip 3D package structure 1 in the first embodiment, and the differences are only: conductive plug 20 replaces conductive post 13.
The conductive material in the conductive plug 20 may be copper, aluminum, or other metal with good conductivity. The number of the conductive plugs 20 may be one, two, or more.
An embodiment of the invention provides a method for manufacturing the multi-chip 3D package structure 2 in fig. 10. Fig. 11 is a flow chart of a method of fabrication. Fig. 12 to 18 are intermediate structural diagrams corresponding to the flow in fig. 11.
First, referring to step S1', fig. 12 and fig. 13 in fig. 11, a carrier 2 and a plurality of packages to be packaged 10' carried on the carrier 2 are provided, each package to be packaged 10' includes: the semiconductor device comprises a first die 11 and a second die 12 which are arranged back to back, wherein the first die 11 comprises a plurality of first bonding pads 111, the first bonding pads 111 are positioned on an active surface 11a of the first die 11, the active surface 11a of the first die 11 is covered with a protective layer 110, the second die 12 comprises a plurality of second bonding pads 121, and the second bonding pads 121 are positioned on an active surface 12a of the second die 12; wherein the active surface 12a of the second die 12 faces the carrier 2. Fig. 12 is a top view of a carrier and a plurality of groups of packages to be packaged; fig. 13 is a sectional view taken along the line BB in fig. 12.
It can be seen that step S1' is substantially the same as step S1 in the first embodiment, except that: the to-be-packaged component 10' has fewer conductive pillars 13 than the to-be-packaged component 10.
For the same or similar structures and manufacturing methods in the steps of the manufacturing methods of the second embodiment and the first embodiment, please refer to the corresponding parts of the foregoing embodiments, and the differences are emphasized in this embodiment.
Next, referring to step S2 'and fig. 14 in fig. 11, a molding layer 14 embedding each group of to-be-packaged components 10' is formed on the surface of the carrier 2; referring to fig. 15, the molding layer 14 is thinned until the protective layer 110 on the active surface 11a of each first die is exposed.
The step S2' is substantially the same as the step S2 in the first embodiment.
Next, referring to step S3' in fig. 11 and fig. 16, an opening 110a is formed in the protection layer 110 to expose the first pad 111; forming a first redistribution layer 15 on the protective layer 110, the first pads 111 and the front surface 14a of the molding layer 14, wherein the first redistribution layer 15 is used for performing circuit layout on each first pad 111 of the first die 11 in the group; a first dielectric layer 16 embedding the first rewiring layer 15 is formed.
The step S3' is substantially the same as the step S3 in the first embodiment.
Thereafter, referring to step S4' in fig. 11 and fig. 17, the carrier board 2 is removed to expose the active surface 12a of each second die 12 and the back surface 14b of the molding layer 14; forming a conductive plug 20 in the molding layer 14 through the back surface 14b of the molding layer 14 to introduce the first rewiring layer 15 to the back surface 14b of the molding layer 14; a second redistribution layer 17 is formed on the active surface 12a of each second die 12, each conductive plug 20, and the back surface 14b of the molding layer 14, the second redistribution layer 17 is used for circuit layout of each second pad 121 of the second die 12 in the group, and the second redistribution layer 17 is electrically connected to the first redistribution layer 15 through the conductive plug 20 in the group.
Step S4' is substantially the same as step S4 in the first embodiment, except that: the step of forming the conductive plug 20 is added. When the material of the plastic package layer 14 is a laser removable material, a through hole can be formed in the plastic package layer 14 by laser irradiation, and then the through hole is filled with a conductive material. When the material of the molding compound layer 14 is a material that can be dry-etched, a through hole can be formed in the molding compound layer 14 by a dry etching method.
Next, referring to step S5 in fig. 11 and fig. 17, the leads 18 are formed on the second redistribution layer 17 and the second dielectric layer 19 at least embedding the second redistribution layer 17 is formed, and the leads 18 are exposed outside the second dielectric layer 19.
This step S5 is the same as step S5 in the first embodiment.
Thereafter, referring to step S6 'in fig. 11, fig. 18 and fig. 10, a plurality of multi-chip 3D package structures 2 are formed by cutting, and each multi-chip 3D package structure 2 includes a group of packages to be packaged 10'.
This step S6' is substantially the same as step S6 in the first embodiment, except that each multichip 3D package structure 2 includes a conductive plug 20.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (22)

1. A multi-chip 3D packaging structure, comprising:
a first die and a second die, the first die including a number of first bonding pads, the first bonding pads being located on an active side of the first die, the second die including a number of second bonding pads, the second bonding pads being located on an active side of the second die; the first die and the second die are arranged back-to-back;
a protective layer covering an active side of the first die, the protective layer exposing the first pad;
conductive pillars located at sides of the first and second dies, the conductive pillars including opposing first and second ends;
a molding compound layer covering the first die, the second die and the conductive pillars, wherein the front surface of the molding compound layer exposes the protective layer, the first bonding pad and the first ends of the conductive pillars, and the back surface of the molding compound layer exposes the active surface of the second die and the second ends of the conductive pillars;
a first redistribution layer directly contacting one surface of the protection layer exposed by the front surface of the plastic package layer, the first pads, the first ends of the conductive pillars, and the front surface of the plastic package layer, for performing circuit layout on the first pads, wherein the first redistribution layer is led to the back surface of the plastic package layer through the conductive pillars;
a first dielectric layer embedding the first rewiring layer;
a second redistribution layer directly contacting the active surface of the second die, the second end of the conductive pillar, and the back surface of the molding layer, for performing circuit layout on each second pad, wherein the second redistribution layer is electrically connected to the first redistribution layer through the conductive pillar;
a pin connected to the second rewiring layer;
and the second dielectric layer at least embeds the second rewiring layer, and the pins are exposed outside the second dielectric layer.
2. The multi-chip 3D package structure of claim 1, wherein the conductive pillars are distributed on sides of the first die and the second die.
3. The multi-chip 3D package structure of claim 1, wherein the second die is a control die for controlling the first die.
4. The multi-chip 3D package structure of claim 1, wherein an area of the second die is larger than an area of the first die.
5. The multi-chip 3D package structure according to claim 1, wherein the material of the protection layer is an insulating resin material or an inorganic material; and/or the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
6. The multi-chip 3D package structure of claim 1, wherein the first redistribution layer comprises two or more layers; and/or the second rewiring layer includes two or more layers.
7. A manufacturing method of a multi-chip 3D packaging structure is characterized by comprising the following steps:
providing a carrier and at least one group of to-be-packaged pieces loaded on the carrier, wherein each group of to-be-packaged pieces comprises: the semiconductor device comprises a conductive column, a first die and a second die, wherein the first die and the second die are arranged back to back, the first die comprises a plurality of first bonding pads, the first bonding pads are positioned on the active surface of the first die, the active surface of the first die is covered with a protective layer, the second die comprises a plurality of second bonding pads, and the second bonding pads are positioned on the active surface of the second die; the conductive post comprises a first end and a second end which are opposite; wherein the active surface of the second die and the second ends of the conductive pillars face the carrier board, and the conductive pillars are located at the sides of the first die and the second die;
forming a plastic packaging layer for embedding the to-be-packaged part on the surface of the carrier plate; thinning the plastic packaging layer until the protective layer and the first end of the conductive column are exposed;
forming an opening in the protective layer to expose the first pad; directly forming a first redistribution layer on the protection layer, the first pads, the first ends of the conductive pillars, and the front surface of the plastic package layer, wherein the first redistribution layer directly contacts one surface of the protection layer exposed by the plastic package layer, the first pads, the first ends of the conductive pillars, and the front surface of the plastic package layer, and is used for performing circuit layout on the first pads, and the first redistribution layer is led to the back surface of the plastic package layer through the conductive pillars; forming a first dielectric layer embedding the first rewiring layer;
removing the carrier plate to expose the active surface of the second bare chip, the second ends of the conductive posts and the back surface of the plastic packaging layer; a second redistribution layer is directly formed on the active surface of the second die, the second end of the conductive pillar and the back surface of the plastic package layer, the second redistribution layer directly contacts the active surface of the second die, the second end of the conductive pillar and the back surface of the plastic package layer, and is used for performing circuit layout on each second pad, and the second redistribution layer is electrically connected with the first redistribution layer through the conductive pillar;
and forming a pin on the second rewiring layer and a second dielectric layer at least embedding the second rewiring layer, wherein the pin is exposed outside the second dielectric layer.
8. The method as claimed in claim 7, wherein a group of packages to be packaged includes a plurality of the conductive pillars distributed on a plurality of sides of the first die and the second die.
9. The method for manufacturing a multi-chip 3D package structure according to claim 7, wherein the packages to be packaged carried by the carrier are multiple groups, the first redistribution layer is used for performing circuit layout on each first pad of the first die in a group, and the first redistribution layer is led to the back surface of the molding layer through the conductive pillars in the group; the second redistribution layer is used for performing circuit layout on each second bonding pad of the second die in the group, and the second redistribution layer is electrically connected with the first redistribution layer through the conductive pillars in the group; and after the pins and the second dielectric layer are formed, cutting to form a plurality of multi-chip 3D packaging structures, wherein each multi-chip 3D packaging structure comprises a group of to-be-packaged parts.
10. The method for manufacturing the multi-chip 3D packaging structure according to claim 7, wherein the material of the protection layer is an insulating resin material or an inorganic material; and/or the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
11. The method of claim 7, wherein the first redistribution layer comprises two or more layers; and/or the second rewiring layer includes two or more layers.
12. A multi-chip 3D packaging structure, comprising:
a first die and a second die, the first die including a number of first bonding pads, the first bonding pads being located on an active side of the first die, the second die including a number of second bonding pads, the second bonding pads being located on an active side of the second die; the first die and the second die are arranged back-to-back;
a protective layer covering an active side of the first die, the protective layer exposing the first pad;
the plastic package layer covers the first bare chip and the second bare chip, the front surface of the plastic package layer exposes the protective layer and the first bonding pad, the back surface of the plastic package layer exposes the active surface of the second bare chip, and a conductive plug is arranged in the plastic package layer and is positioned at the side edges of the first bare chip and the second bare chip;
the first rewiring layer is directly contacted with one surface of the protective layer exposed by the front surface of the plastic packaging layer, the first bonding pad, one end of the conductive plug and the front surface of the plastic packaging layer and used for carrying out circuit layout on each first bonding pad, and the first rewiring layer is led to the back surface of the plastic packaging layer through the conductive plug;
a first dielectric layer embedding the first rewiring layer;
a second redistribution layer directly contacting an active surface of the second die, another end of the conductive plug, and a back surface of the molding layer, for performing circuit layout on each of the second pads, the second redistribution layer being electrically connected to the first redistribution layer through the conductive plug;
a pin connected to the second rewiring layer;
and the second dielectric layer at least embeds the second rewiring layer, and the pins are exposed outside the second dielectric layer.
13. The multi-chip 3D package structure of claim 12, wherein the conductive plugs are distributed on a plurality of sides of the first die and the second die.
14. The multi-chip 3D package structure of claim 12, wherein the second die is a control die for controlling the first die.
15. The multi-chip 3D package structure of claim 12, wherein an area of the second die is larger than an area of the first die.
16. The multi-chip 3D package structure of claim 12, wherein the material of the protection layer is an insulating resin material or an inorganic material; and/or the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
17. The multi-chip 3D package structure of claim 12, wherein the first redistribution layer comprises two or more layers; and/or the second rewiring layer includes two or more layers.
18. A manufacturing method of a multi-chip 3D packaging structure is characterized by comprising the following steps:
providing a carrier and at least one group of to-be-packaged pieces loaded on the carrier, wherein each group of to-be-packaged pieces comprises: the semiconductor device comprises a first die and a second die which are arranged back to back, wherein the first die comprises a plurality of first bonding pads, the first bonding pads are positioned on the active surface of the first die, the active surface of the first die is covered with a protective layer, the second die comprises a plurality of second bonding pads, and the second bonding pads are positioned on the active surface of the second die; wherein an active side of the second die faces the carrier plate;
forming a plastic packaging layer for embedding the to-be-packaged part on the surface of the carrier plate; thinning the plastic packaging layer until the protective layer is exposed;
forming an opening in the protective layer to expose the first pad; directly forming a first rewiring layer on the protective layer, the first pads and the front surface of the plastic packaging layer, wherein the first rewiring layer is directly contacted with one surface of the protective layer exposed by the front surface of the plastic packaging layer, one end of each first pad, one end of each conductive plug and the front surface of the plastic packaging layer, and is used for carrying out circuit layout on each first pad; forming a first dielectric layer embedding the first rewiring layer;
removing the carrier plate, and exposing the active surface of the second bare chip and the back surface of the plastic packaging layer; forming a conductive plug in the plastic packaging layer through the back surface of the plastic packaging layer so as to lead the first rewiring layer to the back surface of the plastic packaging layer; a second redistribution layer is directly formed on the active surface of the second bare chip, the conductive plug and the back surface of the plastic packaging layer, the second redistribution layer is directly contacted with the active surface of the second bare chip, the other end of the conductive plug and the back surface of the plastic packaging layer and is used for carrying out circuit layout on each second bonding pad, and the second redistribution layer is electrically connected with the first redistribution layer through the conductive plug;
and forming a pin on the second rewiring layer and a second dielectric layer at least embedding the second rewiring layer, wherein the pin is exposed outside the second dielectric layer.
19. The method of claim 18, wherein a group of packages to be packaged are formed with a plurality of the conductive plugs, and the plurality of conductive plugs are distributed on a plurality of sides of the first die and the second die.
20. The method for manufacturing a multi-chip 3D package structure according to claim 18, wherein the packages to be packaged carried by the carrier are multiple groups, the first redistribution layer is used for performing circuit layout on each first pad of the first die in a group, and the first redistribution layer is led to the back surface of the molding layer through the conductive plug in the group; the second redistribution layer is used for performing circuit layout on each second bonding pad of the second bare chip in the group, and the second redistribution layer is electrically connected with the first redistribution layer through the conductive plug in the group; and after the pins and the second dielectric layer are formed, cutting to form a plurality of multi-chip 3D packaging structures, wherein each multi-chip 3D packaging structure comprises a group of to-be-packaged parts.
21. The method for manufacturing the multi-chip 3D package structure according to claim 18, wherein the material of the protection layer is an insulating resin material or an inorganic material; and/or the material of the first dielectric layer is an insulating resin material or an inorganic material; and/or the material of the second dielectric layer is an insulating resin material or an inorganic material.
22. The method of claim 18, wherein the first redistribution layer comprises two or more layers; and/or the second rewiring layer includes two or more layers.
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