CN113725182B - Chip packaging structure - Google Patents

Chip packaging structure Download PDF

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Publication number
CN113725182B
CN113725182B CN202010231967.6A CN202010231967A CN113725182B CN 113725182 B CN113725182 B CN 113725182B CN 202010231967 A CN202010231967 A CN 202010231967A CN 113725182 B CN113725182 B CN 113725182B
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conductive
layer
die
conductive part
package structure
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CN202010231967.6A
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CN113725182A (en
Inventor
周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

The invention provides a chip packaging structure, an electric connector is arranged on a bare chip, the electric connector comprises a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part, the first conductive part is electrically connected to the back surface of the bare chip, and the second conductive part and the active surface of the bare chip are basically in the same plane; the bare chip and the electric connecting piece are encapsulated by a first plastic encapsulation layer, and the second conductive part of the electric connecting piece and the active surface of the bare chip are exposed outside the first plastic encapsulation layer; the active surface of the bare chip, the second conductive part of the electric connector and the first plastic sealing layer are provided with a circuit layer, the circuit layer comprises a rewiring layer, and the rewiring layer is at least electrically connected with the second conductive part and the back grounding inner bonding pad. The back surface grounding at the specific electric connection point position of the active surface of the bare chip is realized by using the electric connector.

Description

Chip packaging structure
Technical Field
The present disclosure relates to chip packaging technology, and particularly to a chip packaging structure.
Background
In recent years, with the continuous development of circuit integration technology, electronic products are increasingly miniaturized, intelligent, high-performance and high-reliability. The packaging technology not only affects the performance of the product, but also restricts the miniaturization of the product. In a power chip (power module), it is necessary to back ground specific electrical connection point locations of the active surface of the die.
In view of the above, the present invention provides a new chip packaging structure for packaging a power chip.
Disclosure of Invention
The invention aims to provide a chip packaging structure for packaging a power chip.
In order to achieve the above object, the present invention provides a chip package structure, comprising:
a die including opposing active and back surfaces, the active surface having an inner pad and a protective layer, the protective layer exposing a partial region of the inner pad, the inner pad including at least one back-grounded inner pad;
the electric connector comprises a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part; the first conductive portion is electrically connected to the back surface of the die;
a first plastic package layer coating the bare chip and the electric connector, wherein the second conductive part of the electric connector and the active surface of the bare chip are exposed outside the first plastic package layer;
the circuit layer is positioned on the active surface of the bare chip, the second conductive part of the electric connector and the first plastic sealing layer, and comprises a rewiring layer which is at least electrically connected with the second conductive part and the back grounding inner bonding pad.
Optionally, the second conductive portion of the electrical connector is in the same plane as the active face of the die.
Optionally, the electrical connector is H-shaped.
Optionally, a conductive layer is disposed on the back surface of the die, and/or a conductive adhesive is disposed between the first conductive portion and the back surface of the die.
Optionally, the conductive paste comprises a nano copper/conductive polymer composite.
Optionally, in the nano copper/conductive polymer composite, the conductive polymer is: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide, and/or the particle size of the nano copper is less than 800nm.
Optionally, the particle size of the nano copper ranges from 200nm to 500nm.
Optionally, the circuit layer includes an outer pin; and the rewiring layer is provided with a conductive convex column, and the conductive convex column is the outer pin.
Optionally, the conductive protruding column is provided with an oxidation resistant layer.
Optionally, the circuit layer includes an outer pin; the rewiring layer is provided with a conductive convex column, the conductive convex column is provided with a solder ball, and the solder ball is the outer pin.
Optionally, the rewiring layer comprises at least two layers.
Optionally, a first plastic layer is between the connection portion of the electrical connector and the die.
Optionally, the angles between the first conductive part and the second conductive part of the electric connector and the connecting part are right angles.
Optionally, the material of the protective layer is at least one of insulating resin material, silicon dioxide and silicon nitride. The protection layer can play an insulating role, and in the process of forming the first plastic sealing layer and grinding the first plastic sealing layer, the hardness can be enough to protect the inner bonding pad and the electric interconnection structure in the bare chip from damage, and the invention is not limited to the specific material of the protection layer.
Compared with the prior art, the invention has the beneficial effects that:
arranging an electric connector on the bare chip, wherein the electric connector comprises a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part, the first conductive part is electrically connected to the back surface of the bare chip, and the second conductive part and the active surface of the bare chip are basically in the same plane; the bare chip and the electric connecting piece are encapsulated by a first plastic encapsulation layer, and the second conductive part of the electric connecting piece and the active surface of the bare chip are exposed outside the first plastic encapsulation layer; the active surface of the bare chip, the second conductive part of the electric connector and the first plastic sealing layer are provided with a circuit layer, the circuit layer comprises a rewiring layer, and the rewiring layer is at least electrically connected with the second conductive part and the back grounding inner bonding pad. The back surface grounding at the specific electric connection point position of the active surface of the bare chip is realized by using the electric connector.
Drawings
Fig. 1 is a schematic cross-sectional view of a chip package structure according to a first embodiment of the present invention.
FIG. 2 is a top view of an electrical connector;
FIG. 3 is a flow chart of a method of fabricating the chip package structure of FIG. 1;
fig. 4 to 14 are schematic views of intermediate structures corresponding to the flow in fig. 3;
fig. 15 is a top view of an electrical connector in a chip package structure according to a second embodiment of the invention.
To facilitate an understanding of the present invention, all reference numerals appearing in the present invention are listed below:
die 11 electrical connector 12
Die active side 11a die back side 11b
Inner pad 110 protective layer 111
First conductive portion 12a of first molding layer 10
Second conductive portion 12b connecting portion 12c
Outer pin 13a of circuit layer 13
Second molding layer 133 of metal block 131a
Oxidation-resistant layer 134 of conductive stud 132
Chip packaging structure 1a carrier plate 2
First opening 111a first support plate 3
The second support plate 4 has a first dielectric layer 131b
Second dielectric layer 132b encapsulates intermediate structure 1
Rewiring layer 131 backside ground inner pad 110a
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 is a schematic cross-sectional view of a chip package structure according to a first embodiment of the present invention.
Referring to fig. 1, a chip package structure 1a includes:
a die 11, the die 11 including an active surface 11a and a back surface 11b opposite to each other, the active surface 11a having an inner pad 110 and a protective layer 111, the protective layer 111 exposing a portion of the inner pad 110, the inner pad 110 including at least one back-grounded inner pad 110a;
an electrical connector 12, the electrical connector 12 includes a first conductive portion 12a, a second conductive portion 12b, and a connecting portion 12c connecting the first conductive portion 12a and the second conductive portion 12 b; the first conductive portion 12a is electrically connected to the back surface 11b of the die 11;
a first molding layer 10 for coating the bare chip 11 and the electric connection piece 12, and a second conductive part 12b of the electric connection piece 12 and an active surface 11a of the bare chip 11 are exposed outside the first molding layer 10;
the circuit layer 13, the circuit layer 13 is located on the active surface 11a of the die 11, the second conductive portion 12b of the electrical connector 12 and the first molding layer 10, the circuit layer 13 includes a rewiring layer 131, and the rewiring layer 131 is electrically connected with at least the second conductive portion 12b and the back grounding inner pad 110a.
The die 11 may include a variety of devices formed on a semiconductor substrate and electrical interconnect structures electrically connected to the respective devices. The inner pads 110 of the die active surface 11a are connected to electrical interconnect structures for inputting/outputting electrical signals of the respective devices. The back ground inner pad 110a is for electrical connection with the back surface 11b of the die 11. Die 11 may be a power chip.
The protective layer 111 is made of an insulating material, and may be at least one of an insulating resin material, silicon dioxide, and silicon nitride. Examples of the insulating resin material include polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like.
Fig. 2 is a top view of an electrical connector. Referring to fig. 2, the electrical connector 12 is rectangular in plan view.
Referring to fig. 1, the electrical connector 12 has a semi-convex vertical cross section for receiving the die 11. The material of the electrical connector 12 may be a metal with good electrical conductivity and a certain hardness, such as copper.
In the embodiment shown in fig. 1, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are right angles. In some embodiments, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c may be obtuse angles.
In some embodiments, a conductive paste may be disposed between the first conductive portion 12a and the back surface 11b of the die 11 to electrically connect the two. The conductive paste may include a nano copper/conductive polymer composite.
In the nano-copper/conductive polymer composite, the conductive polymer may be: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide. The conductive polymer is formed by changing an insulator into a conductor through chemical or electrochemical doping by a macromolecule with conjugated pi-bond, has good conductive property, and the conductivity is further enhanced after nano copper is added.
Copper is one of the most excellent metal materials, and when the copper scale is reduced to the nanometer level, the copper material has high specific surface area, high surface activity and more excellent electric and heat conduction characteristics. Preferably, the nano copper is spherical, and the particle size is less than 800nm; further preferably, the particle diameter of the nano copper is in the range of 200nm to 500nm. This is because: the specific surface area of the nano copper material is increased along with the reduction of the particle size of the material, and the electric conduction and heat conduction properties of the material are enhanced; when the particle size is reduced to below 800nm, the material has excellent electric and heat conduction characteristics; however, when the particle size is reduced to below 200nm, the manufacturing cost of the nano material is increased remarkably, the packaging economic benefit is affected, and when the particle size of the nano copper is reduced to below 200nm, the surface energy of the nano copper particles is increased, larger particles are easily formed by agglomeration among the particles, and the electric conductivity and the heat conductivity of the composite material are damaged.
Preferably, the nano-copper is added in an amount of more than 5wt% in the nano-copper/conductive polymer composite.
In some embodiments, the first conductive portion 12a may be in direct contact with the back surface 11b of the die 11 to make electrical connection therebetween.
In some embodiments, the backside 11b of the die 11 may also be provided with a conductive layer. The material of the conductive layer may be copper. A titanium layer may also be provided between the copper layer and the back surface 11b of the die 11 to improve adhesion between the back surface 11b of the die and the copper layer.
In the embodiment shown in fig. 1, there is no gap between the connection portion 12c of the electrical connector 12 and the die 11, and in other embodiments, there may also be a gap between the two, so that the first plastic sealing layer 10 enters, thereby improving the connection firmness between the electrical connector 12 and the die 11.
The material of the first plastic layer 10 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like.
The rewiring layer 131 is a fan-out line (fan-out). In the embodiment shown in fig. 1, the rewiring layer 131 includes a metal block 131a and a second molding layer 133 between adjacent metal blocks 131a, with one layer. In other embodiments, the rewiring layer 131 may include at least two layers. Of the plurality of metal blocks 131a, a part of the plurality of metal blocks 131a is electrically connected to one or more inner pads 110 for performing other functions, in addition to the part of the plurality of metal blocks 131a electrically connecting the second conductive portion 12b with the back-grounded inner pad 110a.
In the embodiment shown in fig. 1, the conductive stud 132 is the outer lead 13a. The conductive stud 132 may be made of a metal such as copper, and may have an oxidation resistant layer 134 thereon. In other embodiments, solder balls may be disposed on the conductive studs 132, and the solder balls are the outer pins 13a.
Referring to fig. 1, the chip package structure 1a implements the rear surface 11b grounding at a specific electrical connection point position (rear ground inner pad 110 a) of the die active surface 11a by using the electrical connector 12.
An embodiment of the present invention provides a method for manufacturing the chip package structure 1a in fig. 1. Fig. 3 is a flow chart of a method of fabrication. Fig. 4 to 14 are schematic views of intermediate structures corresponding to the flow in fig. 3.
First, referring to step S1 in fig. 3, and fig. 4 and 5, a carrier 2 and a plurality of dies 11 are provided, each die 11 includes an active surface 11a and a back surface 11b, the active surface 11a has an inner pad 110 and a protective layer 111 covering the inner pad 110, and the inner pad 110 includes at least one back-grounded inner pad 110a; the active surface 11a of each die 11 is fixed to the carrier plate 2. Wherein fig. 4 is a top view of a carrier plate and a plurality of dies; fig. 5 is a cross-sectional view taken along line AA in fig. 4.
The die 11 is formed for a singulated wafer including a wafer active side having inner pads 110 and an insulating layer (not shown) protecting the inner pads 110, and a wafer back side. The die 11 is formed after dicing, and accordingly, the die 11 includes a die active surface 11a and a die backside surface 11b, the die active surface 11a having an inner pad 110 and an insulating layer protecting the inner pad 110. The protective layer 111 is applied on the active surface 11a of the die, and the protective layer 111 may be applied by: the protective layer 111 is applied on the wafer active surface before dicing the wafer into the die 11, and dicing the wafer with the protective layer 111 into the die 11 with the protective layer 111 may be: after the wafer is diced into dies 11, a protective layer 111 is applied over the dies 11.
The die 11 may include a variety of devices formed on a semiconductor substrate and electrical interconnect structures electrically connected to the respective devices. The inner pads 110 of the die active surface 11a are connected to electrical interconnect structures for inputting/outputting electrical signals of the respective devices. The back ground inner pad 110a is for electrical connection with the back surface 11b of the die 11. Die 11 may be a power chip.
The structure and function of each die 11 may be the same or different.
The protective layer 111 is made of an insulating material, and may be at least one of an insulating resin material, silicon dioxide, and silicon nitride.
The insulating resin material, such as polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), etc., may be laminated on the inner pad 110 and the insulating layer between adjacent inner pads 110 by a) lamination process, or b) coated on the inner pad 110 and the insulating layer between adjacent inner pads 110 first, post-cured, or c) cured on the inner pad 110 and the insulating layer between adjacent inner pads 110 by injection molding process.
When the material of the protective layer 111 is silicon dioxide or silicon nitride, the protective layer may be formed on the inner pads 110 and the insulating layer between adjacent inner pads 110 through a deposition process.
Referring to fig. 5, the protective layer 111 may have a first opening 111a therein exposing the inner pad 110. In some embodiments, the inner pad 110 on the die 11 may be embedded in the protective layer 111, and the first opening 111a is fabricated in a process of forming the wiring layer 13 (see fig. 11).
In the embodiment shown in fig. 5, a first opening 111a exposes a partial region of an inner pad 110. In other embodiments, one first opening 111a may also expose a partial region of two or more inner pads 110.
The number of the die 11 may be two, three, all the die after dicing of one wafer, or even all the die after dicing of a plurality of wafers, and the present invention is not limited to the number of the die 11.
The wafer may be thinned from the back side prior to dicing to reduce the thickness of the die 11.
The carrier plate 2 is a hard plate and may include a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.
An adhesive layer may be disposed between the carrier plate 2 and the die 11, so as to fix the carrier plate and the die. Specifically, an entire adhesive layer may be coated on the surface of the carrier plate 2, and the plurality of dies 11 may be placed on the adhesive layer. The adhesive layer may be made of an easily peelable material so as to peel the carrier plate 2 and the die 11 apart, for example, a thermally separable material which can be made to lose adhesiveness by heating or a UV separable material which can be made to lose adhesiveness by ultraviolet irradiation.
Next, referring to step S2 in fig. 3, and as shown in fig. 2 and 6, a plurality of electrical connectors 12 are provided, the electrical connectors 12 including a first conductive portion 12a, a second conductive portion 12b, and a connection portion 12c connecting the first conductive portion 12a and the second conductive portion 12 b; referring to fig. 7, each electrical connector 12 is disposed on each die 11, the first conductive portion 12a is electrically connected to the back surface 11b of the die 11, and the second conductive portion 12b is disposed on the surface of the carrier 2.
The material of the electrical connector 12 may be a metal with good electrical conductivity and a certain hardness, such as copper.
The electrical connector 12 may be rectangular in shape as shown in fig. 2.
Referring to fig. 6, a plurality of electrical connectors 12 may be disposed on a first support plate 3. The vertical section of the electrical connector 12 may be semi-convex to accommodate the die 11. The semi-convex shape can be formed by at least one method of cutting, stamping, etching and embossing, and can be mass-produced in a batch to reduce the cost.
In the embodiment shown in fig. 6, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are right angles. In some embodiments, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are obtuse angles.
The first support plate 3 is a hard plate and may include a glass plate, a ceramic plate, a metal plate, etc.
An adhesive layer may be provided between the first conductive portion 12a of the electrical connector 12 and the first support plate 3, so as to achieve fixation therebetween. Specifically, an entire adhesive layer may be coated on the surface of the first support plate 3, and the first conductive portions 12a of the plurality of electrical connectors 12 may be disposed on the adhesive layer. The adhesive layer may be made of an easily peelable material for peeling the electrical connection member 12 from the first support plate 3, for example, a heat-peelable material which can be made to lose its tackiness by heating or a UV-peelable material which can be made to lose its tackiness by ultraviolet irradiation.
Referring to fig. 7, the first support plate 3 and the carrier plate 2 are aligned, each electrical connector 12 is disposed on each die 11, the first conductive portion 12a is located on the back surface 11b of the die 11, and the second conductive portion 12b is located on the surface of the carrier plate 2.
In some embodiments, a conductive paste may be disposed between the first conductive portion 12a and the back surface 11b of the die 11 to electrically connect the two. The conductive paste may include a nano copper/conductive polymer composite. The nano copper/conductive polymer composite material is a composite material formed by adding nano copper particles into a conductive polymer and uniformly dispersing nano copper in the conductive polymer. The composite material is a solid, flat sheet-like structure, preferably the same shape and size as the surface of the die backside 11 b.
Specifically, the nano copper/conductive polymer composite material is first placed on the back surface 11b of the die, and then the electrical connection pieces 12 arranged on the first support plate 3 are transferred to predetermined positions on the carrier plate 2, and the first conductive portions 12a of the electrical connection pieces 12 cover the composite material on the back surface 11b of the die. Heating the bare chip 11, the nano copper/conductive polymer composite material and the electric connector 12 on the carrier plate 2 to a temperature above the glass transition temperature of the conductive polymer material; at this time, the conductive polymer material is changed from a solid to a semi-liquid having a certain viscosity, bonding the die backside 11b with the first conductive portion 12 a.
In the nano-copper/conductive polymer composite, the conductive polymer may be: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide. The conductive polymer is formed by changing an insulator into a conductor through chemical or electrochemical doping by a macromolecule with conjugated pi-bond, has good conductive property, and the conductivity is further enhanced after nano copper is added.
Copper is one of the most excellent metal materials, and when the copper scale is reduced to the nanometer level, the copper material has high specific surface area, high surface activity and more excellent electric and heat conduction characteristics. Preferably, the nano copper is spherical, and the particle size is less than 800nm; further preferably, the particle diameter of the nano copper is in the range of 200nm to 500nm. This is because: the specific surface area of the nano copper material is increased along with the reduction of the particle size of the material, and the electric conduction and heat conduction properties of the material are enhanced; when the particle size is reduced to below 800nm, the material has excellent electric and heat conduction characteristics; however, when the particle size is reduced to below 200nm, the manufacturing cost of the nano material is increased remarkably, the packaging economic benefit is affected, and when the particle size of the nano copper is reduced to below 200nm, the surface energy of the nano copper particles is increased, larger particles are easily formed by agglomeration among the particles, and the electric conductivity and the heat conductivity of the composite material are damaged.
Preferably, the nano-copper is added in an amount of more than 5wt% in the nano-copper/conductive polymer composite.
In some embodiments, the first conductive portion 12a may be in direct contact with the back surface 11b of the die 11 to make electrical connection therebetween.
In some embodiments, the backside 11b of the die 11 may also be provided with a conductive layer. The conductive layer may be formed before dicing the die 11.
In the embodiment shown in fig. 7, there is no gap between the connection portion 12c of the electrical connector 12 and the die 11, and in other embodiments, there may be a gap between the two to allow molding compound to enter.
After that, the first support plate 3 is removed. The first support plate 3 may be removed by a conventional removal method such as laser lift-off and UV irradiation.
Then, referring to step S3 in fig. 3, fig. 8 and fig. 9, a first molding layer 10 is formed on the surface of the carrier 2 to embed each die 11 and each electrical connector 12; referring to fig. 10, the carrier plate 2 is removed. Wherein, fig. 8 is a top view of the first plastic sealing layer, and the first plastic sealing layer shows perspective effect; fig. 9 is a cross-sectional view taken along the line BB in fig. 8.
The material of the first plastic layer 10 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. Correspondingly, the packaging can be performed by filling liquid plastic packaging material between each bare chip 11 and each electric connector 12 and then curing the liquid plastic packaging material at high temperature through a plastic packaging mold.
The first plastic layer 10 may be thinned by mechanical grinding, for example, grinding with a grinding wheel, so as to adjust the height of the chip package structure 1a (see fig. 1).
The protective layer 111 may prevent the inner pad 110 and the electrical interconnect structures within the die 11 from being damaged during the formation of the first molding layer 10 and the grinding of the first molding layer 10.
Referring to fig. 10, after the carrier 2 is removed, the second conductive portion 12b of the electrical connector 12 is substantially in the same plane as the active surface 11a of the die 11. In addition, a second support plate 4 may be further disposed on the first plastic sealing layer 10. The second support plate 4 may support the die 11 embedded in the first plastic layer 10 in a subsequent process.
The second support plate 4 is a hard plate and may include a glass plate, a ceramic plate, a metal plate, etc.
Next, referring to step S4 in fig. 3 and fig. 11, a circuit layer 13 is formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10 to form the package intermediate structure 1 including a plurality of dies 11, the circuit layer 13 includes a rewiring layer 131, and the rewiring layer 131 electrically connects at least the second conductive portion 12b and the backside ground inner pad 110a.
In the present embodiment, forming the wiring layer 13 includes the following steps S41 to S42.
Step S41: a rewiring layer 131 is formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10.
The rewiring layer 131 is a fan-out line (fan-out).
Step S42: conductive studs 132 are formed on the rewiring layer 131. The conductive stud 132 is the outer lead 13a.
In one alternative, step S41 of forming the rewiring layer 131 includes steps S410 to S413.
Step S410: a photoresist layer is formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10.
In this step S410, in an alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film can be peeled off from the adhesive tape and applied to the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first plastic sealing layer 10. Alternatively, the photoresist layer may be formed by coating a liquid photoresist and then curing by heating.
Step S411: the photoresist layer is exposed and developed, and the photoresist layer is maintained in a first predetermined region, which is complementary to the region where the metal block 131a of the re-wiring layer 131 to be formed is located.
This step S411 patterns the photoresist layer. In other alternatives, other easily removable sacrificial materials may be used in place of the photoresist layer.
Step S412: the metal layer is filled in a complementary region of the first predetermined region to form a metal block 131a of the rewiring layer 131.
Of the plurality of metal blocks 131a, a part of the number of metal blocks 131a is located so as to electrically connect the second conductive portion 12b with the back ground inner pad 110a. In addition, there are also portions of the number of metal blocks 131a positioned to electrically connect one or more of the inner pads 110 for performing other functions.
This step S412 may be accomplished using an electroplating process. The copper or aluminum electroplating process is mature.
Specifically, before forming the photoresist Layer in step S410, a Seed Layer (Seed Layer) may be formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding Layer 10 by physical vapor deposition or chemical vapor deposition. The seed layer may serve as a power supply layer for electroplating copper or aluminum.
Step S413: ashing removes the photoresist layer remaining in the first predetermined area.
And after ashing, removing the seed crystal layer in the first preset area through dry etching or wet etching.
The metal block 131a of the re-wiring layer 131 may be planarized on the upper surface by a polishing process, for example, a chemical mechanical polishing method.
The metal blocks 131a of the rewiring layer 131 in this step S41 are arranged according to design requirements, and the distribution of the rewiring layers 131 on the respective dies 11 may be the same or different.
This step S42 may include steps S420-S425.
Step S420: a photoresist layer is formed on the metal block 131a, the protective layer 111, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10.
In this step S420, in an alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film may be peeled off from the adhesive tape and applied to the metal block 131a, the protective layer 111, the second conductive portion 12b of each electrical connector 12, and the first plastic sealing layer 10. Alternatively, the photoresist layer may be formed by coating a liquid photoresist and then curing by heating.
Step S421: the photoresist layer is exposed and developed, and the photoresist in the second preset area is reserved. The second predetermined region is complementary to a region where the conductive stud 132 is to be formed.
In this embodiment, the second predetermined area is located such that at least one conductive stud 132 can lead out the metal block 131a electrically connecting the second conductive portion 12b and the back ground inner pad 110a. In some embodiments, the metal block 131a electrically connecting the second conductive portion 12b and the back ground inner pad 110a may also be led out without the conductive bump 132.
The photoresist layer is patterned in this step S421. In other alternatives, other easily removable sacrificial materials may be used in place of the photoresist layer.
Step S422: and filling the complementary region of the second predetermined region with a metal layer to form the conductive stud 132.
This step S422 may be accomplished using an electroplating process. The copper or aluminum electroplating process is mature. A Seed Layer (Seed Layer) may also be deposited as a power Layer prior to electroplating copper or aluminum.
Step S423: ashing removes the photoresist layer remaining in the second predetermined area.
The conductive posts 132 may be planarized by a polishing process, such as chemical mechanical polishing.
Step S424: referring to fig. 11, a second molding layer 133 embedding the conductive stud 132 is formed on the conductive stud 132, the metal block 131a, the protective layer 111, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10.
In one alternative, the step S424 includes: firstly, attaching a semi-solid plastic packaging film on the conductive convex column 132, the metal block 131a, the protective layer 111, the second conductive part 12b of each electric connector 12 and the first plastic packaging layer 10; then, placing the structure to be molded, which is stuck with the semi-solid plastic packaging film, on a lower die body, and closing the high-temperature upper die body; when the upper die body is used for hot-pressing the plastic packaging film, the semi-solid plastic packaging film is changed into a liquid plastic packaging material, and after flowing, the plastic packaging material is continuously heated to change from a liquid state into a solid state to form a second plastic packaging layer 133; the mold is removed.
In another alternative, the second plastic layer 133 formed in the step S424 is formed by an injection molding process. Specifically, firstly, placing a structure to be molded on a lower die body, and closing a high-temperature upper die body; injecting normal-temperature liquid plastic package material into the high-temperature mold cavity; the normal temperature liquid molding compound flows while changing from liquid to solid second molding layer 133 due to heat.
The second molding layer 133 can improve electrical insulation properties between adjacent conductive studs 132 and metal blocks 131a.
Step S425: still referring to fig. 11, the second molding layer 133 is thinned until the conductive posts 132 are exposed.
The second plastic layer 133 may be thinned by mechanical grinding, such as grinding with a grinding wheel.
In some embodiments, step S41 may include S410'-S413'.
Step S410': referring to fig. 12, a first dielectric layer 131b is formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10. The material of the first dielectric layer 131b may be silicon dioxide or silicon nitride, and is formed by physical vapor deposition or chemical vapor deposition.
In step S411', a plurality of second openings are formed in the first dielectric layer 131b, and the second openings expose the inner pads 110. The second opening is a region where the metal block 131a is to be formed. The second opening may be formed by dry etching using the patterned photoresist as a mask.
In step S412', a conductive material layer is formed on the first dielectric layer 131b and in the second opening. The conductive material layer can be made of copper or aluminum, and is formed by physical vapor deposition or chemical vapor deposition.
In step S413', the conductive material layer is polished until the first dielectric layer 131b is exposed, and the conductive material layer in the second opening forms the metal block 131a.
In still other embodiments, at least two rewiring layers 131 may be formed.
In some embodiments, step S42 may include S420'-S422'.
Step S420': referring to fig. 12, conductive studs 132 are formed on the metal block 131a and the first dielectric layer 131b (or the protective layer 111, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10).
Step S421': a second dielectric layer 132b is formed on the conductive studs 132 and between adjacent conductive studs 132. The second dielectric layer 132b may be silicon dioxide or silicon nitride, and is formed by physical vapor deposition or chemical vapor deposition.
In step S422', the second dielectric layer 132b is polished until the conductive bump 132 is exposed.
In other embodiments, a second dielectric layer 132b is formed between adjacent conductive pillars 132, and an upper surface of the second dielectric layer 132b is flush with an upper surface of the conductive pillar 132, and the second dielectric layer 132b is made of an organic material. The organic material may be polyimide with good fluidity, and is cured after heating.
In still other embodiments, a second molding layer 133 is formed over the conductive studs 132 and between adjacent conductive studs 132, and the second molding layer 133 is thinned until the conductive studs 132 are exposed.
In still other embodiments, a second dielectric layer 132b is formed on the metal block 131a, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10, a third opening exposing the metal block 131a is formed in the second dielectric layer 132b, a conductive material is filled in the third opening, and the conductive material is polished until the second dielectric layer 132b is exposed. The conductive material filled in the third opening forms a conductive stud 132.
a) In an alternative, referring to fig. 11 and 12, the conductive stud 132 is an outer lead 13a.
b) Alternatively, referring to fig. 13, after the conductive stud 132 is exposed, an oxidation-resistant layer 134 is further formed on the conductive stud 132.
The oxidation resistant layer 134 may include: b1 Tin layer, or b 2) nickel layer and gold layer stacked from bottom to top, or b 3) nickel layer, palladium layer and gold layer stacked from bottom to top. The oxidation resistant layer 134 may be formed using an electroplating process. The conductive bump 132 may be made of copper, and the oxidation-resistant layer 134 may prevent oxidation of copper, thereby preventing deterioration of electrical connection performance caused by oxidation of copper.
c) Optionally, after exposing the conductive bump 132, a solder ball is further formed on the conductive bump 132 for flip-chip mounting the chip package structure 1a (see fig. 1).
After the outer leads are formed, the second support plate 4 is removed as shown with reference to fig. 14.
The second support plate 4 may be removed by conventional removal methods such as laser lift-off and UV irradiation.
Thereafter, referring to step S5 in fig. 3, fig. 14 and fig. 1, the package intermediate structure 1 is cut to form a plurality of chip package structures 1a, and each chip package structure 1a includes one die 11.
Fig. 15 is a top view of an electrical connector in a chip package structure according to a second embodiment of the invention. Referring to fig. 15, the chip package structure in this embodiment is substantially the same as the chip package structure 1a in fig. 1, except that: the connection portion 12c of the electrical connector 12 is partially removed and is H-shaped. In the thermal expansion and contraction process of the electrical connector 12 and the first plastic sealing layer 10, the removed area of the connecting portion 12c can provide a deformation accommodating space. Preferably, the first conductive portion 12a has a size larger than that of the second conductive portion 12 b.
Accordingly, the method for manufacturing the chip package structure in this embodiment is substantially the same as that of fig. 1 to 14, and the only difference is that: in step S2, the connection portion 12c of the electrical connector 12 is provided with a portion of the material removed, in an H-shape. The removal of portions of material may be formed by at least one of cutting, stamping, etching, embossing.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. A chip package structure, comprising:
a die including opposing active and back surfaces, the active surface having an inner pad and a protective layer, the protective layer exposing a partial region of the inner pad, the inner pad including at least one back-grounded inner pad;
the electric connector comprises a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part; the first conductive portion is electrically connected to the back surface of the die;
a first plastic package layer coating the bare chip and the electric connector, wherein the second conductive part of the electric connector and the active surface of the bare chip are exposed outside the first plastic package layer;
the circuit layer is positioned on the active surface of the bare chip, the second conductive part of the electric connector and the first plastic sealing layer, and comprises a rewiring layer which is at least electrically connected with the second conductive part and the back grounding inner bonding pad;
the electric connecting piece is H-shaped, and the size of the connecting part is respectively smaller than the size of the first conductive part and the size of the second conductive part in the direction perpendicular to the direction that the edge of the first conductive part far away from the connecting part points to the edge of the second conductive part far away from the connecting part and the direction perpendicular to the direction that the active surface points to the back surface.
2. The chip package structure of claim 1, wherein the second conductive portion of the electrical connector is in a same plane as the active surface of the die.
3. The chip package structure according to claim 1, wherein a conductive layer is provided on the back surface of the die, and/or a conductive paste is provided between the first conductive portion and the back surface of the die.
4. The chip package structure of claim 3, wherein the conductive paste comprises a nano-copper/conductive polymer composite.
5. The chip package structure of claim 1, wherein the wiring layer comprises an outer pin; and the rewiring layer is provided with a conductive convex column, and the conductive convex column is the outer pin.
6. The chip package structure of claim 5, wherein the conductive bump has an oxidation resistant layer thereon.
7. The chip package structure of claim 1, wherein the wiring layer comprises an outer pin; the rewiring layer is provided with a conductive convex column, the conductive convex column is provided with a solder ball, and the solder ball is the outer pin.
8. The chip package structure of claim 1, wherein the rewiring layer comprises at least two layers.
9. The chip package structure of claim 1, wherein a first molding layer is provided between the connection portion of the electrical connector and the die.
10. The chip package structure of claim 1, wherein the first conductive portion and the second conductive portion of the electrical connector are respectively at right angles to the connecting portion.
CN202010231967.6A 2020-03-27 2020-03-27 Chip packaging structure Active CN113725182B (en)

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Citations (4)

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Publication number Priority date Publication date Assignee Title
KR20020055687A (en) * 2000-12-29 2002-07-10 마이클 디. 오브라이언 Semiconductor package
CN102244013A (en) * 2010-05-14 2011-11-16 新科金朋有限公司 Semiconductor device and manufacturing method thereof
CN107039337A (en) * 2015-10-29 2017-08-11 商升特公司 With the method and semiconductor devices of the semiconductor element formation DCALGA encapsulation for having microtrabeculae
CN110729258A (en) * 2019-03-11 2020-01-24 Pep创新私人有限公司 Chip packaging method and chip structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020055687A (en) * 2000-12-29 2002-07-10 마이클 디. 오브라이언 Semiconductor package
CN102244013A (en) * 2010-05-14 2011-11-16 新科金朋有限公司 Semiconductor device and manufacturing method thereof
CN107039337A (en) * 2015-10-29 2017-08-11 商升特公司 With the method and semiconductor devices of the semiconductor element formation DCALGA encapsulation for having microtrabeculae
CN110729258A (en) * 2019-03-11 2020-01-24 Pep创新私人有限公司 Chip packaging method and chip structure
CN110729256A (en) * 2019-03-11 2020-01-24 Pep创新私人有限公司 Chip packaging method and chip structure

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