CN113725183B - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN113725183B CN113725183B CN202010231972.7A CN202010231972A CN113725183B CN 113725183 B CN113725183 B CN 113725183B CN 202010231972 A CN202010231972 A CN 202010231972A CN 113725183 B CN113725183 B CN 113725183B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0651—Function
- H01L2224/06515—Bonding areas having different functions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Abstract
The invention provides a chip packaging structure and a manufacturing method thereof.A first electric connector is arranged on a first bare chip, a second electric connector is arranged on a second bare chip, and first conductive parts of the first electric connector and the second electric connector are respectively and electrically connected to the back surfaces of the first bare chip and the second bare chip; the first die, the second die, the first electric connecting piece and the second electric connecting piece are encapsulated by the first plastic encapsulation layer, and the first conductive part and the second conductive part of the first electric connecting piece and the second electric connecting piece and the active surfaces of the first die and the second die are exposed outside the first plastic encapsulation layer; the active surfaces of the first and second dies, the second conductive portions of the first and second electrical connectors, and the first molding layer are formed with a circuit layer including a rewiring layer electrically connecting at least the second conductive portion of the first electrical connector and the backside ground inner pad of the second die. The back surface of the first die is grounded at a specific electric connection point position of the active surface of the second die by using the first electric connector.
Description
Technical Field
The present disclosure relates to chip packaging technology, and more particularly, to a chip packaging structure and a method for manufacturing the same.
Background
In recent years, with the continuous development of circuit integration technology, electronic products are increasingly miniaturized, intelligent, high-performance and high-reliability. The packaging technology not only affects the performance of the product, but also restricts the miniaturization of the product. In a power chip (power module), it is necessary to back ground specific electrical connection point locations of the active surface of the die.
In view of the above, the present invention provides a new chip package structure and a method for manufacturing the same, so as to package a power chip.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a manufacturing method thereof, which are used for packaging a power chip.
To achieve the above object, a first aspect of the present invention provides a chip package structure, including:
a first die and a second die, each of the first die and the second die including opposing active and back surfaces, the active surfaces having an inner pad and a protective layer, the protective layer exposing a partial region of the inner pad; the inner pads of the second die include at least one back-grounded inner pad;
the first electric connecting piece and the second electric connecting piece comprise a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part; the first conductive portion of the first electrical connector is electrically connected to a back side of the first die; the first conductive portion of the second electrical connector is electrically connected to a back side of the second die;
A first plastic layer coating the first die, the second die, the first electrical connector and the second electrical connector, wherein the first conductive part, the second conductive part, the active surface of the first die and the active surface of the second die of the first electrical connector are exposed outside the first plastic layer;
the circuit layer is located on the active surface of the first bare chip, the active surface of the second bare chip, the second conductive part of the first electric connector, the second conductive part of the second electric connector and the first plastic sealing layer, and comprises a rewiring layer which is at least electrically connected with the second conductive part of the first electric connector and at least one back grounding inner bonding pad of the second bare chip.
Optionally, the first electrical connector is H-shaped and/or the second electrical connector is H-shaped.
Optionally, a conductive layer is disposed on the back surface of the first die, and/or a conductive adhesive is disposed between the first conductive portion of the first electrical connector and the back surface of the first die; and/or
A conductive layer is disposed on the back side of the second die, and/or a conductive adhesive is disposed between the first conductive portion of the second electrical connector and the back side of the second die.
Optionally, a first oxidation resistant layer is provided on the first conductive portion of the first electrical connector exposed outside the first plastic package layer; and/or a first oxidation resistant layer is arranged on the first conductive part of the second electric connector exposed outside the first plastic package layer.
Optionally, the circuit layer includes an outer pin; and the rewiring layer is provided with a conductive convex column, and the conductive convex column is the outer pin.
Optionally, the conductive protruding column is provided with a second oxidation resistant layer.
Optionally, the circuit layer includes an outer pin; the rewiring layer is provided with a conductive convex column, the conductive convex column is provided with a solder ball, and the solder ball is the outer pin.
Optionally, the rewiring layer comprises two or more layers.
The second aspect of the present invention provides a method for manufacturing a chip package structure, including:
providing a carrier plate, a plurality of first bare chips and a plurality of second bare chips, wherein each of the first bare chips and the second bare chips comprises an opposite active surface and a back surface, the active surface is provided with an inner bonding pad and a protective layer covering the inner bonding pad, and the inner bonding pad of the second bare chip at least comprises one back grounding inner bonding pad; fixing the active surfaces of the first bare chips and the second bare chips on the carrier plate;
Providing a plurality of first electric connectors and a plurality of second electric connectors, wherein the first electric connectors and the second electric connectors comprise a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part; each first electric connector is arranged on each first bare chip, each second electric connector is arranged on each second bare chip, a first conductive part of each first electric connector is electrically connected to the back surface of each first bare chip, a second conductive part of each first electric connector is arranged on the surface of the carrier plate, a first conductive part of each second electric connector is electrically connected to the back surface of each second bare chip, and a second conductive part of each second electric connector is arranged on the surface of the carrier plate;
forming a first plastic sealing layer which is used for embedding each first bare chip, each second bare chip, each first electric connecting piece and each second electric connecting piece on the surface of the carrier plate; removing the carrier plate;
forming a wiring layer on the active surface of each first die, the active surface of each second die, the second conductive portion of each first electrical connector, the second conductive portion of each second electrical connector, and the first molding layer to form a package intermediate structure comprising a plurality of first dies and second dies, the wiring layer comprising a rewiring layer electrically connecting at least the second conductive portion of the first electrical connector and at least one of the back ground inner pads of the second dies;
And cutting the packaging intermediate structure to form a plurality of chip packaging structures, wherein each chip packaging structure comprises the first bare chip and the second bare chip.
Optionally, a plurality of first electrical connectors and a plurality of second electrical connectors are provided disposed on a first support plate.
Optionally, the first electrical connector is H-shaped, and/or the first electrical connector is formed by at least one of cutting, stamping, etching, embossing; and/or
The second electrical connector is H-shaped and/or the second electrical connector is formed by at least one of cutting, stamping, etching, embossing.
Optionally, the method further comprises: and forming a first oxidation resistant layer on the first conductive parts of the first electric connecting pieces and the second electric connecting pieces exposing the first plastic sealing layer.
Optionally, forming a circuit layer on the active surface of each first die, the active surface of each second die, the second conductive portion of each first electrical connector, the second conductive portion of each second electrical connector, and the first molding layer includes:
forming the rewiring layer on the inner bonding pads of the first and second dies, the protective layer, the first plastic sealing layer between the first and second dies, and the second conductive parts of the first and second electrical connectors;
And forming a conductive stud on the rewiring layer.
Optionally, the rewiring layer comprises two or more layers.
Optionally, the method further comprises: and forming a solder ball on the conductive convex column, wherein the solder ball is an outer pin.
Optionally, the method further comprises: and forming a second oxidation resistance layer on the conductive convex column.
Optionally, forming the conductive stud on the rewiring layer includes:
forming a conductive stud on the metal block of the rewiring layer;
forming a second dielectric layer on the conductive convex columns and between the adjacent conductive convex columns, wherein the second dielectric layer is made of inorganic materials;
the second dielectric layer is polished until the conductive stud is exposed.
Optionally, forming the conductive stud on the rewiring layer includes:
forming a conductive stud on the metal block of the rewiring layer;
and forming a second dielectric layer between adjacent conductive convex columns, wherein the upper surface of the second dielectric layer is flush with the upper surface of the conductive convex column, and the second dielectric layer is made of an organic material.
Optionally, forming the conductive stud on the rewiring layer includes:
forming a second dielectric layer on the rewiring layer;
forming a plurality of third openings in the second dielectric layer, the third openings exposing the metal blocks of the rewiring layer;
Forming a conductive material layer on the second dielectric layer and in the third opening;
and polishing the conductive material layer until the second dielectric layer is exposed, wherein the conductive material layer in the third opening forms a conductive convex column.
Optionally, forming the conductive stud on the rewiring layer includes:
forming a conductive convex column on the metal block of the rewiring layer, and forming a second plastic sealing layer embedding the conductive convex column on the rewiring layer;
and thinning the second plastic sealing layer until the conductive convex columns are exposed.
Optionally, a conductive layer is disposed on the back surface of the first die, and/or a conductive adhesive is disposed between the first conductive portion of the first electrical connector and the back surface of the first die; and/or
A conductive layer is disposed on the back side of the second die, and/or a conductive adhesive is disposed between the first conductive portion of the second electrical connector and the back side of the second die.
Optionally, the conductive paste comprises a nano copper/conductive polymer composite.
Optionally, in the nano copper/conductive polymer composite, the conductive polymer is: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide, and/or the particle size of the nano copper is less than 800nm.
Optionally, the particle size of the nano copper ranges from 200nm to 500nm.
Optionally, the material of the protective layer is at least one of insulating resin material, silicon dioxide and silicon nitride. The protection layer can play an insulating role, and in the process of forming the first plastic sealing layer and grinding the first plastic sealing layer, the hardness can be enough to protect the inner bonding pad and the electric interconnection structure in the bare chip from damage, and the invention is not limited to the specific material of the protection layer.
Optionally, in the step of fixing the active surfaces of each first die and each second die to the carrier, each first die and/or each second die has a first opening in the protective layer exposing the inner pad; or forming a first opening exposing the inner pad in the protective layer of each first die and/or each second die in the step of forming a line layer.
Compared with the prior art, the invention has the beneficial effects that:
the first electric connector is arranged on the first bare chip, the second electric connector is arranged on the second bare chip, the first electric connector and the second electric connector comprise a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part, the first conductive part of the first electric connector is electrically connected to the back surface of the first bare chip, the first conductive part of the second electric connector is electrically connected to the back surface of the second bare chip, and the second conductive parts of the first electric connector and the second electric connector are basically in the same plane with the active surfaces of the first bare chip and the second bare chip; the first die, the second die, the first electric connecting piece and the second electric connecting piece are encapsulated by the first plastic sealing layer, and the first conductive part and the second conductive part of the first electric connecting piece and the second electric connecting piece are exposed outside the first plastic sealing layer; the active surfaces of the first bare chip and the second bare chip, the second conductive parts of the first electric connecting piece and the second electric connecting piece and the first plastic sealing layer are provided with a circuit layer, the circuit layer comprises a rewiring layer, and the rewiring layer is at least electrically connected with the second conductive part of the first electric connecting piece and at least one back grounding inner bonding pad of the second bare chip. The back surface of the first die is grounded at a specific electric connection point position of the active surface of the second die by using the first electric connector.
Drawings
Fig. 1 is a schematic cross-sectional view of a chip package structure according to a first embodiment of the present invention.
FIG. 2 is a top view of a first electrical connector or a second electrical connector;
FIG. 3 is a flow chart of a method of fabricating the chip package structure of FIG. 1;
fig. 4 to 14 are schematic views of intermediate structures corresponding to the flow in fig. 3;
fig. 15 is a schematic cross-sectional structure of a chip package structure according to a second embodiment of the present invention;
fig. 16 is a top view of a first electrical connector or a second electrical connector in a chip package structure according to a third embodiment of the present invention.
To facilitate an understanding of the present invention, all reference numerals appearing in the present invention are listed below:
first die 11c second die 11d
First electrical connector 12d and second electrical connector 12e
Die active side 11a die back side 11b
Inner pad 110 protective layer 111
First conductive portion 12a of first molding layer 10
Second conductive portion 12b connecting portion 12c
Outer pin 13a of circuit layer 13
Second molding layer 133 of metal block 131a
Second oxidation resistant layer 134 of conductive stud 132
First antioxidation layer 121 chip package structure 1a
First opening 111a of carrier plate 2
First support plate 3 second support plate 4
First dielectric layer 131b of package intermediate structure 1
Second dielectric layer 132b rewiring layer 131
Back grounded inner pad 110a
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 is a schematic cross-sectional view of a chip package structure according to a first embodiment of the present invention.
Referring to fig. 1, a chip package structure 1a includes:
the first die 11c and the second die 11d, the first die 11c and the second die 11d each include an active surface 11a and a back surface 11b opposite to each other, the active surface 11a has an inner pad 110 and a protective layer 111, and the protective layer 111 exposes a partial region of the inner pad 110; the inner pads 110 of the second die 11d include at least one back ground inner pad 110a;
the first electrical connector 12d and the second electrical connector 12e, the first electrical connector 12d and the second electrical connector 12e each include a first conductive portion 12a, a second conductive portion 12b, and a connection portion 12c connecting the first conductive portion 12a and the second conductive portion 12 b; the first conductive portion 12a of the first electrical connector 12d is electrically connected to the back surface 11b of the first die 11 c; the first conductive portion 12a of the second electrical connector 12e is electrically connected to the back surface 11b of the second die 11 d;
A first molding layer 10 covering the first die 11c, the second die 11d, the first electrical connector 12d, and the second electrical connector 12e, the first conductive portion 12a, the second conductive portion 12b, the active face 11a of the first die 11c, and the active face 11a of the second die 11d of the first electrical connector 12d being exposed outside the first molding layer 10;
the circuit layer 13, the circuit layer 13 is located on the active surface 11a of the first die 11c, the active surface 11a of the second die 11d, the second conductive portion 12b of the first electrical connector 12d, the second conductive portion 12b of the second electrical connector 12e, and the first molding layer 10, and the circuit layer 13 includes a rewiring layer 131, where the rewiring layer 131 electrically connects at least the second conductive portion 12b of the first electrical connector 12d and the back ground inner pad 110a of the second die 11 d.
The first die 11c and the second die 11d may each include a plurality of devices formed on a semiconductor substrate, and an electrical interconnect structure electrically connected to each device. The inner pads 110 of the die active surface 11a are connected to electrical interconnect structures for inputting/outputting electrical signals of the respective devices. The back ground inner pad 110a is for electrical connection with the back surface 11b of the first die 11 c. The first die 11c and the second die 11d may be power chips, or one may be a power chip, and the other may be a chip with other functions.
The protective layer 111 is made of an insulating material, and may be at least one of an insulating resin material, silicon dioxide, and silicon nitride. Examples of the insulating resin material include polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like.
Fig. 2 is a top view of a first electrical connector or a second electrical connector. Referring to fig. 2, the first electrical connector 12d and the second electrical connector 12e are rectangular in plan view.
Referring to fig. 1, the first electrical connector 12d has a semi-convex vertical cross section for accommodating the first die 11c; the second electrical connector 12e has a semi-convex vertical cross section for accommodating the second die 11d. The first electrical connector 12d and the second electrical connector 12e may be made of metal with good electrical conductivity and certain hardness, such as copper.
In the embodiment shown in fig. 1, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are right angles. In some embodiments, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c may be obtuse angles.
In some embodiments, a conductive adhesive may be disposed between the first conductive portion 12a of the first electrical connector 12d and the back surface 11b of the first die 11c to achieve electrical connection therebetween; conductive glue may also be disposed between the first conductive portion 12a of the second electrical connector 12e and the back surface 11b of the second die 11d to electrically connect the two. The conductive paste may include a nano copper/conductive polymer composite.
In the nano-copper/conductive polymer composite, the conductive polymer may be: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide. The conductive polymer is formed by changing an insulator into a conductor through chemical or electrochemical doping by a macromolecule with conjugated pi-bond, has good conductive property, and the conductivity is further enhanced after nano copper is added.
Copper is one of the most excellent metal materials, and when the copper scale is reduced to the nanometer level, the copper material has high specific surface area, high surface activity and more excellent electric and heat conduction characteristics. Preferably, the nano copper is spherical, and the particle size is less than 800nm; further preferably, the particle diameter of the nano copper is in the range of 200nm to 500nm. This is because: the specific surface area of the nano copper material is increased along with the reduction of the particle size of the material, and the electric conduction and heat conduction properties of the material are enhanced; when the particle size is reduced to below 800nm, the material has excellent electric and heat conduction characteristics; however, when the particle size is reduced to below 200nm, the manufacturing cost of the nano material is increased remarkably, the packaging economic benefit is affected, and when the particle size of the nano copper is reduced to below 200nm, the surface energy of the nano copper particles is increased, larger particles are easily formed by agglomeration among the particles, and the electric conductivity and the heat conductivity of the composite material are damaged.
Preferably, the nano-copper is added in an amount of more than 5wt% in the nano-copper/conductive polymer composite.
In some embodiments, the first conductive portion 12a of the first electrical connector 12d may be in direct contact with the back surface 11b of the first die 11c to make electrical connection therebetween.
In some embodiments, the back surface 11b of the first die 11c may also be provided with a conductive layer.
In some embodiments, the first conductive portion 12a of the second electrical connector 12e may be in direct contact with the back surface 11b of the second die 11d to make electrical connection therebetween.
In some embodiments, the back surface 11b of the second die 11d may also be provided with a conductive layer.
In the embodiment shown in fig. 1, there is no gap between the connection portion 12c of the first electrical connector 12d and the first die 11c, and in other embodiments, there may be a gap between the connection portion 12c of the first electrical connector 12d and the first die 11c, so that the first molding layer 10 enters, thereby improving the connection firmness between the first electrical connector 12d and the first die 11 c. The connection portion 12c of the second electrical connector 12e and the second die 11d have no gap therebetween, and in other embodiments, a gap may be formed therebetween to enable the first molding layer 10 to enter, so as to improve the connection firmness between the second electrical connector 12e and the second die 11 d.
The material of the first plastic layer 10 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like.
In the embodiment shown in fig. 1, the rewiring layer 131 includes a metal block 131a and a second molding layer 133 between adjacent metal blocks 131a, with one layer. In other embodiments, the rewiring layer 131 may include two or more layers. Of the plurality of metal blocks 131a, a portion of the plurality of metal blocks 131a electrically connects one or more inner pads 110 for performing other functions in addition to a portion of the plurality of metal blocks 131a electrically connecting the second conductive portion 12b of the first electrical connector 12d with the back-grounded inner pad 110a of the second die 11 d. In addition, there may be a partial number of metal blocks 131a electrically connected to the second conductive portions 12b of the second electrical connector 12 e.
In the embodiment shown in fig. 1, the conductive stud 132 is the outer lead 13a. The conductive stud 132 may be made of a metal such as copper, and may have a second oxidation resistant layer 134 thereon. In other embodiments, solder balls may be disposed on the conductive studs 132, and the solder balls are the outer pins 13a.
Referring to fig. 1, back grounding of an MCM multi-chip assembly (chip package structure 1 a) is achieved by electrically connecting specific back-grounded inner pads 110 of the first die active surface 11a and/or the second die active surface 11a with first electrical connectors 12d and/or second electrical connectors 12e, depending on the specific design of the circuit. And depending on the specific design of the circuit, the first die active surface 11a and/or specific inner pads 110 of the second die active surface 11a may be electrically interconnected.
In some embodiments, the first conductive portions 12a of the first electrical connector 12d and the second electrical connector 12e may be exposed outside the chip packaging structure 1a, so as to facilitate improving heat dissipation performance of the chip, ensure continuous and efficient operation of the chip, and solve the problem of life-affecting caused by overheating of the chip.
In some embodiments, the chip package structure 1a may further include three or more dies such as a third die, a third electrical connector, etc., and the inner pads of the other dies such as the third die may be electrically connected with the inner pads 110 of the first die 11c (and/or the second die 11 d).
An embodiment of the present invention provides a method for manufacturing the chip package structure 1a in fig. 1. Fig. 3 is a flow chart of a method of fabrication. Fig. 4 to 14 are schematic views of intermediate structures corresponding to the flow in fig. 3.
First, referring to step S1 in fig. 3, as shown in fig. 4 and fig. 5, a carrier 2, a plurality of first dies 11c and a plurality of second dies 11d are provided, each of the first dies 11c and the second dies 11d includes an active surface 11a and a back surface 11b, the active surface 11a has an inner pad 110 and a protective layer 111 covering the inner pad 110, and the inner pad 110 of the second die 11d includes at least one back grounded inner pad 110a; the active surfaces 11a of the first die 11c and the second die 11d are fixed to the carrier 2. Wherein fig. 4 is a top view of a carrier plate, a plurality of first die, and a plurality of second die; fig. 5 is a cross-sectional view taken along line AA in fig. 4.
The first die 11c and the second die 11d are formed for dicing a wafer including a wafer active surface having an inner pad 110 and an insulating layer (not shown) protecting the inner pad 110, and a wafer back surface. After dicing, the wafer forms a first die 11 c/a second die 11d, and accordingly, the first die 11c and the second die 11d include a die active surface 11a and a die back surface 11b, and the die active surface 11a has an inner pad 110 and an insulating layer protecting the inner pad 110. The protective layer 111 is applied on the active surface 11a of the die, and the protective layer 111 may be applied by: the protective layer 111 is applied on the wafer active surface before dicing the wafer into the first die 11 c/second die 11d, and dicing the wafer with the protective layer 111 into the first die 11 c/second die 11d with the protective layer 111 may be: after the wafer is diced into the first die 11 c/second die 11d, a protective layer 111 is applied over the first die 11 c/second die 11 d.
The first die 11c and the second die 11d may each include a plurality of devices formed on a semiconductor substrate, and an electrical interconnect structure electrically connected to each device. The inner pads 110 of the die active surface 11a are connected to electrical interconnect structures for inputting/outputting electrical signals of the respective devices. The back ground inner pad 110a is for electrical connection with the back surface 11b of the first die 11 c. The first die 11c and the second die 11d may be power chips, or one may be a power chip, and the other may be a chip with other functions.
Note that the structures and functions of the first dies 11c may be the same or different; the structure and function of each second die 11d may be the same or different.
The protective layer 111 is made of an insulating material, and may be at least one of an insulating resin material, silicon dioxide, and silicon nitride.
The insulating resin material, for example, polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), etc., may be pressed on the inner pad 110 and the insulating layer between adjacent inner pads 110 by a) lamination process, or b) coated on the inner pad 110 and the insulating layer between adjacent inner pads 110 first, post-cured, or c) cured on the inner pad 110 and the insulating layer between adjacent inner pads 110 by injection molding process.
When the material of the protective layer 111 is silicon dioxide or silicon nitride, the protective layer may be formed on the inner pad 110 and the insulating layer between adjacent inner pads 110 through a deposition process.
Referring to fig. 5, the protective layers 111 of the first and second dies 11c and 11d may have a first opening 111a therein exposing the inner pad 110. In some embodiments, the inner pads 110 on the first die 11c and/or the second die 11d may be embedded within the protective layer 111, and the first opening 111a is made in a process of forming the wiring layer 13 (see fig. 11).
In the embodiment shown in fig. 5, a first opening 111a exposes a partial region of an inner pad 110. In other embodiments, one first opening 111a may also expose a partial region of two or more inner pads 110.
The number of the first die 11c and the second die 11d may be two, three, all die after dicing a wafer, or even all die after dicing a plurality of wafers, and the present invention is not limited to the number of the first die 11c and the second die 11 d.
The wafer may be thinned from the back side prior to dicing to reduce the thickness of the first die 11c and/or the second die 11 d.
The carrier plate 2 is a hard plate and may include a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.
An adhesive layer may be disposed between the carrier 2 and the first die 11c and between the carrier 2 and the second die 11d, so as to fix the two. Specifically, an entire adhesive layer may be coated on the surface of the carrier 2, and the plurality of first dies 11c and the plurality of second dies 11d are disposed on the adhesive layer. The adhesive layer may be made of an easily peelable material to peel the carrier plate 2 from the first die 11c and the second die 11d, and may be made of a thermally separable material that can be made tacky by heating or a UV separable material that can be made tacky by ultraviolet irradiation, for example.
Next, referring to step S2 in fig. 3, and as shown in fig. 2 and fig. 6, a plurality of first electrical connectors 12d and a plurality of second electrical connectors 12e are provided, and each of the first electrical connectors 12d and the second electrical connectors 12e includes a first conductive portion 12a, a second conductive portion 12b, and a connection portion 12c connecting the first conductive portion 12a and the second conductive portion 12 b; referring to fig. 7, each first electrical connector 12d is disposed on each first die 11c, each second electrical connector 12e is disposed on each second die 11d, the first conductive portion 12a of the first electrical connector 12d is electrically connected to the back surface of the first die 11c, the second conductive portion 12b of the first electrical connector 12d is disposed on the surface of the carrier 2, the first conductive portion 12a of the second electrical connector 12e is electrically connected to the back surface of the second die 11d, and the second conductive portion 12b of the second electrical connector 12e is disposed on the surface of the carrier 2.
The first electrical connector 12d and the second electrical connector 12e may be made of metal with good electrical conductivity and a certain hardness, such as copper.
The first electrical connector 12d and the second electrical connector 12e may have a rectangular shape as shown in fig. 2.
Referring to fig. 6, a plurality of first electrical connectors 12d and a plurality of second electrical connectors 12e may be disposed on a first support plate 3. The vertical section of the first electrical connector 12d may be semi-convex to accommodate the first die 11c. The vertical section of the second electrical connector 12e may also be semi-convex to accommodate the second die 11d. The semi-convex shape may be formed by at least one of cutting, stamping, etching, embossing.
In the embodiment shown in fig. 6, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are right angles. In some embodiments, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are obtuse angles.
The first support plate 3 is a hard plate and may include a glass plate, a ceramic plate, a metal plate, etc.
An adhesive layer may be disposed between the first conductive portions 12a of the first and second electrical connectors 12d and 12e and the first support plate 3, so as to fix the two. Specifically, an entire adhesive layer may be coated on the surface of the first support plate 3, and the first conductive portions 12a of the plurality of first electrical connectors 12d and the plurality of second electrical connectors 12e may be disposed on the adhesive layer. The adhesive layer may be made of an easily peelable material so as to peel the first and second electrical connectors 12d, 12e from the first support plate 3, respectively, and may be made of a thermally separable material that can be made to lose adhesiveness by heating or a UV separable material that can be made to lose adhesiveness by ultraviolet irradiation, for example.
Referring to fig. 7, the first support plate 3 and the carrier plate 2 are aligned, each first electrical connector 12d is disposed on each first die 11c, the first conductive portion 12a is located on the back surface 11b of the first die 11c, and the second conductive portion 12b is located on the surface of the carrier plate 2; each second electrical connector 12e is disposed on each second die 11d, the first conductive portion 12a is disposed on the back surface 11b of the second die 11d, and the second conductive portion 12b is disposed on the surface of the carrier 2.
In some embodiments, a conductive adhesive may be disposed between the first conductive portion 12a of the first electrical connector 12d and the back surface 11b of the first die 11c to electrically connect the two; conductive glue may also be disposed between the first conductive portion 12a of the second electrical connector 12e and the back surface 11b of the second die 11d to electrically connect the two. The conductive paste may include a nano copper/conductive polymer composite. The nano copper/conductive polymer composite material is a composite material formed by adding nano copper particles into a conductive polymer and uniformly dispersing nano copper in the conductive polymer. The composite material is a solid, flat sheet-like structure, preferably the same shape and size as the surface of the die backside 11 b.
Specifically, the nano copper/conductive polymer composite material is first placed on the back surfaces 11b of the first die 11c and the second die 11d, and then the plurality of first electrical connectors 12d and the plurality of second electrical connectors 12e arranged on the first support plate 3 are transferred to predetermined positions on the carrier plate 2, and the first conductive portions 12a of the first electrical connectors 12d and the second electrical connectors 12e cover the composite material on the back surfaces 11b of the dies. Then heating the first die 11c, the second die 11d, the nano-copper/conductive polymer composite, the first electrical connector 12d and the second electrical connector 12e on the carrier plate 2 to above the glass transition temperature of the conductive polymer material; at this time, the conductive polymer material is changed from a solid to a semi-liquid having a certain viscosity, and the back surface 11b of the first die 11c and the first conductive portion 12a of the first electrical connector 12d, and the back surface 11b of the second die 11d and the first conductive portion 12a of the second electrical connector 12e are bonded together.
In the nano-copper/conductive polymer composite, the conductive polymer may be: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide. The conductive polymer is formed by changing an insulator into a conductor through chemical or electrochemical doping by a macromolecule with conjugated pi-bond, has good conductive property, and the conductivity is further enhanced after nano copper is added.
Copper is one of the most excellent metal materials, and when the copper scale is reduced to the nanometer level, the copper material has high specific surface area, high surface activity and more excellent electric and heat conduction characteristics. Preferably, the nano copper is spherical, and the particle size is less than 800nm; further preferably, the particle diameter of the nano copper is in the range of 200nm to 500nm. This is because: the specific surface area of the nano copper material is increased along with the reduction of the particle size of the material, and the electric conduction and heat conduction properties of the material are enhanced; when the particle size is reduced to below 800nm, the material has excellent electric and heat conduction characteristics; however, when the particle size is reduced to below 200nm, the manufacturing cost of the nano material is increased remarkably, the packaging economic benefit is affected, and when the particle size of the nano copper is reduced to below 200nm, the surface energy of the nano copper particles is increased, larger particles are easily formed by agglomeration among the particles, and the electric conductivity and the heat conductivity of the composite material are damaged.
Preferably, the nano-copper is added in an amount of more than 5wt% in the nano-copper/conductive polymer composite.
In some embodiments, direct contact may be made between the back surface 11b of the first die 11c and the first conductive portion 12a of the first electrical connector 12d, and/or between the back surface 11b of the second die 11d and the first conductive portion 12a of the second electrical connector 12e, to achieve electrical connection therebetween.
In some embodiments, the back surface 11b of the first die 11c, and/or the back surface 11b of the second die 11d may also be provided with a conductive layer. The conductive layer may be formed before the first die 11c and/or the second die 11d are cut.
In the embodiment shown in fig. 7, there is no gap between the connection portion 12c of the first electrical connector 12d and the first die 11c, and in other embodiments, there may be a gap between the two to allow molding compound to enter. The connection portion 12c of the second electrical connector 12e and the second die 11d have no gap therebetween, and in other embodiments, a gap may be formed therebetween to allow the molding compound to enter.
After that, the first support plate 3 is removed. The first support plate 3 may be removed by a conventional removal method such as laser lift-off and UV irradiation.
Thereafter, referring to step S3 in fig. 3, fig. 8 and fig. 9, a first molding layer 10 is formed on the surface of the carrier 2 to embed each first die 11c, each second die 11d, each first electrical connector 12d and each second electrical connector 12 e; referring to fig. 10, the carrier plate 2 is removed. Wherein, fig. 8 is a top view of the first plastic sealing layer, and the first plastic sealing layer shows perspective effect; fig. 9 is a cross-sectional view taken along the line BB in fig. 8.
The material of the first plastic layer 10 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. Correspondingly, the packaging can be performed by filling liquid plastic packaging material between each first die 11c, each second die 11d, each first electric connector 12d and each second electric connector 12e, and then curing the liquid plastic packaging material at a high temperature through a plastic packaging die.
The first plastic layer 10 may be thinned by mechanical grinding, such as grinding with a grinding wheel.
The protective layer 111 may prevent the inner pad 110 and the electrical interconnection structures within the first die 11c and the second die 11d from being damaged during the formation of the first molding layer 10 and the grinding of the first molding layer 10.
Referring to fig. 10, after the carrier 2 is removed, the first electrical connectors 12d are substantially coplanar with the second conductive portions 12b of the second electrical connectors 12e, and the active surfaces 11a of the first die 11c and the second die 11 d. In addition, a second support plate 4 may be disposed on the first plastic layer 10 and the first conductive portion 12a of each first electrical connector 12d and each second electrical connector 12 e. The second support board 4 can support the first die 11c and the second die 11d embedded in the first molding layer 10 in a subsequent process.
The second support plate 4 is a hard plate and may include a glass plate, a ceramic plate, a metal plate, etc.
Then, referring to step S4 in fig. 3 and fig. 11, a circuit layer 13 is formed on the active surface 11a of each first die 11c, the active surface 11a of each second die 11d, the second conductive portion 12b of each first electrical connection 12d, the second conductive portion 12b of each second electrical connection 12d, and the first molding layer 10 to form the package intermediate structure 1 including a plurality of first dies and second dies, the circuit layer 13 includes a rewiring layer 131, and the rewiring layer 131 electrically connects at least the second conductive portion 12b of the first electrical connection 12d and the back ground inner pad 110a of the second die 11 d.
In the present embodiment, forming the wiring layer 13 includes the following steps S41 to S42.
Step S41: a rewiring layer 131 is formed on the active surface 11a of each first die 11c, the active surface 11a of each second die 11d, the second conductive portion 12b of each first electrical connector 12d, the second conductive portion 12b of each second electrical connector 12e, and the first molding layer 10.
The rewiring layer 131 is a fan-out line (fan-out).
Step S42: conductive studs 132 are formed on the rewiring layer 131. The conductive stud 132 is the outer lead 13a.
In one alternative, step S41 of forming the rewiring layer 131 includes steps S410 to S413.
Step S410: a photoresist layer is formed on the active surface 11a of each first die 11c, the active surface 11a of each second die 11d, the second conductive portion 12b of each first electrical connector 12d, the second conductive portion 12b of each second electrical connector 12e, and the first molding layer 10.
In this step S410, in an alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film can be peeled off from the adhesive tape and applied to the active surface 11a of each first die 11c, the active surface 11a of each second die 11d, the second conductive portion 12b of each first electrical connector 12d, the second conductive portion 12b of each second electrical connector 12e, and the first molding layer 10. Alternatively, the photoresist layer may be formed by coating a liquid photoresist and then curing by heating.
Step S411: the photoresist layer is exposed and developed, and the photoresist layer is maintained in a first predetermined region, which is complementary to the region where the metal block 131a of the re-wiring layer 131 to be formed is located.
This step S411 patterns the photoresist layer. In other alternatives, other easily removable sacrificial materials may be used in place of the photoresist layer.
Step S412: the metal layer is filled in a complementary region of the first predetermined region to form a metal block 131a of the rewiring layer 131.
The metal block 131a is positioned so as to electrically connect at least the second conductive portion 12b of the first electrical connector 12d with the back ground inner pad 110a of the second die 11 d.
This step S412 may be accomplished using an electroplating process. The copper or aluminum electroplating process is mature.
Specifically, before forming the photoresist Layer in step S410, a Seed Layer (Seed Layer) may be formed on the active surface 11a of each first die 11c, the active surface 11a of each second die 11d, the second conductive portion 12b of each first electrical connector 12d, the second conductive portion 12b of each second electrical connector 12e, and the first molding Layer 10 by physical vapor deposition or chemical vapor deposition. The seed layer may serve as a power supply layer for electroplating copper or aluminum.
Step S413: ashing removes the photoresist layer remaining in the first predetermined area.
And after ashing, removing the seed crystal layer in the first preset area through dry etching or wet etching.
The metal block 131a of the re-wiring layer 131 may be planarized on the upper surface by a polishing process, for example, a chemical mechanical polishing method.
The metal blocks 131a of the rewiring layer 131 in the present step S41 are arranged according to the design requirement, and the distribution of the rewiring layers 131 on the respective first dies 11c may be the same or different, and the distribution of the rewiring layers 131 on the respective second dies 11d may be the same or different.
In some embodiments, the metal block 131a of the rewiring layer 131 may enable electrical connection of one, two, or more inner pads 110 of the first die 11 c; or to make electrical connection to one, two or more inner pads 110 of the second die 11 d; or to make electrical connection of the first die 11c with two or more inner pads 110 of the second die 11 d; or the second conductive portion 12b of the second electrical connector 12e is electrically connected, i.e., the rear surface 11b of the second die 11d is grounded with the second electrical connector 12 e.
This step S42 may include steps S420-S425.
Step S420: a photoresist layer is formed on the metal block 131a, the protective layer 111, the second conductive portions 12b of the respective first and second electrical connectors 12d and 12e, and the first molding layer 10.
In this step S420, in an alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film may be peeled off from the adhesive tape and applied to the metal block 131a, the protective layer 111, the second conductive portions 12b of the respective first and second electrical connectors 12d and 12e, and the first molding layer 10. Alternatively, the photoresist layer may be formed by coating a liquid photoresist and then curing by heating.
Step S421: the photoresist layer is exposed and developed, and the photoresist in the second preset area is reserved. The second predetermined region is complementary to a region where the conductive stud 132 is to be formed.
The second predetermined area is located such that the at least one conductive stud 132 can draw out the metal block 131a electrically connecting the second conductive portion 12b of the first electrical connector 12d with the backside ground inner pad 110a of the second die 11 d. In some embodiments, the metal block 131a that electrically connects the second conductive portion 12b of the first electrical connector 12d and the back ground inner pad 110a of the second die 11d may also not be led out through the conductive stud 132.
In addition, the second predetermined area may be located such that at least one conductive stud 132 can draw out the metal block 131a electrically connected to the second conductive portion 12b of the second electrical connector 12 e. In some embodiments, the metal block 131a of the second conductive portion 12b of the second electrical connector 12e may not be led out through the conductive stud 132.
In some embodiments, the conductive stud 132 may also enable extraction of the metal block 131a electrically connected to one, two, or more inner pads 110 of the first die 11 c; or to bring out the metal block 131a electrically connected to one, two or more inner pads 110 of the second die 11 d; or to bring out the metal blocks 131a of two or more inner pads 110 electrically connecting the first die 11c and the second die 11 d.
The photoresist layer is patterned in this step S421. In other alternatives, other easily removable sacrificial materials may be used in place of the photoresist layer.
Step S422: and filling the complementary region of the second predetermined region with a metal layer to form the conductive stud 132.
This step S422 may be accomplished using an electroplating process. The copper or aluminum electroplating process is mature. A Seed Layer (Seed Layer) may also be deposited as a power Layer prior to electroplating copper or aluminum.
Step S423: ashing removes the photoresist layer remaining in the second predetermined area.
The conductive posts 132 may be planarized by a polishing process, such as chemical mechanical polishing.
Step S424: referring to fig. 11, a second molding layer 133 embedding the conductive stud 132 is formed on the conductive stud 132, the metal block 131a, the protective layer 111, the second conductive portion 12b of each of the first and second electrical connectors 12d and 12e, and the first molding layer 10.
In one alternative, the step S424 includes: firstly, a semi-solid plastic film is attached to the conductive protruding columns 132, the metal blocks 131a, the protective layer 111, the second conductive parts 12b of the first electrical connectors 12d and the second electrical connectors 12e, and the first plastic layer 10; then, placing the structure to be molded, which is stuck with the semi-solid plastic packaging film, on a lower die body, and closing the high-temperature upper die body; when the upper die body is used for hot-pressing the plastic packaging film, the semi-solid plastic packaging film is changed into a liquid plastic packaging material, and after flowing, the plastic packaging material is continuously heated to change from a liquid state into a solid state to form a second plastic packaging layer 133; the mold is removed.
In another alternative, the second plastic layer 133 formed in the step S424 is formed by an injection molding process. Specifically, firstly, placing a structure to be molded on a lower die body, and closing a high-temperature upper die body; injecting normal-temperature liquid plastic package material into the high-temperature mold cavity; the normal temperature liquid molding compound flows while changing from liquid to solid second molding layer 133 due to heat.
The second molding layer 133 can improve electrical insulation properties between adjacent conductive studs 132 and metal blocks 131 a.
Step S425: still referring to fig. 11, the second molding layer 133 is thinned until the conductive posts 132 are exposed.
The second plastic layer 133 may be thinned by mechanical grinding, such as grinding with a grinding wheel.
In some embodiments, step S41 may include S410'-S413'.
Step S410': referring to fig. 12, a first dielectric layer 131b is formed on the active surface 11a of each first die 11c, the active surface 11a of each second die 11d, the second conductive portion 12b of each first electrical connector 12d, the second conductive portion 12b of each second electrical connector 12e, and the first molding layer 10. The material of the first dielectric layer 131b may be silicon dioxide or silicon nitride, and is formed by physical vapor deposition or chemical vapor deposition.
In step S411', a plurality of second openings are formed in the first dielectric layer 131b, and the second openings expose the inner pads 110. The second opening is a region where the metal block 131a is to be formed. The second opening may be formed by dry etching using the patterned photoresist as a mask.
In step S412', a conductive material layer is formed on the first dielectric layer 131b and in the second opening. The conductive material layer can be made of copper or aluminum, and is formed by physical vapor deposition or chemical vapor deposition.
In step S413', the conductive material layer is polished until the first dielectric layer 131b is exposed, and the conductive material layer in the second opening forms the metal block 131a.
In still other embodiments, two or more rewiring layers 131 may be formed.
In some embodiments, step S42 may include S420'-S422'.
Step S420': referring to fig. 12, conductive studs 132 are formed on the metal block 131a and the first dielectric layer 131b (or the protective layer 111, the second conductive portions 12b of the respective first and second electrical connectors 12d and 12e, and the first molding layer 10).
Step S421': a second dielectric layer 132b is formed on the conductive studs 132 and between adjacent conductive studs 132. The second dielectric layer 132b may be silicon dioxide or silicon nitride, and is formed by physical vapor deposition or chemical vapor deposition. In some embodiments, the material of the second dielectric layer 132b may also be a molding compound, such as epoxy.
In step S422', the second dielectric layer 132b is polished until the conductive bump 132 is exposed.
In other embodiments, a second dielectric layer 132b is formed between adjacent conductive pillars 132, and an upper surface of the second dielectric layer 132b is flush with an upper surface of the conductive pillar 132, and the second dielectric layer 132b is made of an organic material. The organic material may be polyimide with good fluidity, and is cured after heating.
In still other embodiments, a second molding layer 133 is formed over the conductive studs 132 and between adjacent conductive studs 132, and the second molding layer 133 is thinned until the conductive studs 132 are exposed.
In still other embodiments, a second dielectric layer 132b is formed on the metal block 131a, the second conductive portion 12b of each of the first electrical connector 12d and the second electrical connector 12e, and the first molding layer 10, a third opening exposing the metal block 131a is formed in the second dielectric layer 132b, a conductive material is filled in the third opening, and the conductive material is polished until the second dielectric layer 132b is exposed. The conductive material filled in the third opening forms a conductive stud 132.
a) In an alternative, referring to fig. 11 and 12, the conductive stud 132 is an outer lead 13a.
b) Alternatively, referring to fig. 13, after the conductive stud 132 is exposed, a second oxidation preventing layer 134 is further formed on the conductive stud 132.
The second oxidation resistant layer 134 may include: b1 Tin layer, or b 2) nickel layer and gold layer stacked from bottom to top, or b 3) nickel layer, palladium layer and gold layer stacked from bottom to top. The second oxidation resistant layer 134 may be formed using an electroplating process. The conductive bump 132 may be made of copper, and the second oxidation resistant layer 134 may prevent copper oxidation, thereby preventing deterioration of electrical connection performance caused by copper oxidation.
c) Optionally, after exposing the conductive bump 132, a solder ball is further formed on the conductive bump 132 for flip-chip mounting the chip package structure 1a (see fig. 1).
After the outer leads are formed, the second support plate 4 is removed as shown with reference to fig. 14.
The second support plate 4 may be removed by conventional removal methods such as laser lift-off and UV irradiation.
Thereafter, referring to step S5 in fig. 3, fig. 14 and fig. 1, the chip package intermediate structure 1 is cut to form a plurality of chip package structures 1a, and each chip package structure 1a includes a first die 11c and a second die 11d.
Fig. 15 is a schematic cross-sectional structure of a chip package structure according to a second embodiment of the present invention. Referring to fig. 15, the chip package structure in this embodiment is substantially the same as the chip package structure 1a in fig. 1, except that: the first conductive portions 12a of the first and second electrical connectors 12d and 12e are exposed outside the chip package structure 1 a. The advantages are that: the heat dissipation performance of the chip is improved, continuous and efficient operation of the chip can be guaranteed, and the problem of service life influence caused by overheating of the chip is solved.
A first oxidation preventing layer 121 may be disposed on the first conductive part 12a of the first and/or second electrical connector 12d and/or 12e exposed outside the first molding layer 10. The material of the first oxidation preventing layer 121 refers to the material of the second oxidation preventing layer 134.
Accordingly, the method for manufacturing the chip package structure in this embodiment is substantially the same as that of fig. 1 to 14, and the only difference is that: in step S3, the first molding layer 10 is thinned until the first conductive portions 12a of the first and second electrical connectors 12d and 12e are exposed.
In step S4, after the second support plate 4 is removed, a first oxidation preventing layer 121 may be further formed on the exposed first conductive portion 12 a. The material and the forming method of the first oxidation preventing layer 121 refer to the material and the forming method of the second oxidation preventing layer 134.
Fig. 16 is a top view of a first electrical connector or a second electrical connector in a chip package structure according to a third embodiment of the present invention. Referring to fig. 16, the chip package structure in this embodiment is substantially the same as the chip package structure 1a in fig. 1, except that: the connection portion 12c of the first electrical connector 12d and the second electrical connector 12e is partially removed and has an H-shape. In the thermal expansion and contraction processes of the first electrical connector 12d, the second electrical connector 12e and the first plastic sealing layer 10, the removed area of the connecting portion 12c can provide a deformation accommodating space. Preferably, the first conductive portion 12a has a size larger than that of the second conductive portion 12 b.
Accordingly, the method for manufacturing the chip package structure in this embodiment is substantially the same as that of fig. 1 to 15, and the only difference is that: in step S2, the connection portion 12c of the first electrical connector 12d and the second electrical connector 12e is provided with a portion of the material removed, and is H-shaped. The removal of portions of material may be formed by at least one of cutting, stamping, etching, embossing.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (20)
1. A chip package structure, comprising:
a first die and a second die, each of the first die and the second die including opposing active and back surfaces, the active surfaces having an inner pad and a protective layer, the protective layer exposing a partial region of the inner pad; the inner pads of the second die include at least one back-grounded inner pad;
the first electric connecting piece and the second electric connecting piece comprise a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part; the first conductive portion of the first electrical connector is electrically connected to a back side of the first die; the first conductive portion of the second electrical connector is electrically connected to a back side of the second die;
A first plastic layer coating the first die, the second die, the first electrical connector and the second electrical connector, wherein the first conductive part, the second conductive part, the active surface of the first die and the active surface of the second die of the first electrical connector are exposed outside the first plastic layer;
the circuit layer is located on the active surface of the first bare chip, the active surface of the second bare chip, the second conductive part of the first electric connector, the second conductive part of the second electric connector and the first plastic sealing layer, and comprises a rewiring layer which is at least electrically connected with the second conductive part of the first electric connector and at least one back grounding inner bonding pad of the second bare chip.
2. The chip package structure according to claim 1, wherein the first electrical connector is H-shaped and/or the second electrical connector is H-shaped.
3. The chip package structure of claim 1, wherein a conductive layer is disposed on a back surface of the first die and/or a conductive paste is disposed between the first conductive portion of the first electrical connector and the back surface of the first die; and/or
A conductive layer is disposed on the back side of the second die, and/or a conductive adhesive is disposed between the first conductive portion of the second electrical connector and the back side of the second die.
4. The chip package structure of claim 1, wherein a first oxidation resistant layer is provided on a first conductive portion of the first electrical connector exposed outside the first plastic package layer; and/or a first oxidation resistant layer is arranged on the first conductive part of the second electric connector exposed outside the first plastic package layer.
5. The chip package structure of claim 1, wherein the wiring layer comprises an outer pin; and the rewiring layer is provided with a conductive convex column, and the conductive convex column is the outer pin.
6. The chip package structure of claim 5, wherein the conductive bump has a second oxidation resistant layer thereon.
7. The chip package structure of claim 1, wherein the wiring layer comprises an outer pin; the rewiring layer is provided with a conductive convex column, the conductive convex column is provided with a solder ball, and the solder ball is the outer pin.
8. The chip package structure of claim 1, wherein the rewiring layer comprises more than two layers.
9. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:
providing a carrier plate, a plurality of first bare chips and a plurality of second bare chips, wherein each of the first bare chips and the second bare chips comprises an opposite active surface and a back surface, the active surface is provided with an inner bonding pad and a protective layer covering the inner bonding pad, and the inner bonding pad of the second bare chip at least comprises one back grounding inner bonding pad; fixing the active surfaces of the first bare chips and the second bare chips on the carrier plate;
providing a plurality of first electric connectors and a plurality of second electric connectors, wherein the first electric connectors and the second electric connectors comprise a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part; each first electric connector is arranged on each first bare chip, each second electric connector is arranged on each second bare chip, a first conductive part of each first electric connector is electrically connected to the back surface of each first bare chip, a second conductive part of each first electric connector is arranged on the surface of the carrier plate, a first conductive part of each second electric connector is electrically connected to the back surface of each second bare chip, and a second conductive part of each second electric connector is arranged on the surface of the carrier plate;
Forming a first plastic sealing layer which is used for embedding each first bare chip, each second bare chip, each first electric connecting piece and each second electric connecting piece on the surface of the carrier plate; removing the carrier plate;
forming a wiring layer on the active surface of each first die, the active surface of each second die, the second conductive portion of each first electrical connector, the second conductive portion of each second electrical connector, and the first molding layer to form a package intermediate structure comprising a plurality of first dies and second dies, the wiring layer comprising a rewiring layer electrically connecting at least the second conductive portion of the first electrical connector and at least one of the back ground inner pads of the second dies;
and cutting the packaging intermediate structure to form a plurality of chip packaging structures, wherein each chip packaging structure comprises the first bare chip and the second bare chip.
10. The method of claim 9, wherein the first plurality of electrical connectors and the second plurality of electrical connectors are disposed on a first support plate.
11. The method for manufacturing a chip package structure according to claim 9, wherein the first electrical connector is H-shaped and/or the first electrical connector is formed by at least one of cutting, stamping, etching, and embossing; and/or
The second electrical connector is H-shaped and/or the second electrical connector is formed by at least one of cutting, stamping, etching, embossing.
12. The method of manufacturing a chip package structure according to claim 9, further comprising: and forming a first oxidation resistant layer on the first conductive parts of the first electric connecting pieces and the second electric connecting pieces exposing the first plastic sealing layer.
13. The method of manufacturing a chip package structure according to claim 9, wherein forming a circuit layer on the active surface of each of the first dies, the active surface of each of the second dies, the second conductive portion of each of the first electrical connectors, the second conductive portion of each of the second electrical connectors, and the first molding layer comprises:
forming the rewiring layer on the inner bonding pads of the first and second dies, the protective layer, the first plastic sealing layer between the first and second dies, and the second conductive parts of the first and second electrical connectors;
and forming a conductive stud on the rewiring layer.
14. The method of claim 13, wherein the rewiring layer comprises more than two layers.
15. The method of manufacturing a chip package structure according to claim 13, further comprising: and forming a solder ball on the conductive convex column, wherein the solder ball is an outer pin.
16. The method of manufacturing a chip package structure according to claim 13, further comprising: and forming a second oxidation resistance layer on the conductive convex column.
17. The method of claim 13, wherein forming conductive studs on the rewiring layer comprises:
forming a conductive stud on the metal block of the rewiring layer;
forming a second dielectric layer on the conductive convex columns and between the adjacent conductive convex columns, wherein the second dielectric layer is made of inorganic materials;
polishing the second dielectric layer until the conductive posts are exposed;
or comprises:
forming a conductive stud on the metal block of the rewiring layer;
forming a second dielectric layer between adjacent conductive convex columns, wherein the upper surface of the second dielectric layer is flush with the upper surface of the conductive convex column, and the second dielectric layer is made of an organic material;
or comprises:
forming a second dielectric layer on the rewiring layer;
forming a plurality of third openings in the second dielectric layer, the third openings exposing the metal blocks of the rewiring layer;
Forming a conductive material layer on the second dielectric layer and in the third opening;
polishing the conductive material layer until the second dielectric layer is exposed, wherein the conductive material layer in the third opening forms a conductive convex column;
or comprises:
forming a conductive convex column on the metal block of the rewiring layer, and forming a second plastic sealing layer embedding the conductive convex column on the rewiring layer;
and thinning the second plastic sealing layer until the conductive convex columns are exposed.
18. The method of manufacturing a chip package according to claim 9, wherein a conductive layer is disposed on a back surface of the first die, and/or a conductive paste is disposed between the first conductive portion of the first electrical connector and the back surface of the first die; and/or
A conductive layer is disposed on the back side of the second die, and/or a conductive adhesive is disposed between the first conductive portion of the second electrical connector and the back side of the second die.
19. The method of claim 18, wherein the conductive paste comprises a nano-copper/conductive polymer composite.
20. The method of manufacturing a chip package according to claim 9, wherein in the step of fixing the active surfaces of the first die and the second die to the carrier, the protection layer of the first die and/or the second die has a first opening exposing the inner pad; or forming a first opening exposing the inner pad in the protective layer of each first die and/or each second die in the step of forming a line layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020055687A (en) * | 2000-12-29 | 2002-07-10 | 마이클 디. 오브라이언 | Semiconductor package |
| CN110729258A (en) * | 2019-03-11 | 2020-01-24 | Pep创新私人有限公司 | Chip packaging method and chip structure |
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| US9691706B2 (en) * | 2012-01-23 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip fan out package and methods of forming the same |
| US9331029B2 (en) * | 2014-03-13 | 2016-05-03 | Freescale Semiconductor Inc. | Microelectronic packages having mold-embedded traces and methods for the production thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020055687A (en) * | 2000-12-29 | 2002-07-10 | 마이클 디. 오브라이언 | Semiconductor package |
| CN110729258A (en) * | 2019-03-11 | 2020-01-24 | Pep创新私人有限公司 | Chip packaging method and chip structure |
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