CN101740551A - Laminated die package structure for semiconductor element and method thereof - Google Patents
Laminated die package structure for semiconductor element and method thereof Download PDFInfo
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- CN101740551A CN101740551A CN200810173898A CN200810173898A CN101740551A CN 101740551 A CN101740551 A CN 101740551A CN 200810173898 A CN200810173898 A CN 200810173898A CN 200810173898 A CN200810173898 A CN 200810173898A CN 101740551 A CN101740551 A CN 101740551A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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Abstract
The invention discloses a multi-die package structure for a semiconductor element and a method thereof. The structure comprises a substrate, a first layer of semiconductor dies, a second layer of contact pad and a conductive bump, wherein the substrate is provided with die receiving windows and inter-connecting through holes therein; the first layer of semiconductor dies are formed below a second layer of semiconductor dies through frames arranged back to back and are placed into the die receiving windows, wherein the first multi-die package contains a first layer of contact pad which is formed below the first layer of semiconductor dies, and the first layer of semiconductor dies are provided with a first build up layer which is formed under the first layer of semiconductor dies and is coupled to a first bonding pad of the first layer of semiconductor dies; the second layer of contact pad is formed on the second layer of semiconductor dies, wherein the second layer of semiconductor dies are provided with a second build up layer which is formed on the second layer of semiconductor dies and is coupled to a second bonding pad of the second layer of semiconductor dies; and the conductive bump is formed under the first build up layer.
Description
Technical field
The present invention relates to a kind of semiconductor packages, also particularly, is a kind of laminated die package structure and method thereof that is used for semiconductor element.
Background technology
Integrated circuit crystal grain (dice) or chip (chips) are small-sized, general rectangle integrated circuit component be by as the semiconductor wafer cutting that is shaped on multiple integrated circuit component on it such as silicon wafer form.Traditionally, the naked crystal grain of integrated circuit can be packed to protect them not corrode (corrosion) phenomenon, and it is by they are sealed in the die package material.So integrated circuit crystal grain can be effectively protected in encapsulation, but its structure is excessive for some multicore sheet application that needs the compact-grain encapsulation.Therefore industrial demand is being ordered about the integrated circuit encapsulation and is constantly being improved, increase its heat radiation with electrical aspect performance, and reduce its size and manufacturing cost.In the semiconductor element field, its component density constantly increases and size is constantly dwindled.For in response to above-mentioned situation, in highdensity element like this, for the also increase thereupon of demand of encapsulation or interconnection technique.Solder projection (solder bump) can form by using scolder (solder) composite material.Industry has known that to cover crystalline substance (flip-chip) technology be the technology that a kind of substrate with crystal grain and assembling electrically connects, for example printed circuit board (PCB) (printed wiring board, PWB).The function of Chip Packaging comprises electrical distribution, signal distributions, heat radiation, protection and support etc.Along with the semiconductor more sophisticated that becomes, traditional encapsulation technology for example leaded package (lead frame package), soft encapsulation (flex package) and hard encapsulation (rigid package) waits and can't reach the requirement that production has the high density components small chip.Generally speaking, the array encapsulation, for example (ball grid array BGA) is packaged in relative package surface zone highdensity interconnection can be provided ball grid array.General ball grid array packages contains (convoluted) signal path that circles round that can cause high impedance, and its inefficient hot path can cause disappointing heat dispersion.Along with the increase of packaging density, the heat radiation of element becomes more and more important.In order to reach the encapsulation requirement of new generation electronic product, industry has paid that many effort exploitations are reliable, cost benefit is high, volume is little and high performance encapsulation.Its demand be as: lower delay that electronic signal propagates, lower integral member area and I/O connection gasket layout freely also.
Recently, integrated circuit (chip) encapsulation technology has become the also bottleneck of high-performance package integrated circuit of development.Because the microminiaturized demand of component package, (multi-chips module MCM) has been commonly used in component package and electronic component multi-chip module.Usually the multi-chip module encapsulation mainly comprises at least two Chip Packaging in wherein, to promote the electrical performance of its encapsulation.
As shown in Figure 6, a kind of multicore sheet encapsulation is disclosed in No. the 20040070083rd, the U.S. Patent Publication.It is a kind of lamination chip package, comprises two chip carriers (carrier), and two carriers all contain at least one chip and a plurality of solder projection and are formed on the significant surface (active surface) that chip and chip carrier electrically connect.One first chip carrier is connected in back-to-back mode with one second chip carrier, and it is coated on the non-significant surface (inactive surface) of first chip on this first chip carrier via an insulating binder (insulating adhesive) and the non-significant surface of second chip on second chip carrier is reached.Two non-significant surfaces are joined together and form a multi-chip module.The end face of this multi-chip module and bottom surface all can electrically connect with other element, therefore can get rid of in the Flip Chip about the partial impairment of vertical stack chip, also can increase the elasticity that the encapsulating structure chips is arranged.
Fig. 6 is a kind of cross sectional view of covering brilliant semiconductor package in the prior art more.This preferred embodiment of covering brilliant semiconductor packages almost identical with aforementioned first embodiment more, and unique difference is among this embodiment described at least two multi-chip modules of previous embodiment to be carried out vertical stack.Because multi-chip module 2 ' is to connect first chip carrier 20 ' and second chip carrier 23 by back-to-back mode " form, can form a plurality of connection gaskets 203 ' and 233 ' on the end face 230 ' of this multi-chip module 2 ' and the bottom surface 200 ' and come to electrically connect with other multi-chip module or other element.As shown in the figure, the multi-chip module of this prior art also comprises upper strata multi-chip module 2 ' and lower floor's multi-chip module 2 "; its at the middle and upper levels first chip carrier 20 ' of multi-chip module 2 ' be to electrically connect by a plurality of solder projections 28 and lower floor's multi-chip module 2 " second chip carrier 23 "; therefore; can allow Chip Packaging among multi-chip module 2 ' to electrically connect with lower floor multi-chip module 2 " first substrate 20 ", electrically connect with outer member by being arranged at first chip carrier 20 " a plurality of solder ball at the back side (solder ball) 29 " more afterwards.
Therefore because the project organization of prior art contains the dielectric layer (dielectric layer) and the sealed compound (sealed compound) of too much lamination, its thermal diffusivity extreme difference has lowered the performance of this class component.The engineering properties of these dielectric layers is non-to be " elasticity/soft ", therefore can cause thermal coefficient of expansion (coefficient of thermal expansion, the problem that CTE) does not conform to, but wherein lack the resilient coating of release pressure.Its design architecture and unreliable under thermal cycle (thermal cycle) that encapsulates and running.Moreover it is the design of unidimensional crystal grain, and internal core does not comprise glass fibre (fiber glass), and the technology of its through-hole interconnection is too complicated.
Therefore, the invention provides a kind of encapsulating structure, can overcome above-mentioned problem, and preferable element function is provided.
Summary of the invention
A purpose of the present invention is to provide a kind of semiconductor element encapsulation (chip assembling), and it comprises chip and conducting wiring, and the encapsulating structure of a kind of low cost, high-performance and high-reliability can be provided.
Another object of the present invention is to provide a kind of laminated construction that is used for semiconductor element.
Another object of the present invention is to provide a kind of convenience, low cost method to make the encapsulation of multichip semiconductor crystal grain.
On the one hand, the present invention proposes a kind of first polycrystalline grain encapsulating structure that is used for semiconductor element, and it comprises and a kind ofly has die receiving pane (die receiving window) and through-hole interconnection (inter-connecting through holes) is formed at substrate wherein; One ground floor semiconductor grain, it is formed under the second layer semiconductor grain by back-to-back mode and places in the die receiving pane, wherein this first polycrystalline grain encapsulation contains the ground floor contact mat that is formed under the ground floor semiconductor grain, wherein this ground floor semiconductor grain has one first and increases layer (build up layer BUL) is formed at it down to be coupled first joint sheet (bondingpad) of ground floor semiconductor grain so far; One second layer contact mat is formed on this second layer semiconductor grain, and it is formed thereon that wherein this second layer semiconductor grain has a second layer enhancement layer, with second joint sheet of second layer semiconductor grain so far that is coupled; And form conductive projection under this ground floor enhancement layer, with the ground floor contact mat (contact pad) so far that is coupled.
A kind of method that forms polycrystalline grain encapsulating structure, the significant surface that comprises second crystal grain (with the wafer form) pastes at second adhesive tape (second tape), and first crystal grain (wafer form) back side pasted at first adhesive tape (have on the band-crystal grain adhesive film (die attached film, DAF)) of crystal grain adhesion material.Then during being provided with, first adhesive tape (having the crystal grain adhesive film) can be chosen and be placed (pick and place) step crystal grain is placed the have alignment patterns second adhesive tape back side of (alignment pattern), and its alignment patterns is to be used for reaching accurate contraposition in put procedure.Thereafter, crystal grain sticky material can be cured (cured).The crystal grain adhesive film preferably comprises following ingredients: (1) epoxy resin (epoxy resin) and phenol resin (phenol resin); (2) acrylic rubber (acrylicrubber) and (3) silicon filler.The function of epoxy resin and phenol resin is that thermal endurance is good and have the character of low thermal coefficient of expansion; The function of acrylic rubber is for reducing pressure; And the function of silicon filler is that adhesion strength is good.Therefore, this crystal grain adhesive film can have higher heat-resisting reflow (reflowresistance), preferable temperature cycling test (temperature cycling test, TCT) resistive and higher adhesion strength.The size of silicon particle is lower than one micron (micron-meter) in the silicon filler.The percentage by weight of silicon filler then is lower than 10.
First crystal grain and second crystal grain are to pick out to be positioned in the crystal grain configuration tool (die placement tool) from the chip that cut, and the significant surface of second crystal grain is drawn on the crystal grain place tool.Next step is then aimed at first crystal grain and second crystal grain for the substrate that will have the die receiving pane, and adheres on the crystal grain place tool by viscose glue.Wherein this substrate contains through-hole interconnection; One core paste (core paste) material is formed in the gap between first crystal grain, second crystal grain and the die receiving pane sidewall edge; One side tabular (panel) wafer adheres on the crystal grain place tool.Next then be that first time dielectric layer is coated on the significant surface of first crystal grain, and expose first joint sheet and first contact mat (being connected to through-hole interconnection) of substrate.Once (redistribution layer RDL) is coupled to first joint sheet to the rerouting layer; One second time dielectric layer is formed at down on the heavy distribution layer and exposes first contact mat to form the first bottom bump metal (under bump metal, UBM) structure; Viscose glue can be eliminated with crystal grain configuration tool and panel shape wafer-separate afterwards, then clears up the significant surface of second crystal grain; The formation of one first upper dielectric layer is also exposed second joint sheet of second crystal grain and second contact mat of substrate; The rerouting layer forms and comes therewith the coupling of second joint sheet on one, and forms one second upper dielectric layer and expose its second contact mat to form the second bottom bump metal structure.
The method also comprises the step that forms an isolation base portion (isolation base), and it has sticky material and overlays on (second upper dielectric layer is replaceable to be sticky material) on the rerouting layer and/or second upper dielectric layer, then this is isolated base portion and solidifies.After from the crystal grain place tool, separating, use a carrier to support this panel wafer, and rerouting layer under before first upper dielectric layer forms, protecting.It also is included in and increases on first after layer formation, from the step that carrier separates panel, then clears up its lower surface, and execution tin ball is provided with action formation conductor ball.Second panel can be aimed at and place and make ball grid array contact with the melt of bottom bump metal on first plate, then imposes the interconnection structure in the reflow step formation stacked package.
Description of drawings
Fig. 1 has represented according to the present invention the cross sectional view of semiconductor Chip Packaging;
Fig. 2 has represented the cross sectional view according to the semiconductor Chip Packaging of the embodiment of the invention;
Fig. 3 has represented the cross sectional view according to the semiconductor Chip Packaging of the embodiment of the invention;
Fig. 4 has represented the cross sectional view according to the semiconductor Chip Packaging of the embodiment of the invention;
Fig. 5 has represented the cross sectional view according to another embodiment of the present invention semiconductor Chip Packaging;
Fig. 6 has represented the cross sectional view according to the prior art semiconductor die package.
[main element symbol description]
Covering brilliant semiconductor packages 2 more
2 ' multi-chip module
2 " multi-chip modules
The 2a chip
The 2b chip
The 2c chip
The 2n chip
4 sand core glueing materials
6 core substrates
8 through-hole interconnections
10 chip sticky materials
The 12b joint sheet
(second) rerouting layer under the 14a
14b rerouting layer
16a the 3rd dielectric layer
16b first dielectric layer
18a the 4th dielectric layer
18b second dielectric layer
Isolated base on 20
20 ' first chip carrier
20 " first substrate
22 conductive projections
23 second chip carriers
23 " second chip carrier
24a contacting metal pad
24b contacting metal pad (first contact mat)
28 solder bumps
29 " solder ball
40 scolding tin (conduction) projection
42 encapsulation
44 encapsulation
50 substrates
52 chips hold pane
54 through-hole interconnections
Contact mat on 56
58 times contact mats
Increase layer on 60
Increase layer 62 times
200 ' bottom surface
203 ' joint sheet
230 ' end face
233 ' joint sheet
Embodiment
The present invention will do also detailed explanation with preferred embodiment and the diagram of following.Yet, should be appreciated that preferred embodiment of the present invention is only in order to illustrate.Except preferred embodiment referred in this, the present invention can have other execution mode widely, and is not only the execution mode of clearly describing at this.And scope of the present invention is not limited to other specific expression mode, only based on the claim scope.
The present invention discloses a kind of multilayer encapsulation (multi-package) structure that is used for semiconductor device.The invention provides a kind of semiconductor chip combination, it comprises as Fig. 1 to various chips shown in Figure 5.The main element and the structure of each individual package are roughly the same.Embodiment will be described in the rear.
This encapsulation comprises at least two chip 2a and 2b, and it is centered on by sand core glueing material 4, and embeds among the core substrate 6, and it has the through-hole interconnection 8 of penetrator core substrate 6.The sand core glueing material 4 that centers on is formed between the sidewall of chip 2a and 2b.This sand core glueing material 4 can be used as resilient coating, to discharge thermal stress (thermal stress).Must notice that these chips are to carry out lamination by chip sticky material 10 with the configuration of back-to-back mechanism, as so-called " crystal grain adhesive film-B stage adhesive tape (DAF-B stage tape) ".In an example, the chip 2a of lower floor puts upside down to be formed under the chip 2b.Its top is meant the significant surface with joint sheet.Crystal grain sticky material 10 invests the below of chip 2b, and it can have elasticity can absorb thermogenetic thermal stress.
Through-hole interconnection 8 is to be coupled to the joint sheet 12b of chip 2b by rerouting layer 14b.Increase layer 60 on one and be formed on chip 2b and the sand core glueing material 4, and form rerouting layer 14b.Lower surface also forms and increases layer 62.On increase layer 60 and comprise one first dielectric layer 16b and be formed on the chip 2b, and descend (first) rerouting layer 14b to be formed on the first dielectric layer 16b.The first dielectric layer 18b is overlying on (first) rerouting layer 14b.Isolated base 20 optionally is formed on second dielectric layer 18, to be used for laser labelling on one.Similarly, increase layer 62 down and be formed on chip 2a and the sand core glueing material 4 thereof, and form rerouting layer 14a.Under increase layer and 62 comprise one the 3rd dielectric layer 16a, it is formed at down on chip 2a and time (second) rerouting layer 14a, to form the 3rd dielectric layer 16a.The 4th dielectric layer 18a overlays on down on (second) rerouting layer 14a.This 4th dielectric layer 18a has opening exposed portions serve rerouting layer 14a, and conductive projection 22 then forms on this opening, to be connected to rerouting layer 14a (being bottom bump metal structure, not expression among the figure).
One first contact mat (bottom bump metal structure, not expression among the figure) 24b and one second contact mat 24a are connected with two ends of through-hole interconnection 8 respectively.The first contact mat 24b is formed under the rerouting layer 14b, and aims at through-hole interconnection 8 respectively.The second contact mat 24a is formed at down on the rerouting layer 14a, and is aligned to through-hole interconnection 8 respectively.Contacting metal pad 24a and 24b can be copper/nickel/gold pad or other metal gasket.
An embodiment on Fig. 2 is similar for second embodiment of the invention.This embodiment has omitted the isolated base position and has contained the top contact pulvilliform and has been formed among the second dielectric layer 18b, and it comprises bottom bump metal structure.
In addition, this embodiment also can comprise two encapsulation units of first embodiment, and encapsulates in (side-by-side) framework mode arranged side by side shown in Figure 3, and it has also comprised crystal grain 2a, 2b, 2c and 2n in the column structure.
In addition, crystal grain can be the crystal grain multi-form with other.For example, its can be memory, image sensor in CMOS (CMOS Image Sensor), microcontroller (Mirco-Controller Unit, MCU), radio frequency (radio frequency, RF), simulation and/or passive device etc.
Please refer to Fig. 4, it is to constitute by plural encapsulation unit among first embodiment, and scolding tin (conduction) projection 40 of its upper strata encapsulation 44 is to encapsulate rerouting layer coupling on 42 with lower floor.In addition, its isolated base can be formed on the upper unit.
The size of crystal grain can diminish with upper strata to lower floor among the embodiment.This chip size is more little, and the shared zone of sand core glueing material is big more.Under this architecture design, the nuclear glue of lower floor's crystal grain zone is its maximum, folds the encapsulating structure that carries the upper strata to strengthen its mechanical support.
Fig. 5 has illustrated substrate 50 structures of the present invention.Substrate 50 comprises preformed die receiving pane (opening) 52 and is pre-formed through-hole interconnection 54 in substrate 50. Contact mat 56 and 58 was formed at two ends of through-hole interconnection 54 respectively under last contact mat reached.
Crystal grain is to be arranged to laminated construction among the embodiment, and it is by with the welding of metal interconnect structure or get out the mode that through hole forms conductive interconnecting structure again and come to carry out the lamination of package panel.Its panel level final test (panel level final testing) is applicable to various panel constructions, and each package panel all can adopt the panel level packaging technology with diffusion/fan-out structure.But it also provides a kind of repair structure (repairable), can repair by going weldering (de-soldering) step.Passive device is that (surface mount technique SMT) is stacked in the top by the surface adhering technology among the embodiment.Being set up in parallel framework is feasible design.Because each encapsulating structure has identical thermal coefficient of expansion (using identical nuclear glue material-bismaleimides triazine resin or FR5) with printed circuit board (PCB), so the present invention can provide better reliability degree (reliability).Its resilient coating and dielectric layer have elasticity can discharge thermal stress between silicon and the printed circuit board substrate/bismaleimides triazine resin.This design is applicable to good naked crystalline substance (known good die, KGD) technology (promptly choosing the step of non-defective unit).The present invention is " green encapsulation " design of environmental protection.
The invention provides a kind of method that forms polycrystalline grain encapsulating structure, it comprises significant surface with second crystal grain (wafer form) and sticks on one second adhesive tape and the first crystal grain back side is sticked on one first adhesive tape (band with crystal grain adhesive film structure).Then, during being provided with, the crystal grain on this first adhesive tape (having the crystal grain adhesive film under its first crystal grain back side) is chosen and is placed on the back side of second crystal grain with alignment patterns, to reach the requirement of accurate aligning.Then, the crystal grain sticky material is cured and makes crystal grain and intergranule (back-to-back) fixing and make two crystal grain bonded to each other.
First crystal grain and second crystal grain (being bonded together in back-to-back mode) are to pick out to be positioned over that crystal grain configuration tool (having alignment patterns and graphical glue material) is gone up and the significant surface of second crystal grain is drawn to the crystal grain place tool from the wafer (forming second wafer) after the cutting.Next step will be for will have in the substrate and first crystal grain and the second crystal grain configuration tool of die receiving pane, and wherein this substrate comprises through-hole interconnection; Sand core gummed (die attach) material is to be formed in the space between first crystal grain, second crystal grain and the die receiving pane sidewall edge.Then on the significant surface of first crystal grain, be coated with one first time dielectric substance layer, and expose first joint sheet and suprabasil first contact mat.Rerouting layer coupling once be first joint sheet so far; One second time dielectric layer then is formed at down on the rerouting layer, and exposes the first scolding tin contact mat to form the first bottom bump metal layer structure; Remove viscose glue so that panel shape wafer can be separated from the crystal grain place tool, and then clear up the significant surface of second crystal grain; The formation of one first upper dielectric layer is also exposed second joint sheet of second crystal grain and second contact mat of substrate; The rerouting layer forms second joint sheet so far that is coupled on one, and one second upper dielectric layer forms and exposes the second scolding tin contact mat to form the second bottom bump metal structure.
Proposed to form the other method of crystal grain laminated construction in the embodiment of the invention, it comprises the first crystal grain configuration tool of preparing to have alignment patterns and figure glue (can be heat conduction adhesive tape or ultraviolet tape), grind (lapping) and cut this first wafer (becoming crystal grain), and selection with place first crystal grain (non-defective unit), be to place and stick on the figure glue of crystal grain configuration tool (note: the back side of first crystal grain is bonded at the die attach material band of die attach film) with its significant surface.Next step is also aimed at by special alignment targets (alignment target) for this first crystal grain configuration tool (being equipped with first crystal grain on it) of counter-rotating and connects the second crystal grain place tool (at this moment, the back side of first crystal grain is bonded at the back side of second crystal grain), then, solidify crystal grain sticky material on this crystal grain adhesive film.Next step is the figure glue of removing on the first crystal grain place tool (it can be removed by heat or ultraviolet light).The similar abovementioned steps of following step: place substrate, insert increase under sand core glueing material, curing schedule, the formation layer and on increase layer etc.
The method also comprises the step that forms isolated base, and it has sticky material and is overlying on rerouting layer and/or second upper dielectric layer (second upper dielectric layer is replaceable to be to isolate hypobasal sticky material), then then for solidifying the isolation base portion.In case the panel wafer separates from the crystal grain configuration tool, promptly use a carrier to be supported, and rerouting layer under before forming first upper dielectric layer, protecting.It also is included in and forms on first after the enhancement layer, and the step of separate package panel is then cleared up lower surface and carried out tin ball action of configuration, to form conductor ball under the bottom bump metal from the carrier.The second panel wafer is to aim at and place on the first tabular wafer, makes ball grid array can contact the bottom bump metal of fusion, carry out again the reflow step with form in the stacked package interconnection structure.
The method also comprises the step of cutting package panel from Cutting Road (scribe lines), to separate this encapsulation.Its rerouting layer (be arranged in and increase layer) is by seed metal (seed metal) or photoresist (photoresist, PR) sputter forms the rerouting layer pattern, again via electro-coppering/nickel/gold (or copper/gold), go photoresist, and the wet etching steps such as (wet etching) of seed metal form the conducting wiring (trace) of weight distribution layer.
The present invention is at temperature cycling test, can provide preferable reliability in drop shutter test (drop test) and the soldered ball shearing experiment (ballshear test), because its core base material, the character of isolated base and core base material are to conform to the thermal coefficient of expansion of printed circuit board (PCB) with the thermal coefficient of expansion (isolated base and substrate are good with the material that contains polyimides or bismaleimides triazine resin) of isolated base, moreover, its sand core glueing material and have increasing layer and can absorbing the thermal and mechanical stress that produces between silicon and core substrate during the thermal cycle of elasticity/extension character.
Because isolated base (bismaleimides triazine resin/FR5/FR4/ polyimides etc.) inside has glass fibre, its intensity is higher than the dielectric layer of top, and therefore, it can be avoided increasing layer and be subjected to outside destroy, particularly in the zone at encapsulating structure edge.Be easy to carry out also changing of solder ball/projection between recasting (rework) step: because have isolated base, normal tin ball recasting step can't be damaged the upper surface of encapsulation.
Though preferred embodiment of the present invention is proposed explanation, and the skilled persons will of this area should be understood the present invention and be not limited to described preferred embodiment.In fact, can carry out various changes and correction to the present invention, and still not break away from its spirit and category, it should be defined by the claim scope.
Claims (12)
1. a polycrystalline grain encapsulating structure that is used for semiconductor element is characterized in that, comprises:
One substrate has die receiving pane and through-hole interconnection and forms wherein;
One ground floor semiconductor grain, it is to be formed at second layer semiconductor grain below and to place in this die receiving pane by back-to-back mode, wherein the encapsulation of this polycrystalline grain comprises the ground floor contact mat and is formed under this ground floor semiconductor grain, and this ground floor semiconductor grain has one first and increases layer and be formed at it down to be coupled to one first joint sheet of this ground floor semiconductor grain; One second layer contact mat is formed on this second layer semiconductor grain, wherein this second layer semiconductor grain have one second increase the layer formed thereon to be coupled to second joint sheet of this second layer semiconductor grain; And
Conductive projection is formed at this and first increases under the layer, in order to be coupled to this ground floor contact mat.
2. the polycrystalline grain encapsulating structure that is used for semiconductor element as claimed in claim 1, it is characterized in that, this first increases layer and comprises one and have the sandwich of dielectric layer/rerouting layer/dielectric layer, and also comprises bottom bump metal structure and be formed at this and first increase in the layer, with this rerouting layer that is coupled.
3. the polycrystalline grain encapsulating structure that is used for semiconductor element as claimed in claim 1, wherein this second increases layer and comprises a sandwich structure with dielectric layer/rerouting layer/dielectric layer, it is characterized in that, and also comprise bottom bump metal structure and be formed at this and first increase in the layer, with this rerouting layer that is coupled.
4. the polycrystalline grain encapsulating structure that is used for semiconductor element as claimed in claim 1 is characterized in that, first to increase layer be to be coupled to this via through-hole interconnection second to increase layer for this.
5. the polycrystalline grain encapsulating structure that is used for semiconductor element as claimed in claim 1, it is characterized in that, this ground floor semiconductor grain is bonding by a rubber-like sticky material and this second layer semiconductor grain, and wherein this sticky material comprises silicon rubber, rubber resin, epoxy resin, macromolecule resin or above combination.
6. the polycrystalline grain encapsulating structure that is used for semiconductor element as claimed in claim 1, it is characterized in that, also comprise an isolated base and be formed on this second layer semiconductor die package, wherein this isolated base is formed by epoxy resin, FR4, FR5, polyimides, printed circuit board (PCB), bismaleimides triazine resin or organic material; Wherein comprise glass fibre in this isolated base in wherein.
7. the polycrystalline grain encapsulating structure that is used for semiconductor element as claimed in claim 1 is characterized in that, also comprises the sand core glueing material and is formed at by this ground floor and the second layer semiconductor grain.
8. the polycrystalline grain encapsulating structure that is used for semiconductor element as claimed in claim 1, it is characterized in that, also including but not limited to one second polycrystalline grain encapsulating structure and/or one the 3rd polycrystalline grain encapsulating structure be formed at this polycrystalline grain encapsulating structure other or on, and comprise conductive projection and between a plurality of polycrystalline grain encapsulating structures, provide binding.
9. method that is used for the formation polycrystalline grain encapsulating structure of semiconductor element is characterized in that comprising:
The significant surface of one second crystal grain is bonded on first adhesive tape;
The back side of one first crystal grain is bonded at one second adhesive tape;
Select this first crystal grain and be placed on this second crystal grain back side, to reach accurate contraposition with alignment patterns;
From wafer selecting this first crystal grain and this second crystal grain that go out to adhere to of cutting and place in the crystal grain configuration tool, and this significant surface of this second crystal grain is drawn in this crystal grain configuration tool;
This first crystal grain and this second crystal grain are aimed in one substrate with die receiving pane, and adhered in this crystal grain configuration tool by figure glue material, wherein this substrate comprises through-hole interconnection;
Form the sand core glueing material between the sidewall of this first crystal grain, this second crystal grain and this die receiving pane between in the crack;
One first time dielectric layer is coated on the significant surface of this first crystal grain, and exposed first contact mat of first joint sheet and this substrate;
Form the rerouting layer to be coupled to this first joint sheet;
Form one second time dielectric layer on the heavy distribution layer of this time, and expose the first scolding tin contact mat to form one first bottom bump metal structure;
Remove figure glue material one panel (panel) encapsulation is separated, then clear up this significant surface of this second crystal grain from this crystal grain configuration tool;
Form one second joint sheet of one first upper dielectric layer and this second crystal grain of dew place and second contact mat of this substrate;
The rerouting layer is to be coupled to this second joint sheet in the formation one;
Form one second upper dielectric layer to expose this second contact mat, to form one second bottom bump metal structure.
10. the method that is used for the formation polycrystalline grain encapsulating structure of semiconductor element as claimed in claim 9, it is characterized in that, also comprise and form a step of isolating substrate, wherein this isolation substrate has sticky material on rerouting layer on this and/or this second upper dielectric layer, then solidifies this isolation substrate.
11. the method that is used for the formation polycrystalline grain encapsulating structure of semiconductor element as claimed in claim 9, it is characterized in that, also comprise and use a carrier to support this panel encapsulation, and protect this time rerouting layer before the dielectric substance layer on first in forming this from this crystal grain configuration tool; And comprise from this carrier of this panel encapsulation separation, then clear up lower surface and carry out the tin ball action is set.
12. the method that is used for the formation polycrystalline grain encapsulating structure of semiconductor element as claimed in claim 9, it is characterized in that, also comprise aligning and place one second panel and be packaged in the encapsulation of first panel, make the bottom bump metal contact of ball grid array fusion, then carry out reflow to form interconnection structure.
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