JP2002110714A - Chip-integrating board, its manufacturing method, chip- like electronic component, its manufacturing method, and electronic equipment and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide electronic equipment which enables packaging, reducing man-hours, such as a mount process, superior in reliability and easy at a low cost by utilizing the characteristic of wafer batch processing, dispensing with a mother board and the packaging using till now, and performing cutting after pseudo-wafers are collectively mounted in batch on a wiring board having the similar functions as this. SOLUTION: An adhesive sheet 2 is stuck on the board 1, a plurality of nondefective bare chips are fixed on the adhesive sheet 2 by setting the face of the A1 electrode pad 5 upside down, a resin 4 is adhered on the whole face including a part between the plurality of the good product bare chips 3, the pseudo-wafer 29 fixing the nondefective bare chips 3 are peeled, integrated with a pseudo mother board 80 providing corresponding wiring or the like, the resin 4 is cut between the nondefective bare chips 3 to separate each nondefective chip module 82, and electronic equipment is made, by using it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a chip integrated board and a method of manufacturing the same, a chip-shaped electronic component and a method of manufacturing the same, and an electronic device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, there has been a strong demand for smaller, thinner and lighter portable electronic devices such as digital video cameras, digital cellular phones, and notebook PCs (Personal Computers). The key point is how to increase the density. For this reason, development of a smaller CSP (Chip Scale Package) instead of a package IC (QFP (Quad flat package) or the like) and its use in some parts have already been advanced.

[0003] The CSP is characterized in that it can be repaired in the same manner as a conventional package despite its mounting size close to bare chip mounting. A typical method of manufacturing the CSP is a method of flip-chip mounting on an interposer substrate by using a bump.

[0004] The bump formation technology in flip chip mounting generally includes a method of forming an Au bump on an Al electrode pad by an Au-Stud Bump method or an electrolytic plating method, or a method of collectively forming solder bumps by an electrolytic plating method or a vapor deposition method. A typical example is a method of forming by using the method described above. However, for consumer use, in the case of flip-chip mounting at lower cost, instead of forming bumps after forming chips (Au-Stud Bump method is a typical example), bumps are collectively formed in a wafer state. A forming method is desirable in terms of production tact.

[0005] Such a wafer batch processing method is intended to increase the diameter of a recent wafer (150 mmφ → 200 mmφ → 3
00 mmφ) and the tendency to increase the number of connection pins of an LSI (Large Scale Integrated Circuit) chip is a natural direction.

Hereinafter, a conventional bump forming method will be described.

FIG. 11 shows an Au stud bump (Stud Bum).
p) 24 is an example. Au stud bumps (Stud Bumps) are formed on the surfaces of the Al electrode pads 55 of the semiconductor chip 25 cut into individual pieces by using a wire bonding method.
24 are formed. FIG. 12 shows, for example, the input / output circuit 2
2. This is an example of a solder bump 62 when the Si substrate (wafer) 51 on which the element region (memory) 23 is formed is formed by batch processing at the wafer level (21 in the figure is a scribe line). ).

FIG. 13 shows that the cost is reduced.
The wafer with Ni electroless plating and solder paste printing.
This shows a step of forming bumps all at once. FIG. 13 (a)
Is SiO_TwoShows the Si substrate (wafer) with the film formed
Then, FIG. 2B shows an enlarged chip portion including the electrode.
It is something. 13A and 13B, reference numeral 51 denotes
Si substrate (wafer), 55 is Al electrode pad, etc.
Is SiO_TwoFilm, Si_ThreeN _Four, SiO_TwoFilm or polyimide film
Is a passivation film.

In FIG. 13C, a Ni electroless plating layer (UBM: Under Bump Meta) is selectively formed only on the upper surface of the opened Al electrode pad 55 by the Ni electroless plating method.
l) is formed. This Ni electroless plating layer (UB
M) can be easily formed by pretreating the surface of the Al electrode pad 55 with a phosphoric acid-based etchant, substituting and depositing Zn by Zn treatment, and further immersing the Ni electrode in a Ni-P plating bath. It acts as a UBM to help connect 55 with the solder bumps.

FIG. 13D shows a state in which a metal screen mask 52 is applied, and a solder paste 59 is formed by a printing method using Ni.
The state transferred to the electroless plating layer (UBM) is shown. FIG. 13E shows a state in which the solder bumps 62 are formed by melting the solder paste 59 by a wet back (heating and melting) method. As described above, by using the Ni electroless plating method and the solder paste screen printing method, the solder bumps 62 can be easily formed without using a photo process.

[0011] On the other hand, the CSP is an approach of reducing the size of each LSI and mounting it at a high density. However, when looking at circuit blocks of digital equipment, CSP is composed of several common circuit blocks. These are multi-chip packages or modularized (MCM: Mu
lti Chip Module) technology has also emerged. One example is a package of an SRAM (Static RAM), a flash memory, and a microcomputer in a digital mobile phone.

The MCM technology is expected to exert a great advantage even in recent one-chip system LSI. That is, memory and logic, and analog L
When the SI is integrated into one chip, different LSI processing processes are processed by the same wafer process, and the number of masks and the number of processes are significantly increased, and the development TAT (Turn aroun
The increase in d time) is a problem, and the decrease in yield is also a major concern.

For this purpose, each LSI is individually manufactured and MC
The method of M conversion is considered promising.

FIGS. 14A, 14B, and 14C show a flip-chip system in which a chip 64 is connected face-down to an electrode 63 on a circuit board 60. FIG. In consideration of further miniaturization and thinning, the flip chip shown in FIG. 18 is an advantageous method. Even considering the reduction of the connection distance and the variation of each connection impedance in future high speed,
It seems that it will change to the flip chip method.

A flip-chip type CSP shown in FIG. 15 has an LSI chip 40 on which bumps are formed,
FIG. 3A is a Fan in & Fan out type (where the connection electrodes 53 and 54 of the CSP are arranged on both the inside and outside of the LSI chip), and FIG. The Fan in type (the connection electrodes 53 and 54 of the CSP are arranged only inside the LSI chip) is shown. In any case, a gap between the electrode surface of the LSI and the interposer substrate 41 is filled with an underfill material 42 having a high elastic modulus to fix the bump joint, thereby preventing stress from being concentrated on the bump joint. The interposer substrate 41 is designed to relieve stress.

FIG. 16 shows a mounting structure in which the CSP is connected to the electrodes 44 of the mounting substrate 43 via, for example, solder 45 via the interposer substrate 41.

The flip-chip type MCM uses a plurality of heterogeneous LSIs for each of the Al electrode pads 55 of the respective LSIs.
A method of forming an Au-Stud Bump on the surface of the substrate and connecting it to a circuit board via an anisotropic conductive film (ACF), a method of press-contacting with a resin paste, and a method of forming an Au plated bump or a bump as a bump Various methods have been proposed, such as a method using Ni electroless plating bumps and solder bumps. FIG. 14C shows an example in which the metal is bonded to the substrate 60 with the solder bump 65 and the bonding is performed with lower resistance.

Each of the above-described bump forming methods has already been completed, and has begun to be used as a mass production-based technique. For example, the Au stud bump 24 shown in FIG. 11 is a bump forming method for each chip, and is widely used as a method for forming bumps more easily using existing equipment. Since the process is performed, the cost required for bump formation increases as the number of pins increases.

In recent low-voltage driving of LSIs, a problem of voltage drop in the Al wiring layer occurs. In order to shorten the wiring length, not only the arrangement of peripheral electrode pads but also the active element Also, an area pad having an electrode pad is required, but the Au stud bump 24 in FIG. 11 is not suitable for the area pad from the viewpoint of bonding load and damage. Further, the mounting of the Au stud bump chip has problems such as the pressure welding method for each one and difficulty in mounting on both sides.

On the other hand, the batch solder bump forming method for a wafer can be applied to the area pad arrangement on the mounting surface, and has advantages such as batch reflow and double-side mounting. However, when processing wafers with low cutting-edge yields,
The cost per good chip becomes extremely high.

FIG. 17 shows a semiconductor wafer 53 in a conventional wafer batch process.
Although the high yield is required, among the chips partitioned by the scribe line 21, the number of defective chips 20 indicated by the mark x is larger than the number of non-defective chips 3 indicated by the mark ○. It is.

Further, there is a problem that it is extremely difficult to form bumps when a chip is obtained from another place in the form of a bare chip. That is, the above-described two types of bump forming methods have their respective characteristics, but are not technologies that can be used for all regions, and at present, they are selectively used utilizing each characteristic. The wafer batch bump processing method has a high yield and a large number of terminals in one wafer (for example, 50,000).
It is effective for forming low damage bumps for terminals / wafers and area pads. Au stud bumps are characterized by bump processing when obtained in chip units and simple bump processing.

The semiconductor wafer 53 shown in FIG.
Is cut along the scribe line 21, the chip may be damaged by stress, cracks and the like due to the cutting, which may cause a failure. Furthermore, if the process for forming the non-defective chip 3 and the defective chip 20 together as the semiconductor wafer 53 is performed in a lump until the formation of the solder bumps, the steps performed on the defective chip 20 are wasted, which also causes an increase in cost.

Japanese Patent Application Laid-Open No. 9-260581 discloses a method in which a plurality of semiconductor chips are bonded and fixed on a Si wafer, embedded in a resin provided on a substrate such as alumina under pressure, and then peeled off. Discloses a method of flattening the surface of a wafer and forming a wiring layer for connection between elements on the wafer by photolithography.

According to this known method, wafers can be batch-processed and a low price can be achieved by mass production. However, a hard surface such as the above-mentioned alumina is provided on the back side of each semiconductor chip in the wafer. Since the substrate is present, the hard substrate on the back side must be cut together with the resin between the chips during scribing, and the cutting blade may be damaged. Moreover, although the side surface of the chip is covered with resin, the back surface only has a hard substrate different from the resin, so the back surface of the chip may not be effectively protected, and between the two. Of the adhesive becomes poor.

[0026]

Processes leading to the present invention To solve the above-mentioned conventional problems, the present applicant has taken advantage of the features of the batch processing of wafers as a prior application, and even if it is obtained with the most advanced LSI or bare chip, A chip-like electronic component such as a semiconductor chip and the like, which can be provided with high yield and low cost and with high reliability, and a method for manufacturing the same, and a pseudo wafer used for the manufacture and a method for manufacturing the same are proposed (Japanese Patent Application No. 2000-122112).
issue).

That is, the prior invention discloses a chip-like electronic component such as a semiconductor chip in which at least electrodes are provided only on one surface side, and the entire surface other than the one surface is covered with a continuous protective material. The present invention relates to a pseudo wafer in which a plurality or a plurality of kinds of electronic components are adhered to each other by a protective substance continuously applied between them and on the back surface thereof.

Further, the invention of the prior application relates to a step of adhering an adhesive means on a substrate, which has an adhesive force before treatment but decreases in adhesive force after the treatment, and a plurality or plural kinds of adhesive means on the adhesive means. Fixing the semiconductor chip with its electrode surface down, applying a protective substance to the entire surface including between the plurality of or plural kinds of semiconductor chips, and performing a predetermined treatment on the adhesive means to apply the adhesive. Reducing the adhesive force of the means, peeling off the pseudo wafer fixed the semiconductor chip,
A method of manufacturing a pseudo wafer, further comprising the step of cutting the protective material between the plurality of or plural kinds of semiconductor chips to separate each semiconductor chip or chip-shaped electronic component. A method of manufacturing an electronic component is also provided.

According to the invention of the prior application, a chip-like electronic component such as a semiconductor chip (hereinafter, a semiconductor chip is described as a representative example) is protected by a continuous protective material except for the electrode surface (ie, the chip side surface and the back surface). Therefore, the chip is protected in handling after chip formation, handling becomes easy, and good mounting reliability is obtained.

Further, a chip cut out from a semiconductor wafer and selected only of non-defective products is attached to a substrate, and a protective substance is applied over the entire surface and then peeled off, so that a pseudo wafer composed of all non-defective chips is obtained. , Bump processing etc. of wafers for non-defective chips at the same time becomes possible,
A low-cost bump chip can be formed, and a portion of the protective material between the chips is cut when the semiconductor chip is cut out from the dummy wafer, so that the semiconductor chip body is adversely affected (strain, burrs, cracks, etc.). And can be easily cut.

Further, since the side and back surfaces of the chip are covered with the protective substance, Ni electroless plating can be performed. In addition to a wafer manufactured in-house, a bare chip purchased from another company can be easily solder bumped. In addition, different LS installed in MCM
In many cases, all I-chips are supplied by the same semiconductor maker, and investment in cutting-edge semiconductor lines is increasing, so SRAM, flash memory, microcomputers, and CPUs (Central Processing Units) are used by the same semiconductor maker. Instead of supplying them in the form of a chip, they can be separately supplied in the form of chips from a semiconductor maker that is good at each of them, and these can be converted into MCMs. In addition, if the above-mentioned substrate is selected from durable ones that can be used repeatedly, it is advantageous in terms of bump formation cost and environment.

Hereinafter, the features of the invention of the prior application will be specifically described based on preferred embodiments with reference to the drawings.

First, FIG. 22 shows only the non-defective semiconductor bare chip 3 (or LSI chip) which is cut out from the semiconductor wafer 53 as shown in FIG. 17 and is confirmed as non-defective by open / short or DC (DC) voltage measurement. Are arranged and attached at equal intervals on a circular quartz substrate 1 via an adhesive sheet 2 made of acrylic or the like. FIG.
Is an example in which a large number of non-defective chips 3 are adhered to the limited area by the adhesive sheet 2 by using a rectangular glass substrate 19 instead of the circular quartz substrate 1, and the cost in the subsequent steps is reduced. It is something that can show the merit more.

Hereinafter, a method of forming solder bumps collectively using the quartz substrate 1 as shown in FIG. 22 as a substrate to which a chip is to be attached will be described with reference to FIGS.

FIG. 18A shows a quartz substrate 1 serving as a temporary support substrate. However, the heating process for the substrate is 400 ° C
Less expensive glass substrates can also be used for: The quartz substrate 1 can be used repeatedly.

Next, as shown in FIG.
An acrylic pressure-sensitive adhesive sheet 2 that is used in normal dicing and has a reduced adhesive strength when irradiated with ultraviolet light is attached thereon.

Next, as shown in FIG. 18C, a plurality of non-defective bare chips 3 which have been confirmed as non-defective as described above are arranged with the chip surface (device surface) 28 facing down and attached to the adhesive sheet 2. . The good bare chip 3 may be diced in the normal wafer process shown in FIG. 17 and taken out of the stretched state of the used dicing sheet (not shown), or may be transferred from a chip tray. What is important here is to rearrange only the non-defective bare chips 3 on the substrate 1 irrespective of chips made by the company or other companies.

Next, as shown in FIG. 18D, an organic insulating resin, for example, an acrylic resin 4 is uniformly applied on the chip 3. This application can be easily realized by spin coating or printing.

Next, as shown in FIG.
The pseudo wafer 2 is composed of a plurality of non-defective bare chips 3 whose side and back surfaces are continuously solidified with the resin 4 by irradiating ultraviolet rays from the back side 31 of the adhesive sheet 2 to weaken the adhesive force of the adhesive sheet 2.
9 is peeled off from the quartz substrate 1 at the bonding surface 30.

Next, as shown in FIG. 19 (f), the dummy wafer 29 is turned over so that the non-defective bare chip surface 28 (device surface) faces upward. The pseudo wafer 29 is formed on a Si substrate via an SiO ₂ film as shown in an enlarged scale in FIG.
The electrode pad 5 and the passivation film are formed.

Next, as shown in FIGS. 19 (g) to 20 (i), the same processing as in FIGS. 13 (c) to 13 (e) is performed.
FIG. 19 (g) shows a Ni electroless plating process for forming a UBM, FIG. 2 (h) shows a print transfer of a solder paste 9 using a print mask 8, and FIG. 20 (i) shows a state of formation of a solder bump 12 by a wet back method. It is.

That is, in FIG. 19 (g), only the surface of the opened Al electrode pad 5 is formed by Ni electroless plating.
A Ni electroless plating layer (UBM) is selectively formed. The Ni electroless plating layer (UBM) is made of Al
After pretreatment of the upper surface of the electrode pad 5 with a phosphoric acid-based etchant, Zn treatment is performed to replace and precipitate Zn, and further, Ni-
By immersing in a P plating tank, it can be easily formed,
UB to help connect Al electrode pad 5 and solder bump
Acts as M (Under Bump Metal).

FIG. 19H shows a state in which the print mask 8 is applied to
This is a state in which the solder paste 9 is transferred onto a Ni electroless plating layer (UBM) by a printing method. In FIG. 20 (i), the solder paste 9 is melted by a wet back method,
This is a state in which the solder bumps 12 have been formed. in this way,
By using a Ni electroless plating method, a solder paste screen printing method, or the like, the solder bumps 12 can be easily formed without using a photo process.

As described above, even if the chip is obtained from a cutting-edge LSI with a low yield or obtained from another company, only the good chip 3 is pasted again on the quartz substrate 1 as if
By manufacturing the pseudo wafer 29 composed of only the bare chip 3 of the non-defective product 100%, the bumps can be formed at a low cost in a batch of wafers.

In FIG. 20 (i), the electrical characteristics are measured by probe inspection and burn-in is performed to select non-defective bare chips 3 before the step of FIG. 1 (c). Only good chips can be sorted out.

FIG. 20 (j) shows a dicing 11 along a scribe line 33 with a blade 32 (or laser) in units of non-defective chip parts 26 obtained by protecting and reinforcing the chip 3 with a resin 4. The process of making individual pieces is shown.

Next, as shown in FIG.
6 is mounted on a mounting substrate 27 provided with electrodes 14 covered with a solder (solder) resist 15 and coated with a solder (solder) paste 13.
To mount.

At this time, the side surface and the back surface of the non-defective chip component 26 are covered with the resin 4, so that the non-defective chip component 26 is directly handled by handling such as suction of the non-defective chip component 26 during mounting on the mounting board 27. Without taking any damage,
Therefore, flip-chip mounting with high reliability can be expected.

Although the above description relates to the flip chip mounting technology of a semiconductor chip, it also relates to the connection solder bump forming technology in flip chip high density mounting and its manufacturing method.
Are adhered on the quartz substrate 1 with their front surfaces (device surfaces) 28 facing down at regular intervals, and then the resin 4 is uniformly applied to the back surface or the like to fix the non-defective chips 3 to each other.

After that, peel off from the adhesive sheet 2,
A pseudo wafer 29 in which only good chips 3 are arranged is produced, and bumps are formed on the pseudo wafer 29 at one time.
Bump chips can be manufactured at low cost. This bump chip can be used not only for small and lightweight portable electronic devices but also for all electronic devices.

FIG. 21 shows a bump forming method according to a modification using solder balls 17 in place of the solder paste 9 described above.

That is, first, a portion for forming a bump electrode is opened in the passivation film covering the Al electrode pad 5 formed on the pseudo wafer, and Ni is formed there.
An electroless plating layer (UBM) is formed.

Next, the Ni electroless plating layer (UBM)
The flux 18 is applied on the substrate by a printing method or the like. As a material of the flux 18, a material having a high adhesive strength is preferable so that the solder balls 17 can be easily transferred. The application of the flux 18 is not limited to the printing method because it is strong. However, in practice, the printing method is preferable. This is because the flux 18 can be efficiently applied to a desired pattern with a simple operation as compared with other methods.

Further, the solder balls 17 were changed to flux 1
The solder balls 17 are placed on the solder balls 8 and reflowed (heated and melted). Thereby, the solder balls 17 strongly adhere to the Ni electroless plating layer (UBM). Finally, the flux 18 is washed. This completes the formation of the bump electrode.

As described above, according to the prior application, a non-defective semiconductor chip is cut out from a wafer, rearranged and adhered to a substrate at regular intervals, peeled off after resin is applied, and as if all products were non-defective chips. In order to obtain a pseudo wafer, it is possible to perform solder bump processing or the like on the non-defective chip in a batch of wafers, and to form a low-cost flip-chip solder bump chip. Also, solder bump processing and the like can be easily performed not only on in-house manufactured wafers but also on bare chips purchased from other companies.

Further, at least the side of the chip,
Preferably, since the chip side and back surfaces are covered,
Since i-electroless plating is possible, and the side and back surfaces of the chip are protected by the resin, the chip is protected in the mounting handling after the chip is separated, and good mounting reliability is obtained. The substrate to which the good chip is attached can be used repeatedly after the wafer is separated, which is advantageous in terms of bump formation cost and environment.

Also, by utilizing the feature of low-cost bump processing by batch processing of wafers, it is possible to use a chip obtained in the form of a state-of-the-art LSI or bare chip, and to provide a highly versatile new bump forming method. In addition, when the semiconductor chip is cut from the pseudo wafer, only the resin portion is cut, so that the cutting can be easily performed, the blade is not damaged, and the semiconductor chip body is not adversely affected (strain, burrs, cracks, etc.). Can be suppressed.

[0058]

According to the above-mentioned prior invention and prior art, when assembling an electronic device product, a single chip or a multi-chip is packaged using an interposer and then mounted on a motherboard. Either the chip or chip product obtained by bare is directly mounted (or embedded) on the motherboard, or electronic components such as electrical input / output terminals are directly mounted on the motherboard, and are used for assembling electronic device products. The motherboard was indispensable.

For example, referring to the example shown in FIG. 24, FIGS. 20 (i ') and (j') show FIGS.
(J) (however, chips 3 of different types or sizes are integrated in a multi-chip system). The dummy wafer 29 on which the bumps 12 (in some cases, wiring) are formed in FIG. 24 (i ′) is diced into the chip component 26 in FIG. As shown in FIG. At this time, other electronic components 71, a user interface 72 such as a liquid crystal element, and electrical input / output terminals 73 for connection with other electronic products are also provided on the motherboard 70.
And the whole is covered with an exterior material 74.

However, the size of such an electronic device product is affected by the wiring of the substrate circuit of the motherboard 70 connecting the components and the packaging size of the chips and chip components, and it is difficult to reduce the size. For example, although a process of miniaturization of about 0.2 μm can be used for the wiring of the chip 26 and the chip component 71, the wiring of the motherboard 70 and further the interposer is tens of μm as a standard. Even if the parts are small and thin, it is difficult to downsize the interposer, especially the motherboard,
The miniaturization of the motherboard was an issue in miniaturizing the resulting electronic equipment products.

The same can be said for the weight. Furthermore, from the viewpoint of the manufacturing process of the product, it is sufficient that all the chips and chip components can be mounted by bare, but in fact,
In order to facilitate mounting and wiring of chips and chip components, a re-wiring process called packaging is required, and this packaging requires a lot of cost and time, and the volume and weight of the electronic device itself are reduced. Was causing the increase.

Further, resin or metal is used for the exterior material 74 of the electronic device product main body so that the internal motherboard and electronic components are not exposed. The use of this exterior material also structurally overlaps with the use of resin and metal for packaging and motherboards, greatly affecting the volume and weight, causing increased product costs and processes. .

At this stage, lead-free soldering and halogen-free motherboards are recommended as environmental measures, but not all products have reached the stage where they can cope with the environment.

Therefore, when manufacturing an electronic device product, packaging of chips and chip parts, use of a motherboard, an increase in processes due to the use of an exterior material of the electronic device product body, an increase in cost, a prolonged development and manufacturing time, and It has been strongly desired to solve such problems as increasing the volume and weight of the product, and responding to environmental concerns (lead-free and halogen-free).

On the other hand, when an LSI chip on which bumps are formed by the wafer batch bump formation method is converted into a CSP, usually,
First, the dummy wafer is diced into chips by dicing, and each chip is mounted on a large substrate consisting of a large number of interposer substrates, and the substrate is diced after reflow, cleaning, resin sealing, and resin curing. Get the CSP.

Here, if the bumps are formed on the pseudo wafer and then mounted on the interposer substrate at the same time, the size of the LSI chip and the size of the interposer substrate must necessarily be the same. In this case, it is necessary to clear all the following problems with respect to the interposer substrate.

(A) Since the external electrode pitch of the CSP (interposer) must be matched with the motherboard, it cannot be freely designed only on the CSP side. (B) CS
Since only the so-called Fan-in structure shown in FIG. 15B, in which the P external electrodes are arranged only inside the LSI chip, the maximum number of external electrodes that can be arranged is limited. F
Even if the required number of electrodes can be arranged by design in an an-in structure, a very high-level process is required, so that the cost is increased, and as a result, the cost of the substrate is increased.

Generally, since the above problems cannot be solved, the electrodes of the interposer substrate are not shown in FIG.
Fan in & Fan out as shown in (a) is mixed, and as a result, the size of the interposer substrate becomes larger than that of the LSI chip. Therefore, the wafer and the substrate cannot be mounted collectively. Conversely, manufacturing an LSI chip in accordance with the size of the interposer substrate is wasteful, and it is impossible to adapt to an extremely expensive LSI process.

On the other hand, in the case of manufacturing a CSP based on the invention of the prior application, first, a pseudo wafer is diced into individual LSI chips (no dicing is performed when chips are supplied from other companies or the like). Then, only the non-defective chips are rearranged using a mounter device to form a pseudo substrate, and then bumps are formed by pseudo substrate batch processing. Next, the chips are singulated again by dicing. Then, using the mounter device again, one chip is mounted on a large substrate composed of a large number of interposer substrates, and after dicing the substrate after reflow, cleaning, resin sealing, and resin curing, one CSP is formed. obtain.
As described above, especially when the CSP is formed by the method of the prior application, the dicing and the chip mounter are used twice, and the process is complicated.

When it is necessary to reduce the thickness of the package, the chip is ground from the back surface of the chip, for example, in the state of a pseudo substrate. However, since the chips are connected by resin, the resin on the back surface of the chip is not ground. In such a case, since the resin is bonded only on the side surface of the chip, the bonding force is weakened, and there is a risk that the chip may peel off during grinding.

Further, after dicing the chips into individual pieces, it is troublesome to peel off and handle the very thin chips from the dicing tape.

Therefore, an object of the present invention is to make use of the features of the above-mentioned prior application, eliminate the need for a motherboard and packaging used up to now, and package a pseudo wafer on a wiring board having a similar function. Packaging is possible by cutting after mounting,
An object of the present invention is to reduce the number of steps such as a mounting process and obtain an electronic device with good reliability, easily and at low cost.

[0073]

That is, according to the present invention, a plurality or a plurality of types of chip components having at least one electrode provided on one surface side are fixed by a protective substance adhered to at least the side surface. The present invention relates to a chip integrated board in which a pseudo wafer and a wiring board having wiring corresponding to an electrode surface side of the pseudo wafer are integrated in an electrically connected state.

The present invention also provides a step of fixing a plurality of or a plurality of types of chip parts to an adhesive means provided on a substrate so that the electrodes thereof face down, and a step of applying a protective substance to at least side surfaces of the chip parts. A step of depositing, a step of separating the chip component and the substrate on which the protective substance is deposited and integrated to obtain a pseudo wafer, and a wiring having a wiring corresponding to an electrode surface side of the pseudo wafer Integrating the board and the pseudo wafer in an electrically connected state.

Further, the present invention provides a chip-like electronic component obtained by cutting a chip integrated board in which the pseudo wafer and the wiring board are integrated in an electrically connected state at the position of the protective substance. It is related.

The chip-shaped electronic component of the present invention is manufactured by a step of cutting the chip integrated board obtained by the above-described method at the position of the protective substance.

The present invention also provides a chip-like electronic component obtained by cutting a chip integrated board in which the pseudo wafer and the wiring board are integrated in an electrically connected state at the position of the protective substance. It also provides electronic devices that are being used.

The electronic apparatus according to the present invention is manufactured by a step of incorporating a chip-shaped electronic component obtained by cutting the chip integrated board at the position of the protective substance.

According to the present invention, the chip component and the substrate, on which the protective substance is adhered and integrated, are separated from each other to obtain a pseudo wafer, and a wiring corresponding to the electrode surface side of the pseudo wafer is provided. The wiring board and the pseudo wafer are integrated in an electrically connected state to obtain a chip integrated board, and further the chip integrated board is cut at the position of the protective material to produce a chip-shaped electronic component, and further incorporating the chip-shaped electronic component. Since electronic devices are manufactured, the pseudo wafer is cut and mounted on the pseudo motherboard as the wiring board that performs the same function as the motherboard used so far, and then cut, and the package can be configured as it is, such as a mounting process. The number of steps can be reduced, and an electronic device can be obtained with good reliability, easily and at low cost.

The present invention also has the same features as the above-mentioned prior invention, in which a chip cut out from a semiconductor wafer and only non-defective products are selected is adhered to a substrate, and after a protective material is applied, the chip is peeled off. By doing so, it is possible to obtain a pseudo wafer composed of good chips from all the products.This makes it possible to perform bump processing and the like on wafers for good chips at the same time, to form low-cost bump components, and to remove semiconductor chips from pseudo wafers. Since the portion of the protective material between the chips is cut at the time of cutting, the semiconductor chip can be cut easily without adverse effects on the semiconductor chip body (damage such as distortion, burrs, and cracks).

In addition, since at least the side surface of the chip is covered with the protective substance, the handling is improved. In addition to a wafer manufactured in-house, a bare chip purchased from another company can be easily solder bumped. In addition, there are few cases where all the different LSI chips mounted on the MCM are supplied from the same semiconductor maker, and investment in the most advanced semiconductor lines is increasing.
Furthermore, instead of supplying CPUs (Central Processing Units) by the same semiconductor maker, they are supplied separately by chips from their respective semiconductor manufacturers,
It can be converted to M. The above substrate can be used repeatedly, which is advantageous in terms of bump formation cost and environment.

[0082]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a non-defective chip module as a pseudo wafer having non-defective chip components mounted on a motherboard such as an LSI chip, a chip resistor, and a chip capacitor is integrated with a rewiring on a device surface. Electronic devices (electronic products) on the pseudo motherboard as the wiring board for forming a circuit
A liquid crystal display, a key panel, a user interface such as a speaker, an electric input / output terminal with another electronic device, or an electronic component that is not a chip shape may be attached.

Further, the chip integrated board of the present invention is cut at the position of the protective substance, and a single semiconductor chip or a plurality of or a plurality of types of semiconductor chips is simulated motherboard or interposer substrate as the wiring board. It is preferable to be processed into a chip integrated with the above.

As the protective substance, an organic insulating resin or an inorganic insulating substance is preferable.

It is preferable that the pseudo wafer is mounted on the pseudo motherboard or the interposer substrate, then reflowed, washed, and sealed with resin, and then diced into individual pieces.

Further, the protective material and the chip are preferably ground from the back side of the pseudo wafer to reduce the thickness, and then cut into individual pieces by a blade or a laser.

The electronic device according to the present invention incorporates the chip-shaped electronic component, and the chip-shaped electronic component is housed in a housing, or the protective substance forms an exterior structure. Is preferred.

Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

First Embodiment FIGS. 1 to 4 show a first embodiment of the present invention.

First, after being cut out from the semiconductor wafer 53 as shown in FIG.
Only non-defective semiconductor bare chips 3 (or LSI chips) confirmed as non-defective by C (direct current) voltage measurement are selected, and FIG.
FIG. 1A shows an acrylic adhesive sheet 2 attached on a quartz substrate 1 shown in FIG. 1A as shown in FIG.
As shown in (c), they are arranged at equal intervals and pasted.

As a temporary supporting substrate, the quartz substrate 1 or a cheaper glass substrate can be used because the heating process for the substrate is 400 ° C. or less. The quartz substrate 1 can be used repeatedly. Further, the pressure-sensitive adhesive material composed of the pressure-sensitive adhesive sheet 2 is used in ordinary dicing, and for example, the pressure-sensitive adhesive strength is reduced when irradiated with ultraviolet rays, for example, an acrylic, silicon, polystyrene, or polyether-based pressure-sensitive adhesive sheet 2 Alternatively, an adhesive substance having solvent solubility and releasability is used.
If the adhesive substance is a film, it is applied by a method such as roller lamination, and if it is a liquid substance, it is applied by a technique such as spin coating or printing.

As described above, a plurality of non-defective bare chips 3 confirmed to be non-defective are arranged with the chip surface (device surface) 28 facing down and affixed to the adhesive sheet 2. The non-defective bare chips 3 are processed in a normal wafer process. The sheet may be diced and removed from the stretched state of a used dicing sheet (not shown), or may be transferred from a chip tray. The important thing here is whether you own or a third-party chip,
The purpose is to rearrange only good bare chips on the substrate 1.

Next, as shown in FIG. 1D, an organic insulating resin, for example, a resin 4 such as an epoxy-based, polyimide-based, or polyester-based resin is uniformly applied on the chip 3. This application can be easily realized by spin coating or printing. In this case, as long as the resin 4 has a releasing effect on the adhesive substance 2, the resin may be uniformly poured from the back surface of the chip and cured, but at this time, the chip is held and fixed by the adhesive property of the adhesive substance. So it doesn't move.

Next, as shown in FIG. 1 (e), for example, ultraviolet rays are irradiated from the side of the quartz substrate 1 to weaken the adhesive force of the adhesive sheet 2, or by the releasing action of the adhesive substance 2.
A pseudo wafer 29 comprising a plurality of non-defective bare chips 3 whose side and back surfaces are continuously hardened with resin 4 is placed on a quartz substrate 1.
(Specifically, it is peeled off from the adhesive sheet 2). As shown in FIG. 19, the pseudo wafer 29 is made of SiO ₂ on a Si substrate.
An Al electrode pad 5 and a passivation film are formed via a film.

Next, FIG. 19 (g) to FIG.
The same processing as in (i) is performed, or necessary wiring is provided between chips, and predetermined bumps and wiring are formed collectively on the wafer.

Here, in the invention of the prior application, a dummy wafer 29 composed of a resin substrate having a large number of non-defective chips arranged thereon and having an exposed device surface is cut with wiring and terminals attached thereto (FIG. 20 (j)). (Fig. 2
0 (k)) in the present embodiment does not use a motherboard, but adds additional value to this resin substrate.

That is, the rewiring and circuit formation performed by the interposer of the motherboard and the package are formed on the device surface of the pseudo wafer 29 obtained in FIG. 1E by using the conventional wafer process. I do. In this case, the pseudo motherboard 80 is integrally formed on the device surface of the pseudo wafer 29 as shown in FIG. 2 (f), and the corresponding wirings and electrodes 83 are integrated correspondingly to form a chip module board as a whole. 81 are formed. Here, if the resin 4 covering each chip of the pseudo wafer 29 is made of a transparent resin such as polyester or epoxy, the position of the chip can be easily determined from the outside and the wiring can be easily aligned.

The wiring material of the pseudo motherboard 80 is made of lead-free solder, considering connection reliability with the device surface.
Desirably, the insulating film is formed of Cu, Au, Al, or the like, and polyimide or the like is preferable as the insulating film. The wiring at this time may be a single layer or a plurality of layers.

Next, as shown in FIG. 2 (g), the resin substrate 29 is cut into a module 82 composed of individual pieces or a plurality of chips and chip parts, and is used for a low-cost non-defective chip module or an electronic device product. Provide a pseudo motherboard.

The module 82 thus obtained is, for example, multi-layered, and is used as a non-defective chip module or a pseudo motherboard composed of non-defective chip modules as shown in FIG.
On the side opposite to the chip module 82, the user interface 72 such as a liquid crystal, a key panel, and a speaker necessary for use as an electronic device product, and the chip-shaped (or non-chip-shaped) electronic component 7
1, furthermore, electrical input / output terminals 7 with other electronic equipment products
3 is attached. Until now, the chip module 82 was mounted and mounted on the motherboard as shown in FIG. 24 (k ′). However, in this embodiment, the chip module 82 is treated as a wired pseudo motherboard, and other components are placed thereon. Is mounted directly and mounted. In this mounting method, for example, ACF connection using a flexible printed circuit or solder connection using lead-free solder is possible.

In FIG. 3A, an exterior material 84 is further provided. In order to omit the exterior material, the chip is covered and cured on a non-defective chip module or a pseudo mother board made of a non-defective chip module (chip). The front side portion of the resin (on the back side) can also be used as the exterior resin of the electronic device product body.

That is, as shown in FIG. 3B, for example, two different non-defective chip modules 82 and 82 '(pseudo motherboards) each having various electronic components mounted thereon are opposed to each other with the device surfaces inside. to paste together. The bonding method may be a structure of mechanically bonding with an adhesive, or a method of covering the mounting surface with a resin or the like.
This reduces the necessity of using a motherboard or an exterior material made of a material such as glass epoxy, thereby producing an electronic device body including all necessary multichips and components.

FIG. 4 shows a method for forming the other module 82 'in order to obtain the electronic device shown in FIG. 3B.

First, as shown in FIG. 4A, non-defective bare chips 3 (or LSI chips), other electronic components 71, and user interface components 72 are arranged and adhered on an acrylic adhesive sheet 2 or the like.

Next, as shown in FIG. 4B, an organic insulating resin, for example, an epoxy resin 4 'is uniformly applied on the chip 3 and the like. This coating can be easily realized by spin coating, dispensing or printing.

Next, as shown in FIG. 4C, for example, ultraviolet rays are irradiated from the side of the quartz substrate 1 to weaken the adhesive force of the adhesive sheet 2 or to release the adhesive substance 2 by a releasing action.
The pseudo wafer 29 'composed of a plurality of non-defective bare chips 3 and other parts 72, etc., whose at least side surfaces are continuously solidified with the resin 4', is peeled off from the quartz substrate 1 (specifically, the adhesive sheet 2).

Next, as shown in FIG. 4D, wirings and the like are formed on the device surface of the pseudo wafer 29 'obtained in FIG. 4C, and the pseudo motherboard 80' is integrated. This is formed on the device surface of the pseudo wafer 29 ', and the corresponding wirings and electrodes 83' are correspondingly integrated with each other to form the chip module board 81 'as a whole.

In the subsequent steps, chip modules 82 'are cut into individual pieces in the same manner as in FIG.
As shown in (B), the chip module 82 is bonded to and integrated with the one chip module 82, and the side surfaces are further hardened with an adhesive 85 or the like.

As described above, according to the present embodiment,
Electronic equipment products can be assembled without using conventional packaging, motherboards, and exterior materials as much as possible.Conventional packaging of chips and chip components, use of motherboards, increased processes due to the use of electronic products' original packaging materials, Increased cost, bloated development and manufacturing time, increased product volume and weight, environmentally friendly (lead-free,
Halogen-free) can be improved together.
If various electronic components that cannot be made into a chip shape at present are increasingly system-on-a-chip in the future, the method according to the present embodiment will be used in the first basic process of arranging chip components. Becomes possible, and it becomes easier to manufacture.

Further, since at least the side surface of the module is covered and protected by the resin 4 as in the prior invention, good mounting reliability can be obtained in mounting handling. The substrate to which the good chip is attached can be used repeatedly after the wafer is separated, which is advantageous in terms of bump formation cost and environment.

Further, by utilizing the feature of low-cost bump processing by batch processing of wafers, it is possible to use a chip obtained in the form of a state-of-the-art LSI or bare chip, and to provide a highly versatile new bump forming method. When cutting out from the chip module board, only the resin part is cut, so cutting can be done easily, there is no damage to the blade, and the adverse effect on the semiconductor chip body (damage such as distortion, burrs, cracks, etc.) is suppressed. it can.

Here, the functions and effects obtained in the present embodiment are summarized as follows (1) to (5).

(1) In addition to the conventional semiconductor chip,
Chip components such as chip capacitors and chip resistors,
A resin substrate 29 obtained by arranging the system-on-chip together with the device side down and curing with resin.
Has a more functional added value, and has a structure closer to the electronic device product itself.

(2) As shown in (1), a device surface with a higher added value in terms of function can be formed not only by a batch bump but also by a bump.
Since a single-layer or multi-layer wiring is formed by using the wiring method of the wafer process, this resin substrate is not simply "mounting" on a conventional motherboard, but this resin substrate itself mounts other electronic components Can be the structure of a pseudo motherboard.

(3) Various parts (user interface, electrical input / output terminal, etc.) of electronic products to be mounted on the conventional motherboard are mounted and mounted on the pseudo motherboard of (2), so that the conventional motherboard can be used. The old motherboard is no longer needed.

(4) The front side portion of the hardened resin (on the back side of the chip) which covers the chip of the non-defective chip module or the pseudo motherboard composed of the non-defective chip module can also be used as the exterior resin material of the electronic product body. Exterior materials are not required.

(5) In (1) to (4), an interposer for packaging a chip or a chip component, a motherboard, and an exterior material are not required.
These have resulted in increased processes, increased costs,
Enlargement of development and production time, increase of product volume and weight,
Environmental measures (lead-free, halogen-free) can be improved collectively.

Second Embodiment FIGS. 5 to 10 show a second embodiment of the present invention.

In the present embodiment, the pseudo wafer 29 manufactured in the steps of FIGS. 1A to 1E in the first embodiment described above is
As shown in (a), (b), and (c), the electrodes or wirings are integrated while corresponding to each other. Here, the interposer substrate 80 corresponds to the above-described pseudo motherboard,
The double-sided substrate is provided with the cream solder 92 facing the bump electrode 12 of the pseudo wafer 29.

The interposer substrate 80 is a double-sided substrate, and is penetrated from the land on the front surface to the land surface on the rear surface by through holes. For example, a cream solder 92 is printed on the land on the surface for subsequent soldering.

The interposer substrate 80 after dicing
Are larger in size than the LSI chip. As the material of the interposer substrate, for example, glass epoxy, ceramic or the like is suitable. on the other hand,
On the pseudo substrate 29, the LSI chips 3 manufactured by silicon, gallium arsenide substrate or the like are arranged. The pitch of the arrangement is the same as the pitch of each substrate block of the interposer substrate.

As shown in FIGS. 5B and 5C, the pseudo substrate 29 is face down and the interposer substrate 8 is turned down.
0, and perform reflow heating, soldering, and flux cleaning. At this time, if a perforated slit 90 is formed on the dicing line of the interposer substrate 80 as shown in FIG. 7E, the flux detergent easily penetrates, and high cleaning performance is realized. it can.

Next, as shown in FIG. 7D, the gap is sealed with an underfill resin 91, and is cured by heating.
Also in this case, by providing the through slit 90 on the dicing line described above, voids and the like can be easily removed. If a vacuum defoamer or the like is used, it is possible to forcibly remove the void from the slit. Therefore,
The residual voids are eliminated, and the generation of cracks and the like can be prevented even when heating is performed in a later step. Further, the slit 90 has an effect of reducing the warpage of the interposer substrate. As shown in FIG. 8F, the underfill material can be filled directly from the slit 90.

Next, as shown in FIG. 9G, the interposer substrate 80 is diced using a blade 92 (or a laser). The CSP 93 is completed through the above steps.

Further, as shown in FIGS. 10 (h) and 10 (i), a thin CSP 95 can be obtained by grinding only the LSI portion by grinding the pseudo substrate 29 side with a grindstone 94.

At this time, since the thick interposer substrate 80 can be fixed and ground, the LSI portion can be thinned to the extent permitted by mechanical strength. For example, LSI
The thickness of the portion can be reduced to about 20 μm. Since the resin portion on the side surface of the LSI chip is also firmly bonded to the underfill resin 91, there is no danger of peeling due to insufficient bonding force both in grinding and in the subsequent dicing process.

As described above, according to this embodiment, the CSP can be used while taking advantage of the low-cost bump processing in the pseudo-substrate batch processing as in the first embodiment.
Can be obtained the following effects (1) to (4).

(1) By preparing a pseudo substrate on which an LSI is arranged in accordance with the pitch of the interposer substrate, the pseudo substrate and the interposer substrate can be mounted collectively. Thereby, the mounting process can be greatly reduced.

(2) By forming a through slit on the interposer substrate side, the flux cleaning property and the underfill resin filling property are improved. As a result, generation of cracks due to residual voids can be suppressed, and reliability is improved.

(3) Since an LSI chip as a pseudo substrate is firmly adhered to a large substrate composed of a large number of interposer substrates with an underfill resin,
The SI chip can be ground as thin as possible, resulting in an extremely thin CSP.

(4) Since the steps of chip mounting and dicing can be reduced, the processing time of the CSP can be reduced, and as a result, a low-cost CSP can be obtained.

The embodiments described above can be variously modified based on the technical idea of the present invention.

For example, the layer structure of the pseudo motherboard or the interposer substrate or the method of integrating the pseudo wafer with the pseudo wafer may be of course other methods. As a substrate to which a good bare chip is attached, other materials may be used as long as they have the same effect and strength in addition to quartz and glass. Also,
The shape and thickness of the substrate can be freely changed. Substrates such as the quartz substrate 1 described above can be used repeatedly as many times as possible, which is advantageous in terms of cost and environment.

The pressure-sensitive adhesive material such as the pressure-sensitive adhesive sheet 2 may be made of an acrylic material or any of various other materials which can achieve the same purpose. Desirable on separation.

The material of the insulating protective material such as the resin 4 may be selected from a wide range of materials.
An in-glass (SiO _x film) may be used. In addition, non-defective bare chips may be of the same type or a plurality of types, and may be the same or different in size, and may be arranged at any intervals. Further, it is also possible to form bumps using metal balls (solder balls) instead of the above-mentioned solder paste.

The object to which the present invention is applied is not limited to a semiconductor chip, but may be various other chip-shaped electronic components that involve cutting into individual chips.

[0137]

According to the present invention, the chip component and the substrate, on which the protective substance is adhered and integrated, are separated from each other to obtain a pseudo wafer, which corresponds to the electrode surface side of the pseudo wafer. A wiring board having wiring and the pseudo wafer are integrated in an electrically connected state to obtain a chip integrated board, and the chip integrated board is cut at the position of the protective material to produce a chip-shaped electronic component. Since the electronic device is manufactured by incorporating the above, the pseudo wafer can be cut and mounted on the pseudo motherboard as the wiring board having the same function as the conventionally used motherboard, and then the package can be configured as it is. The number of steps such as a mounting process can be reduced, and an electronic device can be obtained with good reliability, easily and at low cost.

Further, a chip cut out of a semiconductor wafer and selected only for non-defective products is attached to a substrate, and a protective substance is applied and then peeled off, so that a pseudo wafer composed of all non-defective chips can be obtained. Therefore, it is possible to perform bump processing on non-defective chips in a batch of wafers, and it is possible to form low-cost bump parts, and to cut the protective material between chips when cutting out from a pseudo wafer. It is possible to cut easily, while suppressing the adverse effect on the surface (damage such as distortion, burrs and cracks).

In addition, since at least the side surface of the chip is covered with the protective substance, the handling is improved. In addition to a wafer manufactured in-house, a bare chip purchased from another company can be easily solder bumped. In addition, there are few cases where all the different LSI chips mounted on the MCM are supplied from the same semiconductor maker, and investment in the most advanced semiconductor lines is increasing.
Furthermore, instead of supplying CPUs (Central Processing Units) by the same semiconductor maker, they are supplied separately by chips from their respective semiconductor manufacturers,
It can be converted to M. The above substrate can be used repeatedly, which is advantageous in terms of bump formation cost and environment.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view sequentially showing a manufacturing process of a module component according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view sequentially showing a manufacturing process of the module component.

FIG. 3 is a cross-sectional view of an electronic device incorporating the module component obtained by the manufacturing process.

FIG. 4 is a sectional view sequentially showing a manufacturing process of a module component used in the electronic device.

FIG. 5 is a perspective view sequentially showing a manufacturing process of an electronic component according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view sequentially showing a manufacturing process of the electronic component.

FIG. 7 is a cross-sectional view sequentially showing a manufacturing process of the electronic component.

FIG. 8 is a perspective view showing a manufacturing process of the electronic component.

FIG. 9 is a perspective view showing a manufacturing process of the electronic component.

FIG. 10 is a perspective view sequentially showing a manufacturing process of the electronic component.

FIG. 11 shows an Au stud bump (Stud B) in a conventional example.
FIG. 4 is a perspective view showing an example of a ump).

FIG. 12 is a partial plan view of the semiconductor wafer which has been subjected to bump processing by batch soldering at the wafer level.

FIG. 13 is a cross-sectional view sequentially showing the steps of manufacturing the semiconductor chip.

14A and 14B are a perspective view and a partial cross-sectional side view of another example of a mounting structure converted into an MCM.

FIG. 15 is a cross-sectional view of the example of the mounting structure.

FIG. 16 is a cross-sectional view of another example of the mounting structure.

FIG. 17 is a perspective view of a semiconductor wafer for coping with wafer batch processing.

FIG. 18 is a sectional view sequentially showing a manufacturing step of the semiconductor chip according to the embodiment of the prior application;

FIG. 19 is a cross-sectional view sequentially showing the manufacturing process.

FIG. 20 is a cross-sectional view sequentially showing a manufacturing step and a mounting step thereof.

FIG. 21 is a cross-sectional view of another pseudo wafer.

FIG. 22 is a perspective view of the substrate to which the conforming bare chip is attached.

FIG. 23 is a perspective view of the substrate to which the conforming bare chip is attached.

FIG. 24 is a cross-sectional view of an electronic device incorporating the pseudo wafer and a chip module cut out therefrom.

[Explanation of symbols]

1: Quartz substrate, 2: Adhesive sheet, 3: Good bare chip,
4, 4 ': resin (protective substance), 5: Al electrode pad, 8
... Print mask, 9 ... Solder paste, 11 ... Dicing, 12 ... Solder bump, 13 ... Solder (solder) paste, 14 ... Electrode, 16 ... Wiring board, 19 ... Large glass substrate, 20 ... Defective bare chip, 26 ... Good product Chip parts, 27: mounting board, 28: non-defective bare chip surface (device surface), 29, 29 ': pseudo wafer, 32: blade, 33: scribe line, 71: other electronic parts, 7
2: User interface, 80: Pseudo motherboard or interposer board, 81, 81 ': Chip module board, 82, 82': Module, 83,
83 ': electrode (wiring), 84: exterior material, 90: slit, 91: underfill resin, 92: cream solder

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuo Nishiyama 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 5F061 AA01 BA07 CA05 CA10 CA12 CB02 CB13

Claims (34)

[Claims] 1. A pseudo wafer in which a plurality or a plurality of types of chip components having at least one electrode provided on one surface side are fixed by a protective substance adhered to at least a side surface, and an electrode surface of the pseudo wafer. A chip integrated board in which a wiring board having wiring corresponding to the side is integrated in an electrically connected state. 2. The wiring board which is integrated with a non-defective chip module as a pseudo wafer having non-defective chip components to be mounted on a mother board such as an LSI chip, a chip resistor, a chip capacitor, and re-wires and forms a circuit on a device surface. Liquid crystal, key panels, user interfaces such as speakers, electrical input / output terminals with other electronic devices, or electronic components that are not chip-shaped are attached to the pseudo motherboard of the electronic device, The chip integrated board according to claim 1. 3. The chip integrated board according to claim 1, wherein the protective material is an organic insulating resin or an inorganic insulating material. 4. The semiconductor chip is cut at the position of the protective material to be processed into a single semiconductor chip or a chip in which a plurality of or plural kinds of semiconductor chips are integrated with a pseudo motherboard or an interposer substrate as the wiring board. The chip integrated board according to claim 1, wherein: 5. A step of fixing a plurality of or a plurality of types of chip components to an adhesive means provided on a substrate so that an electrode surface thereof faces down, and a step of applying a protective substance to the plurality of or a plurality of types of chip components. A step of attaching at least a side surface, a step of separating the chip component and the substrate, each of which has the protective substance attached thereto and integrated, to obtain a pseudo wafer, and a wiring corresponding to an electrode surface side of the pseudo wafer Integrating the wiring board having the pseudo wafer and the pseudo wafer in an electrically connected state,
A method for manufacturing a chip integrated board comprising: 6. The wiring board which is integrated with a non-defective chip module as a pseudo wafer having non-defective chip components to be mounted on a motherboard such as an LSI chip, a chip resistor, a chip capacitor, and re-wires and forms a circuit on a device surface. 6. A user interface such as a liquid crystal, a key panel, and a speaker, an electric input / output terminal for other electronic devices, or an electronic component that is not in a chip shape necessary for use as an electronic device is attached to the pseudo motherboard. 3. The method for manufacturing a chip integrated board according to claim 1. 7. The method for manufacturing a chip integrated board according to claim 5, wherein the protective material is an organic insulating resin or an inorganic insulating material. 8. A single semiconductor chip or a plurality or a plurality of kinds of semiconductor chips are cut into a chip integrated with a pseudo motherboard or an interposer substrate as the wiring board by cutting at a position of the protective material. The method for manufacturing an integrated board according to claim 5, wherein a chip integrated board to be obtained is obtained. 9. The pseudo wafer is mounted on the pseudo motherboard or interposer substrate, and reflow is performed.
The method for manufacturing a chip integrated board according to claim 8, wherein washing and resin encapsulation are performed. 10. The method of manufacturing a chip integrated board according to claim 8, wherein the cutting is performed after grinding from the back side of the pseudo wafer. 11. A pseudo wafer in which a plurality or a plurality of types of chip components having at least one electrode provided on one surface side are fixed by a protective substance adhered to at least a side surface, and an electrode surface of the pseudo wafer. A chip-shaped electronic component obtained by cutting a chip integrated board in which a wiring board having wiring corresponding to a side is integrated in an electrically connected state at a position of the protective substance. 12. The wiring board which is integrated with a non-defective chip module as a pseudo wafer having non-defective chip components mounted on a mother board, such as an LSI chip, a chip resistor, and a chip capacitor, and re-wires and forms a circuit on a device surface. The pseudo-motherboard is mounted with a user interface such as a liquid crystal, a key panel, a speaker, an electrical input / output terminal with other electronic devices, or an electronic component that is not a chip shape, necessary for use as an electronic device. 12. The chip-shaped electronic component according to item 11. 13. The chip-shaped electronic component according to claim 11, wherein the protective material is an organic insulating resin or an inorganic insulating material. 14. A single semiconductor chip or a plurality of semiconductor chips or a plurality of semiconductor chips are cut at the position of the protective material to obtain a chip integrated with a pseudo motherboard or an interposer substrate as the wiring board. The chip-shaped electronic component according to claim 9, wherein 15. A step of fixing a plurality of or a plurality of types of chip components to an adhesive means provided on a substrate so that an electrode surface thereof faces down, and a step of applying a protective substance to the plurality of or a plurality of types of chip components. A step of attaching at least a side surface, a step of separating the chip component and the substrate, each of which has the protective substance attached thereto and integrated, to obtain a pseudo wafer, and a wiring corresponding to an electrode surface side of the pseudo wafer A step of obtaining a chip integrated board by integrating the wiring board having the above and the pseudo wafer in an electrically connected state, and a step of cutting the chip integrated board at the position of the protective material. Production method. 16. The wiring board which is integrated with a non-defective chip module as a pseudo wafer having non-defective chip components mounted on a mother board such as an LSI chip, a chip resistor, and a chip capacitor, and re-wiring and forming a circuit on a device surface. A user interface such as a liquid crystal, a key panel, and a speaker necessary for use as an electronic device, an electrical input / output terminal with other electronic devices, or an electronic component that is not a chip shape. 3. The method for producing a chip-shaped electronic component according to claim 1. 17. The method according to claim 15, wherein the protection material is an organic insulating resin or an inorganic insulating material. 18. The semiconductor device is cut at the position of the protective material, and processed into a single semiconductor chip or a chip in which a plurality of or a plurality of types of semiconductor chips are integrated with a pseudo motherboard or an interposer substrate as the wiring board. The method for manufacturing a chip-like electronic component according to claim 15, wherein a chip integrated board is obtained. 19. The method according to claim 18, wherein the pseudo wafer is mounted on the pseudo motherboard or the interposer substrate, and reflow, cleaning, and resin encapsulation are performed. 20. The method of manufacturing a chip-like electronic component according to claim 15, wherein the cutting is performed after grinding from the back side of the pseudo wafer. 21. A pseudo wafer in which a plurality or a plurality of types of chip components having at least one electrode provided on one surface side are fixed by a protective substance adhered to at least a side surface, and an electrode surface of the pseudo wafer. An electronic device in which a chip-like electronic component obtained by cutting a chip integrated board in which a wiring board having wiring corresponding to a side is integrated in an electrically connected state at the position of the protective substance is incorporated. 22. The wiring board which is integrated with a non-defective chip module as a pseudo wafer having non-defective chip components mounted on a motherboard, such as an LSI chip, a chip resistor, and a chip capacitor, and re-wires and forms a circuit on a device surface. The pseudo-motherboard is mounted with a user interface such as a liquid crystal, a key panel, a speaker, an electrical input / output terminal with other electronic devices, or an electronic component that is not a chip shape, necessary for use as an electronic device. 22. The electronic device according to 21. 23. The electronic device according to claim 21, wherein the protective material is an organic insulating resin or an inorganic insulating material. 24. A chip in which a single semiconductor chip or a plurality or a plurality of kinds of semiconductor chips are integrated with a pseudo motherboard or an interposer substrate as the wiring board by being cut at the position of the protective material. The electronic device according to claim 21, wherein 25. The electronic device according to claim 21, wherein the chip-shaped electronic component is housed in a housing. 26. The electronic device according to claim 21, wherein the protective material for the chip-shaped electronic component forms an exterior structure. 27. A step of fixing a plurality of or a plurality of types of chip components to an adhesive means provided on a substrate so that an electrode surface thereof faces down, and applying a protective substance to the plurality of or a plurality of types of chip components. A step of attaching at least a side surface, a step of separating the chip component and the substrate, each of which has the protective substance attached thereto and integrated, to obtain a pseudo wafer, and a wiring corresponding to an electrode surface side of the pseudo wafer A step of obtaining a chip integrated board by integrating the wiring board having the above and the pseudo wafer in an electrically connected state, a step of cutting the chip integrated board at the position of the protective material, and a chip-like electronic device obtained by the step A method of manufacturing an electronic device, comprising: a step of incorporating components. 28. The wiring board which is integrated with a non-defective chip module as a pseudo wafer having non-defective chip components mounted on a motherboard, such as an LSI chip, a chip resistor, and a chip capacitor, and re-wires and forms a circuit on a device surface. 28. A user interface such as a liquid crystal, a key panel, and a speaker, an electrical input / output terminal with other electronic devices, or an electronic component that is not in a chip shape necessary for use as an electronic device is attached to the pseudo motherboard. 3. The method for manufacturing an electronic device according to claim 1. 29. The method for manufacturing an electronic device according to claim 27, wherein the protective material is an organic insulating resin or an inorganic insulating material. 30. The semiconductor substrate is cut at the position of the protective material to process a single semiconductor chip or a plurality of or a plurality of types of semiconductor chips into a chip integrated with a pseudo motherboard or an interposer substrate as the wiring board. The method for manufacturing an electronic device according to claim 27, wherein a chip integrated board is obtained. 31. The method for manufacturing an electronic device according to claim 30, wherein the pseudo wafer is mounted on the pseudo motherboard or the interposer substrate, and reflow, cleaning, and resin encapsulation are performed. 32. The method of manufacturing an electronic device according to claim 27, wherein the cutting is performed after grinding from the back side of the pseudo wafer. 33. The method for manufacturing an electronic device according to claim 27, wherein said chip-shaped electronic component is housed in a housing. 34. The method for manufacturing an electronic device according to claim 27, wherein the protective material for the chip-shaped electronic component forms an exterior structure.