JP2013117720A - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a high-performance liquid crystal display device while suppressing reduction in yield resulting from initial failure of a VLSI chip, and the liquid crystal display device.SOLUTION: Excellent and independent VLSI chips 6 with no functional failure are exclusively selected from a plurality of VLSI chips cut from a mother VLSI substrate. Thereafter, the chips 6 are fixed on a single independent-VLSI-chip-mounted substrate 11 in a matrix pattern so that a chip-mounted complex substrate 16 is prepared. The substrate 16 is used as one mother substrate to be employed for manufacturing a liquid crystal display device.

Description

  The present invention relates to a liquid crystal display device and a manufacturing method thereof.

  A liquid crystal display device that has become smaller and more detailed is commonly called a microdisplay, and has a small pixel and wiring, and an increase in the number of pixels, for example, from a mother VLSI (integrated circuit) substrate made of 8-inch wafer. The number of good single VLSI chips that can be taken decreases, that is, the yield decreases. Therefore, when a liquid crystal display device is manufactured using a glass substrate having the same size as the mother VLSI substrate, the glass substrate, the sealing material, etc., where the defective single VLSI chip is mounted are wasted. The problem becomes more prominent when the resolution is further increased or the yield of the mother VLSI substrate at the beginning of development is poor.

  The following conventional techniques are known for such problems. 13-a, 13-b, and 13-c are cross-sectional views showing the prior art. In this prior art, only the good single VLSI chip 6 taken out from the mother VLSI substrate and the other good parts 87 are transferred onto the mounting substrate (glass substrate) 85 via the adhesive sheet 86, and the transferred good single unit is transferred. After the individual VLSI chip 6 and the non-defective part 87 are filled with the resin 89, the resin 89 and the non-defective part 87 are peeled off from the mounting substrate 85, so that a plurality of the non-defective VLSI chips 6 and the non-defective part 87 are integrally fixed to the resin 89. A resin film (resin 89) is produced and mounted on a circuit board (motherboard) 91 provided with a through electrode 92, wiring 93, and the like in advance. (See Patent Document 1)

  In this prior art, only a good single VLSI chip taken out from the mother VLSI substrate is used, so that it is possible to solve the problem of discarding other good members caused by a defective single VLSI chip.

JP 2002-110714 A

  When the prior art is applied to the manufacture of a liquid crystal display device, a good single VLSI chip fixed to a resin film is bonded to the counter substrate through a sealing material. The flatness of a single VLSI chip, that is, the uniformity of the gap (gap) between a good single VLSI chip and the counter substrate, and the adhesion between the single good VLSI chip and the counter substrate are very important. Since the non-defective single VLSI chips are fixed only by the resin, there is a problem that when the non-defective single VLSI chip is bonded to the counter substrate, a variation easily occurs between the non-defective single VLSI chips.

  In particular, in the case of a liquid crystal display device using a ferroelectric liquid crystal as the liquid crystal, the liquid crystal layer has a layer thickness that is higher than that in the case of using a super twist nematic (STN) liquid crystal, a twist nematic (TN) liquid crystal, a vertical alignment liquid crystal, or the like. Since the thickness is very thin, the uniformity of the gap between the single good VLSI chip and the counter substrate is more important.

  The present invention has been made in view of the above-described problems in the prior art, and a liquid crystal display device capable of manufacturing a high-quality liquid crystal display device while suppressing a decrease in yield due to an initial failure of a VLSI chip and its manufacture. It aims to provide a method.

  A step of selectively placing a plurality of non-defective VLSI chips that are functionally good on the VLSI chip mounting substrate, and fixing the plurality of non-defective VLSI chips arranged on the VLSI chip mounting substrate on the VLSI chip mounting substrate. A step of providing a single sealing portion on the plurality of non-defective VLSI chips fixed on the VLSI chip mounting substrate, and bonding a counter substrate to the VLSI chip mounting substrate via the single sealing portion. A step of cutting the VLSI chip mounting substrate and the counter substrate bonded to each other in each region where the non-defective VLSI chip is provided, and a step of injecting liquid crystal into a region surrounded by the single seal portion And a manufacturing method of a liquid crystal display device.

  A method of manufacturing a liquid crystal display device can be provided in which a chip alignment mark is formed on the VLSI chip mounting substrate, and the non-defective VLSI chip is transferred onto the VLSI chip mounting substrate based on the chip alignment mark.

  A method for manufacturing a liquid crystal display device in which the non-defective VLSI chip is fixed onto the VLSI chip mounting substrate by a surface activated bonding method can be employed.

  A manufacturing method of a liquid crystal display device in which the back surface of the non-defective VLSI chip and the surface of the VLSI chip mounting substrate are polished, and the polished surfaces are fixed by a surface activated bonding method.

  A method for manufacturing a liquid crystal display device in which the non-defective VLSI chip is fixed onto the VLSI chip mounting substrate with an adhesive can be used.

  A liquid crystal display device in which the non-defective VLSI chip is arranged so that a gap is formed between the non-defective VLSI chips when the non-defective VLSI chip is arranged on the VLSI chip mounting substrate, and the gap is filled with a filler. It can be set as the manufacturing method of this.

  Before disposing the non-defective VLSI chip on the VLSI chip mounting substrate, a liquid crystal display that polishes the back surface of the non-defective VLSI chip so that the thickness of the non-defective VLSI chip is smaller than the thickness of the VLSI chip mounting substrate. It can be set as the manufacturing method of an apparatus.

  After fixing the non-defective VLSI chip on the VLSI chip mounting substrate, the non-defective VLSI chip is covered with a filler so as to fill a gap between the non-defective VLSI chips, and the surface of the non-defective VLSI chip is covered. It can be set as the manufacturing method of the liquid crystal display device grind | polished until the surface of this is exposed.

  A method of manufacturing a liquid crystal display device in which the back surface of the VLSI chip mounting substrate is polished at the same time as the surface of the filler is polished.

  Manufacture of a liquid crystal display device in which an outer peripheral seal portion surrounding the single seal portion is provided between the VLSI chip stack substrate and the counter substrate before the VLSI chip stack substrate and the counter substrate bonded to each other are cut. It can be a method.

  A non-defective VLSI chip that is functionally non-defective, a VLSI chip mounting substrate on which the non-defective VLSI chip is mounted, a counter substrate bonded on the non-defective VLSI chip via a single seal portion, and the single seal portion A liquid crystal display device including liquid crystal injected into the enclosed region.

  A liquid crystal display device in which the thermal expansion coefficient of the non-defective VLSI chip and the thermal expansion coefficient of the VLSI chip mounting substrate are the same can be obtained.

  The material of the non-defective VLSI chip and the material of the VLSI chip mounting substrate can be the same liquid crystal display device.

  A liquid crystal display device in which the thermal expansion coefficient of the non-defective VLSI chip and the thermal expansion coefficient of the counter substrate are the same can be obtained.

  A circuit board is connected to an outer periphery of the non-defective VLSI chip, and an outer periphery of the VLSI chip mounting substrate facing the outer periphery of the non-defective VLSI chip to which the circuit board is connected is the non-defective product to which the circuit board is connected. A liquid crystal display device can be provided in which the outer peripheral portion of the VLSI chip extends to the outer peripheral side, and a filler is filled between the protruding outer peripheral portion of the VLSI chip mounting substrate and the FPC.

  A liquid crystal display device in which a heater unit for heating the liquid crystal is formed between the non-defective VLSI chip and the VLSI chip mounting substrate can be provided.

  A liquid crystal display device in which a heater unit for heating the liquid crystal is formed on a surface of the VLSI chip mounting substrate on which the non-defective VLSI chip is not mounted.

  According to the present invention, only a plurality of non-defective single VLSI chips are taken out from the mother VLSI substrate and fixed on the single VLSI chip mounting substrate, whereby a pseudo collective substrate composed only of non-defective single VLSI chips is obtained. Since the liquid crystal display device is manufactured by using this, it is possible to eliminate the discard of the counter substrate, the sealing material, the liquid crystal, and the like caused by the defective single VLSI chip, which has been generated conventionally, and By making each VLSI substrate an individual good VLSI chip, the stress generated from a large VLSI substrate can be reduced to an individual level, and at the same time, warping of a good single VLSI chip by a single VLSI chip mounting substrate. Etc. can be corrected and the flatness can be improved, so the gap between a good VLSI chip and the counter substrate is appropriate. Kept, it is possible to improve the display quality.

  Even if the stress increases due to the miniaturization of the wiring pattern of the mother VLSI substrate, the stress can be dispersed (divided into stresses per unit) by making a single good VLSI chip, and further, a single VLSI chip can be mounted. Since it can be reinforced by mounting on the substrate, the adhesion between the single VLSI chip mounting substrate and the counter substrate can be improved without increasing the width of the sealing material.

  In addition, when a chip alignment mark is provided on a single VLSI chip mounting substrate and a good single VLSI chip is loaded, if the chip alignment mark is used as a reference, a plurality of good single VLSI chips are accurately arranged in a matrix. be able to. Further, if the chip alignment mark is provided on the back side of the single VLSI chip mounting substrate, it is possible to solve the problems of stacking the non-defective single VLSI chip, the adhesion with the counter electrode, and the uniformity.

  Also, if a good single VLSI chip is bonded to a single VLSI chip mounting substrate by surface activation bonding, the flatness of the single good VLSI chip on the single VLSI chip mounting substrate, the surface of the single good VLSI chip, The inner flatness, and the adhesion between a good single VLSI chip and a single VLSI chip mounting board can be improved, and thermal stress is greatly reduced by surface activation bonding at a low temperature. Therefore, it is possible to improve display uniformity and reliability of the liquid crystal display device.

1 is a plan view of a mother VLSI substrate of a liquid crystal display device according to a first embodiment of the present invention. A-A sectional view of FIG. FIG. 2 is a plan view showing a state in which a non-defective single VLSI chip of the liquid crystal display device according to the first embodiment of the present invention is stacked on a single VLSI chip mounting substrate. BB sectional view of Fig. 2-a Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 1st Embodiment of this invention Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 1st Embodiment of this invention Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 1st Embodiment of this invention Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 1st Embodiment of this invention Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 1st Embodiment of this invention The top view of the liquid crystal display device in the 1st Embodiment of this invention CC sectional view of FIG. The top view of the liquid crystal display device in the 2nd Embodiment of this invention DD sectional view of FIG. Sectional drawing of the liquid crystal display device in the 3rd Embodiment of this invention Sectional drawing of the liquid crystal display device in the 4th Embodiment of this invention Sectional drawing of the liquid crystal display device in the 5th Embodiment of this invention Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 6th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 6th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 6th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 7th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 7th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 7th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 7th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the liquid crystal display device in the 7th Embodiment of this invention. Sectional drawing of the liquid crystal display device in the 8th Embodiment of this invention Sectional drawing of the liquid crystal display device in the 9th Embodiment of this invention Sectional view showing the prior art Sectional view showing the prior art Sectional view showing the prior art

  FIG. 1A is a plan view of the mother VLSI substrate of the liquid crystal display device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line AA of FIG. FIG. 2A is a plan view showing a state in which a non-defective single VLSI chip of the liquid crystal display device according to the first embodiment of the present invention is stacked on a single VLSI chip mounting substrate, and FIG. It is BB sectional drawing of. 3A, 3B, 3C, 3D, and 3E are cross-sectional views illustrating manufacturing steps of the liquid crystal display device according to the first embodiment of the present invention. 4A is a plan view of the liquid crystal display device according to the first embodiment of the present invention, and FIG. 4-B is a cross-sectional view taken along the line CC in FIG. 4-A.

  In the first embodiment of the present invention, first, as shown in FIGS. 1A and 1B, a plurality of single VLSI (large scale integrated circuit) chips 5 are integrally arranged in a matrix. The mother VLSI substrate 1 is bonded on a dicing tape 10 (not shown in FIG. 1A), and a dicing groove 7 (not shown in FIG. 1A) is formed between each single VLSI chip 5 by a dicing apparatus. The dicing tape 10 is stretched in the horizontal direction to divide each single VLSI chip 5 into individual pieces. Further, before and after the process, the function of each single VLSI chip 5 is inspected, and those that pass the inspection are selected as non-defective single VLSI chips 6.

  Next, as shown in FIGS. 2-a and 2-b, a single VLSI chip mounting substrate made of a silicon substrate in which a chip alignment mark 13 is previously formed on the back surface by laser processing and the surface is mirror-finished. 11 is prepared, and only the non-defective VLSI chip 6 is bonded via the surface activated bonding layer 15 by the surface activated bonding method.

  In order to form the surface activation bonding layer 15, it is preferable that both the surfaces of the non-defective single VLSI chip 6 and the single VLSI chip mounting substrate 11 that are in contact with each other are made mirror surfaces by polishing or the like. Further, it is preferable to remove dirt on the surface by performing argon plasma treatment and hydrogen plasma treatment on both sides.

  When surface activated bonding is performed, surface contamination is removed in vacuum, both surfaces to be bonded are activated, and a plurality of non-defective VLSI chips are formed at a predetermined pitch with reference to the chip alignment mark 13. 6 are transferred onto a single VLSI chip mounting substrate 11 in a matrix and bonded by applying heat while applying pressure. As a result, a chip stacking composite substrate 16 in which a plurality of non-defective single VLSI chips 6 are arranged in a matrix on the single VLSI chip mounting substrate 11 via the surface activation bonding layer 15 is produced. Since the surface activated bonding is an intermolecular bonding, the chip-carrying composite substrate 16 becomes very robust.

  As shown in FIG. 3A, the chip stacking composite substrate 16 has an inter-chip gap 17 between adjacent good VLSI chips 6, and plasma CVD (chemical vapor phase) is used to fill the inter-chip gap 17. The initial inter-chip gap filling material 21 made of a silicon nitride (SiNx) film is uniformly provided on the entire upper surface of the chip stacking composite substrate 16 so as to cover the non-defective VLSI chip 6.

  The surface of the initial inter-chip gap filling material 21 is flattened even if it is left as it is. However, if the initial inter-chip gap filling material 21 is formed on the pixel electrode of the non-defective single VLSI chip 6, the non-defective single VLSI chip 6. When the voltage is applied to the liquid crystal 36 between the single counter substrate and the single counter substrate, the voltage is applied to the initial inter-chip gap filling material 21, and thus the voltage cannot be efficiently applied to the liquid crystal 36.

  Therefore, as shown in FIG. 3B, the surface of the initial inter-chip gap filler 21 is polished by CMP (chemical mechanical polishing) until the surface of the single good VLSI chip 6 is exposed or close to it. As a result, a part of the initial inter-chip gap filler 21 remains as the inter-chip gap filler 23 after processing between each good VLSI chip 6.

  Next, as shown in FIG. 3C, a chip-carrying composite substrate 16 having a post-chip gap filler 23 and a counter substrate 31 made of a glass substrate having a counter electrode are approximately 1 micrometer (μm). A plurality of single seal portions 33 formed by mixing a spacer ball made of quartz of approximately 1 micrometer (μm) with a resin material so as to be a gap of the spacer, and a spacer ball arranged so as to surround them The plurality of liquid crystal display panels 40 before processing are manufactured by bonding them with an outer peripheral seal portion 37 made of only a non-resin material.

  Here, each single seal portion 33 is provided with an opening (liquid crystal injection port) for injecting the liquid crystal 36 into the liquid crystal injection space 35. Accordingly, in the dicing process using water, since water enters the liquid crystal injection space 35 from the opening, the outer periphery of the single seal portion 33 is sealed by the outer peripheral seal portion 37 to prevent water from entering. A plurality of outer peripheral seal portions 37 are preferably provided concentrically.

  Next, as shown in FIG. 3D, a single VLSI chip mounting substrate dicing groove 41 is formed on the surface of the single VLSI chip mounting substrate 6 by the dicing method, and the counter substrate 31 is formed on the surface of the counter substrate 31. The dicing groove 42 is formed by a dicing method. The position where the single VLSI chip mounting substrate dicing groove 41 is formed is an area between adjacent non-defective single VLSI chips 6, and the position where the counter substrate dicing groove 42 is formed is adjacent single seal portion 33. It is an area between.

  Next, the portion where the dicing groove 41 for the single VLSI chip mounting substrate and the dicing groove 42 for the counter substrate are pressed with rubber, and the single VLSI chip mounting is performed with the dicing groove 41 for the single VLSI chip mounting substrate as a boundary. A single liquid crystal display panel 39 as shown in FIG. 3E is obtained by dividing the substrate 6 and the inter-chip gap filling material 23 after processing, and further dividing the counter substrate 31 with the counter substrate dicing groove 42 as a boundary. Is made.

  After processing, the inter-chip gap filler 23 may be removed after the single liquid crystal display panel 39 is manufactured, but may be left attached to the outer periphery of the single VLSI chip mounting substrate 6. In this case, the post-process gap filling material 23 attached to the outer periphery of the single VLSI chip mounting substrate 6 serves as a protective film for protecting the outer periphery of the single VLSI chip mounting substrate 6. In the present embodiment, the processed inter-chip gap filler 23 is removed after the single liquid crystal display panel 39 is manufactured.

  Thereafter, the ferroelectric liquid crystal is introduced into the liquid crystal injection space 35 between the single VLSI chip mounting substrate 12 after single processing and the counter substrate 32 after single processing through an opening provided in a part of the single seal portion 33. Liquid crystal 36 made of liquid crystal is injected, and the opening is sealed with a sealing material 38.

  Next, as shown in FIG. 4-a and FIG. 4-b, the single liquid crystal display panel 39 is bonded to the external circuit board 51 having the connector 52 for connecting to the peripheral circuit by the double-sided adhesive tape, An aluminum wire 55 made of an aluminum thin wire is attached between the substrate 51 and the single good VLSI chip 6 by an ultrasonic wire bonding method, the aluminum wire 55 is covered with a wire protective resin 56, and the counter substrate 32 is further processed after single processing. A counter electrode conducting portion 58 made of a conductive adhesive is provided between the upper transparent electrode and the electrode terminal on the external circuit board 51.

  Next, a second embodiment will be described with reference to FIGS. FIG. 5-a is a plan view of a liquid crystal display device according to the second embodiment of the present invention, and FIG. 5-b is a cross-sectional view taken along the line DD in FIG. In the second embodiment, the single liquid crystal display panel 39 and an external circuit are electrically connected by a flexible printed circuit board (hereinafter referred to as FPC) 61. The FPC 61 is connected to one side of the outer peripheral portion of the single good VLSI chip 11, and further, on the one side, the outer peripheral portion of the single VLSI chip mounting substrate 12 after single processing is the outer periphery of the single good VLSI chip 11. The FPC reinforcing step 65 is formed by projecting to the outer peripheral side from the portion and the projecting portion. An FPC back surface protective resin 63 is applied to the FPC reinforcing step 65, and the back surface of the FPC 61 is reinforced by the FPC back surface protective resin 63 and the FPC reinforcing step 65. In order to increase the effect of the FPC reinforcing step 65, it is preferable to reduce the thickness of the non-defective VLSI chip 6 and bring the back surface of the FPC 6 closer to the FPC reinforcing step 65. Further, the FPC surface protection resin 62 is applied to the surface (upper surface) of the FPC 61, and thereby the connection portion of the FPC 61 is further reinforced.

  On the three sides except one side to which the FPC 61 is connected, each end face of the single VLSI chip mounting substrate 12, the surface activated bonding layer 15, the single good VLSI chip 11, and the counter substrate 32 after the single processing after single processing. Are processed so as to be flush with each other. The adjustment of each end face including the formation of the FPC reinforcing step 65 is performed by adjusting the positions of the single VLSI chip mounting substrate dicing groove 41 and the counter substrate dicing groove 42 in the step of FIG. If necessary, it is performed by processing each end face after dividing.

  After single processing, the voltage is applied to the transparent electrode on the counter substrate 32 by connecting the electrode provided on the non-defective single VLSI chip 11 and the FPC 61 via an anisotropic conductive film (ACF), and further transparent This is done by connecting the electrode and the electrode on the single good VLSI chip 6 through an anisotropic conductive seal portion 67 made of an insulating seal material containing conductive particles.

  Next, Embodiment 3 will be described with reference to FIG. FIG. 6 is a cross-sectional view of the liquid crystal display device according to the third embodiment of the present invention, and shows another embodiment of the liquid crystal display device shown in the cross-sectional view of FIG. In addition, the same code | symbol is used for the same member. In the third embodiment, a single VLSI chip mounting substrate 11 made of a light-transmitting glass substrate is used as a substrate for mounting a non-defective single VLSI chip 6 on the single VLSI chip mounting substrate 11. A single good VLSI chip 6 is fixed via a chip adhesive 25 made of a photo-curable epoxy resin.

  More specifically, first, a chip adhesive 25 made of a photo-curable epoxy resin is uniformly applied on the single VLSI chip mounting substrate 11, and a plurality of non-defective single VLSI chips 6 are transferred thereon. (Mounter) is used to accurately arrange in a matrix with reference to the chip alignment mark 13 on the back surface of the single VLSI chip mounting substrate 11. Thereafter, the single VLSI chip mounting substrate 11 is placed on a transparent stage, and the chip adhesive 25 made of a photocurable epoxy resin is irradiated with ultraviolet rays from the transparent stage side while applying pressure from the good VLSI chip 6 side. Is hardened, and the non-defective single VLSI chip 6 is fixed on the single VLSI chip mounting substrate 11 via the chip adhesive 25 to produce the chip-mounted composite substrate 16.

  By using the chip adhesive 25, the non-defective single VLSI chip 6 can be securely fixed to the single VLSI chip mounting substrate 11 made of a material not suitable for surface activation bonding. In consideration of the strength of the adhesive force of the chip adhesive 25 and the generation of stress caused by filling the inter-chip gap 17 with resin, the inter-chip gap 17 is not filled with resin or the like.

  In the third embodiment, a gap corresponding to the thickness of the single good VLSI chip 6 is generated by the gap 17 between the chips. Therefore, the alignment film of the liquid crystal is an alignment film in which an inorganic film is deposited by oblique vapor deposition. Alternatively, an organic film (polymer) may be spray-coated and rotated to be uniform, and then an alignment film subjected to a photo-alignment treatment may be used.

  The single VLSI chip mounting substrate 11 uses glass having a thermal expansion coefficient substantially the same as the thermal expansion coefficient of the silicon substrate, for example, NA32SG glass manufactured by Avant Straight Co., Ltd. If the single VLSI chip mounting substrate 11 and the non-defective single VLSI chip 6 have the same thermal expansion coefficient, the generation of stress during heat treatment or the like can be reduced. Furthermore, it is more effective to make the three members of the single VLSI chip mounting substrate 11, the non-defective single VLSI chip 6, and the counter substrate 31 have the same thermal expansion coefficient.

  Next, Embodiment 4 will be described with reference to FIG. FIG. 7 is a cross-sectional view of the liquid crystal display device according to the fourth embodiment of the present invention, and shows another embodiment of the liquid crystal display device shown in the cross-sectional view of FIG. In addition, the same code | symbol is used for the same member. In the fourth embodiment, in order to prevent a decrease in response speed due to an increase in viscosity of liquid crystal at a low temperature, a back heater circuit portion 71 that generates heat is provided on the back surface of a single VLSI chip mounting substrate 11 made of a glass substrate. Forming.

  The wiring pattern shape of the back surface heater circuit portion 71 is a thin line folded back, and a gap is provided between the thin lines so that light can be transmitted. The material of the thin wire may be a metal, but a transparent material such as indium tin oxide (ITO) is preferable in order to improve light transmission. Other configurations are the same as those of the third embodiment.

  Next, Embodiment 5 will be described with reference to FIG. FIG. 8 is a cross-sectional view of the liquid crystal display device according to the fifth embodiment of the present invention, and is a cross-sectional view showing another embodiment of the liquid crystal display device shown in the cross-sectional view of FIG. In addition, the same code | symbol is used for the same member. In the fifth embodiment, the surface heater circuit unit 73 that generates heat and the heater control circuit unit 75 that controls the operation thereof are formed of silicon in order to prevent a decrease in response speed due to an increase in viscosity of the liquid crystal at a low temperature. It is formed on the surface (upper surface) of a single VLSI chip mounting substrate 11 made of a substrate.

  A good VLSI chip 6 is bonded onto the surface heater circuit portion 73 via a chip adhesive 25 made of a heat conductive resin. Further, in order to prevent the generation of gas from the chip adhesive 25 during alignment film coating and alignment processing, the chip adhesive 25 other than the portion overlapping the non-defective VLSI chip 6 is removed, and the adjacent non-defective single unit A chip adhesive removing unit 26 is provided between the VLSI chips 6. Other configurations are the same as those in the fourth embodiment.

  Next, a sixth embodiment will be described with reference to FIGS. 9A to 9C. FIG. 9A, FIG. 9B, and FIG. 9C are cross-sectional views showing the manufacturing process of the liquid crystal display device according to the sixth embodiment of the present invention, respectively. The chip-mounted composite substrate 16 shown in FIG. 3 shows another embodiment of the manufacturing process. In addition, the same code | symbol is used for the same member. In the sixth embodiment, first, as shown in FIG. 9A, the non-defective single VLSI chip 6 is bonded onto the single VLSI chip mounting substrate 11 via the surface activation bonding layer 15, and then, As shown in FIG. 9B, in order to fill the inter-chip gap 17 between the adjacent good VLSI chips 6, the initial inter-chip gap made of a silicon nitride (SiNx) film is formed by a plasma CVD (chemical vapor deposition) method. The gap filling material 21 is formed on the entire top surface of the chip stacking composite substrate 16.

  Thereafter, the front surface (upper surface) of the initial inter-chip gap filler 21 and the back surface (lower surface) of the single VLSI chip mounting substrate 11 are simultaneously polished by chemical mechanical polishing (CMP), as shown in FIG. All the initial inter-chip gap filling material 21 on the non-defective VLSI chip 6 is removed to form a post-chip gap filling material 23 between the adjacent non-defective VLSI chips 6, and at the same time, the single VLSI chip. The loaded substrate 11 is formed as a single VLSI chip loaded substrate 14 after polishing, which is about half the normal thickness.

  Thus, by simultaneously polishing the inter-chip gap filler 21 and the single VLSI chip mounting substrate 11, it is possible to reduce the generation and accumulation of stresses such as warping. Moreover, since the thickness of the entire liquid crystal display device is reduced by making the single VLSI chip mounting substrate 11 thinner, a small and lightweight liquid crystal display device can be manufactured.

  Next, the seventh embodiment will be described with reference to FIGS. 10A to 10E. 10A, FIG. 10B, FIG. 10C, FIG. 10D, and FIG. 10E are cross-sectional views showing the manufacturing process of the liquid crystal display device according to the seventh embodiment of the present invention. Another embodiment of the manufacturing process of the chip mounting composite substrate 16 shown to 2-b is shown. In addition, the same code | symbol is used for the same member. In the seventh embodiment, the back surface of the mother VLSI substrate 1 is polished in advance to produce a good thin single VLSI chip 9 that is thinner than the good single VLSI chip 6. If the good thin single VLSI chip 9 is used, the gap filling material 21 between the initial chips for covering it may be thinly laminated, and the good thin single VLSI chip 9 and the chip for the single VLSI chip mounting substrate 11 may be used. The stress due to the gap filling material 23 can also be greatly reduced. Specific steps are as follows, for example.

  As shown in FIG. 10-a, the back surface of the mother VLSI substrate is polished with the polishing protective resin 3 uniformly applied to the surface of the mother VLSI substrate to reduce the thickness to 100 micrometers (μm). Thus, the mother VLSI substrate 2 is manufactured after the back surface polishing.

  Next, as shown in FIG. 10B, the back surface of the mother VLSI substrate 2 after back polishing is bonded onto the dicing tape 10, and dicing grooves 7 are formed at a predetermined pitch on the surface of the mother VLSI substrate 2 after back polishing. As a result, a plurality of thin single VLSI chips 8 are produced.

  Next, as shown in FIG. 10-c, only the good thin single VLSI chip 9 which is functionally good and selected from the plurality of thin single VLSI chips 8 is made of a glass substrate having a thermal expansion coefficient substantially equal to that. On the single VLSI chip mounting substrate 11, an inter-chip gap 17 is provided between the single VLSI chip mounting substrates 11 and fixed in a matrix form via a chip adhesive 25, and further, the single VLSI chip 9 is covered so as to cover the non-defective thin single VLSI chip 9. An initial inter-chip gap filling material 21 is uniformly applied on the individual VLSI chip mounting substrate 11.

  Here, a laser mark 19 is previously formed on the single VLSI chip mounting substrate 11 by a laser marking device. Since the laser mark 19 can be formed inside the single VLSI chip mounting substrate 11 by adjusting the depth of focus and the laser energy, the surface of the single VLSI chip mounting substrate 11 is not damaged. When the good thin single VLSI chip 9 is transferred onto the single VLSI chip mounting substrate 11, the laser mark 19 is used as a positioning reference, and a plurality of good thin single VLSI chips 9 are aligned with high accuracy.

  In this embodiment, since the good thin single VLSI chip 9 is thin and the initial inter-chip gap filling material 21 is also thin, as means for fixing the good thin single VLSI chip 9 on the single VLSI chip mounting substrate 11, Even if the chip adhesive 25 is used instead of the surface activated bonding method, it can be securely fixed.

  Next, as shown in FIG. 10-d, the surface of the initial interchip gap filler 21 is etched by dry reactive chemical etching (RIE) to expose the surface of the good thin single VLSI chip 9. At the same time, by forming the initial inter-chip gap filler 21 remaining in the inter-chip gap 17 as the inter-chip gap filler 23 after processing, the chip stacking composite substrate 16 is manufactured.

  The RIE method is suitable as a means for removing the initial inter-chip gap filler 21 because no mechanical force is applied to the chip adhesive 25. Note that since the chip adhesive 25 hardly comes into contact with the etching gas during the RIE, no contamination gas is generated.

  Next, as shown in FIG. 10E, after the counter substrate 31 is bonded onto the chip stacking composite substrate 16 via a plurality of single seal portions 33 and a peripheral seal portion 37 surrounding them, a single VLSI chip is formed. A single VLSI chip mounting substrate dicing groove 41 is formed on the mounting substrate 11, and a counter substrate dicing groove 42 is formed on the counter substrate 31. The subsequent steps are the same as the steps shown in FIG.

  In the present embodiment, the non-defective thin single VLSI chip 9 is thin, the inter-chip gap filling material 23 is thin, and the single VLSI chip mounting substrate 11 and the counter substrate 31 are made of the same material (glass). The uniformity of the injection space 35 is good and can be easily divided by dicing or the like.

  Next, an eighth embodiment will be described with reference to FIG. FIG. 11 is a cross-sectional view of the liquid crystal display device according to the eighth embodiment of the present invention, and is a cross-sectional view showing another embodiment of the pre-processing multiple liquid crystal display panel 40 shown in FIG. In addition, the same code | symbol is used for the same member. In the eighth embodiment, one drop sealing (ODF) method is used when injecting liquid crystal, and the single seal portion 33 has a closed shape without having an opening (liquid crystal injection port). ing. When the single liquid crystal display panel 39 is manufactured from the multiple liquid crystal display panels 40 before processing, the multiple liquid crystal display panels 40 before processing are bonded onto the dicing tape 10, and the counter substrate 31 and the single VLSI chip mounting substrate 11 are thickened. Perform full dicing to cut everything in the vertical direction. In full dicing, since the chipping or breakage of the outer periphery of the single liquid crystal display panel 39 can be prevented when cutting, the quality of the liquid crystal display device is improved.

  Further, in order to make electrical connection between the electrode on the counter substrate 31 of the single liquid crystal display panel 39 and the electrode on the non-defective single VLSI chip 6, a seal made of conductive resin or the like is provided separately from the single seal portion 33. A separate body conducting portion 45 is provided. Since the seal part separate conduction part 45 is a separate body from the single seal part 33, there is no restriction on the position and the application range is wide.

  In the eighth embodiment, first, a chip mounting composite substrate in which a plurality of non-defective thin single VLSI chips 6 are bonded onto a single VLSI chip mounting substrate 11 having a chip alignment mark 13 via a surface activation bonding layer 15. 16, a plurality of single seal portions 33 and separate seal portion conductive portions 45 are provided, the liquid crystal 36 is dropped on a region surrounded by the single seal portions 33, the counter substrate 31 is stacked, and pressurization and heating are performed. While performing, the ultraviolet-ray (UV light) is irradiated from the counter substrate 31 side, the single seal part 33 is hardened, and the multiple liquid crystal display panel 40 before a process is produced. Since it is better not to touch the liquid crystal, the separate seal portion conductive portion 45 is preferably provided outside the region surrounded by the single seal portion 33. Thereafter, an ultraviolet curable resin is applied to the outer periphery of the plurality of liquid crystal display panels 40 before processing to provide an outer peripheral seal portion 37, and ultraviolet rays are irradiated from the counter substrate 31 side to be cured.

  Next, the single VLSI chip mounting substrate 11 side of the plurality of liquid crystal display panels 40 before processing is bonded onto the dicing tape 10 to form a full dicing groove 27 at a predetermined position from the counter substrate 31 side. The full dicing grooves 27 cut all the counter substrate 31 and the single VLSI chip mounting substrate 11 in the thickness direction. Thereafter, a full dicing groove 28 is formed in the counter substrate 31 so that the terminal portion of the single good VLSI chip 6 is processed so as to project from the end surface of the counter substrate 32.

  As described above, it is possible to manufacture a single liquid crystal display panel 39 having a single seal portion 33 having no opening, good outer shape accuracy, and having good display quality with no outer peripheral chipping or breakage. Furthermore, since the dicing process can be performed only from the counter substrate 31 side, the plurality of liquid crystal display panels 40 before processing are not repeatedly bonded, peeled, bonded, and peeled to the dicing tape 10 multiple times. Stress can be reduced.

  Further, by making the seal part separate conduction part 45 separate from the single seal part 33, the seal part separate conduction part 45 can be formed in a portion where it does not come into contact with the liquid crystal 36, so the reliability of the liquid crystal display device is improved. Furthermore, since the thickness variation of the liquid crystal 36 due to the seal-part-specific body conducting portion 45 can be reduced, the display quality can also be improved.

  Next, a ninth embodiment will be described with reference to FIG. FIG. 12 is a cross-sectional view of the liquid crystal display device according to the ninth embodiment of the present invention, and shows another embodiment of the pre-processing multiple liquid crystal display panel 40 shown in FIG. In addition, the same code | symbol is used for the same member. In the ninth embodiment, a drop injection (ODF) method is used when injecting liquid crystal, and the single seal portion 33 is made of two types of seal materials, an insulating seal material and a conductive seal material. It is configured to be connected and has a closed shape without having an opening (liquid crystal injection port). In this configuration, the vertical conduction part that electrically connects the electrode on the counter substrate 31 and the electrode on the non-defective VLSI chip 6 at a position different from the single seal part 33 is separated from the single seal part 33. Since it is not necessary to provide it, the ratio of the display area of the non-defective VLSI chip 6 can be increased.

  In the ninth embodiment, first, a chip mounting composite substrate 16 in which a plurality of non-defective single VLSI chips 6 are bonded onto a single VLSI chip mounting substrate 11 having a chip alignment mark 13 via a surface activation bonding layer 15. A single seal portion 33 in which two kinds of conductive seal materials 30 including conductive particles are connected to a plurality of insulating seal materials and an insulating seal material is provided on a region surrounded by the single seal portion 33. The liquid crystal 36 is dropped, the counter substrate 31 is overlapped, and ultraviolet (UV light) is irradiated from the counter substrate 31 side while applying pressure and heating, and the single seal portion 33 is cured, thereby a plurality of liquid crystal displays before processing. Panel 40 is produced.

  Thereafter, an ultraviolet curable resin is applied to the outer periphery of the plurality of liquid crystal display panels 40 before processing to provide an outer peripheral seal portion 37, and cured by irradiating ultraviolet light from the counter substrate 31 side. In the present embodiment, when the outer peripheral seal portion 37 is irradiated with ultraviolet rays, a mask having an opening at a portion corresponding to the conductive seal material 30 of the single seal portion 33 is used as the counter substrate 31 of the plurality of liquid crystal display panels 40 before processing. The conductive sealing material 30 of the single seal portion 33 is irradiated with ultraviolet rays. This is intended to improve poor curing of the conductive sealing material 30 due to the conductive particles contained in the conductive sealing material 30 reducing the transmittance of ultraviolet rays.

  Next, the single VLSI chip mounting substrate 11 side of the plurality of liquid crystal display panels 40 before processing is bonded onto the dicing tape 10 with an adhesive material, and a full dicing groove 27 is formed at a predetermined position from the counter substrate 31 side. The full dicing grooves 27 cut all the counter substrate 31 and the single VLSI chip mounting substrate 11 in the thickness direction. Thereafter, a full dicing groove 28 is provided in the counter substrate 31 so that the terminal portion of the single good VLSI chip 6 is processed so as to project from the end surface of the counter substrate 32.

  As described above, it has a single seal portion 33 without an opening (liquid crystal injection port) where the insulating seal material and the conductive seal material 30 are connected, and the outer shape accuracy is good, and the outer periphery is not chipped or damaged. A single liquid crystal display panel with good display quality can be produced. Furthermore, since the dicing process can be performed only from the counter substrate 31 side, the plurality of liquid crystal display panels 40 before processing are not repeatedly bonded, peeled, bonded, and peeled to the dicing tape 10 multiple times. Stress can be reduced.

DESCRIPTION OF SYMBOLS 1 Mother VLSI substrate 2 Back surface polished mother VLSI substrate 5 Single VLSI chip 6 Good single VLSI chip 7 Dicing groove 8 Thin single VLSI chip 9 Good single thin VLSI chip 10 Dicing tape 11 Single VLSI chip mounting substrate 13 Chip alignment mark 15 Surface activated bonding layer 16 Chip-laden composite substrate 17 Inter-chip gap 20 Laser mark 23 Inter-chip gap filling material 25 Chip adhesive 27 Full dicing groove 30 Conductive sealing material 31 Counter substrate 33 Single seal part 36 Liquid crystal 39 Single liquid crystal display panel 40 Multiple liquid crystal display panels 45 before processing 45 Separate conductive part 51 for sealing part External circuit board 55 Aluminum wire 58 Conductive part for counter electrode

Claims (17)

A step of selectively placing a plurality of non-defective VLSI chips that are functionally non-defective on a VLSI chip mounting substrate;
Fixing the plurality of non-defective VLSI chips arranged on the VLSI chip mounting substrate on the VLSI chip mounting substrate;
Providing a single seal part on the plurality of non-defective VLSI chips fixed on the VLSI chip mounting substrate;
Bonding a counter substrate to the VLSI chip mounting substrate through the single seal portion;
Cutting the VLSI chip mounting substrate and the counter substrate bonded to each other in each region where the non-defective VLSI chip is provided;
Injecting liquid crystal into a region surrounded by the single seal part;
A method for manufacturing a liquid crystal display device, comprising:   2. The liquid crystal display according to claim 1, wherein a chip alignment mark is formed on the VLSI chip mounting substrate, and the non-defective VLSI chip is transferred onto the VLSI chip mounting substrate based on the chip alignment mark. Device manufacturing method.   3. The method of manufacturing a liquid crystal display device according to claim 1, wherein the non-defective VLSI chip is fixed on the VLSI chip mounting substrate by a surface activation bonding method.   4. The method of manufacturing a liquid crystal display device according to claim 3, wherein the back surface of the non-defective VLSI chip and the surface of the VLSI chip mounting substrate are polished, and the polished surfaces are fixed by a surface activated bonding method.   3. The method of manufacturing a liquid crystal display device according to claim 1, wherein the non-defective VLSI chip is fixed on the VLSI chip mounting substrate with an adhesive.   When the non-defective VLSI chip is disposed on the VLSI chip mounting substrate, the non-defective VLSI chip is disposed so that a gap is generated between the adjacent non-defective VLSI chips, and the gap is filled with a filler. A method for manufacturing a liquid crystal display device according to any one of claims 1 to 5.   Before placing the non-defective VLSI chip on the VLSI chip mounting substrate, the back surface of the non-defective VLSI chip is polished so that the thickness of the non-defective VLSI chip is smaller than the thickness of the VLSI chip mounting substrate. The method of manufacturing a liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device.   After fixing the non-defective VLSI chip on the VLSI chip mounting substrate, the non-defective VLSI chip is covered with a filler so as to fill a gap between the adjacent non-defective VLSI chips, and the surface of the filler is covered with the non-defective VLSI chip. The method of manufacturing a liquid crystal display device according to claim 1, wherein the surface is polished until the surface of the liquid crystal display device is exposed.   9. The method of manufacturing a liquid crystal display device according to claim 8, wherein the back surface of the VLSI chip mounting substrate is polished simultaneously with the polishing of the surface of the filler.   Before cutting the VLSI chip mounting substrate and the counter substrate bonded to each other, an outer peripheral seal portion surrounding the single seal portion is provided between the VLSI chip mounting substrate and the counter substrate. A method for manufacturing a liquid crystal display device according to claim 1. A good VLSI chip that is functionally good,
A VLSI chip mounting board on which the non-defective VLSI chip is mounted;
A counter substrate bonded on the non-defective VLSI chip through a single seal part;
Liquid crystal injected into a region surrounded by the single seal part;
A liquid crystal display device comprising:   12. The liquid crystal display device according to claim 11, wherein a thermal expansion coefficient of the non-defective VLSI chip and a thermal expansion coefficient of the VLSI chip mounting substrate are the same.   13. The liquid crystal display device according to claim 11, wherein a material of the non-defective VLSI chip and a material of the VLSI chip mounting substrate are the same.   The liquid crystal display device according to claim 11, wherein a thermal expansion coefficient of the non-defective VLSI chip and a thermal expansion coefficient of the counter substrate are the same.   A circuit board is connected to an outer periphery of the non-defective VLSI chip, and an outer periphery of the VLSI chip mounting substrate facing the outer periphery of the non-defective VLSI chip to which the circuit board is connected is the non-defective product to which the circuit board is connected. 15. The method according to any one of claims 11 to 14, wherein a filler is filled between the outer peripheral portion of the VLSI chip and the FPC between the outer peripheral portion of the VLSI chip mounting substrate and the FPC. A liquid crystal display device according to any one of the above.   The liquid crystal display device according to claim 11, wherein a heater unit for heating the liquid crystal is formed between the non-defective VLSI chip and the VLSI chip mounting substrate. .   17. The liquid crystal display according to claim 11, wherein a heater portion for heating the liquid crystal is formed on a surface of the VLSI chip mounting substrate on which the non-defective VLSI chip is not mounted. apparatus.

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