JP2003203938A - Manufacturing method of chip-type electronic component, and manufacturing method of dummy wafer employed for manufacturing the component - Google Patents

Manufacturing method of chip-type electronic component, and manufacturing method of dummy wafer employed for manufacturing the component

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Publication number
JP2003203938A
JP2003203938A JP2002003463A JP2002003463A JP2003203938A JP 2003203938 A JP2003203938 A JP 2003203938A JP 2002003463 A JP2002003463 A JP 2002003463A JP 2002003463 A JP2002003463 A JP 2002003463A JP 2003203938 A JP2003203938 A JP 2003203938A
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JP
Japan
Prior art keywords
chip
chips
manufacturing
adhesive
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002003463A
Other languages
Japanese (ja)
Inventor
Ayumi Senda
亜由美 仙田
Hiroyuki Fukazawa
博之 深澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2002003463A priority Critical patent/JP2003203938A/en
Publication of JP2003203938A publication Critical patent/JP2003203938A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a chip-type electronic component, such as a semiconductor chip utilizing the characteristic of package treatment of a wafer, and to provide a manufacturing method of a dummy wafer for the manufacturing of the component. <P>SOLUTION: The dummy wafer is manufactured through a process of bonding an adhesive means 102 onto a substrate 101, a process of fixing a plurality of pieces or a plurality of kinds of semiconductor chip 103 to the adhesive means, while facing the surface of an electrode downward, a process of degassing the adhesive surface of the semiconductor chip 103 and the adhesive means 102, a process of adhering a protective substance 107 over the whole surface, including the same between a plurality of pieces or kinds of the semiconductor chips 103 and a process of separating the dummy wafer 129, to which the semiconductor chip is adhered, by the protective substance 197. Air, pinched between the adhering surfaces, is removed to improve an adhesiveness between the chip 103 and the adhering means 102 to obtain the dummy wafer, which is high in the positioning accuracy of the chip 103, while being reduced in defects and high in the quality of the same, then, the chip-type electronic component 126 is manufactured at a low cost with superior reliability and a high yield, by cutting the dummy wafer into pieces to obtain the individual pieces of the same. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明が属する技術分野】本発明は、半導体装置の製造
に好適なチップ状電子部品の製造方法、並びにその製造
に用いる疑似ウェーハの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip-shaped electronic component suitable for manufacturing a semiconductor device, and a method for manufacturing a pseudo wafer used for the manufacturing.

【０００２】[0002]

【従来の技術】従来、デジタルビデオカメラやデジタル
携帯電話、更にノートＰＣ（PersonalComputer）等に代
表される携帯用電子機器の、小型化や薄型化、軽量化に
対する要求は強く、半導体部品の表面実装密度をいかに
向上させるかが重要なポイントである。この為、パッケ
ージＩＣ（ＱＦＰ（Quad Flat Package）等）に代る、
より小型のＣＳＰ（Chip Scale Package）の開発や一部
での採用が既に進められているが、究極の半導体高密度
実装を考えると、ベアチップ実装でしかもフリップチッ
プ方式による接続技術の普及が強く望まれる。2. Description of the Related Art Conventionally, there is a strong demand for downsizing, thinning, and weight reduction of portable electronic devices represented by digital video cameras, digital mobile phones, and notebook PCs (Personal Computers), and surface mounting of semiconductor components. How to improve the density is an important point. Therefore, instead of package ICs (QFP (Quad Flat Package), etc.),
Smaller CSP (Chip Scale Package) has already been developed and partly adopted, but considering ultimate semiconductor high-density mounting, widespread use of bare chip mounting and flip-chip connection technology is strongly desired. Be done.

【０００３】なお、上記フリップチップ実装におけるバ
ンプ形成技術には、一般にＡｌ電極パッド上にAu-Stud
Bump法や電解めっき法によってＡｕバンプを形成する方
法や、電解めっき法や蒸着法等ではんだバンプを一括し
て形成する方法が代表的である。しかし、民生用では、
より低コストのフリップチップ実装の場合に、チップに
してからバンプを形成(Au-Stud Bump法がその代表例で
ある。)するのではなく、ウェーハ状態で一括してバン
プを形成する方法が望ましい。In the bump forming technique in the flip chip mounting, Au-Stud is generally formed on the Al electrode pad.
A typical example is a method of forming Au bumps by the Bump method or electrolytic plating method, or a method of collectively forming solder bumps by an electrolytic plating method or a vapor deposition method. But for consumer use,
In the case of lower-cost flip-chip mounting, it is desirable to form bumps in a wafer state at once instead of forming bumps after forming them into chips (Au-Stud Bump method is a typical example). .

【０００４】このようなウェーハ一括処理法は、近年の
ウェーハの大口径化（１５０ｍｍφ→２００ｍｍφ→３
００ｍｍφ）と、ＬＳＩ（大規模集積回路）チップの接
続ピン数の増加傾向とを考えれば、当然の方向性であ
る。Such a batch processing method for wafers is used in recent years to increase the diameter of wafers (150 mmφ → 200 mmφ → 3
00 mmφ) and an increasing tendency of the number of connecting pins of LSI (Large Scale Integrated Circuit) chips, this is a natural directionality.

【０００５】以下に、従来のバンプ形成方法を説明す
る。A conventional bump forming method will be described below.

【０００６】図７は、Ａｕスタッドバンプ（Stud Bum
p）２４の一例である。各々、個片に切り出された半導
体チップ２５のＡｌ電極パッド５５面にワイヤーボンデ
ィング手法を用いてＡｕスタッドバンプ（Stud Bump）
２４が形成されている。図８は、例えば入出力回路２
２、素子領域（メモリー）２３が形成されたＳｉ基板
（ウェーハ）５１を、ウェーハレベルで一括処理して形
成したときのはんだバンプ６２の一例である（なお、図
中の２１はスクライブラインである。）。FIG. 7 shows an Au stud bump (Stud Bum).
p) 24 is an example. Au stud bumps (Stud Bump) are formed on the surface of the Al electrode pad 55 of the semiconductor chip 25, which is cut into individual pieces, using a wire bonding method.
24 are formed. FIG. 8 shows, for example, the input / output circuit 2
2. An example of the solder bump 62 when the Si substrate (wafer) 51 on which the element region (memory) 23 is formed is collectively processed at the wafer level (21 in the drawing is a scribe line. .).

【０００７】また、図９には、より低コストを目指し
て、Ｎｉ無電解めっきとはんだペーストの印刷とでウェ
ーハ一括でバンプを形成する工程を示す。図９（ａ）
は、ＳｉＯ2膜が形成されたＳｉ基板（ウェーハ）を示
し、同図（ｂ）はその電極を含むチップ部分を拡大した
ものである。図９（ａ）、（ｂ）において、５１はＳｉ
基板（ウェーハ）、５５はＡｌ電極パッド、その他はＳ
ｉＯ2膜、Ｓｉ3Ｎ4、ＳｉＯ2膜やポリイミド膜から成る
パッシベーション膜である。Further, FIG. 9 shows a step of forming bumps on a wafer at a time by Ni electroless plating and solder paste printing, aiming at lower cost. FIG. 9 (a)
Shows a Si substrate (wafer) on which a SiO 2 film is formed, and FIG. 6B is an enlarged view of a chip portion including the electrode. In FIGS. 9A and 9B, 51 is Si
Substrate (wafer), 55 is Al electrode pad, other is S
It is a passivation film made of an iO 2 film, a Si 3 N 4 , a SiO 2 film and a polyimide film.

【０００８】図９（ｃ）では、Ｎｉ無電解めっき法によ
り、開口されたＡｌ電極パッド５５の上面のみに、選択
的にＮｉ無電解めっき層（ＵＢＭ：Under Bump Metal）
が形成されている。このＮｉ無電解めっき層（ＵＢＭ）
は、Ａｌ電極パッド５５面をリン酸系エッチ液で前処理
した後に、Ｚｎ処理によりＺｎを置換析出させ、更に、
Ｎｉ−Ｐめっき槽に浸漬することによって容易に形成で
き、Ａｌ電極パッド５５とはんだバンプとの接続を助け
るＵＢＭとして作用する。In FIG. 9C, a Ni electroless plating method is used to selectively form a Ni electroless plating layer (UBM: Under Bump Metal) only on the upper surface of the opened Al electrode pad 55.
Are formed. This Ni electroless plating layer (UBM)
Is prepared by subjecting the surface of the Al electrode pad 55 to pretreatment with a phosphoric acid-based etchant and then performing Zn treatment to substitute and deposit Zn.
It can be easily formed by immersing it in a Ni-P plating bath, and acts as a UBM that helps the connection between the Al electrode pad 55 and the solder bump.

【０００９】図９（ｄ）は、メタルスクリーンマスク５
２を当てて、はんだペースト５９を印刷法によりＮｉ無
電解めっき層（ＵＢＭ）上に転写した状態を示す。図９
（ｅ）は、ウエットバック（加熱溶融）法ではんだペー
スト５９を溶融して、はんだバンプ６２を形成したもの
である。このように、Ｎｉ無電解めっき法及びはんだペ
ーストスクリーン印刷法等を用いることにより、フォト
プロセスを用いずに、簡単にはんだバンプ６２を形成す
ることができる。FIG. 9D shows a metal screen mask 5
2 shows a state in which the solder paste 59 is transferred onto the Ni electroless plating layer (UBM) by a printing method by applying 2. Figure 9
In (e), the solder paste 59 is melted by the wet back (heating and melting) method to form the solder bumps 62. As described above, by using the Ni electroless plating method, the solder paste screen printing method, or the like, the solder bumps 62 can be easily formed without using a photo process.

【００１０】上記のはんだペースト５９に代えて、金属
ボール（はんだボール）を用いてはんだバンプを形成す
ることもできる。即ち、Ｎｉ無電解めっき層（ＵＢＭ）
の上にフラックスを印刷法等により塗布する。次に、金
属ボールをフラックス上に載置して金属ボールのリフロ
ー（加熱溶融）を行い、フラックスの洗浄を行う。これ
により、金属ボールはＮｉ無電解めっき層（ＵＢＭ）に
強く付着し、これを以ってバンプ電極の形成は完了す
る。Instead of the solder paste 59, metal balls (solder balls) may be used to form the solder bumps. That is, Ni electroless plating layer (UBM)
The flux is applied onto the top surface by a printing method or the like. Next, the metal balls are placed on the flux to reflow (heat and melt) the metal balls to clean the flux. As a result, the metal balls adhere strongly to the Ni electroless plating layer (UBM), and the formation of bump electrodes is completed.

【００１１】他方、ＣＳＰは、１ケ１ケのＬＳＩをいか
に小さくして高密度で実装するかのアプローチである
が、デジタル機器の回路ブロックを見た場合、いくつか
の共通回路ブロックで成り立っており、これらをマルチ
チップパッケージとしたり、モジュール化（ＭＣＭ：Mu
lti Chip Module）する技術も登場している。デジタル
携帯電話におけるＳＲＡＭ（スタティック・ラム）、フ
ラッシュメモリー、マイコンの１パッケージ化等はその
一例である。On the other hand, CSP is an approach of how to reduce the size of one LSI and package it at a high density. When looking at the circuit blocks of digital equipment, it consists of several common circuit blocks. We have made these into a multi-chip package or modularized (MCM: Mu
Lti Chip Module) technology has also appeared. An example is SRAM (static RAM), flash memory, and one package of a microcomputer in a digital mobile phone.

【００１２】このＭＣＭ技術は、最近の１チップシステ
ムＬＳＩにおいても大きな利点を発揮するものと期待さ
れている。即ち、メモリーやロジック、更にアナログＬ
ＳＩを１チップ化する場合は、異なったＬＳＩ加工プロ
セスを同一ウェーハプロセスで処理することとなり、マ
スク数や工程数の著しい増加と開発ＴＡＴ（Turnaround
time）の増加が問題となり、歩留りの低下も大きな懸
念材料である。This MCM technology is expected to exert a great advantage even in the recent one-chip system LSI. That is, memory, logic, and analog L
When SI is made into one chip, different LSI processing processes are processed in the same wafer process, which significantly increases the number of masks and processes and the development TAT (Turnaround).
increase in time) becomes a problem, and the decrease in yield is also a major concern.

【００１３】このために、各ＬＳＩを個別に作り、ＭＣ
Ｍ化する方式が有力視されている。こうしたＭＣＭ化技
術の例を図１０に示す。For this purpose, each LSI is individually manufactured and MC
The method of converting to M is considered to be the most promising. An example of such MCM technology is shown in FIG.

【００１４】図１０（ａ）、（ｂ）、（ｃ）はフリップ
チップ方式であって、回路基板６０上の電極６３にフェ
イスダウンでチップ６４を接続している。より小型化、
薄型化を考えた場合には、図１０のフリップチップが有
利な方式となっている。今後の高速化での接続距離の縮
小や各接続インピーダンスのバラツキを考えても、フリ
ップチップ方式が主流になるものと思われる。10 (a), 10 (b) and 10 (c) show a flip-chip method in which a chip 64 is connected face down to an electrode 63 on a circuit board 60. Smaller size,
The flip chip of FIG. 10 is an advantageous method in consideration of thinning. The flip-chip method is expected to become the mainstream in consideration of the reduction in connection distance and variations in connection impedance in the future increase in speed.

【００１５】フリップチップ方式のＭＣＭでは、複数の
異種ＬＳＩについて各々のＡｌ電極パッド５５の面にＡ
ｕ−Ｓｔｕｄ Ｂｕｍｐを形成し、異方性導電フィルム
（ＡＣＦ：Aniso Conductive Film）を介して回路基板
と接続する方法や、樹脂ペーストを用いて圧接する方
法、更にバンプとしてＡｕめっきバンプやＮｉ無電解め
っきバンプ、はんだバンプを用いる方法等、種々のもの
が提案されている。図１０（ｃ）は、はんだバンプ６５
による基板６０との金属間接合で、より低抵抗で確実に
接合させた例である。In the flip-chip type MCM, A is formed on the surface of each Al electrode pad 55 for a plurality of heterogeneous LSIs.
A method of forming a u-Stud Bump and connecting it to a circuit board through an anisotropic conductive film (ACF), a method of pressure welding using a resin paste, and an Au plating bump or a Ni electroless bump as a bump. Various methods such as a method using plated bumps and solder bumps have been proposed. FIG. 10C shows the solder bump 65.
This is an example in which the metal-to-metal bonding with the substrate 60 is performed with lower resistance and reliably.

【００１６】[0016]

【発明に至る経過】上記した各バンプ形成法は既に完成
されていて、量産ベースの技術として活用が始まってい
る。例えば、図７に示したＡｕスタッドバンプ２４はチ
ップ単位のバンプ形成法であり、既存の設備を用いて、
より簡便にバンプを形成する方法として広く用いられて
いるが、各端子毎にバンプ形成処理を行うので、多ピン
になる程、バンプ形成に要するコストが上昇してしま
う。Progress to the Invention Each of the above bump forming methods has already been completed and is now being used as a mass-production-based technique. For example, the Au stud bump 24 shown in FIG. 7 is a bump forming method for each chip, and using existing equipment,
It is widely used as a method for forming bumps more simply, but since bump formation processing is performed for each terminal, the cost required for bump formation increases as the number of pins increases.

【００１７】また、最近のＬＳＩの低電圧駆動において
は、Ａｌ配線層の電圧降下の問題が生じることから、周
辺の電極パッドの配置だけでなく、アクティブ素子上に
も電極パッドを配置したエリアパッドが必要とされる
が、図７のＡｕスタッドバンプ２４はボンディング荷重
とダメージの面からエリアパッドには不向きである。更
に、Ａｕスタッドバンプチップの実装は、１個ずつの圧
接工法であることや、両面実装に難がある等の問題を抱
えている。In addition, since the problem of voltage drop in the Al wiring layer occurs in low voltage driving of recent LSIs, not only the arrangement of the peripheral electrode pads but also the area pad in which the electrode pads are arranged also on the active element. However, the Au stud bump 24 of FIG. 7 is not suitable for the area pad in terms of bonding load and damage. Furthermore, the mounting of the Au stud bump chips has problems such as a pressure welding method for each one and difficulty in double-sided mounting.

【００１８】一方、ウェーハ一括のはんだバンプ形成法
は実装面でエリアパッド配置にも適用でき、一括リフロ
ーや両面実装が可能である等の利点がある。しかし、最
先端の歩留まりが低いウェーハに対して処理をすると、
良品チップ１個当たりのコストは極めて高くなる。On the other hand, the method of forming solder bumps on a wafer at a time is advantageous in that it can be applied to the area pad arrangement on the mounting surface, and batch reflow and double-sided mounting are possible. However, when processing the latest wafers with low yield,
The cost per good chip is extremely high.

【００１９】即ち、図１１には、従来のウェーハ一括処
理における半導体ウェーハ５３を示すが、最先端ＬＳＩ
では高歩留りが必要とされるにも拘らず、スクライブラ
イン２１で仕切られたチップの内、×印で示す不良品チ
ップ２０の数が○印で示す良品チップ３の数より多くな
るのが実情である。That is, FIG. 11 shows a semiconductor wafer 53 in the conventional batch processing of wafers.
In spite of the fact that a high yield is required, the number of defective chips 20 indicated by X is larger than the number of non-defective chips 3 indicated by ○ in the chips partitioned by the scribe line 21. Is.

【００２０】また、図１１に示した半導体ウェーハ５３
をスクライブライン２１に沿って切断すると、切断の影
響でチップにストレス、亀裂等のダメージが生じて、故
障の原因になることがある。そして、良品ベアチップ３
及び不良品ベアチップ２０を共に半導体ウェーハ５３と
して一括ではんだバンプ形成まで工程を進行させると、
不良品ベアチップ２０に施した工程が無駄になり、これ
もコストアップの原因となる。Further, the semiconductor wafer 53 shown in FIG.
If is cut along the scribe line 21, the chip may be damaged by stress, cracks or the like due to the cutting, which may cause a failure. And good bare chip 3
When the defective bare chips 20 are collectively used as the semiconductor wafer 53 to proceed to the solder bump formation,
The process performed on the defective bare chip 20 is wasted, which also causes an increase in cost.

【００２１】また、チップをベアチップの形で他所から
入手した場合のバンプ形成は極めて難しいという問題が
あった。Further, there is a problem that it is extremely difficult to form bumps when the chip is obtained from another place in the form of a bare chip.

【００２２】即ち、上記した２種類のバンプ形成方法は
各々特徴を持つが、全ての領域に使える技術ではなく、
各々の特徴を活かした使い分けをされるのが現状であ
る。Ａｕスタッドバンプは、チップ単位で入手した場合
のバンプ処理や、簡便なバンプ処理に特徴を発揮する。
又、ウェーハ一括バンプ処理法は、歩留まりが高く、ウ
ェーハ１枚の中に占める端子数が多い場合（例えば５０
０００端子／ウェーハ）や、エリアパッド対応の低ダメ
ージバンプ形成に特徴を発揮する。That is, although the above-mentioned two types of bump forming methods have their respective characteristics, they are not technologies that can be used in all areas.
The current situation is that they are used properly by taking advantage of each feature. The Au stud bump is characterized by bump processing when it is obtained in chip units and simple bump processing.
In addition, the wafer batch bump processing method has a high yield and a large number of terminals in one wafer (for example, 50
000 terminals / wafer) and low damage bump formation for area pads.

【００２３】特開平９−２６０５８１号公報には、Ｓｉ
ウェーハ上に複数の半導体チップを接着固定し、これを
アルミナの如き基板上に設けた樹脂に加圧下で埋め込ん
でから剥離することにより、ウェーハの表面を平坦に
し、ホトリソグラフィの技術によりこのウェーハ上で素
子間の接続用の配線層を形成する方法が示されている。Japanese Unexamined Patent Publication No. 9-260581 discloses that Si
A plurality of semiconductor chips are bonded and fixed on a wafer, embedded in a resin such as alumina under pressure on a substrate under pressure, and then peeled off to make the surface of the wafer flat and the photolithography technique Describes a method of forming a wiring layer for connection between elements.

【００２４】この公知の方法によれば、ウェーハの一括
処理が可能となり、大量生産による低価格化を達成でき
るとしているが、ウェーハにおいて個々の半導体チップ
の裏面側には上記のアルミナの如き硬質の基板が存在し
ているために、スクライビング時にチップ間の樹脂と共
に、裏面側の硬質の基板も切断しなければならず、切断
用のブレードが破損するおそれがある。しかも、チップ
の側面は樹脂で覆われてはいるが、裏面は樹脂とは異質
の硬質の基板が存在しているだけであるため、チップの
裏面側は有効に保護されないことがあり、また両者間の
密着性が悪くなる。According to this known method, the wafers can be collectively processed, and the cost can be reduced by mass production. However, on the back surface side of each semiconductor chip in the wafer, a hard material such as the above alumina is used. Since the substrate is present, the hard substrate on the back side must be cut together with the resin between the chips during scribing, and the cutting blade may be damaged. Moreover, although the side surface of the chip is covered with resin, the back surface of the chip may not be effectively protected because only the hard substrate, which is different from resin, exists on the back surface. Adhesion between them becomes poor.

【００２５】先に本出願人は、上記のような問題点を解
決する方法として、特開２００１−３０８１１６号公報
に、ウェーハ一括処理の特徴を生かしつつ、最先端のＬ
ＳＩやベアチップで入手した場合でも、高歩留り、低コ
ストにして信頼性良く提供可能な半導体チップ等のチッ
プ状電子部品、並びにその製造方法を提案した。As a method of solving the above-mentioned problems, the present applicant has made use of the feature of wafer batch processing in Japanese Patent Laid-Open No. 2001-308116, and at the same time, state-of-the-art L
The present invention has proposed a chip-like electronic component such as a semiconductor chip that can be provided with high yield, low cost, and high reliability even when obtained as an SI or bare chip, and a manufacturing method thereof.

【００２６】即ち、特開２００１−３０８１１６号公報
に係る発明（以下、先願発明と称する。）は、少なくと
も電極が一方の面側にのみ設けられ、この一方の面以外
の全面が連続した保護物質で覆われている半導体チップ
の如きチップ状電子部品、並びに、このチップ状電子部
品の複数個又は複数種が、これらの間及びその裏面に連
続して被着された保護物質によって互いに固着されてい
る疑似ウエーハに係るものである。That is, in the invention according to Japanese Patent Application Laid-Open No. 2001-308116 (hereinafter referred to as prior invention), at least an electrode is provided only on one surface side, and the entire surface other than this one surface is continuously protected. A chip-shaped electronic component such as a semiconductor chip covered with a substance, and a plurality or a plurality of types of the chip-shaped electronic component are fixed to each other by a protective substance continuously applied between them and on the back surface thereof. It is related to the pseudo wafer.

【００２７】また、先願発明は、基板上に粘着手段を貼
り付ける工程と、この粘着手段の上に複数個又は複数種
の半導体チップをその電極面を下にして固定する工程
と、保護物質を複数個又は複数種の半導体チップ間を含
む全面に被着する工程と、保護物質によって半導体チッ
プを固着した疑似ウエーハを剥離する工程とを有する、
疑似ウエーハの製造方法に係わり、更にこれに加えて、
前記複数個又は複数種の半導体チップ間において保護物
質を切断して各半導体チップ又はチップ状電子部品を分
離する工程とを有する、チップ状電子部品の製造方法を
も提供するものである。In the prior invention, a step of attaching an adhesive means on a substrate, a step of fixing a plurality of or a plurality of types of semiconductor chips on the adhesive means with their electrode surfaces facing down, and a protective substance And a step of depositing the entire surface including a plurality of or a plurality of types of semiconductor chips, and a step of peeling off the pseudo wafer to which the semiconductor chips are fixed by a protective substance.
In connection with the manufacturing method of the pseudo wafer, in addition to this,
The present invention also provides a method for manufacturing a chip-shaped electronic component, which comprises a step of cutting a protective material between the plurality of or a plurality of types of semiconductor chips to separate each semiconductor chip or the chip-shaped electronic component.

【００２８】図１２に先願発明に基づく疑似ウエーハの
製造方法の一例を示す。FIG. 12 shows an example of a method for manufacturing a pseudo wafer according to the invention of the prior application.

【００２９】まず、図１２（ａ）に示す仮の支持基板と
しての石英基板１上に、図１２（ｂ）のように粘着シー
ト２を貼り付ける。First, as shown in FIG. 12B, the adhesive sheet 2 is attached onto the quartz substrate 1 as a temporary supporting substrate shown in FIG. 12A.

【００３０】次に、図１２（ｃ）のように、良品と確認
された複数個の良品ベアチップ３を、その電極面（デバ
イス面）２８を下にして、粘着シート２の上に配列し、
固定する。Next, as shown in FIG. 12C, a plurality of non-defective non-defective bare chips 3 are arrayed on the adhesive sheet 2 with their electrode surfaces (device surfaces) 28 facing down.
Fix it.

【００３１】次に、図１２（ｄ）のように、ベアチップ
３の上から保護物質、例えばアクリル系等の樹脂４を流
し込み、複数のベアチップ間を含む全面に被着する。樹
脂４を硬化させる。Next, as shown in FIG. 12 (d), a protective substance, for example, a resin 4 such as an acrylic resin is poured from above the bare chip 3 and deposited on the entire surface including a plurality of bare chips. The resin 4 is cured.

【００３２】しかる後、図１２（ｅ）のように、樹脂４
で側面及び裏面が連続して固着され、複数の良品ベアチ
ップ３が一体化した疑似ウエーハ２９を石英基板１から
接着面３０で剥離する。この剥離には、基板１側から紫
外線を照射したり、或いは加熱によって、粘着シート２
の粘着剤の粘着力を低下させる。Then, as shown in FIG. 12 (e), the resin 4
Then, the side surface and the back surface are continuously fixed, and the pseudo wafer 29 in which the plurality of non-defective bare chips 3 are integrated is separated from the quartz substrate 1 at the bonding surface 30. For this peeling, the pressure-sensitive adhesive sheet 2 is irradiated with ultraviolet rays from the substrate 1 side or by heating.
To reduce the adhesive strength of the adhesive.

【００３３】続いて、疑似ウエーハ２９に対してウエー
ハ一括でのはんだバンプ処理等を行った後、チップを個
々の個片に切り分け、実装基板にマウントする。これら
の工程の詳細は、後に記す実施の形態１での記述と重複
するので、ここでは省略する。Subsequently, the dummy wafer 29 is subjected to solder bump processing and the like in a batch of wafers, and then the chip is cut into individual pieces and mounted on a mounting board. Details of these steps are the same as those in Embodiment 1 described later, and thus are omitted here.

【００３４】図１３は、良品と確認されたベアチップ３
のみを、円形の石英基板１上に粘着シート２を介して等
間隔に配列して貼り付けた一例である。また、円形の石
英基板１に替えて、角形のより大きなガラス基板を用
い、より多数の良品チップからなる疑似ウエーハを製造
し、その後の工程におけるウエーハ一括処理のコストメ
リットをより一層発揮することもできる。なお、これら
の基板は繰り返し使用できて、バンプ形成のコストや環
境面でも有利である。FIG. 13 shows a bare chip 3 which is confirmed to be a good product.
This is an example of arranging and bonding only the same on a circular quartz substrate 1 with an adhesive sheet 2 interposed therebetween. Further, instead of the circular quartz substrate 1, a larger square glass substrate may be used to manufacture a pseudo wafer composed of a larger number of non-defective chips, and the cost advantage of batch processing of wafers in subsequent steps may be further exerted. it can. It should be noted that these substrates can be repeatedly used, which is advantageous in terms of bump formation cost and environment.

【００３５】この先願発明によれば、半導体ウエーハか
ら切出されたチップのうち、良品チップ３のみを選択し
て基板１に貼り付け、保護物質４を全面に被着した後に
剥離することにより、あたかも良品チップのみからなる
ウエーハのような疑似ウエーハ２９を得るので、良品チ
ップのみに対するウエーハ一括でのはんだバンプ処理等
が可能となり、低コストで歩留り良く、フリップチップ
用はんだバンプチップを形成することができる。According to the invention of the prior application, among the chips cut out from the semiconductor wafer, only the good chips 3 are selected and attached to the substrate 1, and the protective substance 4 is deposited on the entire surface and then peeled off. Since a pseudo wafer 29 such as a wafer composed of only non-defective chips is obtained, solder bump processing or the like can be performed on the non-defective chips at one time, and the solder bump chips for flip chips can be formed at low cost and with good yield. it can.

【００３６】また、半導体チップ等のチップ状電子部品
（以下、半導体チップ３を代表例として説明する。）の
電極面以外の面（即ち、チップ側面及び裏面）は、連続
した保護物質４によって保護されるので、Ｎｉ無電解め
っき処理も可能である。また、チップの個片化後の実装
ハンドリングにおいても、チップが保護され、良好な実
装信頼性が得られる。Surfaces other than the electrode surfaces (that is, the chip side surface and the back surface) of a chip-shaped electronic component such as a semiconductor chip (hereinafter, the semiconductor chip 3 will be described as a typical example) are protected by a continuous protective substance 4. Therefore, Ni electroless plating treatment is also possible. Further, the chip is protected even in the mounting handling after the chip is divided into individual pieces, and good mounting reliability is obtained.

【００３７】その上、チップ状電子部品を疑似ウエーハ
２９から切り出す際に、チップ３間の保護物質４の部分
を切断するので、チップ状電子部品本体への悪影響（歪
みやばり、亀裂等のダメージ）が抑えられる。In addition, when the chip-shaped electronic component is cut out from the pseudo wafer 29, the portion of the protective material 4 between the chips 3 is cut, so that the chip-shaped electronic component body is adversely affected (damage such as distortion, burrs, and cracks). ) Is suppressed.

【００３８】さらに、自社製ウエーハのみならず、他社
から購入したベアチップでも、容易にはんだバンプ処理
等が可能になる。また、ＭＣＭに搭載される異種ＬＳＩ
チップを全て同一半導体メーカーから供給されるケース
は少なく、最先端の半導体ラインの投資が大きくなって
きているために、ＳＲＡＭ、フラッシュメモリーやマイ
コン、更にＣＰＵ（中央演算処理ユニット）を同一半導
体メーカーで供給するのではなく、各々得意とする半導
体メーカーから別々にチップで供給してもらい、これら
をＭＣＭ化することもできる。Further, not only in-house manufactured wafers but also bare chips purchased from other companies can be easily subjected to solder bump processing and the like. Also, heterogeneous LSI mounted on MCM
It is rare for all chips to be supplied from the same semiconductor maker, and investment in cutting-edge semiconductor lines is increasing. Therefore, SRAM, flash memory, microcomputer, and CPU (Central Processing Unit) are manufactured by the same semiconductor maker. Instead of supplying it, it is also possible to have each semiconductor manufacturer who is good at supplying it separately as a chip and convert these into MCM.

【００３９】[0039]

【発明が解決しようとする課題】しかしながら、これら
の優れた特長をもつ上記先願発明にも解決すべき問題点
があることが明らかになった。これについて、以下に説
明する。However, it has become clear that the above-mentioned prior inventions having these excellent features also have problems to be solved. This will be described below.

【００４０】上記した粘着手段としての粘着シート２
に、例えば「リバアルファ（日東電工社製）」のよう
に、厚さが１０μｍ程度の薄い微粘着性アクリル系粘着
材を用いた場合、厚さが例えば４００μｍもある厚い半
導体チップ３とは密着しにくいことがある。そのため、
粘着材の上に半導体チップを固定する時、図１４（ａ）
に示すように、チップ３と粘着材２との粘着面に空気１
００ａを挟み込んでしまうことがある。Adhesive sheet 2 as the above-mentioned adhesive means
In addition, when a thin slightly adhesive acrylic adhesive material having a thickness of about 10 μm is used, such as “Riva Alpha (manufactured by Nitto Denko Corporation)”, it adheres to a thick semiconductor chip 3 having a thickness of, for example, 400 μm. It may be difficult to do. for that reason,
When fixing the semiconductor chip on the adhesive material, as shown in FIG.
As shown in Fig. 1, air 1 is attached to the adhesive surface between the chip 3 and the adhesive material 2.
00a may be caught.

【００４１】このように粘着面に空気を挟み込んだま
ま、保護物質、例えばアクリル系等の樹脂４をチップ３
間を含む全面に流し込んで被着しようとすると、樹脂４
の流動でチップ３が動いてしまうこと（位置ずれ）があ
る。また、樹脂４を真空排気によって脱泡する時、図１
４（ｂ）に示すように、粘着面に挟み込まれていた空気
１００ａが膨張してチップ３を持ち上げたり、外へ逃げ
ようとする空気がチップ３周辺にボイド（空隙）１００
ｂを形成したりする。In this way, with the air sandwiched between the adhesive surfaces, a protective substance, for example, an acrylic resin 4 is applied to the chip 3
If you try to apply it over the entire surface including the space, resin 4
There is a case where the chip 3 moves due to the flow of (positional deviation). In addition, when the resin 4 is degassed by evacuation,
As shown in FIG. 4 (b), the air 100a sandwiched between the adhesive surfaces expands to lift the chip 3 or to escape to the outside.
b is formed.

【００４２】このように、空気１００ａがチップを持ち
上げると、半導体チップ３の電極パッドの部分に未硬化
の樹脂４が入り込んでしまい、樹脂４を硬化させた後に
疑似ウエーハ２９を剥離してみると、電極パッドが樹脂
４で覆われてしまっていて、電極パッドと外部（例えば
配線回路基板）との導通を取ることのできない状態、又
は、電極パッドとの接続部が高抵抗の状態になってしま
うことがある。In this way, when the air 100a lifts the chip, the uncured resin 4 enters the electrode pad portion of the semiconductor chip 3, and when the resin 4 is cured, the pseudo wafer 29 is peeled off. , The electrode pad is covered with the resin 4 and the electrode pad cannot be electrically connected to the outside (for example, a wiring circuit board), or the connection portion with the electrode pad is in a high resistance state. It may end up.

【００４３】また、空気がチップ３周辺にボイド１００
ｂを形成する場合、樹脂４を硬化させた後に疑似ウエー
ハ２９を剥離してみると、半導体チップ３の周囲の疑似
ウエーハ２９表面（剥離面）にボイド１００ｂが残され
ていることがあり、その場合は、ウエーハ表面上での再
配線をチップ３間に施す際に、レジストを均一かつ安定
に塗布することができず、レジストがボイド１００ｂの
部分ではじかれたり、凹凸になったり、このために後続
の配線工程で結線不良や短絡を生じる原因になる。In addition, air causes voids 100 around the chip 3.
In the case of forming b, when the pseudo wafer 29 is peeled off after the resin 4 is cured, the void 100b may be left on the surface (peeling surface) of the pseudo wafer 29 around the semiconductor chip 3. In this case, when rewiring on the surface of the wafer is performed between the chips 3, the resist cannot be applied uniformly and stably, and the resist is repelled or uneven in the void 100b. In addition, it may cause connection failure or short circuit in the subsequent wiring process.

【００４４】但し、図１４（ｃ）に示すように、粘着材
２の厚さを厚くすると、粘着材２とチップ３とは密着し
やすくなり、粘着面に空気を挟み込むことは少なくなる
が、チップ３が粘着材２に沈み込むことになるため、樹
脂４を硬化させた後に、疑似ウエーハ２９を剥離してみ
ると、半導体チップ３の電極面と樹脂４との境界に段差
を生じることになる。この場合も、レジスト塗布を良好
に行えず、後続の配線工程で配線不良を生じる原因にな
る。However, as shown in FIG. 14 (c), when the thickness of the adhesive material 2 is increased, the adhesive material 2 and the chip 3 are easily adhered to each other, and air is less likely to be trapped in the adhesive surface. Since the chip 3 sinks into the adhesive material 2, if the pseudo wafer 29 is peeled off after the resin 4 is cured, a step may be formed at the boundary between the electrode surface of the semiconductor chip 3 and the resin 4. Become. Also in this case, the resist coating cannot be satisfactorily performed, which causes wiring failure in the subsequent wiring process.

【００４５】本発明の目的は、上記のような実情に鑑
み、先願発明の特長を生かしつつ、チップと粘着手段と
の粘着を空気の挟み込み等なしに良好に行い、チップを
覆う樹脂等の保護物質にボイドを発生させることなし
に、高歩留り、低コストにして信頼性良く半導体チップ
等のチップ状電子部品を製造する方法、並びにその製造
に用いる疑似ウェーハの製造方法を提供することにあ
る。In view of the above situation, the object of the present invention is to make good use of the features of the invention of the prior application, to perform good adhesion between the chip and the adhesive means without entrapment of air, etc. It is to provide a method for manufacturing a chip-shaped electronic component such as a semiconductor chip with high yield, low cost and reliability without generating voids in a protective material, and a method for manufacturing a pseudo wafer used for the manufacturing. .

【００４６】[0046]

【課題を解決するための手段】即ち、本発明は、基体上
に粘着手段を貼り付け等により設ける工程と、この粘着
手段の上に複数個又は複数種の半導体チップ又はチップ
部品等（以下、単にチップと称することがある。）を特
にその電極面を下にして固定する工程と、前記チップと
前記粘着手段との粘着面を脱ガスする工程と、保護物質
を前記複数個又は複数種のチップ間を含む全面に被着す
る工程と、前記保護物質によって前記チップを固着した
疑似ウエーハを剥離する工程と有する疑似ウエーハの製
造方法に係わり、更にこれに加えて、前記複数個又は複
数種のチップ間において前記保護物質を切断して各半導
体チップ又はチップ部品等からなるチップ状電子部品を
分離する工程を有する、チップ状電子部品の製造方法も
提供するものである。That is, according to the present invention, a step of providing an adhesive means on a substrate by pasting or the like, and a plurality of or a plurality of types of semiconductor chips or chip parts etc. on the adhesive means (hereinafter, referred to as May be simply referred to as a chip.), Especially with its electrode surface facing downward, a step of degassing the adhesive surface between the chip and the adhesive means, and a protective substance of the plurality or plural types. It relates to a method for producing a pseudo wafer having a step of adhering to the entire surface including between chips and a step of peeling off the pseudo wafer to which the chips are fixed by the protective substance, and in addition to this, a plurality of or a plurality of kinds of the above Also provided is a method for manufacturing a chip-shaped electronic component, which has a step of cutting the protective substance between chips to separate a chip-shaped electronic component including each semiconductor chip or chip component. .

【００４７】本発明によれば、前記粘着手段の上に前記
チップ（以下、半導体チップを代表例とする。）を固定
する際、前記粘着面を脱ガスする工程を行うので、前記
粘着手段の厚みや材料等をこれまでのものから変更する
ことなしに、チップと前記粘着手段との密着性を向上さ
せ、前記チップを安定して前記粘着手段上に固定するこ
とができ、前記保護物質を被着する際に前記チップが位
置ずれすることがなく、前記疑似ウエーハにおける前記
チップの位置決め精度を向上させることができる。According to the present invention, the step of degassing the adhesive surface is performed when the chip (hereinafter, a semiconductor chip is a typical example) is fixed on the adhesive means. It is possible to improve the adhesion between the chip and the adhesive means without changing the thickness, material, etc., so that the chip can be stably fixed on the adhesive means, and the protective substance is used. It is possible to improve the positioning accuracy of the chip on the pseudo wafer without the displacement of the chip during the deposition.

【００４８】また、前記粘着面に挟み込まれていた空気
等のガスを取り除いてから樹脂などの前記保護物質を前
記チップ間を含む全面に被着する工程を行うので、前記
保護物質を排気によって脱泡する時、前記粘着面に挟み
込まれていた空気が膨張して前記チップを持ち上げた
り、外に逃げようとする空気がチップ周辺にボイドを形
成したりすることはない。このため、前記チップの電極
パッドの部分に未硬化の保護物質が入り込んでしまうこ
とによる電極パッドでの導通不良は起こらない。また、
前記チップの周囲の疑似ウエーハ表面にボイドが残るこ
とはなく、ボイドに起因するレジスト塗布の不良が生じ
ることもなく、配線を良好に施すことができる。Further, since the step of removing the gas such as air sandwiched between the adhesive surfaces and then depositing the protective substance such as resin on the entire surface including between the chips, the protective substance is removed by exhausting. When bubbles occur, the air sandwiched by the adhesive surface does not expand and lift the chip, and the air trying to escape to the outside does not form a void around the chip. Therefore, no conduction failure occurs in the electrode pad due to the uncured protective substance entering the electrode pad portion of the chip. Also,
Voids do not remain on the surface of the pseudo wafer around the chips, and resist coating defects due to the voids do not occur, so that wiring can be satisfactorily provided.

【００４９】このように、本発明によれば、前記疑似ウ
エーハの表面（剥離面）にすべての良品チップの電極面
が平坦に整列し、電極パッドを含めて前記チップの電極
面が前記保護物質で汚染されず、しかも、表面にボイド
などの欠陥のない、高品質の疑似ウエーハを製造でき
る。このような高品質の疑似ウエーハを用いれば、後続
の疑似ウエーハ一括のはんだバンプ処理や配線工程等の
処理を、高い精度で確実に行うことができる。したがっ
て、最終的にチップやモジュールごとに個片化した時、
良品チップや良品モジュールを高い歩留まりで安価に生
産できる。本発明で得られるチップやチップモジュール
は、小型・軽量の携帯用電子機器のみならず全てのエレ
クトロニクス機器に利用され得るものである。As described above, according to the present invention, the electrode surfaces of all non-defective chips are aligned flat on the surface (release surface) of the pseudo wafer, and the electrode surfaces of the chips including the electrode pads are protected by the protective material. It is possible to manufacture a high-quality pseudo-wafer that is not contaminated by the above and has no surface defects such as voids. By using such a high quality pseudo wafer, it is possible to surely perform the subsequent processes such as the solder bump process and the wiring process of the pseudo wafer collectively with high accuracy. Therefore, when it is finally diced into chips and modules,
Good chips and good modules can be produced inexpensively with high yield. The chip or chip module obtained by the present invention can be used not only for small and lightweight portable electronic devices but also for all electronic devices.

【００５０】また、本発明によれば、半導体ウエーハか
ら切出されたチップのうち、良品チップのみを選択して
前記基体に貼り付け、前記保護物質を全面に被着した後
に剥離することにより、あたかも良品チップのみからな
るウエーハのような前記疑似ウエーハを得るので、良品
チップのみに対するウエーハ一括でのはんだバンプ処理
等が可能となり、低コストで歩留り良く、フリップチッ
プ用はんだバンプチップを形成できる。Further, according to the present invention, among the chips cut out from the semiconductor wafer, only non-defective chips are selected and attached to the substrate, and the protective substance is deposited on the entire surface and then peeled off. Since a pseudo wafer such as a wafer made of only good chips is obtained, solder bump processing or the like can be performed on the good chips only in a batch, and the solder bump chips for flip chips can be formed at low cost with good yield.

【００５１】また、半導体チップ等の電極面以外の面
（即ち、チップ側面及び裏面）は、連続した前記保護物
質によって保護できるので、Ｎｉ無電解めっき処理も可
能である。また、チップの個片化後の実装ハンドリング
においても、チップが保護され、良好な実装信頼性が得
られる。Further, since the surface other than the electrode surface of the semiconductor chip or the like (that is, the side surface and the back surface of the chip) can be protected by the continuous protective material, the Ni electroless plating treatment is also possible. Further, the chip is protected even in the mounting handling after the chip is divided into individual pieces, and good mounting reliability is obtained.

【００５２】その上、前記チップ状電子部品を前記疑似
ウエーハから切り出す際に、チップ間の前記保護物質の
部分を切断するので、チップ状電子部品本体への悪影響
（歪みやばり、亀裂等のダメージ）を抑えられる。Moreover, when the chip-shaped electronic component is cut out from the pseudo wafer, the portion of the protective material between the chips is cut, so that the chip-shaped electronic component body is adversely affected (damage such as distortion, burrs, and cracks). ) Can be suppressed.

【００５３】さらに、自社製ウエーハのみならず、他社
から購入したベアチップでも、容易にはんだバンプ処理
等が可能になる。また、ＭＣＭに搭載される異種ＬＳＩ
チップを全て同一半導体メーカーから供給されるケース
は少なく、最先端の半導体ラインの投資が大きくなって
きているために、ＳＲＡＭ、フラッシュメモリーやマイ
コン、更にＣＰＵ（中央演算処理ユニット）を同一半導
体メーカーで供給するのではなく、各々得意とする半導
体メーカーから別々にチップで供給してもらい、これら
をＭＣＭ化することもできる。Further, not only in-house manufactured wafers but also bare chips purchased from other companies can be easily subjected to solder bump processing and the like. Also, heterogeneous LSI mounted on MCM
It is rare for all chips to be supplied from the same semiconductor maker, and investment in cutting-edge semiconductor lines is increasing. Therefore, SRAM, flash memory, microcomputer, and CPU (Central Processing Unit) are manufactured by the same semiconductor maker. Instead of supplying it, it is also possible to have each semiconductor manufacturer who is good at supplying it separately as a chip and convert these into MCM.

【００５４】[0054]

【発明の実施の形態】本発明においては、前記チップ、
特に半導体チップに関して前記粘着面とは反対側から前
記粘着面に向かって前記チップに荷重を加えることと、
前記粘着面を加温することとの少なくとも一方の条件下
で、真空排気（真空引き）によって前記粘着面を脱ガス
することが好ましい。BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, the chip,
Particularly with respect to the semiconductor chip, applying a load to the chip from the side opposite to the adhesive surface toward the adhesive surface,
It is preferable to degas the adhesive surface by evacuation (evacuation) under at least one condition of heating the adhesive surface.

【００５５】また、前記複数個又は複数種のチップの高
さが異なる場合、荷重治具の前記チップとの接触面に凹
凸を設け、この凹面及び／又は凸面によって前記チップ
のそれぞれに均等に前記荷重が加えられるように構成す
ることが好ましい。When the heights of the plurality of or a plurality of types of chips are different from each other, the contact surface of the loading jig with the chips is provided with unevenness, and the concave and / or convex surfaces make it possible to evenly distribute the chips. It is preferable that the load be applied.

【００５６】また、前記チップと荷重治具との間に緩衝
材を挟んで前記荷重を加えることが好ましい。It is preferable that a cushioning material is sandwiched between the chip and the load jig to apply the load.

【００５７】また、弾性材料を介して前記荷重を前記チ
ップに伝達するように構成されていることが好ましく、
荷重治具の少なくとも一部が前記弾性材料からなること
が好ましい。Further, it is preferable that the load is transmitted to the tip through an elastic material,
At least a part of the loading jig is preferably made of the elastic material.

【００５８】本発明に使用可能な前記基体は、樹脂の硬
化温度等において変性、分解、反りなどがなければ、材
質は特に限定されるべきものではなく、例示するなら
ば、シリコンウェーハやガラス基板、石英基板、セラミ
ック基板、ポリテトラフルオロエチレン製基板等が挙げ
られる。支持基板の形態も、先に図１３に示した円形基
板でも、角形のより大きな基板でもよい。また、基板は
何回でも繰り返して使用することができるため、バンプ
形成のコストや環境面においても有利である。The substrate that can be used in the present invention is not particularly limited in material as long as there is no denaturation, decomposition, warpage or the like at the curing temperature of the resin. For example, a silicon wafer or a glass substrate can be used. , A quartz substrate, a ceramic substrate, a polytetrafluoroethylene substrate, and the like. The form of the supporting substrate may be the circular substrate shown in FIG. 13 or a larger square substrate. In addition, the substrate can be used repeatedly as many times as desired, which is advantageous in terms of bump formation cost and environment.

【００５９】次に、本発明の好ましい実施の形態を図面
を参照しながら具体的に説明する。Next, preferred embodiments of the present invention will be specifically described with reference to the drawings.

【００６０】実施の形態１ 以下に、荷重治具を使用してチップに荷重を加えなが
ら、粘着面に挟み込まれた空気を真空排気することによ
り、高品質の疑似ウエーハやチップ状電子部品を製造す
る方法の１例を、図１〜３を参照しながら順を追って説
明する。図１（ａ）〜図２（ｉ）は疑似ウエーハの製造
過程を、図２（ｊ）〜図３（ｌ）ははんだバンプの形成
過程を、図３（ｍ）と（ｎ）はチップを個々の個片に切
り分け、実装基板にマウントする様子を示す。In the first and subsequent embodiments , a high-quality pseudo-wafer or chip-shaped electronic component is manufactured by applying a load to the chip using a loading jig and evacuating the air sandwiched between the adhesive surfaces. An example of the method for doing so will be described step by step with reference to FIGS. 1 (a) to 2 (i) show a manufacturing process of a pseudo wafer, FIGS. 2 (j) to 3 (l) show a solder bump forming process, and FIGS. 3 (m) and 3 (n) show a chip. It shows how to cut into individual pieces and mount them on a mounting board.

【００６１】図１（ａ）は、チップを仮固定する（一時
的に固定する）ための平坦な支持基板１０１を示す。FIG. 1A shows a flat support substrate 101 for temporarily fixing (temporarily fixing) a chip.

【００６２】まず、図１（ｂ）のように、支持基板１０
１上に、粘着性固定材１０２を均一に付着させる。この
粘着性固定材１０２がフィルムならばローラーラミネー
トの手法で貼り付け、液状のものならばスピンコートや
印刷の手法で塗り付ける。First, as shown in FIG. 1B, the supporting substrate 10
The adhesive fixing material 102 is evenly attached onto the surface 1. If the adhesive fixing material 102 is a film, it is attached by a roller laminating method, and if it is liquid, it is applied by a spin coating or printing method.

【００６３】次に、図１（ｃ）のように、良品と確認さ
れた複数のベアチップ１０３を電極面（デバイス面）を
下にして、粘着性固定材１０２の上にその粘着性を利用
して固定する。ここでいう良品のベアチップ１０３と
は、例えば図１１に示したごとき半導体ウェーハ５３よ
り切り出された後、オープン／ショート或いはＤＣ（直
流）電圧測定で良品と確認されたベアチップ１０３（又
はＬＳＩチップ）等を言う。また、図１（ｃ）には固定
するベアチップ１０３が同一種である場合を示したが、
複数種のベアチップを複数個固定することもできる。Next, as shown in FIG. 1 (c), a plurality of bare chips 103 confirmed to be non-defective are placed on the adhesive fixing material 102 with their electrode surfaces (device surfaces) facing down. To fix. The non-defective bare chip 103 referred to here is, for example, a bare chip 103 (or LSI chip) which is confirmed to be non-defective by open / short or DC (direct current) voltage measurement after being cut out from the semiconductor wafer 53 as shown in FIG. Say Further, FIG. 1C shows the case where the bare chips 103 to be fixed are of the same type.
It is also possible to fix a plurality of types of bare chips.

【００６４】次に、図１（ｄ）のように、荷重治具１０
４をチップ１０３の上面に載せ、チップ１０３の位置を
動かさないように粘着面に向かって荷重をかけながら、
全体を真空チャンバ１０５に入れ、真空に排気する。こ
れによって、チップ１０３の粘着性固定材１０２との粘
着面（又はチップの電極面）に空気等が存在している場
合には、強制排気される。図１（ｄ）では、荷重治具１
０４の自重で荷重をかける場合を示したが、機械的に荷
重をかける方式にすることもできる。Next, as shown in FIG. 1D, the loading jig 10
4 is placed on the upper surface of the chip 103, and a load is applied toward the adhesive surface so as not to move the position of the chip 103,
The whole is put in the vacuum chamber 105 and evacuated to a vacuum. As a result, if air or the like is present on the adhesive surface of the chip 103 with the adhesive fixing material 102 (or the electrode surface of the chip), the air is forcibly exhausted. In FIG. 1D, the loading jig 1
Although the case where the load is applied by the own weight of 04 is shown, a method of applying the load mechanically may be used.

【００６５】このような荷重の代りに、或いは荷重と共
に、支持基板１０１の全体を加温ガスやヒータで加温し
た状態で、同様に真空排気しても、上記粘着面に存在す
る空気等を除去することができる。Instead of such a load, or together with the load, even if the entire supporting substrate 101 is heated by a heating gas or a heater, the air existing on the adhesive surface can be removed even if the vacuum is similarly exhausted. Can be removed.

【００６６】図１（ｄ）のようにチップの厚さがすべて
同じであれば、荷重治具１０４は厚さが一様な板状の物
体でよい。If all the chips have the same thickness as shown in FIG. 1D, the loading jig 104 may be a plate-shaped object having a uniform thickness.

【００６７】次に、図１（ｅ）のように、チップ１０３
を四方から取り囲むように、予め離型剤をスプレー塗布
しておいた型枠１０６を粘着性固定材１０２の上に固定
する。Next, as shown in FIG. 1E, the chip 103
The mold 106, which has been spray-coated with a release agent in advance, is fixed on the adhesive fixing material 102 so as to surround the four sides.

【００６８】次に、図１（ｆ）のように、保護物質とし
て、粘着性固定材１０２が離型作用を持つ液状樹脂１０
７をチップ１０３上部から均一に流し込み、硬化させ
る。ここで用いる液状樹脂１０７は、エポキシ樹脂やそ
の他のモールド樹脂としてよいが、液状セラミックス等
であってもよい。Next, as shown in FIG. 1 (f), the liquid resin 10 as a protective substance, in which the adhesive fixing material 102 has a releasing action.
7 is evenly poured from the upper part of the chip 103 to be cured. The liquid resin 107 used here may be epoxy resin or other mold resin, but may be liquid ceramics or the like.

【００６９】次に、図２（ｇ）のように、粘着性固定材
１０２の離型作用を利用して、チップ１０３を埋設した
型枠付き樹脂板１２８を支持基板１０１から剥離し、さ
らに、図２（ｈ）のように型枠１０６を外して、チップ
１０３を埋設した疑似ウエーハ１２９を得る。Next, as shown in FIG. 2G, the mold-releasing function of the adhesive fixing material 102 is utilized to peel off the resin plate 128 with a mold in which the chip 103 is embedded from the support substrate 101, and further, As shown in FIG. 2H, the mold 106 is removed to obtain the pseudo wafer 129 in which the chips 103 are embedded.

【００７０】図２（ｉ）は、良品ベアチップ電極面（デ
バイス面）２８が上になるように疑似ウエーハ１２９を
ひっくり返した状態を示す。電極面２８は同図に拡大し
て示すように、Ｓｉ基板上にＳｉＯ2膜を介してＡｌ電
極パッド５及びパッシベーション膜が形成されたもので
ある。FIG. 2I shows a state in which the pseudo wafer 129 is turned upside down so that the non-defective bare chip electrode surface (device surface) 28 faces upward. As shown in an enlarged view in the figure, the electrode surface 28 is formed by forming an Al electrode pad 5 and a passivation film on a Si substrate via a SiO 2 film.

【００７１】図２（ｊ）は、Ｎｉ無電解めっき法にて、
開口されたＡｌ電極パッド５面の上のみに、選択的にＮ
ｉ無電解めっき層（ＵＢＭ）を形成した状態を示す。な
お、このＮｉ無電解めっき層（ＵＢＭ）は、Ａｌ電極パ
ッド５の上面をリン酸系エッチ液で前処理した後に、Ｚ
ｎ処理によりＺｎを置換析出させ、さらにＮｉ−Ｐめっ
き槽に浸漬させることにより、容易に形成でき、Ａｌ電
極パッド５とはんだバンプとの接続を助けるＵＢＭ（Un
der Bump Metal）として作用する。FIG. 2 (j) shows a Ni electroless plating method.
Selectively N only on the surface of the opened Al electrode pad 5
i shows a state in which an electroless plating layer (UBM) is formed. The Ni electroless plating layer (UBM) was formed on the upper surface of the Al electrode pad 5 by pretreatment with a phosphoric acid-based etchant and then Z
Zn is deposited by substitution treatment by n treatment, and further dipped in a Ni-P plating bath, so that it can be easily formed and the UBM (Un
der Bump Metal).

【００７２】図２（ｋ）は、印刷マスク８を当てて、は
んだペースト９を印刷法によりＮｉ無電解めっき層（Ｕ
ＢＭ）上に転写した状態である。図３（ｌ）は、ウエッ
トバック法ではんだペースト９を溶融して、はんだバン
プ１２を形成した状態である。このように、Ｎｉ無電解
めっき法及びはんだペーストスクリーン印刷法等を用い
ることにより、フォトプロセスを用いずに簡単にはんだ
バンプ１２を形成できる。In FIG. 2 (k), the printing mask 8 is applied and the solder paste 9 is printed by a Ni electroless plating layer (U
BM). FIG. 3L shows a state in which the solder paste 9 is melted by the wet back method to form the solder bumps 12. Thus, by using the Ni electroless plating method and the solder paste screen printing method, the solder bumps 12 can be easily formed without using a photo process.

【００７３】図３（ｌ）において、プローブ検査による
電気的特性の測定やバーンインテストを行って、図１
（ｃ）の工程前に良品ベアチップ１０３を選別したこと
に加えて、更により確実に良品チップのみを選別でき
る。In FIG. 3 (l), the electrical characteristics are measured by the probe inspection and the burn-in test is performed, and the result of FIG.
In addition to selecting the non-defective bare chips 103 before the step (c), it is possible to more reliably select only non-defective chips.

【００７４】図３（ｍ）は、ブレード３２（又はレー
ザ）でスクライブライン３３に沿ってダイシング１１し
て、チップ１０３を樹脂１０７で保護して補強した良品
チップ部品１２６の単位で個々の個片とする工程を示
す。In FIG. 3 (m), a blade 32 (or a laser) is used to perform dicing 11 along the scribe line 33 to protect the chip 103 with a resin 107 and reinforce the chip 103 in units of good chips 126. The process of

【００７５】次に、図３（ｎ）のように、配線基板１６
上のソルダー（はんだ）レジスト１５で囲まれかつソル
ダー（はんだ）ペースト１３を被着した電極１４を設け
た実装基板２７に、個片化された良品チップ部品１２６
をマウントする。この時、良品チップ部品１２６の側面
と裏面は樹脂１０７で覆われているため、良品チップ部
品１２６が実装時のハンドリング等で直接のダメージを
受けることがなく、高い信頼性を持つフリップチップ実
装が期待できる。Next, as shown in FIG. 3N, the wiring board 16
A good chip component 126 that is singulated into individual pieces on a mounting substrate 27 that is surrounded by the upper solder (solder) resist 15 and provided with the electrodes 14 to which the solder (solder) paste 13 is applied.
Mount. At this time, since the side surface and the back surface of the non-defective chip component 126 are covered with the resin 107, the non-defective chip component 126 is not directly damaged by handling during mounting, and flip chip mounting with high reliability can be achieved. Can be expected.

【００７６】上記したように、本実施の形態によれば、
半導体チップ１０３と粘着性固定材１０２との粘着面に
挟み込まれていた空気等のガスを真空吸引により取り除
いてから、樹脂などの保護物質１０７を半導体チップ１
０３に被着しているので、厚さの厚いチップであって粘
着性固定材１０２と密着の悪いチップであっても、荷重
治具又は／及び温度、真空引きなどを組み合わせること
により、半導体チップ１０３と粘着手段１０２との密着
性が向上し、半導体チップ１０３が位置ずれせず、その
位置決め精度が高く、また電極パッドを含めてチップの
電極面が保護物質で汚染されず、全て露出した状態で良
品チップ１０３のみが多数個配列され、しかも、表面に
ボイドなどの欠陥のない、高品質の疑似ウエーハ１２９
を製造できる。このような高品質の疑似ウエーハ１２９
を用いれば、良品チップや良品モジュールを高い歩留ま
りで安価に生産でき、再配線も精度及び信頼性共に良好
に行うことができる。そして、得られたチップやチップ
モジュールは、小型・軽量の携帯用電子機器のみなら
ず、全てのエレクトロニクス機器に利用され得るもので
ある。As described above, according to this embodiment,
After removing the gas such as air sandwiched between the adhesive surfaces of the semiconductor chip 103 and the adhesive fixing material 102 by vacuum suction, the protective substance 107 such as resin is removed from the semiconductor chip 1
No. 03 on the semiconductor chip, even if the chip has a large thickness and does not adhere well to the adhesive fixing material 102, a semiconductor chip can be obtained by combining a loading jig and / or temperature, vacuuming, etc. The adhesiveness between the adhesive layer 103 and the adhesive means 102 is improved, the semiconductor chip 103 is not displaced, its positioning accuracy is high, and the electrode surface of the chip including the electrode pads is not contaminated with a protective substance and is entirely exposed. A large number of non-defective chips 103 are arranged, and the surface is free of defects such as voids, and is a high quality pseudo wafer 129.
Can be manufactured. Such a high quality pseudo wafer 129
By using, the good chip and the good module can be produced at a high yield at a low cost, and the rewiring can be performed with good accuracy and reliability. The obtained chip or chip module can be used not only for small and lightweight portable electronic devices but also for all electronic devices.

【００７７】また、良品チップ１０３のみを選択し、良
品チップ１０３のみからなる疑似ウエーハ１２９を作
り、疑似ウエーハ一括でのはんだバンプ処理等を行うこ
とで、生産を高効率化することができる。さらに、他社
から購入したベアチップでも、はんだバンプ処理等のウ
エーハ一括処理が可能になる。したがって、ＭＣＭに搭
載される異種ＬＳＩチップ、ＳＲＡＭ、フラッシュメモ
リー、マイコン、更にＣＰＵ（中央演算処理ユニット）
を各々得意とする半導体メーカーから供給してもらい、
これらをＭＣＭ化することもできる。Further, by selecting only the non-defective chips 103, forming the pseudo wafer 129 consisting of only the non-defective chips 103, and performing the solder bump processing or the like on the pseudo wafer at a time, the production efficiency can be improved. In addition, even bare chips purchased from other companies can be subjected to batch wafer processing such as solder bump processing. Therefore, heterogeneous LSI chip mounted on MCM, SRAM, flash memory, microcomputer, and CPU (central processing unit)
Are supplied from semiconductor manufacturers that are good at
These can also be converted to MCM.

【００７８】また、半導体チップ等の良品チップ部品１
２６において、電極面以外の面は、連続した保護物質１
０７によって保護されるので、Ｎｉ無電解めっき処理も
可能である。また、チップ状電子部品１２６を疑似ウエ
ーハ１２９から切り出す際に、チップ間の保護物質の部
分を切断するので、チップ状電子部品本体への悪影響
（歪みやばり、亀裂等のダメージ）を抑えられる。Also, a non-defective chip component 1 such as a semiconductor chip
26, the surface other than the electrode surface is a continuous protective substance 1.
Since it is protected by 07, Ni electroless plating treatment is also possible. Further, when the chip-shaped electronic component 126 is cut out from the pseudo wafer 129, the portion of the protective material between the chips is cut, so that adverse effects (damage such as distortion, burrs, cracks, etc.) on the chip-shaped electronic component body can be suppressed.

【００７９】実施の形態２ 上記した荷重治具１０４は、半導体チップ１０３にダメ
ージを与えずに、必要な荷重を加えられる構造のものが
望ましい。上記の実施の形態１では、図４（ａ）のよう
に荷重治具１０４が半導体チップ１０３の上面を直接押
す構造になっていたが、チップ１０３にダメージを与え
ないために、図４（ｂ）のように、荷重治具１０４と半
導体チップ１０３との間に緩衝材１０８を挟んで荷重を
加える構造にすることもできる。 Embodiment 2 It is desirable that the above-mentioned loading jig 104 has a structure that can apply a required load without damaging the semiconductor chip 103. In the first embodiment described above, the load jig 104 has a structure of directly pressing the upper surface of the semiconductor chip 103 as shown in FIG. 4A. However, since the chip 103 is not damaged, the load jig 104 shown in FIG. ), A structure in which a cushioning material 108 is sandwiched between the load jig 104 and the semiconductor chip 103 to apply a load can be adopted.

【００８０】緩衝材１０８として、粘着性固定材１０２
と付着し合わない、例えばテフロン（登録商標）やポリ
エチレンテレフタレートの薄いシートを用いると、荷重
を加えたときに、半導体チップ１０３に直接衝撃が加わ
ることを防ぐ緩衝作用とともに、真空排気時にシート１
０２が半導体チップ１０３を部分的に包み込みながら、
その吸着作用で支持基板１０１側に貼り付き、その結果
として、シート１０２が半導体チップ１０３を粘着性固
定材１０２の方へ引き寄せようとする作用も期待でき
る。As the cushioning material 108, the adhesive fixing material 102
If a thin sheet of, for example, Teflon (registered trademark) or polyethylene terephthalate that does not adhere to the sheet is used, the sheet 1 has a cushioning function that prevents a direct impact from being applied to the semiconductor chip 103 when a load is applied, and the sheet 1 is evacuated.
02 partially wraps the semiconductor chip 103,
It is possible to expect an action of sticking the semiconductor chip 103 toward the adhesive fixing material 102 by the sheet 102 as a result of sticking to the supporting substrate 101 side by the adsorption action.

【００８１】その他、実施の形態１に記したと同じ効果
が期待できることは、言うまでもない。Needless to say, the same effects as those described in the first embodiment can be expected.

【００８２】実施の形態３ 半導体チップの高さや大きさが様々である場合には、半
導体チップの位置をずらさず、半導体チップにダメージ
を与えず、その位置ずれも生じさせないで荷重を加える
には、平坦で堅い荷重治具よりも、図５のように、チッ
プ１０３の高さや大きさの違いを吸収してすべてのチッ
プ１０３に均等に荷重が加えられるように構成すること
が望ましい。 Third Embodiment When a semiconductor chip has various heights and sizes, the position of the semiconductor chip is not displaced, the semiconductor chip is not damaged, and the load is applied without causing the positional deviation. As shown in FIG. 5, it is preferable to adopt a structure in which the difference in height and size of the chips 103 is absorbed and the load is uniformly applied to all the chips 103, rather than a flat and rigid loading jig.

【００８３】例えば、図６（ａ）のように、荷重治具１
０４の半導体チップ１０３との接触面に、半導体チップ
１０３の高低差に見合う凹凸１０９を設け、それぞれの
半導体チップ１０３に均等の荷重が加えられるように構
成することである。この場合、それぞれのチップ１０３
の組み合わせに対して専用の荷重治具１０４を用意する
ことが必要であるが、チップ１０３の高低差にかかわら
ず、効果は確実である。同じ操作を何度も繰り返す大量
生産の場合には、このような専用の荷重治具を作るのが
望ましい。For example, as shown in FIG. 6A, the loading jig 1
No. 04 is provided on the contact surface with the semiconductor chip 103, and the unevenness 109 corresponding to the height difference of the semiconductor chip 103 is provided so that an even load is applied to each semiconductor chip 103. In this case, each chip 103
It is necessary to prepare a dedicated load jig 104 for the combination of the above, but the effect is certain regardless of the height difference of the chip 103. In the case of mass production in which the same operation is repeated many times, it is desirable to make such a dedicated loading jig.

【００８４】他方、図６（ｂ）のように、荷重治具１０
４の少なくともチップ１０３側に弾性材料１１０を設け
るか、或いは荷重治具１０４自体の少なくともチップ１
０３側を弾性材料で構成したり、バネ材を適切な位置に
配して荷重治具１０４に弾力性を持たせ、バネ材を介し
て半導体チップ１０３に荷重を伝達するよう構成するか
である。適当な弾性材料としては、例えばゴムやウレタ
ンがある。この方法は、チップの高低差が比較的小さい
場合には、汎用性を期待できる方法であり、また度々チ
ップの組み合わせが変わるような場合に適している。On the other hand, as shown in FIG. 6B, the loading jig 10
4 is provided with an elastic material 110 on at least the chip 103 side, or at least the chip 1 of the loading jig 104 itself.
No. 03 side is made of an elastic material, or a spring material is arranged at an appropriate position so that the loading jig 104 has elasticity, and the load is transmitted to the semiconductor chip 103 via the spring material. . Suitable elastic materials include, for example, rubber and urethane. This method can be expected to be versatile when the height difference between chips is relatively small, and is suitable when the combination of chips changes frequently.

【００８５】これらのいずれの方法も、上記の実施の形
態２に記した緩衝材１０８と併用出きることは言うまで
もない。また、上記の実施の形態１に記したのと同じ効
果が期待できる。It goes without saying that any of these methods can be used together with the cushioning material 108 described in the second embodiment. Further, the same effect as that described in the first embodiment can be expected.

【００８６】以上に説明した実施の形態は、本発明の技
術的思想に基づいて更に変形が可能である。The embodiment described above can be further modified based on the technical idea of the present invention.

【００８７】例えば、上述した粘着性固定材１０２とし
ては、保護物質１０７との離型性の良好なものが望まし
いが、紫外線照射等による処理で離型性を発現させても
よい。For example, as the above-mentioned adhesive fixing material 102, one having a good releasability with respect to the protective substance 107 is desirable, but the releasability may be exhibited by a treatment such as ultraviolet irradiation.

【００８８】本発明は、半導体チップやＬＳＩチップに
限らず、チップ抵抗等の他のチップ部品やそのモジュー
ルにも適用可能である。The present invention is not limited to semiconductor chips and LSI chips, but can be applied to other chip parts such as chip resistors and their modules.

【００８９】[0089]

【発明の作用効果】本発明によれば、粘着手段の上にチ
ップを固定する際、粘着面を脱ガスする工程を行うの
で、チップと粘着手段との密着性が向上し、チップを安
定して粘着手段上に固定することができ、これによっ
て、疑似ウエーハにおけるチップの位置決め精度を向上
させることができる。According to the present invention, since the step of degassing the adhesive surface is carried out when fixing the chip on the adhesive means, the adhesion between the chip and the adhesive means is improved and the chip is stabilized. It can be fixed on the adhesive means by means of the adhesive, which can improve the positioning accuracy of the chip on the pseudo wafer.

【００９０】また、上記粘着面に挟み込まれていた空気
等のガスを取り除いてから樹脂などの保護物質をチップ
に被着する工程を行うので、保護物質を排気によって脱
泡する時、上記粘着面に挟み込まれていた空気が膨張し
てチップを持ち上げたり、外に逃げようとする空気がチ
ップ周辺にボイドを形成したりすることはない。このた
め、チップの電極パッドの部分に未硬化の樹脂が入り込
んでしまうことによる電極パッドでの導通不良は起こら
ない。また、チップの周囲の疑似ウエーハ表面にボイド
が残ることはなく、ボイドに起因するレジスト塗布の不
良が生じることもない。Further, since the step of depositing a protective substance such as a resin on the chip after removing the gas such as air sandwiched in the adhesive face is performed, when the protective substance is degassed by exhausting, the adhesive face is removed. The air sandwiched between the chips does not expand and lift the chip, and the air trying to escape to the outside does not form a void around the chip. Therefore, the conduction failure in the electrode pad due to the uncured resin entering the electrode pad portion of the chip does not occur. Further, no void is left on the surface of the pseudo wafer around the chip, and no defect in resist coating due to the void occurs.

【００９１】このように、本発明によれば、疑似ウエー
ハの表面（剥離面）にすべての良品チップの電極面が平
坦に整列し、電極パッドを含めてチップの電極面が保護
物質で汚染されず、しかも、表面にボイドなどの欠陥の
ない、高品質の疑似ウエーハを製造できる。このような
高品質の疑似ウエーハを用いれば、後続の疑似ウエーハ
一括のはんだバンプ処理や再配線工程等の処理を、高い
精度で確実に行うことができる。したがって、最終的に
チップやモジュールごとに個片化した時、良品チップや
良品モジュールを高い歩留まりで安価に生産できる。本
発明で得えられるチップやチップモジュールは、小型・
軽量の携帯用電子機器のみならず全てのエレクトロニク
ス機器に利用され得るものである。As described above, according to the present invention, the electrode surfaces of all non-defective chips are flatly aligned with the surface (release surface) of the pseudo wafer, and the electrode surfaces of the chips including the electrode pads are contaminated with the protective substance. Moreover, it is possible to manufacture a high-quality pseudo wafer without defects such as voids on the surface. By using such a high quality pseudo wafer, it is possible to surely perform the subsequent processes such as the solder bump process and the rewiring process for the pseudo wafer all together with high accuracy. Therefore, when the chips and modules are finally diced into individual pieces, good chips and good modules can be produced at a high yield at low cost. The chips and chip modules obtained by the present invention are small and
It can be used not only for lightweight portable electronic devices but also for all electronic devices.

【００９２】また、良品チップのみを選択し、良品チッ
プのみからなる疑似ウエーハを作り、疑似ウエーハ一括
でのはんだバンプ処理等を行うことで、生産を高効率化
することができる。さらに、他社から購入したベアチッ
プでも、はんだバンプ処理等のウエーハ一括処理が可能
になる。したがって、ＭＣＭに搭載される異種ＬＳＩチ
ップ、ＳＲＡＭ、フラッシュメモリー、マイコン、更に
ＣＰＵ（中央演算処理ユニット）を各々得意とする半導
体メーカーから供給してもらい、これらをＭＣＭ化する
こともできる。Also, by selecting only non-defective chips, making a pseudo wafer consisting of only non-defective chips, and performing solder bump processing and the like in a batch of pseudo wafers, production efficiency can be improved. In addition, even bare chips purchased from other companies can be subjected to batch wafer processing such as solder bump processing. Therefore, a heterogeneous LSI chip, an SRAM, a flash memory, a microcomputer, and a CPU (central processing unit) mounted on the MCM can be supplied from semiconductor manufacturers who are good at each, and these can be converted into the MCM.

【００９３】半導体チップ等のチップ状電子部品の電極
面以外の面は、連続した保護物質によって保護できるの
で、Ｎｉ無電解めっき処理も可能であり、個片化後のハ
ンドリング時もチップが保護され、実装を良好に行なえ
る。また、チップ状電子部品を疑似ウエーハから切り出
す際に、チップ間の保護物質の部分を切断するので、チ
ップ状電子部品本体への悪影響（歪みやばり、亀裂等の
ダメージ）を抑えられる。Surfaces other than the electrode surface of the chip-shaped electronic component such as a semiconductor chip can be protected by a continuous protective material, so that Ni electroless plating treatment is also possible, and the chip is protected during handling after singulation. , Can be implemented well. Further, when the chip-shaped electronic component is cut out from the pseudo wafer, the portion of the protective material between the chips is cut, so that adverse effects (damage such as distortion, burrs, cracks, etc.) on the chip-shaped electronic component body can be suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施の形態１におけるチップ状電子部
品の作製工程を順次示す断面図である。FIG. 1 is a sectional view sequentially showing a manufacturing process of a chip-shaped electronic component according to a first embodiment of the present invention.

【図２】同、作製工程を順次示す断面図である。FIG. 2 is a cross-sectional view showing the manufacturing steps in sequence.

【図３】同、作製工程を順次示す断面図である。FIG. 3 is a cross-sectional view showing the manufacturing steps in sequence.

【図４】本発明の実施の形態２における、荷重の加え方
を示す断面図である。FIG. 4 is a cross-sectional view showing how to apply a load according to the second embodiment of the present invention.

【図５】本発明の実施の形態３における、脱ガス工程前
後のチップ状電子部品の作製工程を順次示す断面図であ
る。FIG. 5 is a cross-sectional view sequentially showing a manufacturing process of a chip-shaped electronic component before and after a degassing process in Embodiment 3 of the present invention.

【図６】本発明の実施の形態３における、荷重の加え方
を示す断面図である。FIG. 6 is a cross-sectional view showing how to apply a load according to the third embodiment of the present invention.

【図７】従来例におけるＡｕスタッドバンプ（Stud Bum
p）の一例を示す斜視図である。FIG. 7 shows a conventional Au stud bump (Stud Bum).
It is a perspective view showing an example of p).

【図８】同、ウェーハレベルで一括はんだでバンプ処理
をした半導体ウェーハの部分平面図ある。FIG. 8 is a partial plan view of a semiconductor wafer that has been bump-processed by collective soldering at the wafer level.

【図９】同、チップ状電子部品の作製工程を順次示す断
面図である。FIG. 9 is a cross-sectional view sequentially showing the manufacturing process of the chip-shaped electronic component.

【図１０】同、ＭＣＭ化された実装構造のほかの例の斜
視図（ａ）とその一部断面側面図（ｂ）、（ｃ）であ
る。FIG. 10 is a perspective view (a) and a partial cross-sectional side view (b) and (c) of another example of the MCM-implemented mounting structure.

【図１１】同、ウェーハ一括処理に対処する半導体ウェ
ーハの斜視図である。FIG. 11 is a perspective view of a semiconductor wafer that handles wafer batch processing.

【図１２】先願発明（特開２００１−３０８１１６号）
における、チップ状電子部品の作製工程を順次示す断面
図である。FIG. 12: Prior invention (Japanese Patent Application Laid-Open No. 2001-308116)
FIG. 5 is a cross-sectional view sequentially showing the manufacturing process of the chip-shaped electronic component in FIG.

【図１３】同、良品ベアチップのみを貼り付けた石英基
板の斜視図である。FIG. 13 is a perspective view of a quartz substrate to which only non-defective bare chips are attached.

【図１４】同、保護物質の被着時の状況を示す断面図で
ある。FIG. 14 is a cross-sectional view showing a situation when a protective substance is adhered.

【符号の説明】[Explanation of symbols]

１…石英基板、２…粘着シート、３…良品ベアチップ、
４…樹脂、５、５５…Ａｌ電極パッド、８…印刷マス
ク、９…はんだペースト、１１…ダイシング、１２…は
んだバンプ、１３…ソルダー（はんだ）ペースト、１４
…電極、１５…ソルダー（はんだ）レジスト、１６…配
線基板、２０…不良品ベアチップ、２１、３３…スクラ
イブライン、２７…実装基板、２８…良品ベアチップ電
極面（デバイス面）、２９…疑似ウエーハ、３０…接着
面、３２…ブレード、１００ａ…粘着面に挟み込んだ空
気、１００ｂ…ボイド（空隙）、１０１…支持基板、１
０２…粘着性固定材、１０３…良品チップ、１０４…荷
重治具、１０５…真空チャンバ、１０６…型枠、１０７
…樹脂、１０８…緩衝材、１０９…凹凸、１１０…弾性
材料、１２６…良品チップ部品、１２８…型枠付き樹脂
板、１２９…疑似ウエーハ1 ... Quartz substrate, 2 ... Adhesive sheet, 3 ... Good bare chip,
4 ... Resin, 5, 55 ... Al electrode pad, 8 ... Printing mask, 9 ... Solder paste, 11 ... Dicing, 12 ... Solder bump, 13 ... Solder (solder) paste, 14
... electrodes, 15 ... solder resist, 16 ... wiring board, 20 ... defective bare chip, 21, 33 ... scribe line, 27 ... mounting substrate, 28 ... non-defective bare chip electrode surface (device surface), 29 ... pseudo wafer, 30 ... Adhesive surface, 32 ... Blade, 100a ... Air sandwiched between adhesive surfaces, 100b ... Void (void), 101 ... Support substrate, 1
02 ... Adhesive fixing material, 103 ... Non-defective chip, 104 ... Loading jig, 105 ... Vacuum chamber, 106 ... Formwork, 107
... resin, 108 ... buffer material, 109 ... unevenness, 110 ... elastic material, 126 ... non-defective chip component, 128 ... resin plate with formwork, 129 ... pseudo wafer

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 基体上に粘着手段を設ける工程と、この
粘着手段の上に複数個又は複数種のチップを固定する工
程と、前記チップと前記粘着手段との粘着面を脱ガスす
る工程と、保護物質を前記複数個又は複数種のチップ間
を含む全面に被着する工程と、前記保護物質によって前
記チップを固着した疑似ウエーハを剥離する工程と、前
記複数個又は複数種のチップ間において前記保護物質を
切断してチップ状電子部品を分離する工程とを有する、
チップ状電子部品の製造方法。1. A step of providing an adhesive means on a substrate, a step of fixing a plurality of or a plurality of types of chips on the adhesive means, and a step of degassing the adhesive surfaces of the chips and the adhesive means. A step of depositing a protective substance on the entire surface including the plurality of or a plurality of types of chips, a step of peeling off the pseudo wafer on which the chips are fixed by the protective substance, and a step of separating the plurality of or a plurality of types of chips. Cutting the protective substance to separate the chip-shaped electronic component,
Manufacturing method of chip-shaped electronic component. 【請求項２】 前記粘着面に向かって前記チップに荷重
を加えることと、前記粘着面を加温することとの一方又
は両方の条件下で、真空排気によって前記粘着面を脱ガ
スする、請求項１に記載したチップ状電子部品の製造方
法。2. The adhesive surface is degassed by vacuum evacuation under one or both conditions of applying a load to the chip toward the adhesive surface and heating the adhesive surface. Item 1. A method for manufacturing a chip-shaped electronic component according to item 1. 【請求項３】 前記複数個又は複数種のチップの高さが
異なる場合、荷重治具の前記チップとの接触面に凹凸を
設け、この凹面及び／又は凸面によって前記チップのそ
れぞれに均等に前記荷重が加えられるように構成され
た、請求項２に記載したチップ状電子部品の製造方法。3. When the heights of the plurality of chips or a plurality of types of chips are different, unevenness is provided on a contact surface of the loading jig with the chip, and the concave surface and / or the convex surface evenly distributes the chips to each of the chips. The method for manufacturing a chip-shaped electronic component according to claim 2, wherein the method is configured to apply a load. 【請求項４】 前記チップと荷重治具との間に緩衝材を
挟んで前記荷重を加える、請求項２に記載したチップ状
電子部品の製造方法。4. The method for manufacturing a chip-shaped electronic component according to claim 2, wherein a buffer material is sandwiched between the chip and the load jig to apply the load. 【請求項５】 弾性材料を介して前記荷重を前記チップ
に伝達する、請求項２に記載したチップ状電子部品の製
造方法。5. The method of manufacturing a chip-shaped electronic component according to claim 2, wherein the load is transmitted to the chip via an elastic material. 【請求項６】 荷重治具の少なくとも一部が前記弾性材
料からなる、請求項５に記載したチップ状電子部品の製
造方法。6. The method for manufacturing a chip-shaped electronic component according to claim 5, wherein at least a part of the load jig is made of the elastic material. 【請求項７】 基体上に粘着手段を設ける工程と、この
粘着手段の上に複数個又は複数種のチップを固定する工
程と、前記チップと前記粘着手段との粘着面を脱ガスす
る工程と、保護物質を前記複数個又は複数種のチップ間
を含む全面に被着する工程と、前記保護物質によって前
記チップを固着した疑似ウエーハを剥離する工程とを有
する、疑似ウエーハの製造方法。7. A step of providing an adhesive means on a substrate, a step of fixing a plurality of or a plurality of types of chips on the adhesive means, and a step of degassing the adhesive surfaces of the chips and the adhesive means. A method of manufacturing a pseudo wafer, comprising: a step of depositing a protective substance on the entire surface including a plurality of chips or a plurality of types of chips; and a step of peeling off the pseudo wafer to which the chips are fixed by the protective substance. 【請求項８】 前記粘着面に向かって前記チップに荷重
を加えることと、前記粘着面を加温することとの一方又
は両方の条件下で、真空排気によって前記粘着面を脱ガ
スする、請求項７に記載した疑似ウエーハの製造方法。8. The adhesive surface is degassed by vacuum evacuation under one or both conditions of applying a load to the chip toward the adhesive surface and heating the adhesive surface. Item 7. A method for manufacturing a pseudo wafer according to Item 7. 【請求項９】 前記複数個又は複数種のチップの高さが
異なる場合、荷重治具の前記チップとの接触面に凹凸を
設け、この凹面及び／又は凸面によって前記半導体チッ
プのそれぞれに均等に前記荷重が加えられるように構成
された、請求項８に記載した疑似ウエーハの製造方法。9. When the heights of the plurality of or a plurality of types of chips are different, unevenness is provided on a contact surface of the load jig with the chips, and the concave and / or convex surfaces make the semiconductor chips even. The method for manufacturing a pseudo wafer according to claim 8, wherein the load is applied. 【請求項１０】 前記チップと荷重治具の間に緩衝材を
挟んで前記荷重を加える、請求項８に記載した疑似ウエ
ーハの製造方法。10. The method of manufacturing a pseudo wafer according to claim 8, wherein a buffer material is sandwiched between the chip and the load jig to apply the load. 【請求項１１】 弾性材料を介して前記荷重を前記チッ
プに伝達する、請求項８に記載した疑似ウエーハの製造
方法。11. The method for manufacturing a pseudo wafer according to claim 8, wherein the load is transmitted to the chip via an elastic material. 【請求項１２】 荷重治具の少なくとも一部が前記弾性
材料からなる、請求項１１に記載した疑似ウエーハの製
造方法。12. The method for manufacturing a pseudo wafer according to claim 11, wherein at least a part of the load jig is made of the elastic material.
JP2002003463A 2002-01-10 2002-01-10 Manufacturing method of chip-type electronic component, and manufacturing method of dummy wafer employed for manufacturing the component Pending JP2003203938A (en)

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