JP2004087661A - Chip-shaped electronic component and method for manufacturing the same and pseudo wafer used for its manufacturing and method for manufacturing the same, and mounting structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip-shaped electronic component obtained while shortening a manufacturing process, with a high yield and a low cost by eliminating the waste of chip components, and to provide a method for manufacturing the chip-shaped electronic component, a pseudo wafer used for its manufacturing, a method for manufacturing the pseudo wafer, and a mounting structure. <P>SOLUTION: A wiring material 3A is formed on a supporting layer constituted of a metal material 1 and a metal layer 2, the wiring material 3A is worked to form wiring(basic pattern) 3, and a photosensitive adhesive layer 4 is formed on the wiring(basic pattern) 3. Holes 5(via hole) are formed in the adhesive layer 4. A plurality of kinds of semiconductor chips 6 are fixed to positions corresponding to the holes 5 in the adhesive layer 4, and the whole face including the chips 6 and 7 is coated with a protecting material layer 8. At least either the metal material 1 or the metallic layer 2 is removed, and the holes 5 are packed with conductive paste 10 to connect an electrode pad 31 to the wiring(basic pattern) 3, and the protecting material layer 8 is cut between the chips 6 and 7 to separate a non-defective chip-shaped electronic component 19. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a chip-shaped electronic component suitable for manufacturing a semiconductor device and a method for manufacturing the same, a pseudo wafer used for the manufacturing, a method for manufacturing the same, and a mounting structure.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there is a strong demand for reduction in size, thickness, and weight of portable electronic devices such as digital video cameras, digital mobile phones, and notebook PCs (Personal Computers), and how to increase the surface mounting density of semiconductor components. Is an important point.
[0003]
For this reason, a smaller CSP (Chip Scale Package), which replaces a package IC (QFP (Quad Flat Package), etc.), has already been developed or partially adopted, but the ultimate semiconductor high-density mounting has been advanced. Considering this, it is strongly desired to spread the connection technology using the bare chip and the flip chip method.
[0004]
Further, with the recent improvement in operation speed and low voltage of LSI (Large Scale Integrated Circuit), the connection between a semiconductor chip and an interposer or a motherboard has been aimed at shortening wiring paths and reducing wiring resistance. The use of the flip-chip connection described above is increasing.
[0005]
For such flip-chip connection using a bump forming technique in flip-chip mounting, for example, a solder bump is formed on a connection pad of a semiconductor chip, and then the solder is again melted by heat to form a mounting board which is a motherboard. A connection method, a method of forming an Au bump on an Al electrode pad by an Au-Stud bump method, an electrolytic plating method, or the like, and a method of connecting to a motherboard using an anisotropic conductive film or the like, an electrolytic plating method, or a vapor deposition method A typical method is to collectively form solder bumps by a method or the like.
[0006]
However, in the case of consumer use, in the case of flip-chip mounting at a lower cost, bumps are formed in a wafer state at once instead of forming bumps after forming chips (Au-Stud @ Bump method is a typical example). A forming method is desirable.
[0007]
In view of the recent tendency of the wafer to increase in diameter (150 mmφ → 200 mmφ → 300 mmφ) and the tendency of increasing the number of connection pins of LSI (Large Scale Integrated Circuit) chips (to increase the number of pins), It is a natural direction.
[0008]
Hereinafter, a conventional bump forming method will be described.
[0009]
FIG. 15 shows a process of forming bumps in a batch of wafers by Ni electroless plating and printing of a solder paste, aiming at lower cost. FIG.₂This shows a silicon substrate (wafer) on which a film is formed, and FIG. 2B is an enlarged view of a chip portion including the electrode. 15A and 15B, 85 is a silicon substrate (wafer), 65 is an Al electrode pad, and 84 is SiO₂Film, 83 is Si₃N₄, SiO₂This is a passivation film made of a film, a polyimide film, or the like.
[0010]
In FIG. 15C, the Ni electroless plating layer (UBM: Under \ Bump \ Metal) 72 is selectively formed only on the upper surface of the opened Al electrode pad 65 by the Ni electroless plating method. The Ni electroless plating layer (UBM) 72 is obtained by pre-treating the surface of the Al electrode pad 65 with a phosphoric acid-based etchant, substituting Zn by Zn treatment, and further immersing in a Ni-P plating bath. It can be easily formed and acts as a UBM to help connect the Al electrode pad 65 and the solder bump.
[0011]
FIG. 15D shows a state where the solder paste 74 is transferred onto the Ni electroless plating layer (UBM) 72 by a printing method with a print mask 73 (metal screen) applied. FIG. 15E shows a state in which the solder paste 74 is melted by a wet back (heating and melting) method to form a solder bump 75. As described above, by using the Ni electroless plating method, the solder paste screen printing method, or the like, the solder bumps 75 can be easily formed without using a photo process.
[0012]
On the other hand, the CSP is an approach of reducing the size of each LSI and mounting it at a high density. However, when looking at circuit blocks of digital equipment, CSP is composed of several common circuit blocks. A technology for making a multi-chip package or modularizing (MCM: Multi Chip Module) has also appeared. An example is a package of an SRAM (Static RAM), a flash memory, and a microcomputer in a digital mobile phone.
[0013]
This MCM technology is expected to exert a great advantage even in recent one-chip system LSI. That is, when a memory, a logic, and an analog LSI are integrated into one chip, different LSI processing processes are processed by the same wafer process, so that the number of masks and processing constants increase remarkably and the development TAT (Turn around time) increases. Is a problem, and a decrease in yield is also a major concern.
[0014]
For this reason, a method in which each LSI is individually manufactured and converted to MCM is considered to be promising. FIG. 16 shows an example of such an MCM technology.
[0015]
FIGS. 16A and 16B show a flip-chip system in which semiconductor chips 53 and 54 are connected face-down to electrodes 78 on a wiring board (circuit board) 79 and fixed with an underfill material 95. I have. Here, when considering miniaturization and thinning, the flip chip of FIG. 16 is an advantageous method. Considering the reduction of the connection distance and the variation of each connection impedance in future high-speed operation, the flip-chip method seems to be the main method.
[0016]
As the flip-chip type MCM, for example, for a plurality of different types of LSIs, an Au-Stud @ Bump is formed on the surface of the Al electrode pad 65 of each LSI, and an anisotropic conductive film (ACF: Anisotropic @ Conductive @ Film) is formed. Various methods have been proposed, such as a method of connecting to a circuit board via a via, a method of pressure contact using a resin paste, and a method of using an Au plating bump, a Ni electroless plating bump, and a solder bump as a bump.
[0017]
FIG. 16B is an example in which the metal can be bonded to the wiring board 79 by the solder bumps 75 and the bonding can be reliably performed with lower resistance.
[0018]
The above-described method of forming solder bumps on a wafer at a time can be applied to area pad arrangement on a mounting surface, and has advantages such as batch reflow and double-sided mounting. However, when processing is performed on a wafer having a low cutting-edge yield, the cost per good chip becomes extremely high.
[0019]
That is, FIG. 17 shows a semiconductor wafer 99 in the conventional wafer batch processing. In spite of the need for a high yield in a state-of-the-art LSI, among the chips partitioned by the scribe line 71, a cross mark is used. Actually, the number of defective bare chips 97 shown is larger than the number of good bare chips 98 shown by a mark.
[0020]
Further, there is a problem that it is extremely difficult to form a bump when a chip is obtained from another place in the form of a bare chip. That is, although the above two types of bump forming methods have their respective characteristics, they are not technologies that can be used for all areas, and at present, they are selectively used taking advantage of each characteristic. The wafer batch bump processing method is characterized by high yield, a large number of terminals in one wafer (for example, 50,000 terminals / wafer), and formation of low-damage bumps corresponding to area pads. Au stud bumps are characterized by bump processing when obtained in chip units and simple bump processing.
[0021]
When the semiconductor wafer 99 shown in FIG. 17 is cut along the scribe line 71, the chip may be damaged by stress, cracks, or the like due to the cutting, which may cause a failure. Furthermore, if the process is performed for the non-defective bare chip 98 and the defective bare chip 97 together as a semiconductor wafer 99 until the formation of the solder bumps, the process performed on the defective bare chip 97 becomes useless, which also increases the cost. .
[0022]
Further, in the above-described connection method using solder bumps, it is necessary to form solder bumps on a semiconductor chip in advance, and thus the following problems are raised.
[0023]
For example, the lead time of the manufacturing process from the process of manufacturing a semiconductor chip to the process of forming a solder bump becomes relatively long, and the manufacturing cost increases. This tendency becomes more remarkable especially in a chip state in which a wafer including a plurality of semiconductor chips is divided into respective semiconductor chips.
[0024]
Also, in the formation of solder bumps, certain intervals must be provided in order to prevent adjacent solder bumps on the semiconductor chip from contacting each other and causing a short circuit, and a certain amount of space is required. In a semiconductor chip of a type in which the pitch between adjacent electrode pads for connection to the bump is narrow, the structure becomes relatively unsuitable. This is inconsistent with the recent tendency to increase the number of pins, and is a problem.
[0025]
[Procedure leading to the invention]
Therefore, the present applicant has already proposed a method and a structure that have solved the above-described problems (hereinafter, this will be referred to as a prior application invention). An example will be described below with reference to FIGS.
[0026]
FIG. 18A shows a substrate 51 serving as a temporary support substrate. However, since the heating process for the substrate is performed at 400 ° C. or less, a less expensive glass substrate can be used. This substrate 51 can be used repeatedly.
[0027]
Next, as shown in FIG. 18B, an adhesive sheet 52 of a predetermined thickness, for example, made of an acrylic material, is applied to the substrate 1, the adhesive strength being reduced when heated to a certain temperature or more.
[0028]
Next, as shown in FIG. 18C, a plurality of semiconductor (non-defective bare) chips 53 and 54 which are confirmed as non-defective products are arranged with the surface where the electrode pads 65 are exposed downward, and an adhesive sheet 52 is formed. Paste on top. These non-defective semiconductor chips 53 and 54 may be diced in the process of the normal semiconductor wafer 99 shown in FIG. 17, and may be taken out from the stretched state of the used dicing sheet (not shown). It may be transferred from the tray. What is important here is that only good semiconductor chips 53 and 54 are rearranged on the substrate 51 irrespective of chips made by the company or other companies.
[0029]
Next, as shown in FIG. 18D, a protective material such as an organic insulating resin, for example, an acrylic material is uniformly applied on the chips 53 and 54 to form a protective material layer 55. This application step can be easily realized by a spin coating method, a printing method, or the like.
[0030]
Next, as shown in FIG. 18 (e), by heating to a certain temperature or more, the adhesive force of the adhesive sheet 52 is weakened, and a plurality of the side surfaces and the back surface are continuously solidified by the protective material layer 55. The plate 101 including the good semiconductor chips 53 and 54 is peeled off from the substrate 51.
[0031]
Next, as shown in FIG. 18F, the plate 101 peeled off from the substrate 51 is turned upside down so that the electrode pads 65 of the semiconductor chips 53 and 54 come to the upper surface.
[0032]
Next, as shown in FIG. 18G, an interlayer insulating layer 56 is formed on the upper surface of the plate 101.
[0033]
Next, as shown in FIG. 18H, a hole 57 for forming a wiring is formed in the interlayer insulating layer 56 and a part of the upper surface of the electrode pad 65 is formed on the electrode pad 65 of each of the semiconductor chips 53 and 54. Provided to be exposed.
[0034]
Next, after a wiring material is applied to the upper surface of the interlayer insulating layer 56 and the hole 57, a predetermined wiring pattern 57 is formed using a photoresist or the like as shown in FIG. From this point, the plate 101 is referred to as a pseudo wafer 67.
[0035]
Next, as shown in FIG. 19J, a wiring protection layer 58 is formed so as to cover the rearrangement wiring 57 formed in a predetermined pattern.
[0036]
Next, as shown in FIG. 19K, a plurality of openings 59 (land openings) for taking out wiring are provided in the wiring protection layer 58 at predetermined positions so that a part of the upper surface of the wiring 57 is exposed. .
[0037]
Next, as shown in FIG. 19 (l), a scribing line is formed with a blade 68 (or laser) in units of non-defective chip-shaped electronic components 69 formed by protecting and reinforcing the semiconductor chips 53 and 54 with a protective material layer 55. Dicing 70 is performed along 71 to make individual pieces.
[0038]
FIG. 20 (m) is an enlarged view of the non-defective chip-shaped electronic component 69.
[0039]
FIG. 20 (m ') is a detailed view mainly showing the vicinity of the semiconductor chip 54 in the enlarged view. The semiconductor chip 54 (semiconductor chip 53 is also the same)₂This has a structure in which an Al electrode pad 65 and a passivation film 83 are formed via a film 84.
[0040]
Next, as shown in FIG. 20 (n), a Ni electroless plating layer (UBM) 72 is formed in the opening 59 by a Ni electroless plating method. The Ni electroless plating layer (UBM) 72 is, for example, after pre-treating the upper surface of the wiring 57 with a phosphoric acid-based etchant, substituting and depositing Zn by Zn treatment, and further immersing in a Ni-P plating tank. Thereby, it can be easily formed and acts as a UBM (Under \ Bump \ Metal) which assists the connection between the Al electrode pad 65 and a solder bump described later.
[0041]
Here, the electroless plating layer 72 is continuously formed not only on the opening 59 but also on the wiring protection layer 58 so as to form the land 100 shown by the broken line.
[0042]
Next, as shown in FIG. 20 (o), the solder paste 74 is transferred onto the Ni electroless plating layer (UBM) 72 by a printing method by applying a print mask 73.
[0043]
Next, as shown in FIG. 21 (p), the solder paste 74 is melted by a wet back method to form a solder bump 75. As described above, by using the Ni electroless plating method, the solder paste screen printing method, or the like, the solder bumps 75 can be easily formed without using a photo process.
[0044]
As described above, even for the most advanced LSIs with low yield or chips obtained from other companies, only the good semiconductor chips 53 and 54 are attached to the substrate 51, and as if they were 100% good semiconductor chips 53 and 54. By being able to produce the pseudo wafer 67 composed of only the wafer, it is possible to form the solder bumps at a low cost in one wafer.
[0045]
In the state of FIG. 19 (i), measurement of electrical characteristics by probe inspection and burn-in were performed to select good semiconductor chips 53 and 54 before the step of FIG. 18 (c). Thereby, only good chips can be sorted out.
[0046]
Next, as shown in FIG. 21 (q), the mounting substrate 60 is provided with an electrode 78 surrounded by a solder (solder) resist 76 on a substrate 79 and provided with an electrode 78 coated with a solder (solder) paste 77. The non-defective chip-shaped electronic component 69 is mounted.
[0047]
At this time, since the side surface and the back surface of the non-defective chip-shaped electronic component 69 are covered with the protective material layer 55, the chips 53, Since the 54 is not damaged, high reliability flip-chip mounting can be expected.
[0048]
Although the above description relates to a flip chip mounting technique for a semiconductor chip, it also relates to a connection solder bump forming technique in flip chip high density mounting and a manufacturing method thereof. The chips 53 and 54 are fixed to each other by applying the protective material layer 55 uniformly on the back surface or the like, with the front surface facing down and being arranged on the substrate 51 at equal intervals.
[0049]
Thereafter, the dummy sheet is peeled off from the adhesive sheet 52 to produce a pseudo wafer 67 in which only good semiconductor chips 53 and 54 are arranged, and bumps are formed on the wafer 67 at a time to produce bump chips at low cost. . This bump chip can be used not only for small and lightweight portable electronic devices but also for all electronic devices.
[0050]
According to the above-described steps, the chip-shaped electronic components (such as the semiconductor chips 53 and 54) and the like (hereinafter, a semiconductor chip will be described as a representative example) 69 other than the surface of the electrode pad 65 (that is, the side surfaces and the back surfaces of the chips 53 and 54). Are protected by the continuous protective material layer 55, so that the chips 53 and 54 are protected during handling after chip formation, which facilitates handling and provides good mounting reliability.
[0051]
Also, the semiconductor chips 53 and 54 cut out from the above-described semiconductor wafer 99 and selected only for non-defective products are adhered to the substrate 51, and the protective material layer 55 is applied over the entire surface and then peeled off. Since the pseudo wafer 67 including only the semiconductor chips 53 and 54 is obtained, wiring formation and bump processing can be performed on the wafer at a time, and a good-quality chip-shaped electronic component 69 which is a low-cost bump chip can be formed.
[0052]
Further, when the chips 53 and 54 are cut out from the pseudo wafer 67, the portion of the protective material layer 55 between the chips is cut, so that the semiconductor chips 53 and 54 have an adverse effect (damage such as distortion, burrs, cracks, etc.). And can be easily cut.
[0053]
Moreover, since the side and back surfaces of the chips 53 and 54 are covered with the protective material layer, Ni electroless plating can be performed. And, not only the wafers manufactured in-house but also bare chips purchased from other companies can be easily subjected to solder bump processing and the like.
[0054]
In addition, there are few cases where all the different LSI chips mounted on the MCM are supplied from the same semiconductor maker, and investment in cutting-edge semiconductor lines is increasing. Instead of supplying the arithmetic processing units) by the same semiconductor maker, they may be supplied separately by chips from the respective semiconductor manufacturers, and these may be converted into MCMs.
[0055]
The above substrate can be used repeatedly, which is advantageous in terms of bump formation cost and environment.
[0056]
Further, in the above-described process, the manufacturing process of the semiconductor chips 53 and 54 is performed as a separate process, and only the chips 53 and 54 that have already been determined as good products are used. The lead time, inspection time, and the like of the manufacturing process before the step of forming the semiconductor device can be relatively shortened, and increase in manufacturing cost can be suppressed.
[0057]
In the formation of solder bumps, a certain space must be provided to prevent short-circuiting due to contact between adjacent solder bumps on the semiconductor chip, and a certain amount of space is required. As shown in FIG. 2), the degree of freedom in the formation position of the solder bumps is increased by the arrangement shape of the wiring 57, the land 100, and the like, and in a semiconductor chip of a type in which the pitch between adjacent electrode pads 65 for connection to these solder bumps is narrow. Also, the pitch of the electrode pads can be made shorter and the density can be increased, so that the number of pins can be increased.
[0058]
[Problems to be solved by the invention]
However, although the above-mentioned prior invention has the above-mentioned excellent features, it has been found that there are still the following problems to be improved.
[0059]
That is, as shown in FIGS. 18A to 19I, the pseudo wafer 67 is manufactured through the steps of arranging and fixing the non-defective semiconductor chips 53 and 54 and forming the wiring 57. If a defect such as a pattern defect occurs in the module, the module itself composed of the chips 53 and 54 becomes defective, and the good chips 53 and 54 and the like are discarded, resulting in waste. This has a significant adverse effect on the fabrication cost, especially when dealing with expensive good chips.
[0060]
Since each process is started after the non-defective semiconductor chips 53 and 54 are obtained, the lead time for obtaining the non-defective chip-shaped electronic component 69 having the chips 53 and 54 (or TAT: Turn @ Around \ Time). ) Becomes very long. This increases the in-process inventory in the process using the semiconductor chips 53 and 54.
[0061]
Further, as shown in FIG. 19 (i), a part of the wiring 57 exists on the interlayer insulating layer 56, so that irregularities are easily generated on the interlayer insulating layer 56. For this reason, the wiring 57 is easily damaged by contact with the outside, and when the opening 59 is formed in the wiring protection layer 58 in the next step, the wiring protection layer 58 is not connected to the wiring 57 or the interlayer insulating layer 56. The degree of adhesion and flatness may be insufficient, and as a result, the opening 58 may not be formed with high accuracy.
[0062]
An object of the present invention is to make use of the features of the invention of the prior application as described above, eliminate waste of chip components, obtain high-quality chip-like electronic components at a high yield, at low cost, and shorten the manufacturing process. An object of the present invention is to provide a chip-shaped electronic component and a method for manufacturing the same, a pseudo wafer used for the manufacture thereof, a method for manufacturing the same, and a mounting structure.
[0063]
[Means for Solving the Problems]
That is, in the present invention, the protective substance is applied to almost the entire surface other than the electrode surface of the chip component, and the protective substance is connected to the electrode so as to form substantially the same surface as the surface of the insulating layer provided on the electrode surface. A method of manufacturing a pseudo-wafer or chip-shaped electronic component in which the wiring is embedded in the insulating layer,
Forming a wiring material layer on the support layer,
Processing the wiring material layer to form a wiring basic pattern,
Forming an insulating layer on the wiring basic pattern;
Forming a connection hole in the insulating layer;
A step of fixing a plurality or a plurality of types of the chip components on the insulating layer so that electrodes are located at positions corresponding to the connection holes,
Applying a protective substance to the entire surface including between the plurality or types of chip components,
Removing at least a portion of the support layer;
Connecting the electrode and the wiring basic pattern through the connection hole, a method of manufacturing a pseudo wafer, and further comprising:
A step of separating the chip-shaped electronic component by cutting the protective material between the plurality or the plurality of types of chip components;
And a method for manufacturing a chip-shaped electronic component. Here, the “wiring basic pattern” does not only indicate the pattern of the portion except for the connection hole as compared with the intended final pattern, but may also mean the final pattern (hereinafter the same).
[0064]
In the present invention, the protective substance is applied to almost the entire surface of the chip component other than the electrode surface, and is connected to the electrode so as to be substantially flush with the surface of the insulating layer provided on the electrode surface. The present invention relates to a pseudo wafer or a chip-like electronic component in which wiring is embedded in the insulating layer, and further relates to a mounting structure in which the chip-like electronic component is connected and fixed to a mounting board via the wiring.
[0065]
According to the present invention, before the step of fixing the plurality of or a plurality of types of the chip components on the insulating layer so that the electrodes are located at positions corresponding to the connection holes, a wiring material layer is formed on the support layer. The wiring material layer is processed to form a basic wiring pattern, and the insulating layer is formed on the basic wiring pattern. Therefore, before fixing the chip component, a defective portion is formed in the basic wiring pattern. If there is, this can be determined early by inspection, so that it is possible to prevent the chip component from being fixed to a defective portion of the basic wiring pattern, and thus to eliminate the waste of the chip component and reduce the manufacturing cost. Can be suppressed.
[0066]
Further, the step of preparing or selecting a good chip part as the chip part in advance and the step of forming the basic wiring pattern are performed as separate steps, and after the wiring is formed to some extent, the fixing of the chip part is performed. Therefore, the process (lead time) can be shortened, and the inventory of the chip components to be used in the process can be reduced.
[0067]
Further, since the wiring connected to the electrode is buried in the insulating layer so as to form substantially the same surface as the surface of the insulating layer provided on the electrode surface, the wiring is formed on the insulating layer. There is no protrusion, and the flatness of the insulating layer is improved. Thereby, the wiring is protected by the insulating layer and is hardly damaged, and the adhesion when the wiring protection layer is provided on the wiring and the opening when the land opening is formed in the wiring protection layer. Patterning accuracy can be improved.
[0068]
Also, similar to the prior invention, since the non-defective chip components are rearranged into a pseudo wafer, a wafer composed of all non-defective chips can be obtained. Thus, a low-cost flip-chip chip can be formed, and not only a chip manufactured in-house but also a bare chip purchased from another company can be easily formed with wiring and solder bump processing. Then, when the chip-shaped electronic component is cut out from the pseudo wafer, the portion of the protective material is cut, so that adverse effects on the chip component body (damage such as distortion, burrs, cracks, etc.) are suppressed. In addition, since the chip side surface and the back surface are covered with the protective material, Ni electroless plating can be performed, and the chip side surface and the back surface are protected by the protective material. In this case, the chip is protected and good mounting reliability is obtained.
[0069]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present invention, in order to more reliably achieve the above objects of the present invention,
Forming the wiring material layer on a metal layer;
Removing the part of the wiring material layer to form the wiring basic pattern,
Forming a photosensitive adhesive layer on the wiring basic pattern,
Exposing the photosensitive adhesive layer to a predetermined pattern and developing to form a first connection hole;
A step of fixing the plurality or the plurality of types of semiconductor chips on the photosensitive adhesive layer such that an electrode is positioned at the position of the first connection hole, with the electrode surface thereof facing down,
Applying the protective substance to the entire surface including between the plurality or the plurality of types of semiconductor chips,
Removing at least a portion of the metal layer;
Forming a wiring by filling the first connection hole with a conductive substance;
Forming a protective layer on the wiring,
Forming a second connection hole communicating with the wiring in the protective layer;
Performing the cutting; and
It is desirable to carry out.
[0070]
The first connection hole may be filled with a conductive substance by a printing method or a physical vapor deposition method.
[0071]
Alternatively, in order to further improve the connectivity between the chip-shaped electronic component and the mounting board,
Forming the wiring material layer on a metal layer;
Removing the part of the wiring material layer to form the wiring basic pattern,
Forming a photosensitive adhesive layer on the wiring basic pattern,
Exposing the photosensitive adhesive layer to a predetermined pattern and developing to form a first connection hole;
A step of fixing the plurality or the plurality of types of semiconductor chips on the photosensitive adhesive layer such that an electrode is positioned at the position of the first connection hole, with the electrode surface thereof facing down,
Applying the protective substance to the entire surface including between the plurality or the plurality of types of semiconductor chips,
A step of partially removing the metal layer to leave a protruding shape on the wiring basic pattern;
Forming a wiring by filling the first connection hole with a conductive substance;
Forming a protective layer on the wiring, leaving a tip of the protruding metal layer;
Performing the cutting; and
It is desirable to carry out.
[0072]
Further, it is preferable that the plurality of or a plurality of types of semiconductor chips be connected to each other by the wiring via the first connection hole.
[0073]
Further, in order to increase the degree of freedom in selecting a solder bump formation position, it is desirable to take out the wiring through the second connection hole.
[0074]
In mounting, it is preferable that the semiconductor device is connected and fixed to a mounting substrate via the second connection hole or the protruding metal layer.
[0075]
In order to avoid wasting the semiconductor chip, it is desirable that the chip component determined to be non-defective by characteristic measurement be fixed on the wiring basic pattern only in a portion where the wiring basic pattern is in a normal state.
[0076]
In order to process the connection hole in the insulating layer, the insulating layer is a photosensitive adhesive layer, and the photosensitive adhesive layer is filled into the first connection hole formed by exposure and development. It is preferable that the electrode and the wiring are connected by the conductive material.
[0077]
Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.
[0078]
First embodiment
1 to 4 sequentially show a manufacturing process of a non-defective chip-shaped electronic component according to the present embodiment and a mounting process of the chip-shaped electronic component on a mounting board.
[0079]
First, as shown in FIG. 1A, as a starting material, a metal material 1 made of, for example, Cu and having a predetermined thickness is used as a support material, and a different material from the metal material 1 is provided on the upper surface of the metal material 1. A metal layer 2 which is a metal thin film is formed to a predetermined thickness. At this time, if the same effect is obtained, various forming methods can be arbitrarily selected.
[0080]
Here, the material of the metal layer 2 has an etching ratio sufficiently different from that of the metal material 1 in an etching step described later, and the metal layer 2 is etched when the metal material 1 is etched. The material is not particularly limited as long as the etch rate is sufficiently different so as not to be eroded. For example, if the metal material 1 is Cu, the material of the metal layer 2 is preferably Ti or Ni.
[0081]
If the later-described wiring member 3 is formed by a plating method, the material of the metal layer 2 is selected to have conductivity.
[0082]
Here, in the case of the present embodiment, since both of the metal material 1 and the metal layer 2 may be removed in a process described later, there is no problem in the process, and these may be integrated into a single material layer. Further, as long as the material has the necessary strength and the like as the support material and is easily removable, the material can be arbitrarily selected without being limited to metal.
[0083]
Next, as shown in FIG. 1B, a wiring member 3A made of a conductive material is formed on the entire surface of the metal layer 2 with a predetermined thickness. The material and forming method of the wiring member 3A are not particularly limited. Since the material itself of the metal layer 2 is a conductive substance, even when a semi-additive method suitable for forming a fine circuit is used for forming a wiring, a seed layer for improving electrical connectivity is required. There is an advantage that there is no need to form.
[0084]
Next, as shown in FIG. 1C, the wiring material 3 is processed into a predetermined pattern to form a wiring (basic pattern) 3. As this processing method, for example, a photolithography method or the like can be used.
[0085]
Next, as shown in FIG. 1D, a photosensitive adhesive is applied to a predetermined thickness on the entire surface of the metal layer 2 so as to cover the formed wiring 3, and the photosensitive adhesive layer is formed. 4 is formed.
[0086]
Here, as the material of the photosensitive adhesive, for example, an adhesive material manufactured by Sumitomo Bakelite Co., Ltd. can be used, but the material can be arbitrarily selected if the same effect is obtained. Alternatively, an insulating layer or the like made of a non-photosensitive insulator may be used. When the photosensitive adhesive is used, the photosensitive adhesive may be applied to the substrate 1 by coating a liquid photosensitive adhesive, or by applying a dry film photosensitive adhesive on the metal layer 2 or the like. Lamination may be used.
[0087]
Next, by exposing and developing the photosensitive adhesive layer 4, as shown in FIG. 1E, the photosensitive adhesive layer 4 is to be connected to respective electrode pads 31 of the semiconductor chips 6 and 7, which will be described later. The photosensitive adhesive layer 4 at the location is removed, and a hole 5 (via hole) is formed until a part of the upper surface of the metal layer 2 is exposed.
[0088]
Here, the conditions for exposing and developing the photosensitive adhesive layer 4 can be arbitrarily selected as long as they have the same effect. In addition, the size, position, quantity, and size of the holes 5 (via holes) can be selected. The formation method and the like can be determined according to the arrangement and the like of the semiconductor chips 6 and 7 described later.
[0089]
Next, an appearance inspection of the wiring (basic pattern) 3 is performed in this state.
[0090]
The timing of performing the appearance inspection may be performed before the formation of the photosensitive adhesive layer 4 shown in FIG. 1. For example, if the photosensitive adhesive is a transparent material, the photosensitive adhesive layer 4 may be used. Even after the formation of the wiring 4, the wiring (basic pattern) 3 can be visually observed from the outside. In this case, the appearance of the wiring (basic pattern) 3 under the photosensitive adhesive layer 4 can be inspected, so that dust or the like can be prevented from adhering to the wiring (basic pattern) 3, which is desirable. In any case, if there is a defective portion 32A in the wiring (basic pattern) 3, it can be determined.
[0091]
Next, as shown in FIG. 1 (f), at a good wiring position other than the defective wiring (basic pattern) portion 32A, the position of the hole 5 (via hole) formed in the photosensitive adhesive layer 4 is determined. A plurality of non-defective semiconductor chips 6 and 7 are placed so that the circuit surfaces where the electrode pads 31 are exposed face down, so that the positions of the electrode pads 31 of the semiconductor chips 6 and 7 are matched. Align and fix on top.
[0092]
Here, if the photosensitive adhesive layer 4 is made of a transparent material, the position of the electrode pad 31 on the lower surface of the semiconductor chips 6 and 7 made of an opaque material can be relatively easily aligned with the hole 5. .
[0093]
These non-defective semiconductor chips 6 and 7 may be diced in a normal wafer process and taken out of the stretched state of the used dicing sheet, or may be transferred from a chip tray. Here, it is important to rearrange only good semiconductor chips 6 and 7 manufactured in another process on the photosensitive adhesive layer 4 irrespective of chips made by the company or other companies. Further, the semiconductor chips 6 and 7 to be used may be plural or plural types, and the thicknesses of the chips 6 and 7 may be different from each other.
[0094]
When the semiconductor chips 6 and 7 are aligned and fixed, non-defective semiconductor chips 6 and 7 are not mounted on a portion determined to be a wiring (basic pattern) defective portion 32A in the above-described visual inspection. This can eliminate waste of the semiconductor chips 6 and 7 due to wiring (basic pattern) defects.
[0095]
Next, the semiconductor chips 6 and 7 are completely bonded and fixed to the photosensitive adhesive layer 4 by heat curing or the like. The method for producing such adhesiveness can be other than heat curing.
[0096]
Next, as shown in FIG. 1 (g), the side and back surfaces of each of the semiconductor chips 6 and 7 and the entire surface on the photosensitive adhesive layer 4 are covered with a protective material to form a protective material layer 8.
[0097]
Here, an epoxy resin is generally used as the protective material that is the material of the protective material layer 8. For example, an organic insulating resin such as an acrylic resin 4 is placed on the semiconductor chips 6 and 7. The same material as described above may be applied uniformly. This coating step can be easily realized by a spin coating method or a printing method. Further, the material of the protective substance is not particularly limited as long as the semiconductor chips 6 and 7 can be protected from external impact such as mechanical impact or humidity. The plate 37 in which the semiconductor chips 6 and 7 are protected by the protective material layer 8 is formed by the coating with the protective material layer 8 as described above.
[0098]
Next, as shown in FIG. 2H, after the plate 37 is turned upside down, as shown in FIG. 2I, the metal material 1 made of Cu or the like is removed by etching. As an etchant used in this etching method, an etchant that can completely etch the metal material 1 completely without dissolving the metal material 1 but eroding the metal layer 2 as a metal thin film is used. Here, the kind of the etchant, the etching method, the etching condition, and the like can be arbitrarily selected as long as they have the same effect.
[0099]
Next, as shown in FIG. 2J, the metal layer 2 is removed with a solution capable of selectively etching only the metal layer 2. This makes it possible to remove only the metal layer 2 without damaging the microcircuit already formed under the metal layer 2 in the above-described process, that is, the wiring 3. The wiring 3 is embedded in the photosensitive adhesive layer 4 and has a flat surface without protruding from the upper surface thereof.
[0100]
Here, for example, instead of completely removing the metal material 1 and the metal layer 2 described above, etching is performed so that the metal material 1 and the metal layer 2 can remain on the photosensitive adhesive layer 4 while maintaining an arbitrary shape. However, it can be effectively used as an intermediate material such as a mere support material.
[0101]
For example, by placing markings at necessary places in the process and selectively leaving a part of the metal material 1 or the metal layer 2 as the markings during the above-described etching, the arrangement of the semiconductor chips 6 and 7 can be improved. You can check the position. Further, as will be described later, the necessary portions of the metal material 1 and the metal layer 2 can be left for connection terminals to a motherboard (mounting board).
[0102]
Next, as shown in FIG. 2 (k), when the removal of the metal material 1 and the metal layer 2 is completed, the already formed hole 5 (via hole) is exposed. The inside is filled with a conductive paste 10 such as a silver paste. As a result, the already formed wiring (basic pattern) 3 and the respective electrode pads 31 of the semiconductor chips 6 and 7 are electrically connected. The wiring 3 also connects the semiconductor chips for MCM. At this point, the probing inspection of the chips 6 and 7 can be performed using the wiring 3.
[0103]
Here, in filling the holes 5, for example, a metal sputtering method that has been used in forming a semiconductor circuit is also effective. After a predetermined metal is deposited from the hole 5 (via hole) side by sputtering or the like, unnecessary portions are removed by etching or the like to complete the connection. If the holes 5 (via holes) are filled with the conductive paste 10 or the like after the sputtering, the metal attached in the holes 5 is not eroded.
[0104]
The plate 37 is referred to as a pseudo wafer 17 from the time when the conductive paste 10 is filled (the same applies to the subsequent steps). It is embedded in the agent layer 4 and has a flat surface.
[0105]
Next, as shown in FIG. 2 (l), a predetermined thickness of the wiring protection is formed over the upper surface of the hole 5 filled with the conductive paste 10, the upper surface of the photosensitive adhesive layer 4 and the upper surface of the wiring 3. The layer 13 is formed.
[0106]
Next, as shown in FIG. 2 (m), openings 14 (land openings) for electrical connection between the semiconductor chips 6 and 7 and a mounting substrate 30 described later are formed in the wiring protection layer 13 by photolithography or the like. Is formed such that a part of the upper surface of the wiring 3 is exposed at a predetermined position on the wiring 3.
[0107]
Next, as shown in FIG. 3 (n), a scribe line is formed by a blade 18 (or laser) in units of non-defective chip-shaped electronic components 19 in which the semiconductor chips 6 and 7 are protected by a protective material layer 13 and reinforced. Dicing 20 is performed along 21 to make individual pieces.
[0108]
FIG. 3 (o) is an enlarged view of the singulated non-defective chip-shaped electronic component 19, and FIG. 3 (o ') is a partially detailed view mainly showing the semiconductor chip 54. The semiconductor chip 7 (semiconductor chip 6 is also the same)₂This has a structure in which an Al electrode pad 31 and a passivation film 33 are formed via a film 34.
[0109]
Next, as shown in FIG. 3 (p), a Ni electroless plating layer (UBM) 22 is formed in the opening 14 by a Ni electroless plating method.
[0110]
The Ni electroless plating layer (UBM) 22 is prepared by, for example, pretreating the upper surface of the wiring material 3 with a phosphoric acid-based etchant, substituting and depositing Zn by Zn treatment, and further immersing the Ni-P plating tank. By doing so, it can be easily formed and acts as a UBM (Under \ Bump \ Metal) which helps to connect the Al electrode pad 31 to a solder bump described later.
[0111]
Note that the lands 36 may be formed on the wiring protection layer 13 through the openings 14 as indicated by broken lines.
[0112]
Next, as shown in FIG. 4 (q), a print mask 23 is applied to transfer the solder paste 24 onto the Ni electroless plating layer (UBM) 22 by a printing method, and further as shown in FIG. 4 (r). Next, the solder paste 24 is melted by a wet back method to form a solder bump 25.
[0113]
As described above, by using the Ni electroless plating method and the solder paste screen printing method, the solder bumps 25 can be formed relatively easily without using a photo process.
[0114]
Next, as shown in FIG. 4 (s), the above-mentioned individualized non-defective chip-shaped electronic components 19 are mounted on a mounting substrate 30 provided with an electrode 28 surrounded by a solder (solder) resist 26 on a substrate 29. Is mounted to produce a functional module. At this time, since the solder bumps 25 are already formed on the non-defective chip-shaped electronic component 19, the solder (solder) paste provided on the electrodes 28 on the substrate 29 can be omitted.
[0115]
5 to 6 sequentially show a manufacturing process of another non-defective chip-shaped electronic component 19 and a mounting process of the chip-shaped electronic component 19 on the mounting board 30 according to the present embodiment.
[0116]
That is, as shown in FIG. 5A and a partially enlarged view of FIG. 5A ′, the connection opening 14 (land) is formed in the wiring protection layer 13 as shown in FIG. After performing a step of providing an opening) at a predetermined position on the wiring 3 so that a part of the upper surface of the wiring 3 is exposed, as shown in FIG. A Ni electroless plating layer (UBM) 22 is formed in the opening 14 by an electroless plating method. Note that lands 36 indicated by broken lines may be formed on the wiring protection layer 13 from the openings 14.
[0117]
Next, as shown in FIG. 5C, the solder paste 24 is transferred onto the Ni electroless plating layer (UBM) 22 by a printing method by applying a print mask 23. FIG. 6D shows a state in which the solder paste 24 is melted by, for example, a wet back method to form a solder bump 25.
[0118]
Next, as shown in FIG. 6E, a scribing line is formed by a blade 18 (or laser) in units of non-defective chip-shaped electronic components 19 in which the semiconductor chips 6 and 7 are protected by the protective material layer 13 and reinforced. Dicing 20 is performed along 21 to make individual pieces.
[0119]
Next, as shown in FIG. 6F, the singulated non-defective chip-shaped electronic component 19 is mounted on a mounting substrate 30 provided with an electrode 28 surrounded by a solder (solder) resist 26 on a substrate 29. I do. At this time, since the solder bumps 25 are already formed on the non-defective chip-shaped electronic component 19, the solder (solder) paste provided on the electrodes 28 on the substrate 29 can be omitted.
[0120]
According to such another manufacturing process, the solder bumps 25 are collectively kept in the pseudo wafer 17 rather than forming the solder bumps 25 after dividing the pseudo wafer 17 into individual pieces and separating them into good chip parts 19. Is more efficient.
[0121]
Although all of the above examples relate to the flip-chip mounting technology of a semiconductor chip, they also relate to the wiring and solder bump forming technology in flip-chip high-density mounting and the manufacturing method thereof. In this manner, a chip-shaped electronic component can be manufactured at low cost by forming wiring and bumps. This chip-shaped electronic component can be used not only for small and lightweight portable electronic devices but also for all electronic devices.
[0122]
The protective material layer 8 may be made of an organic insulating resin or an inorganic insulating material. In a state where the semiconductor chips 6 and 7 are fixed with the protective material layer 8, the characteristics of the semiconductor chips 6 and 7 are measured, and a non-defective semiconductor chip or A good chip-shaped electronic component may be selected.
[0123]
According to the present embodiment, as described above, a plurality or a plurality of types of semiconductor chips 6 and 7 are fixed on the photosensitive adhesive layer 4 such that the electrodes 31 are located at positions corresponding to the connection holes 5. Before the step of forming, a wiring material 3A is formed on the metal material 1 and the metal layer 2 as a support material, and the wiring material 3A is processed to form a wiring basic pattern 3, and the photosensitive material is exposed on the wiring basic pattern 3. Since the conductive adhesive layer 4 is formed and the semiconductor chips 6 and 7 are fixed thereon, if there is a defect in the wiring basic pattern 3 before fixing these chips, this is determined early by inspection. Therefore, it is possible to prevent the chips 6 and 7 from being fixed to the defective portion of the basic wiring pattern 3, so that the chips 6 and 7 are not wasted and the manufacturing cost can be reduced.
[0124]
Further, as described above, in order to use the chips 6 and 7 already manufactured as the semiconductor chips, the manufacturing process of the wiring basic pattern 3 is performed as a separate process from the manufacturing process of the chips 6 and 7, Since the chips 6 and 7 can be fixed after the formation to some extent, the manufacturing process (lead time) can be shortened (for example, the entire process time can be shortened to about 1/2), and the chip components 6 and 7 can be reduced.
[0125]
Further, since the photosensitive adhesive layer 4 is used, the connection holes 5 can be formed with high accuracy by exposure and development due to its photosensitive performance, and the fixing of the semiconductor chips 6 and 7 to the photosensitive adhesive layer 4 can be performed by photosensitive. Since the bonding can be performed by the adhesive force of the adhesive, the bonding and fixing can be performed more reliably.
[0126]
Further, since the wiring 3 connected to the electrode 31 is embedded in the photosensitive adhesive layer 4 so as to be substantially flush with the surface of the photosensitive adhesive layer 4 provided on the surface of the electrode 31, The wiring 3 does not protrude above the conductive adhesive layer 4, and the surface flatness is improved. As a result, the wiring 3 is protected by the photosensitive adhesive layer 4 and is less likely to be damaged. In addition, when the wiring protection layer 13 is provided on the wiring 3, the adhesion and the land opening 14 are formed in the wiring protection layer 13. And the patterning accuracy of the opening when forming the pattern can be improved.
[0127]
In addition, since the non-defective chips 6 and 7 are rearranged into the pseudo wafer 17, a wafer including all non-defective chips can be obtained, so that wiring formation and solder bump processing can be performed on the wafer at a time. A low-cost flip-chip chip can be formed, and not only a chip manufactured in-house but also a bare chip purchased from another company can be easily formed with wiring and solder bump processing. Then, when the chip-shaped electronic component 19 is cut out from the pseudo wafer 17, the portion of the protective material 8 is cut, so that adverse effects on the chips 6 and 7 (damage such as distortion, burrs, cracks, etc.) can be suppressed. In addition, since the chip side surface and the back surface are covered with the protective material 8, Ni electroless plating can be performed, and the chip side surface and the back surface are similarly protected by the protective material. The chip is protected during mounting handling, and good mounting reliability is obtained.
[0128]
As shown in FIG. 1E, by forming the photosensitive adhesive layer 4 with a transparent material, the wiring (basic pattern) 3 and the like can be easily viewed, and the semiconductor chips 6 and 7 can be easily observed. Can be performed relatively easily.
[0129]
Then, the photosensitive adhesive layer 4 remains as an interlayer insulating layer of the non-defective chip-shaped electronic component 19 without being removed and removed, and also in the resin molding step of FIG. 1 (g) for protecting the semiconductor chips 6 and 7. It also has sufficient heat resistance without deterioration.
[0130]
Second embodiment
In the present embodiment, as shown in FIGS. 7 and 8, in the step of etching the metal material 1 and the metal layer 2, the metal material 1 and the metal layer 2 are not entirely removed by etching, but are partially removed. Is substantially the same as the above-described first embodiment except that the structure is left as a post portion 9 serving as a connection terminal to a motherboard (mounting board).
[0131]
First, the structure shown in FIG. 7A is the same as the structure shown in FIG. 1H described above, and the semiconductor chips 6 and 7 are removed by performing the steps shown in FIGS. 1A to 1G. This shows a state in which a plate 37 having a structure protected by the protective material layer 8 is manufactured, and this is turned upside down so that the metal material 1 is on the upper side.
[0132]
Next, as shown in FIG. 7B, an upper layer of the post portion 9 is formed in order to leave a post portion 9 having a substantially trapezoidal cross section serving as a connection terminal to the mounting substrate 30 described later on the wiring 3. The portion of the metal material 1 is selectively etched and removed.
[0133]
Next, as shown in FIG. 7C, in order to leave the post portion 9 on the wiring 3, the lower metal layer 2 is selectively etched and partially removed using the post upper layer 1 as a mask. I do. In this way, the post portion 9 in which the two layers of the upper metal material 1 and the lower metal layer 2 are laminated is completely formed. This can be performed accurately because the etching rates of the metal layers 1 and 2 are different. By this etching, the surface of the photosensitive adhesive layer 4, the hole 5, and the surface of the wiring 3 are exposed.
[0134]
Next, as shown in FIG. 7D, the wiring 3 is formed by filling the exposed hole 5 (via hole) with the conductive paste 10, and the plate 37 is used as the pseudo wafer 17. At this point, in order to determine the wiring (basic pattern) defective portion 32A, the probing inspection of the semiconductor chips 6 and 7 can be performed in addition to the visual inspection of the wiring (basic pattern) 3 already performed.
[0135]
Next, as shown in FIG. 7 (e), the exposed surface of the photosensitive adhesive layer 4 and the surface of the wiring 3, etc. are covered with the protective material 8 adhered to the back surfaces of the semiconductor chips 6 and 7. Is covered with a protective material layer 12 which may be the same material. At this time, a part of the head of the post part 9 on the wiring 3 (mainly the part of the metal material 1) is made to protrude from the protective material layer 12.
[0136]
Next, as shown in FIG. 8F, the dummy wafer 17 is diced into individual non-defective chip-shaped electronic components 19.
[0137]
Next, as shown in FIG. 8 (g), an individual is mounted on a mounting substrate 30 provided with an electrode 28 surrounded by a solder (solder) resist 26 on a substrate 29 and having a solder (solder) paste 27 applied thereto. The pieced non-defective chip-shaped electronic component 19 is mounted to produce a functional module. At this time, solder bumps may be formed on the mounting substrate 30 side (the same applies hereinafter).
[0138]
Here, the size, shape, position, and the like of the post portion 9 can be determined by conditions such as the arrangement of the semiconductor chips. In addition, the conditions of each of the above-described etchings, the type of the etchant, the material and the forming method of the wiring protection layer 12, and the like may be arbitrarily selected as long as they have the same effect.
[0139]
FIG. 9A shows a main part of the connection state of the non-defective chip-shaped electronic component 19 and the mounting board 30 using the post part 9 by the solder part 38 according to the present embodiment, and FIG. Shows a main part in a state where the non-defective chip component 19 and the mounting board 30 are connected by the solder part 38 without using the post part 9.
[0140]
9A and 9B, d1 and d2 represent the distance between the surface of the mounting board 30 and the surface of the non-defective chip-shaped electronic component 19, respectively, and F1 and F1 'denote the non-defective chip-shaped components at the time of soldering. The difference between the thermal expansion coefficients of the electronic component 19 (especially, the silicon substrate) and the mounting substrate 30 indicates the vector value of the stress generated in the solder connection portion from the base point 39 in the horizontal direction, and F2, F2 ', F3, and F3'. Represents vector values obtained by decomposing F1 and F1 ′.
[0141]
Here, when the vector value F1 generated in the horizontal direction from the base point 39 shown in FIG. 9A is the same value as the vector value F1 ′ shown in FIG. Since the portion 9 has a protruding shape, the distance d1 between the surface of the mounting substrate 30 and the surface of the non-defective chip-shaped electronic component 19 is equal to the distance d1 between the surface of the mounting substrate 30 and the non-defective chip-shaped electronic component 19 shown in FIG. It is longer than the distance d2 to the surface (d1> d2).
[0142]
For this reason, when the vector value F1 shown in FIG. 9A is decomposed into F2 and F3, the angle between F1 and F2 is changed from the vector value F1 ′ shown in FIG. 9B to F2 ′ and F3. The angle is larger than the angle between F1 'and F2' when decomposed.
[0143]
As a result, the vector value F2 becomes smaller than the vector value F2 ′. In the present embodiment, the stress F2 (at the time of contraction) generated in the solder connection portion in the horizontal direction from the base point 39 is reduced, and the solder connection portion is reduced. Is considered to be difficult to destroy.
[0144]
For this reason, the underfill material conventionally provided between the non-defective chip-shaped electronic component 69 and the mounting board 60 in order to alleviate the stress due to the difference in the thermal expansion coefficient and prevent the destruction of the solder connection portion is used in the present embodiment. In the embodiment, it can be omitted. That is, if the underfill material is present, it cannot be removed from the mounting substrate when the non-defective chip-shaped electronic component 69 is to be repaired (replaced) after being mounted. However, in the present embodiment, the underfill material can be omitted. The electronic component can be easily repaired.
[0145]
As described above, according to the present embodiment, the stress on the solder portion 38 (connection portion) is relatively reduced by the post portion 9, so that the connection reliability between the chip-like electronic component 19 and the mounting board 30 as the motherboard is reduced. The property can be secured without the underfill material.
[0146]
Further, since the underfill material is unnecessary, the repair of the chip-shaped electronic component 19 is facilitated, and the heat generated at the time of driving the circuit can be released from the space without the underfill material.
[0147]
In addition, since a Cu plate is used for the metal material 1 as a support material, the Cu plate is formed in various shapes other than the connection terminals (post portions 9) described above, so that various changes in manufacturing or structure can be achieved. It can be developed. For example, the metal material 1 is processed to form a wiring, and the wiring can be used as a wiring between an interposer (intermediate substrate) and a semiconductor chip.
[0148]
In addition, in the present embodiment, the same operations and effects as those described in the first embodiment can be obtained.
[0149]
Third embodiment
In the present embodiment, as shown in FIGS. 10 to 12, a metal material 11 is formed with a predetermined thickness on a metal material 1, and at the time of etching these metal materials 1, 11 and a metal layer 2, The second embodiment is described above except that the metal materials 1 and 11 and the metal layer 2 are not entirely removed by etching, but a part is left as a post portion 9 serving as a connection terminal to a motherboard (mounting board). This is almost the same as the embodiment.
[0150]
First, the structure of FIG. 10A is the same as the structure of FIG. 2A described above, and a plate 37 having a structure in which the semiconductor chips 6 and 7 are protected by the protective material layer 8 is manufactured through the above-described steps. This shows a state in which the metal material 1 is turned upside down and turned upside down.
[0151]
Next, as shown in FIG. 10B, a metal material 11 is formed on the entire surface of the metal material 1 with a predetermined thickness. At this time, since the metal material 1 is not etched at the same time as the metal material 11 in an etching process of the metal material 11 described later, the material of the metal material 11 is assumed to have an etch rate different from that of the metal material 1. Further, if the material of the metal material 11 is solder, it can be used as a connection member in a mounting step described later.
[0152]
Next, as shown in FIG. 10C, an upper layer of the post portion 9 is formed in order to leave a pillar-shaped post portion 9 having a substantially trapezoidal cross section serving as a connection terminal to the mounting board 30 described later on the wiring 3. The portion of the metal material 11 is selectively etched to leave an island shape.
[0153]
Next, as shown in FIG. 10D, the portion of the metal material 1 forming the intermediate layer of the post 9 is selectively etched using the island-shaped metal material 11 as a mask.
[0154]
Next, as shown in FIG. 11E, using the metal materials 11 and 2 as a mask, the portion of the metal layer 2 forming the lower layer of the post 9 is selectively etched. In this manner, a post portion 9 in which the three layers of the upper metal material 11, the intermediate metal material 1, and the lower metal layer 2 are laminated is formed, and the surface of the photosensitive adhesive layer 4, the hole 5, and the wiring 3 are formed. Expose the surface.
[0155]
Next, as shown in FIG. 11 (f), the exposed holes 5 (via holes) are filled with the conductive paste 10, and the plate 37 is used as the pseudo wafer 17. At this point, probing inspection of the semiconductor chips 6 and 7 can be performed in addition to the appearance inspection of the wiring (basic pattern) 3 already performed to determine the wiring (basic pattern) defective portion 32A.
[0156]
Next, as shown in FIG. 11 (g), the exposed surface of the photosensitive adhesive layer 4 and the surface of the wiring 3 are made to adhere to the back surface side of the semiconductor chips 6 and 7 with a protective substance. It is covered with a protective material layer 12, which may be the same material. At this time, a part of the head of the post part 9 on the wiring 3 (mainly the part of the metal material 11) is made to protrude from the protective material layer 12.
[0157]
Next, as shown in FIG. 12 (h), the pseudo wafer 17 is diced into individual non-defective chip-shaped electronic components 19.
[0158]
Next, as shown in FIG. 12 (i), an individual is mounted on a mounting substrate 30 provided with an electrode 28 surrounded by a solder (solder) resist 26 on a substrate 29 and having a solder (solder) paste 27 applied thereto. The pieced non-defective chip-shaped electronic component 19 is mounted to produce a functional module. At this time, if the material of the metal material 11 that forms the upper part of the post part 9 and comes into contact with the mounting board 30 is solder, the amount of the solder (solder) paste 27 to be applied can be reduced.
[0159]
In addition, in the present embodiment, the same operations and effects as those described in the above-described first and second embodiments can be obtained.
[0160]
Fourth embodiment
In the present embodiment, as shown in FIG. 13, when forming the wiring (basic pattern) 3, the portion of the wiring material 3A located below the hole 5 is left without being removed, and the semiconductor chips 6 and 7 are further removed. Is substantially the same as that of the above-described first embodiment except that the holes 5 are filled with the conductive paste 10 before the array is fixed on the photosensitive adhesive layer 4.
[0161]
First, as shown in FIG. 13A, a metal material 1 as a supporting material is prepared, and a metal layer 2 which is a metal thin film different from the metal material 1 is provided on the upper surface of the metal material 1 to a predetermined thickness. Formed.
[0162]
Next, as shown in FIG. 13B, a wiring material 3A made of a conductive substance is formed on the entire surface of the metal layer 2 to a predetermined thickness.
[0163]
Next, as shown in FIG. 13C, the wiring material 3A is processed into a predetermined pattern to form the wiring (basic pattern) 3. At this time, the wiring member 3A at the position where the hole 5 is formed is not removed. The appearance of the wiring 3 is inspected, and the quality of the wiring 3 can be determined.
[0164]
Next, as shown in FIG. 13D, a photosensitive adhesive is applied to a predetermined thickness on the entire surface so as to cover the formed wiring 3 to form a photosensitive adhesive layer 4.
[0165]
Next, by performing exposure and development processing on the photosensitive adhesive layer 4, as shown in FIG. 13E, the respective electrode pads 31 of the semiconductor chips 6 and 7 and the wiring 3 are electrically connected. The portion of the photosensitive adhesive layer 4 where the connection is made is removed, and a hole 5 (via hole) is formed until a part of the upper surface of the wiring 3 is exposed. At this time, an appearance inspection for determining the wiring (basic pattern) defective portion 32A can be performed.
[0166]
Next, as shown in FIG. 13F, the conductive paste 10 is filled in the holes 5.
[0167]
Next, as shown in FIG. 13 (g), the positions of the holes 5 (that is, the conductive paste 10) formed in the conductive adhesive layer 4 and the positions of the electrode pads 31 of the non-defective semiconductor chips 6 and 7 are determined. And a plurality of non-defective semiconductor chips 6 and 7 are aligned and fixed on the photosensitive adhesive layer 4 with the exposed circuit surfaces of the electrode pads 31 facing down except for the defective wiring portions 32. Then, the electrode pad 31 and the wiring 3 are electrically connected.
[0168]
Next, the semiconductor chips 6 and 7 are bonded and fixed on the photosensitive adhesive layer 4 by heat curing or the like.
[0169]
Thereafter, the metal materials 1 and 2 are removed to obtain a state similar to that of FIG. 2K, and in this state, the probing inspection of the semiconductor chips 6 and 7 can be performed. Then, the non-defective chip-shaped electronic component 19 can be mounted on the mounting board 30 through substantially the same steps as those shown in FIGS. 2 (l) to 4 (s).
[0170]
In the present embodiment, as shown in FIG. 13C, when the wiring material 3A is processed into a predetermined pattern to form the wiring (basic pattern) 3, the wiring material 3A is formed below the hole 5. Since it is not removed, a part of the wiring member 3A is not wasted.
[0171]
Before the semiconductor chips 6 and 7 are bonded and fixed, the conductive paste 10 is filled in the holes 5 and is already connected to the wiring 3. Therefore, after the metal materials 1 and 2 are removed, the probing of the semiconductor chips 6 and 7 is performed. Inspection can be performed.
[0172]
In addition, in the present embodiment, the same operations and effects as those described in the first embodiment can be obtained.
[0173]
Fifth embodiment
In this embodiment, as shown in FIG. 14, after the wiring (basic pattern) 3 and the conductive portion in the hole 5 (via hole) are integrally formed, the semiconductor chips 6 and 7 are coated with the photosensitive adhesive layer. The arrangement is almost the same as that of the above-described first embodiment except that the arrangement is fixed on the upper surface 4.
[0174]
First, as shown in FIG. 14A, a metal material 1 as a supporting material is prepared, and a metal layer 2 which is a metal thin film different from the metal material 1 is provided on the upper surface of the metal material 1 to a predetermined thickness. Formed.
[0175]
Next, as shown in FIG. 14B, a wiring member 3B made of a conductive material is formed on the entire surface of the metal layer 2 to a predetermined thickness.
[0176]
Next, as shown in FIG. 14C, a part of the wiring member 3B is processed and removed to an intermediate depth to form a wiring convex portion 15, and further, as shown in FIG. The wiring material 3 </ b> B is partially processed at portions other than the portion 15 to form a structure in which the protrusion 15 and the wiring (basic pattern) 3 are integrated. Here, the position, quantity, shape, size, and the like of the wiring protrusions 15 correspond to the holes 5 described above. In addition, as a processing method of the wiring member 3B, for example, an etching method, a sand blast method, or the like can be used.
[0177]
Next, as shown in FIG. 14 (e), a photosensitive adhesive is applied to a predetermined thickness on the upper surface of the metal layer 2 so as to cover the formed wiring 3 and the convex portion 15, and An adhesive layer 4 is formed. At this point, the appearance inspection of the wiring (basic pattern) 3 can be performed, but it is needless to say that the inspection may be performed at the stage of FIG.
[0178]
At this time, the top surface of the wiring projection 15 made of a conductive material is present on the same plane as the surface of the photosensitive adhesive layer 4 or slightly protrudes from the electrode pads 31 of the semiconductor chips 6 and 7 and the wiring 3. This is desirable for good connection between. To make this connection sufficient, for example, the connection can be made using an anisotropic conductive film or the like.
[0179]
Next, as shown in FIG. 14F, the positions of the tops 15 of the wiring protrusions 15 embedded in the photosensitive adhesive layer 4 and the positions of the electrode pads 31 of the good semiconductor chips 6 and 7 are described. A plurality of non-defective semiconductor chips 6 and 7 are aligned and fixed on the photosensitive adhesive layer 4 with the exposed circuit surfaces of the electrode pads 31 facing downward.
[0180]
Next, the semiconductor chips 6 and 7 are bonded and fixed on the photosensitive adhesive layer 4 by thermal curing or the like, and further, the metal materials 1 and 2 are removed, and the probing inspection of the semiconductor chips 6 and 7 can be performed.
[0181]
Thereafter, the step of filling the conductive paste 10 shown in FIG. 2 (k) is omitted, and through substantially the same steps as those of FIGS. 2 (l) to 4 (s), the non-defective chip-shaped electronic component 19 is formed. Can be mounted on the mounting substrate 30.
[0182]
In the present embodiment, in the step shown in FIG. 14D, a conductive substance (contact plug) connected to the wiring 3 is integrally formed also in the hole 5 described above. The connection process can be simplified, and when the metal material 1 and the metal layer 2 are removed, the process can be immediately shifted to the process of forming the protective layer 13 because the wiring 3 has already been completed.
[0183]
In addition, in the present embodiment, the same operations and effects as those described in the first embodiment can be obtained.
[0184]
The embodiment described above can be further modified based on the technical idea of the present invention.
[0185]
For example, in the state shown in FIG. 2 (k) in which the conductive paste 10 is filled in the hole 5, the wiring paste can be mounted on the mounting substrate 30 without providing the wiring protection layer 13 and the opening 14 (land opening). At this time, a solder bump may be formed on the mounting substrate 30 and connected by solder.
[0186]
In FIG. 7E, if the strength of the post portion 9 is sufficient, the protective material layer 12 may be thin or may be omitted in some cases. In these cases, the chip-shaped electronic component 19 and the mounting substrate 30 can be further separated, which is advantageous.
[0187]
Further, the object to which the present invention is applied is not limited to a semiconductor chip, and may be various other chip-shaped electronic components that involve cutting into individual chips.
[0188]
Operation and Effect of the Invention
According to the present invention, before the step of fixing the plurality of or a plurality of types of the chip components on the insulating layer so that the electrodes are located at positions corresponding to the connection holes, a wiring material layer is formed on the support layer. The wiring material layer is processed to form a basic wiring pattern, and the insulating layer is formed on the basic wiring pattern. Therefore, before fixing the chip component, a defective portion is formed in the basic wiring pattern. If there is, this can be determined early by inspection, so that it is possible to prevent the chip component from being fixed to a defective portion of the basic wiring pattern, and thus to eliminate the waste of the chip component and reduce the manufacturing cost. Can be suppressed.
[0189]
Further, the step of preparing or selecting a good chip part as the chip part in advance and the step of forming the basic wiring pattern are performed as separate steps, and after the wiring is formed to some extent, the fixing of the chip part is performed. Therefore, the process (lead time) can be shortened, and the inventory of the chip components to be used in the process can be reduced.
[0190]
Further, since the wiring connected to the electrode is buried in the insulating layer so as to form substantially the same surface as the surface of the insulating layer provided on the electrode surface, the wiring is formed on the insulating layer. There is no protrusion, and the flatness of the insulating layer is improved. Thereby, the wiring is protected by the insulating layer and is hardly damaged, and the adhesion when the wiring protection layer is provided on the wiring and the opening when the land opening is formed in the wiring protection layer. Patterning accuracy can be improved.
[0191]
In addition, since non-defective chip components are rearranged into a pseudo wafer, it is possible to obtain a wafer consisting of non-defective chips, so that wiring formation and solder bump processing can be performed on the whole wafer and low cost. Flip chip chips can be formed, and wiring formation and solder bump processing can be easily performed not only on in-house chips but also on bare chips purchased from other companies. Then, when the chip-shaped electronic component is cut out from the pseudo wafer, the portion of the protective material is cut, so that adverse effects on the chip component body (damage such as distortion, burrs, cracks, etc.) are suppressed. In addition, since the chip side surface and the back surface are covered with the protective material, Ni electroless plating can be performed, and the chip side surface and the back surface are protected by the protective material. In this case, the chip is protected and good mounting reliability is obtained.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views sequentially showing steps of manufacturing a chip-shaped electronic component according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view sequentially showing a manufacturing process.
FIG. 3 is a cross-sectional view sequentially showing a manufacturing process.
FIG. 4 is a cross-sectional view showing a mounting process of the chip-shaped electronic component.
FIG. 5 is a sectional view sequentially showing another manufacturing step.
FIG. 6 is a cross-sectional view sequentially showing another manufacturing process and a mounting process thereof.
FIG. 7 is a sectional view sequentially showing a step of manufacturing a chip-shaped electronic component according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a mounting process of the chip-shaped electronic component.
FIG. 9 is an enlarged sectional view of an essential part for comparing and explaining a situation at the time of mounting.
FIGS. 10A to 10C are cross-sectional views sequentially showing steps of manufacturing a chip-shaped electronic component according to a third embodiment of the present invention.
FIG. 11 is a cross-sectional view showing the manufacturing process.
FIG. 12 is a cross-sectional view showing a mounting process of the chip-shaped electronic component.
FIG. 13 is a cross-sectional view sequentially showing the steps of manufacturing the chip-shaped electronic component according to the fourth embodiment of the present invention.
FIG. 14 is a cross-sectional view sequentially showing the steps of manufacturing the chip-shaped electronic component according to the fifth embodiment of the present invention.
FIG. 15 is a cross-sectional view sequentially showing steps of manufacturing a chip-shaped electronic component according to a conventional example.
FIGS. 16A and 16B are partial cross-sectional side views of the mounting structure converted into the MCM.
FIG. 17 is a perspective view of a semiconductor wafer for coping with wafer batch processing.
FIG. 18 is a sectional view sequentially showing the steps of manufacturing the chip-shaped electronic component according to the invention of the prior application.
FIG. 19 is a cross-sectional view sequentially showing the manufacturing process.
FIG. 20 is a cross-sectional view sequentially showing the manufacturing process.
FIG. 21 is a cross-sectional view showing a step of mounting the chip-shaped electronic component.
[Explanation of symbols]
11 metal material, 2 metal layer, 3 wiring, 3A, 3B wiring material,
4: photosensitive adhesive layer, 5: hole (via hole), 6, 7: semiconductor chip,
8, 12: protective material layer, 9: post part, 10: conductive paste,
13: wiring protection layer, 14: opening (land opening), 15: wiring projection,
17: pseudo wafer, 18: blade, 19: non-defective chip-shaped electronic component,
20: dicing, 21: scribe line, 22: electroless plating layer,
23: printing mask, 24: solder paste, 25: solder bump,
26, 27: solder (solder) resist, 28: electrode, 30: mounting board,
31: electrode pad, 32: defective wiring location,
32A: defective wiring (basic pattern), 33: passivation film,
34 ... SiO₂Film, 35: silicon substrate, 36: land, 37: plate,
38: solder part, 39: base point,
d1, d2: distance between the surface of the mounting board and the surface of the non-defective chip-shaped electronic component;
F1, F1 ', F2, F2', F3, F3 '... stress vector values

Claims (34)

A wiring connected to the electrode is formed on the insulating layer so that the protective substance is applied to almost the entire surface of the chip component other than the electrode surface, and forms substantially the same surface as the surface of the insulating layer provided on the electrode surface. A method of manufacturing a chip-like electronic component embedded in
Forming a wiring material layer on the support layer,
Processing the wiring material layer to form a wiring basic pattern,
Forming an insulating layer on the wiring basic pattern;
Forming a connection hole in the insulating layer;
A step of fixing a plurality or a plurality of types of the chip components on the insulating layer so that electrodes are located at positions corresponding to the connection holes,
Applying a protective substance to the entire surface including between the plurality or types of chip components,
Removing at least a portion of the support layer;
Connecting the electrode and the wiring basic pattern via the connection hole;
Cutting the protective material between the plurality or the plurality of types of chip components to separate the chip electronic components. Forming the wiring material layer on a metal layer;
Removing the part of the wiring material layer to form the wiring basic pattern,
Forming a photosensitive adhesive layer on the wiring basic pattern,
Exposing the photosensitive adhesive layer to a predetermined pattern and developing to form a first connection hole;
A step of fixing the plurality or the plurality of types of semiconductor chips on the photosensitive adhesive layer such that an electrode is positioned at the position of the first connection hole, with the electrode surface thereof facing down,
Applying the protective substance to the entire surface including between the plurality or the plurality of types of semiconductor chips,
Removing at least a portion of the metal layer;
Forming a wiring by filling the first connection hole with a conductive substance;
Forming a protective layer on the wiring,
Forming a second connection hole communicating with the wiring in the protective layer;
The method for manufacturing a chip-shaped electronic component according to claim 1, further comprising the step of performing the cutting. The method for manufacturing a chip-shaped electronic component according to claim 2, wherein the filling of the first connection hole with a conductive substance is performed by printing or physical vapor deposition. Forming the wiring material layer on a metal layer;
Removing the part of the wiring material layer to form the wiring basic pattern,
Forming a photosensitive adhesive layer on the wiring basic pattern,
Exposing the photosensitive adhesive layer to a predetermined pattern and developing to form a first connection hole;
A step of fixing the plurality or the plurality of types of semiconductor chips on the photosensitive adhesive layer such that an electrode is located at the position of the first connection hole, with the polar face thereof facing down,
Applying the protective substance to the entire surface including between the plurality or the plurality of types of semiconductor chips,
A step of partially removing the metal layer to leave a protruding shape on the wiring basic pattern;
Forming a wiring by filling the first connection hole with a conductive substance;
Forming a protective layer on the wiring, leaving a tip of the protruding metal layer;
The method for manufacturing a chip-shaped electronic component according to claim 1, further comprising the step of performing the cutting. The method for manufacturing a chip-shaped electronic component according to claim 2, wherein the plurality of or a plurality of types of semiconductor chips are connected by the wiring via the first connection holes. The method for manufacturing a chip-shaped electronic component according to claim 2, wherein the wiring is taken out through the second connection hole. The method for manufacturing a chip-shaped electronic component according to claim 2, wherein a chip-shaped electronic component connected and fixed to a mounting board via the second connection hole or the protruding metal layer is manufactured. 2. The method for manufacturing a chip-like electronic component according to claim 1, wherein the chip component determined to be non-defective by characteristic measurement is fixed onto the basic wiring pattern when the basic wiring pattern is in a normal state. A wiring connected to the electrode is formed on the insulating layer so that the protective substance is applied to almost the entire surface of the chip component other than the electrode surface, and forms substantially the same surface as the surface of the insulating layer provided on the electrode surface. Chip-shaped electronic components embedded in The said insulating layer is a photosensitive adhesive layer, The said electrode and the said wiring are connected by the electrically conductive substance filled in the 1st connection hole formed in this photosensitive adhesive layer. 2. The chip-shaped electronic component according to item 1. The chip-shaped electronic component according to claim 9, wherein a protective layer is formed on the wiring, and the wiring is taken out through a second connection hole formed in the protective layer. The chip-shaped electronic component according to claim 11, wherein a conductive layer connected to the wiring is provided in the second connection hole so as to protrude above the protective layer. The chip-shaped electronic component according to claim 9, wherein the plurality or the plurality of types of semiconductor chips are connected to each other by the wiring via the first connection hole. The chip-shaped electronic component according to claim 9, wherein the chip component determined to be non-defective by characteristic measurement is connected to the wiring in a normal state. A protective substance is applied to almost the entire surface other than the electrode surface of a plurality or a plurality of types of chip components, and is connected to the electrode so as to form substantially the same surface as the surface of an insulating layer provided on the electrode surface. A method of manufacturing a pseudo wafer in which the wiring is embedded in the insulating layer,
Forming a wiring material layer on the support layer,
Processing the wiring material layer to form a wiring basic pattern,
Forming an insulating layer on the wiring basic pattern;
Forming a connection hole in the insulating layer;
A step of fixing a plurality or a plurality of types of the chip components on the insulating layer so that electrodes are located at positions corresponding to the connection holes,
Applying a protective substance to the entire surface including between the plurality or types of chip components,
Removing at least a portion of the support layer;
Connecting the electrode and the wiring basic pattern via the connection hole. Forming the wiring material layer on a metal layer;
Removing the part of the wiring material layer to form the wiring basic pattern,
Forming a photosensitive adhesive layer on the wiring basic pattern,
Exposing the photosensitive adhesive layer to a predetermined pattern and developing to form a first connection hole;
A step of fixing the plurality or the plurality of types of semiconductor chips on the photosensitive adhesive layer such that an electrode is positioned at the position of the first connection hole, with the electrode surface thereof facing down,
Applying the protective substance to the entire surface including between the plurality or the plurality of types of semiconductor chips,
Removing at least a portion of the metal layer and filling the first connection hole with a conductive material to form a wiring;
Forming a protective layer on the wiring,
Forming a second connection hole communicating with the wiring in the protective layer. 17. The method for manufacturing a pseudo wafer according to claim 16, wherein the first connection hole is filled with a conductive substance by printing or physical vapor deposition. Forming the wiring material layer on a metal layer;
Removing the part of the wiring material layer to form the wiring basic pattern,
Forming a photosensitive adhesive layer on the wiring basic pattern,
Exposing the photosensitive adhesive layer to a predetermined pattern and developing to form a first connection hole;
A step of fixing the plurality or the plurality of types of semiconductor chips on the photosensitive adhesive layer such that an electrode is positioned at the position of the first connection hole, with the electrode surface thereof facing down,
Applying the protective substance to the entire surface including between the plurality or the plurality of types of semiconductor chips,
A step of partially removing the metal layer to leave a protruding shape on the wiring basic pattern;
Forming a wiring by filling the first connection hole with a conductive substance;
Forming a protective layer on the wiring while leaving a tip of the protruding metal layer, the method of manufacturing a pseudo wafer according to claim 15. 19. The method of manufacturing a pseudo wafer according to claim 16, wherein the plurality or the plurality of types of semiconductor chips are connected to each other by the wiring via the first connection hole. 17. The method of manufacturing a pseudo wafer according to claim 16, wherein the wiring is taken out through the second connection hole. 19. The method for manufacturing a pseudo wafer according to claim 16, wherein a chip-shaped electronic component connected and fixed to a mounting substrate via the second connection hole or the protruding metal layer is manufactured. 16. The method of manufacturing a pseudo wafer according to claim 15, wherein when the basic wiring pattern is in a normal state, the chip component determined to be non-defective by characteristic measurement is fixed on the basic wiring pattern. A protective substance is applied to almost the entire surface other than the electrode surface of the plurality of or plural types of chip components, and the plurality of or plural types of chip components are integrated, and the surface of the insulating layer provided on the electrode surface A pseudo wafer, wherein a wiring connected to the electrode is embedded in the insulating layer so as to have substantially the same surface as that of the pseudo wafer. 24. The insulating layer is a photosensitive adhesive layer, and the electrode and the wiring are connected by a conductive material filled in a first connection hole formed in the photosensitive adhesive layer. A pseudo wafer according to item 1. 24. The pseudo wafer according to claim 23, wherein a protective layer is formed on the wiring, and the wiring is taken out through a second connection hole formed in the protective layer. 26. The pseudo wafer according to claim 25, wherein a conductive layer connected to the wiring is provided in the second connection hole so as to protrude above the protective layer. 24. The pseudo wafer according to claim 23, wherein a plurality or a plurality of types of semiconductor chips are connected to each other by the wiring via the first connection hole. 24. The pseudo wafer according to claim 23, wherein the chip component determined to be non-defective by characteristic measurement is connected to the wiring in a normal state. A wiring connected to the electrode is formed on the insulating layer so that the protective substance is applied to almost the entire surface of the chip component other than the electrode surface, and forms substantially the same surface as the surface of the insulating layer provided on the electrode surface. A chip-shaped electronic component embedded in the substrate is connected and fixed to a mounting substrate via the wiring. 30. The insulating layer is a photosensitive adhesive layer, and the electrode and the wiring are connected by a conductive material filled in a first connection hole formed in the photosensitive adhesive layer. Mounting structure. 30. The mounting structure according to claim 29, wherein a protective layer is formed on the wiring, and the wiring is taken out through a second connection hole formed in the protective layer. 32. The mounting structure according to claim 31, wherein a conductive layer connected to the wiring is provided in the second connection hole so as to protrude above the protective layer. 30. The mounting structure according to claim 29, wherein a plurality of or a plurality of types of semiconductor chips are connected by the wiring via the first connection hole. 30. The mounting structure according to claim 29, wherein the chip component determined to be non-defective by characteristic measurement is connected to the wiring in a normal state.

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