JP2008060485A - Packaging structure of semiconductor device and portable electronic apparatus - Google Patents

Packaging structure of semiconductor device and portable electronic apparatus Download PDF

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JP2008060485A
JP2008060485A JP2006238366A JP2006238366A JP2008060485A JP 2008060485 A JP2008060485 A JP 2008060485A JP 2006238366 A JP2006238366 A JP 2006238366A JP 2006238366 A JP2006238366 A JP 2006238366A JP 2008060485 A JP2008060485 A JP 2008060485A
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circuit board
semiconductor device
underfill agent
portable electronic
underfill
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JP5230917B2 (en
JP2008060485A5 (en
Inventor
Motoyuki Tanaka
基之 田中
Masaki Uesugi
雅樹 上杉
Ryuichi Ito
隆一 伊藤
Takashi Ishikawa
高司 石川
Yoshitaka Imakado
義隆 今門
Yutaka Chiba
千葉　　裕
Yoshibumi Ishii
義文 石井
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Casio Hitachi Mobile Communications Co Ltd
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Casio Hitachi Mobile Communications Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the stresses at impact application, as a packaging structure of a semiconductor device, using an underfill agent. <P>SOLUTION: In a structure in which a semiconductor device is mounted on a circuit board by using an underfill agent, a plurality of semiconductor devices 21 and 22 are mounted adjacent on the circuit board 6, by using the underfill agents 25 and 26 with mutually different elastic moduli. The circuit board 6 has a structure such that the stresses tend to concentrate on the vicinity of the boundary part, adjacent to a plurality of semiconductors 21 and 22. More specifically, in the circuit board 6, the end part of a battery pack 7 is located on the back face side in the vicinity of the boundary part, adjacent to a plurality of the semiconductors 21 and 22. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、携帯電子機器における半導体装置の実装構造及び携帯電子機器に関する。   The present invention relates to a mounting structure of a semiconductor device in a portable electronic device and the portable electronic device.

携帯電子機器においては、高機能化と共に小型軽量化が求められており、半導体装置としてボールグリッドアレイタイプの半導体装置、すなわちＢＧＡ（Ball Grid Array）タイプのＩＣ（Integrated Circuit）やＣＳＰ（Chip Size/Scale Package）タイプＩＣが用いられている。ボールグリッドアレイタイプの半導体装置は回路基板との接着強度は弱いため、回路基板と半導体装置との間に、アンダーフィル剤と呼ばれる封止用樹脂が充填されている。
最近では、このようなアンダーフィル剤を必要とする半導体装置を回路基板に多数実装することも多くなってきている。例えば特許文献１には、配線基板の裏面側にアンダーフィル剤を必要とする半導体装置が４つ隣接して実装されている。より具体的には、パッケージサイズが大きい半導体装置が１つ、中くらいの半導体装置が１つ、小さい半導体装置が２つの計４つが隣接して実装されている。
ところで、携帯電子機器には、通常、電池パックを収納する電池収納部が設けられている。このような携帯電子機器では、回路基板は、通常、電池収納部の底の裏面側に電池収納部の底に近接して配置されるが、電池収納部の底の板厚（ケース厚）は外装部に比べて薄い。また、携帯電子機器には、電池収納部の底に貫通孔が形成されているもの（特許文献２参照）や、電池収納部に底板がなく電池パックの底面が直接回路基板に接する構造のものもある（特許文献３参照）。
特開２０００−２２０４８号公報（図３） 特開２００１−２４４００４号公報（段落０００９） 特開平１０−２７６２４９号公報（段落０００６〜００１０） In portable electronic devices, there is a demand for miniaturization and weight reduction with high functionality. As a semiconductor device, a ball grid array type semiconductor device, that is, a BGA (Ball Grid Array) type IC (Integrated Circuit) or CSP (Chip Size / Scale Package) type IC is used. Since the ball grid array type semiconductor device has low adhesive strength with the circuit board, a sealing resin called an underfill agent is filled between the circuit board and the semiconductor device.
Recently, many semiconductor devices that require such an underfill agent are often mounted on a circuit board. For example, in Patent Document 1, four semiconductor devices that require an underfill agent are mounted adjacent to the back side of the wiring board. More specifically, a total of four semiconductor devices are mounted adjacent to each other, one semiconductor device having a large package size, one medium semiconductor device, and two small semiconductor devices.
By the way, the portable electronic device is usually provided with a battery storage unit for storing a battery pack. In such a portable electronic device, the circuit board is usually arranged on the back side of the bottom of the battery storage unit in the vicinity of the bottom of the battery storage unit, but the thickness (case thickness) of the bottom of the battery storage unit is Thin compared to the exterior. In addition, the portable electronic device has a through-hole formed in the bottom of the battery housing (see Patent Document 2), or has a structure in which the bottom of the battery pack is in direct contact with the circuit board without the battery housing There is also (refer patent document 3).
Japanese Patent Laid-Open No. 2000-22048 (FIG. 3) JP 2001-244004 A (paragraph 0009) JP-A-10-276249 (paragraphs 0006 to 0010)

ところで、特許文献１のように、パッケージサイズが異なる複数のボールグリッドアレイタイプの半導体装置が隣接して実装され、且つその実装に同種のアンダーフィル剤が使用されていると、サイズの異なる半導体装置が実装されている各領域の回路基板の剛性は相互に異なるので、隣接する半導体装置の境界部付近に外力が掛かると、パッケージサイズが小さい方の半導体装置実装部に曲げ応力が強く掛かり、半田付け部が剥離しやすいという問題がある。この問題は、回路基板が電池収納部の底に面して配置されている場合に特に生じやすい。   By the way, as in Patent Document 1, when a plurality of ball grid array type semiconductor devices having different package sizes are mounted adjacent to each other and the same type of underfill agent is used for the mounting, semiconductor devices having different sizes are used. Since the circuit board in each region where the circuit board is mounted has a different rigidity, if an external force is applied near the boundary between adjacent semiconductor devices, bending stress is strongly applied to the semiconductor device mounting portion with the smaller package size, and soldering is performed. There is a problem that the attachment part is easily peeled off. This problem is particularly likely to occur when the circuit board is arranged facing the bottom of the battery housing.

本発明の課題は、アンダーフィル剤を使用する半導体の実装構造として、衝撃印加時の応力を低減できるようにすることである。   The subject of this invention is enabling it to reduce the stress at the time of an impact application as a semiconductor mounting structure which uses an underfill agent.

以上の課題を解決するため、請求項１に記載の発明は、回路基板上に半導体装置がアンダーフィル剤を使用して実装される構造において、回路基板上に隣接して複数の半導体装置を、互いに弾性率の異なるアンダーフィル剤を使用して実装したことを特徴とする。   In order to solve the above problems, the invention according to claim 1 is a structure in which a semiconductor device is mounted on a circuit board using an underfill agent, and a plurality of semiconductor devices are adjacent to the circuit board. It is mounted using underfill agents having different elastic moduli.

請求項２に記載の発明は、携帯電子機器において、複数の半導体装置を互いに弾性率の異なるアンダーフィル剤を使用して隣接して実装した回路基板を搭載していることを特徴とする携帯電子機器。   According to a second aspect of the present invention, there is provided a portable electronic device comprising a circuit board in which a plurality of semiconductor devices are mounted adjacent to each other using underfill agents having different elastic moduli. machine.

請求項３に記載の発明は、請求項２に記載の携帯電子機器であって、前記回路基板には、前記複数の半導体装置の隣接する境界部付近の裏面側に電池パックの端部が位置していることを特徴とする。   A third aspect of the present invention is the portable electronic device according to the second aspect, wherein the circuit board has an end portion of the battery pack positioned on a back surface side in the vicinity of adjacent boundary portions of the plurality of semiconductor devices. It is characterized by that.

本発明によれば、回路基板上に隣接して複数の半導体装置を、互いに弾性率の異なるアンダーフィル剤を使用して実装することにより、回路基板の半導体装置が隣接する境界部付近に応力が集中しやすい構造の場合において、隣接する複数の半導体装置の実装部分に一様の剛性を形成し、衝撃印加時の応力破壊を低減できる。   According to the present invention, by mounting a plurality of semiconductor devices adjacent to each other on the circuit board using underfill agents having different elastic moduli, stress is applied near the boundary portion where the semiconductor devices of the circuit board are adjacent to each other. In the case of a structure that tends to concentrate, uniform rigidity is formed in the mounting portions of a plurality of adjacent semiconductor devices, and stress breakdown during application of an impact can be reduced.

以下、図を参照して本発明を実施するための最良の形態を詳細に説明する。
図１は本発明を適用した回路基板を搭載した携帯電子機器の一実施形態としての折り畳み式携帯電話機を開いた状態で示したものであり、
その機器ケースは、第一の筐体１と第二の筐体２がヒンジ部３を介して互いに折り畳み自在に連結して構成されている。
第一の筐体１には、各種キーによる操作部４や通話用マイク等が備えられている。第二の筐体２には、メイン表示部５や通話用スピ−カ等が備えられている。 Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a state in which a foldable mobile phone as an embodiment of a portable electronic device equipped with a circuit board to which the present invention is applied is opened.
The device case is configured such that a first housing 1 and a second housing 2 are connected to each other via a hinge portion 3 so as to be foldable.
The first housing 1 is provided with an operation unit 4 using various keys, a microphone for calling, and the like. The second housing 2 is provided with a main display unit 5, a telephone speaker, and the like.

図２は図１の携帯電話機を折り畳んだ状態での中央縦断面図、図３は図１の携帯電話機を折り畳んだ状態を第一の筐体１側から見た底面図である。第一の筐体１は、下ケース１１、上ケース１２及び中ケース１３をビス止めにより合体して構成されており、第一の筐体１内には、回路基板６、電池パック７等が収納されている。回路基板６は、中ケース１３にビス止めして固定されており、電池パック７は、回路基板６を挟んで操作部４と反対側に配置され、電池蓋８で覆われている。なお、回路基板６と電池パック７との間には、絶縁シート１４が配置されている。第二の筐体２には、サブ表示部９等が設けられている。サブ表示部９は、メイン表示部５と反対側に配置されている。   2 is a central longitudinal sectional view of the cellular phone of FIG. 1 in a folded state, and FIG. 3 is a bottom view of the folded cellular phone of FIG. 1 as viewed from the first housing 1 side. The first housing 1 is configured by combining a lower case 11, an upper case 12, and an intermediate case 13 with screws, and in the first housing 1, a circuit board 6, a battery pack 7, and the like are provided. It is stored. The circuit board 6 is fixed to the middle case 13 with screws, and the battery pack 7 is disposed on the opposite side of the operation unit 4 with the circuit board 6 interposed therebetween, and is covered with a battery lid 8. An insulating sheet 14 is disposed between the circuit board 6 and the battery pack 7. The second housing 2 is provided with a sub display unit 9 and the like. The sub display unit 9 is arranged on the side opposite to the main display unit 5.

図４は本発明が適用される回路基板６を示した平面図で、回路基板６上には各種半導体を含む電子部品、すなわち、図示のように、制御用のＩＣ２１とメモリ用のＩＣ２２が隣接して実装されるとともに、その他の各種電子部品が実装されている。
そして、この回路基板６には、制御用のＩＣ２１及びメモリ用のＩＣ２２の隣接する境界部付近の裏面側、すなわち、図示のように、メモリ用のＩＣ２２における制御用のＩＣ２１側寄りの裏面側に電池パック７の端部が位置している。 FIG. 4 is a plan view showing a circuit board 6 to which the present invention is applied. On the circuit board 6, an electronic component including various semiconductors, that is, as shown, a control IC 21 and a memory IC 22 are adjacent to each other. And various other electronic components are mounted.
The circuit board 6 has a back surface near the boundary between the control IC 21 and the memory IC 22 adjacent to each other, that is, on the back surface near the control IC 21 side of the memory IC 22 as illustrated. The end of the battery pack 7 is located.

ここで、ＩＣ２１及びＩＣ２２は共にＢＧＡタイプのＩＣであり、パッケージの大きさ（平面形状）はＩＣ２１の方がＩＣ２２よりも大きいが、パッケージの厚み及び半田ボール２３，２４の径は両者ほぼ同等である。
そして、本実施例では、図５に示すように、パッケージの大きさが大きい方のＩＣ２１のアンダーフィル剤として弾性率の大きいアンダーフィル剤２５を使用し、パッケージの大きさが小さい方のＩＣ２２のアンダーフィル剤として弾性率の小さいアンダーフィル剤２６を使用している。弾性率の大きいアンダーフィル剤２５としては、一液性エポキシ系樹脂の接着剤によるAS3903(EXS-05-04-1)（アセック（株））を使用し、例えば弾性率の小さいアンダーフィル剤２６としては、一液性エポキシ樹脂の接着剤で硬化によりゴム弾性体となるAS3335（アセック（株））を使用した。なお、アンダーフィル剤２５，２６は、ＩＣ２１及びＩＣ２２の裏面（回路基板側面）全体に充填しても良いし、四隅部や四側縁部などの一部にのみ充填するようにしても良い。 Here, the IC 21 and the IC 22 are both BGA type ICs, and the size (planar shape) of the package of the IC 21 is larger than that of the IC 22, but the thickness of the package and the diameters of the solder balls 23 and 24 are almost the same. is there.
In this embodiment, as shown in FIG. 5, the underfill agent 25 having a large elastic modulus is used as the underfill agent for the IC 21 having the larger package size, and the IC 22 having the smaller package size is used. An underfill agent 26 having a low elastic modulus is used as the underfill agent. As the underfill agent 25 having a large elastic modulus, AS3903 (EXS-05-04-1) (ASEC Co., Ltd.) using an adhesive of a one-component epoxy resin is used. For example, the underfill agent 26 having a small elastic modulus is used. As, AS3335 (ASEC Co., Ltd.), which becomes a rubber elastic body by curing with a one-component epoxy resin adhesive, was used. The underfill agents 25 and 26 may be filled on the entire back surfaces (circuit board side surfaces) of the IC 21 and the IC 22, or may be filled only on a part of the four corners or the four side edges.

これにより、ＩＣ２１を実装している部分の回路基板６の剛性とＩＣ２２を実装している部分の回路基板６の剛性とを略同じにすることができる。
従って、携帯電話機の落下時において、その背面側の電池パック７の端部により回路基板６に衝撃力Ｆが印加されると、図６に示すように、ＩＣ２１及びＩＣ２２のアンダーフィル剤として同じ弾性率のアンダーフィル剤を使用していた場合には、破線Ａで示すように曲がっていた回路基板の曲げが小さくなり、半田付け部の剥がれ等は生じない。 Thereby, the rigidity of the part of the circuit board 6 on which the IC 21 is mounted and the rigidity of the part of the circuit board 6 on which the IC 22 is mounted can be made substantially the same.
Therefore, when an impact force F is applied to the circuit board 6 by the end portion of the battery pack 7 on the back side when the mobile phone is dropped, as shown in FIG. 6, the same elasticity as the underfill agent of the IC 21 and the IC 22 is obtained. When an underfill agent with a high rate is used, bending of the circuit board that has been bent as shown by the broken line A becomes small, and peeling of the soldered portion does not occur.

図７は、比較例として、ＩＣ２１及びＩＣ２２のアンダーフィル剤として同じ弾性率のアンダーフィル剤２９を使用していた場合の衝撃印加時の歪みを示したものである。この場合、ＩＣ２２のアンダーフィル剤２９はＩＣ２１側の部分Ｂに亀裂や剥がれが生じ、また回路基板との半田接合部においてもＩＣ２１側の部分Ｃに剥がれが生じる。   FIG. 7 shows, as a comparative example, distortion at the time of applying an impact when an underfill agent 29 having the same elastic modulus is used as the underfill agent for IC21 and IC22. In this case, the underfill agent 29 of the IC 22 is cracked or peeled off at the portion B on the IC 21 side, and also peeled off at the portion C on the IC 21 side at the solder joint with the circuit board.

以上のとおり、回路基板６とＢＧＡタイプのＩＣ２１・２２との間に充填するアンダーフィル剤を使用する際、応力が集中する箇所に弾性率の異なる２種類のアンダーフィル剤２５・２６を使用することにより、回路基板６上に隣接して実装した異なるＩＣ２１・２２の部分に一様の剛性を形成し、衝撃印加時の応力破壊を低減できる。
すなわち、回路基板６の裏面側に電池パック７の端面が位置する箇所において、形状が大きい方のＩＣ２１の方に弾性率の大きいアンダーフィル剤２５を使用し、形状が小さい方のＩＣ２２での方に弾性率の小さいアンダーフィル剤２６を使用したことにより、回路基板６上に隣接して実装した異なるＩＣ２１・２２の部分に一様の剛性をそれぞれ具備できる。
従って、携帯電話機の落下時において、その背面側の電池パック７の端部により回路基板６に衝撃力Ｆが印加されても、図６に示すように、回路基板６のＩＣ２１・２２が隣接する境界部付近の歪みを小さく抑えて、応力による破壊を防止できるものとなる。 As described above, when using the underfill agent filled between the circuit board 6 and the BGA type ICs 21 and 22, two types of underfill agents 25 and 26 having different elastic moduli are used in places where stress is concentrated. As a result, uniform rigidity is formed in the portions of the different ICs 21 and 22 mounted adjacent to each other on the circuit board 6, and stress breakdown during impact application can be reduced.
That is, in the place where the end surface of the battery pack 7 is located on the back surface side of the circuit board 6, the underfill agent 25 having a larger elastic modulus is used for the larger IC 21 and the smaller IC 22 is used. In addition, by using the underfill agent 26 having a low elastic modulus, uniform rigidity can be provided in the portions of the different ICs 21 and 22 mounted adjacently on the circuit board 6.
Therefore, even when an impact force F is applied to the circuit board 6 by the end of the battery pack 7 on the back side when the mobile phone is dropped, the ICs 21 and 22 of the circuit board 6 are adjacent to each other as shown in FIG. The strain near the boundary can be suppressed to a small level, and breakage due to stress can be prevented.

図８は、パッケージの大きさ及び厚みがほぼ同じで半田ボールの径が異なるＢＧＡタイプのＩＣの実装に本発明を適用した例を示す図である。ここで、ＩＣ２１の構成は図５と同一のものである、ＩＣ３２は半田ボール３４の径が半田ボール２３の径よりも大きい。そして、ＩＣ３２のアンダーフィル剤３６として、アンダーフィル剤２５よりも弾性率の小さいアンダーフィル剤を使用している。   FIG. 8 is a diagram showing an example in which the present invention is applied to the mounting of a BGA type IC in which the package size and thickness are substantially the same and the solder ball diameter is different. Here, the configuration of the IC 21 is the same as that in FIG. 5. In the IC 32, the diameter of the solder ball 34 is larger than the diameter of the solder ball 23. As the underfill agent 36 of the IC 32, an underfill agent having a smaller elastic modulus than the underfill agent 25 is used.

図９は、ＩＣ２１及びＩＣ３２が実装された回路基板６の衝撃印加時の歪みを示したものであり、図１０は、比較例として、ＩＣ２１及びＩＣ３２のアンダーフィル剤として同じ弾性率のアンダーフィル剤３９を使用していた場合の衝撃印加時の歪みを示したものである。図中の記号Ａ，Ｂ，ｃは図６及び図７で説明したものと同じである。
図８に示した構成においても、図５に示した構成と同様の作用効果を有し、回路基板との半田接合部における剥がれなどが生じない。 FIG. 9 shows the strain at the time of impact application of the circuit board 6 on which the IC 21 and the IC 32 are mounted. FIG. 10 shows, as a comparative example, an underfill agent having the same elastic modulus as the underfill agent of the IC 21 and the IC 32. The distortion | strain at the time of the impact application at the time of using 39 is shown. The symbols A, B, and c in the figure are the same as those described with reference to FIGS.
The configuration shown in FIG. 8 also has the same function and effect as the configuration shown in FIG. 5 and does not cause peeling at the solder joint with the circuit board.

なお、以上の実施形態においては、ＢＧＡタイプのＩＣの実装としたが、本発明はこれに限定されるものではなく、ＣＳＰ（Chip Size/Scale Package）タイプのＬＳＩ（Large Scale Integration）の実装であっても良い。
また、実施形態では、本発明が適用される携帯電子機器として折り畳み式携帯電話機としたが、ＰＤＡ、その他の携帯型の電子機器であっても良い。
さらに、回路基板上の半導体装置の種類や配置箇所や数、アンダーフィル剤の種類、回路基板の裏面側に当接する部品の種類も任意であり、その他、具体的な細部構造等についても適宜に変更可能であることは勿論である。 In the above embodiment, the BGA type IC is mounted. However, the present invention is not limited to this, and a CSP (Chip Size / Scale Package) type LSI (Large Scale Integration) is mounted. There may be.
Further, in the embodiment, the foldable mobile phone is used as the portable electronic device to which the present invention is applied, but a PDA or other portable electronic device may be used.
Furthermore, the type and location and number of semiconductor devices on the circuit board, the type of underfill agent, the type of parts that contact the back side of the circuit board are arbitrary, and other specific details such as the detailed structure are also appropriate. Of course, it can be changed.

本発明を適用した携帯電子機器の一実施形態の構成を示すもので、折り畳み式携帯電話機を開いた状態の正面図である。1 is a front view showing a configuration of a mobile electronic device according to an embodiment of the present invention, in a state in which a foldable mobile phone is opened. 図１の携帯電話機を折り畳んだ状態での中央縦断面図である。It is a center longitudinal cross-sectional view in the state which folded the mobile telephone of FIG. 図１の携帯電話機を折り畳んだ状態を第一の筐体１側から見た底面図である。It is the bottom view which looked at the state which folded the cellular phone of Drawing 1 from the 1st case 1 side. 本発明が適用される回路基板を示した平面図である。It is the top view which showed the circuit board to which this invention is applied. 本発明による半導体装置の実装構造を示した断面図である。It is sectional drawing which showed the mounting structure of the semiconductor device by this invention. 図５の半導体装置の実装構造における衝撃印加時の歪みを示した断面図である。FIG. 6 is a cross-sectional view showing distortion at the time of applying an impact in the semiconductor device mounting structure of FIG. 5. 対比例として一般的な半導体装置の実装構造における衝撃印加時の歪みを示した断面図である。It is sectional drawing which showed the distortion at the time of the impact application in the mounting structure of a general semiconductor device as contrast. 本発明による半導体装置の実装構造の他の例を示した断面図である。It is sectional drawing which showed the other example of the mounting structure of the semiconductor device by this invention. 図８の半導体装置の実装構造における衝撃印加時の歪みを示した断面図である。FIG. 9 is a cross-sectional view showing strain at the time of applying an impact in the semiconductor device mounting structure of FIG. 8. 対比例として一般的な半導体装置の実装構造における衝撃印加時の歪みを示した断面図である。It is sectional drawing which showed the distortion at the time of the impact application in the mounting structure of a general semiconductor device as contrast.

符号の説明Explanation of symbols

１・２ 筐体
６ 回路基板
７ 電池パック
８ 電池蓋
２１・２２・３２ 半導体装置
２３・２４・３４ 半田ボール
２５・２６・３６ アンダーフィル剤 1.2 Case 6 Circuit board 7 Battery pack 8 Battery lid 21, 22, 32 Semiconductor device 23/24/34 Solder balls 25/26/36 Underfill agent

Claims (3)

回路基板上に半導体装置がアンダーフィル剤を使用して実装される構造において、
回路基板上に隣接して複数の半導体装置を、互いに弾性率の異なるアンダーフィル剤を使用して実装したことを特徴とする半導体装置の実装構造。 In a structure where a semiconductor device is mounted on a circuit board using an underfill agent,
A mounting structure of a semiconductor device, wherein a plurality of semiconductor devices are mounted adjacent to each other on a circuit board using underfill agents having different elastic moduli. 複数の半導体装置を互いに弾性率の異なるアンダーフィル剤を使用して隣接して実装した回路基板を搭載していることを特徴とする携帯電子機器。   A portable electronic device comprising a circuit board on which a plurality of semiconductor devices are mounted adjacent to each other using underfill agents having different elastic moduli. 前記回路基板には、前記複数の半導体装置の隣接する境界部付近の裏面側に電池パックの端部が位置していることを特徴とする請求項２に記載の携帯電子機器。   3. The portable electronic device according to claim 2, wherein an end portion of the battery pack is located on a back surface side of the circuit board near an adjacent boundary portion of the plurality of semiconductor devices.
JP2006238366A 2006-09-01 2006-09-01 Mounting structure of semiconductor device Expired - Fee Related JP5230917B2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004087661A (en) * 2002-08-26 2004-03-18 Sony Corp Chip-shaped electronic component and method for manufacturing the same and pseudo wafer used for its manufacturing and method for manufacturing the same, and mounting structure
JP2004172489A (en) * 2002-11-21 2004-06-17 Nec Semiconductors Kyushu Ltd Semiconductor device and its manufacturing method
JP2005183561A (en) * 2003-12-18 2005-07-07 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004087661A (en) * 2002-08-26 2004-03-18 Sony Corp Chip-shaped electronic component and method for manufacturing the same and pseudo wafer used for its manufacturing and method for manufacturing the same, and mounting structure
JP2004172489A (en) * 2002-11-21 2004-06-17 Nec Semiconductors Kyushu Ltd Semiconductor device and its manufacturing method
JP2005183561A (en) * 2003-12-18 2005-07-07 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor device

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