JP5078631B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP5078631B2
JP5078631B2 JP2008006341A JP2008006341A JP5078631B2 JP 5078631 B2 JP5078631 B2 JP 5078631B2 JP 2008006341 A JP2008006341 A JP 2008006341A JP 2008006341 A JP2008006341 A JP 2008006341A JP 5078631 B2 JP5078631 B2 JP 5078631B2
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circuit board
semiconductor chip
adhesive resin
semiconductor
sealing adhesive
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JP2009170617A5 (en
JP2009170617A (en
Inventor
鉄平 岩瀬
一博 登
善広 戸村
浩二郎 中村
謙太郎 熊澤
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2008006341A priority Critical patent/JP5078631B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a desired structure without separating semiconductor chips by reducing a load on the semiconductor chips and a sealing resin, in a semiconductor device of a double-sided mounting structure where a plurality of semiconductor chips are arranged and jointed on/to both sides of a circuit board. <P>SOLUTION: In a region where a semiconductor chip 31 mounted on the upper surface of the circuit board overlaps a semiconductor chip 32 mounted on the undersurface thereof, a recessed part 21 (or a projecting part 22) is formed on a surface of the circuit board. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は回路基板の両面に複数の半導体チップを配置して接合する半導体チップの両面実装構造に関するものである。   The present invention relates to a semiconductor chip double-sided mounting structure in which a plurality of semiconductor chips are arranged and bonded on both sides of a circuit board.

ＩＣチップはプラスチックなどのパッケージに封入し、これを回路基板に実装する実装方法が一般的である。最近では、このような半導体パッケージの実装に比較して実装面積を大幅に縮小できるベアチップ実装が利用されている。   In general, the IC chip is encapsulated in a package such as plastic and mounted on a circuit board. Recently, bare chip mounting has been used that can significantly reduce the mounting area compared to mounting of such a semiconductor package.

ＩＣチップの状態のまま回路基板に実装するベアチップ実装には、次の３種類がある。
（１）チップ上の電極と回路基板の電極をワイヤボンディング
（２）チップ上の電極と回路基板の電極をリード線を備えたフィルムで接続
（３）ＩＣチップをフェイスダウンして回路基板に直接に接続
３番目のフリップチップでは、回路基板の回路形成面に半導体チップの回路形成面を対向させ、金などの金属で形成されるバンプを介して重ね合わせることで導通をとるフェイスダウン実装であって、１番目のワイヤボンディングの場合のように、回路基板の回路形成面と半導体チップの回路形成面の反対側の面を対向させ、ワイヤボンディングによって金属細線を引き出しているフェイスアップ実装と比較して、小型化が可能であり、幅広く利用されている。 There are the following three types of bare chip mounting that is mounted on a circuit board in the state of an IC chip.
(1) Wire bonding the electrode on the chip and the electrode on the circuit board (2) Connect the electrode on the chip and the electrode on the circuit board with a film having lead wires (3) Face down the IC chip directly to the circuit board In the third flip chip, the circuit formation surface of the semiconductor substrate is opposed to the circuit formation surface of the circuit board, and the conductive state is achieved by superimposing via a bump formed of a metal such as gold. Compared with face-up mounting, where the circuit formation surface of the circuit board and the surface opposite to the circuit formation surface of the semiconductor chip are opposed to each other and the fine metal wires are drawn by wire bonding, as in the case of the first wire bonding. Therefore, it can be miniaturized and is widely used.

近年、高機能化を図るために、回路基板の両面に半導体チップを実装する両面実装構造が採用される場合においても、小型化の実現のためフェイスダウン実装によりベアチップと回路基板を接続する方法がとられている。
特開２００４−２３０４５号公報 In recent years, in order to achieve high functionality, even when a double-sided mounting structure in which semiconductor chips are mounted on both sides of a circuit board is adopted, there is a method for connecting a bare chip and a circuit board by face-down mounting in order to achieve downsizing. It has been taken.
JP 200423045 A

半導体の両面実装構造においては、複数の機能を持たせるため、回路基板の両面に実装される半導体チップは必ずしも同一ではなく、チップの厚み、サイズなどが異なる場合が多い。また、その他、受動部品と一緒に実装しワンモジュール化する場合、受動部品との配置関係より、図１０に示すようにそれぞれの半導体チップ３１，３２が回路基板２に対し対称的ではなく、ずれて配置されている場合がある。５１，５２はバンプ、４１は封止接着樹脂である。   In a semiconductor double-sided mounting structure, in order to have a plurality of functions, semiconductor chips mounted on both sides of a circuit board are not necessarily the same, and the thickness and size of the chip are often different. In addition, when mounting together with passive components to form one module, the semiconductor chips 31 and 32 are not symmetrical with respect to the circuit board 2 as shown in FIG. May be arranged. 51 and 52 are bumps, and 41 is a sealing adhesive resin.

一般に、半導体チップ３１，３２の熱膨張係数は、回路基板２への接合に用いる封止接着樹脂４１や回路基板２そのものの熱膨張係数と比べ極端に小さく、サイズの異なる半導体チップがずれて配置されている場合には、反り傾向が、回路基板２の上下で異なるため、実装時の加熱、冷却処理によって生じる各構成部材の膨張、収縮差によって図１１に示すように、回路基板２の全体が大きく反る。そのずれに起因して回路基板２の全体がうねった形状になる。その際、一方の半導体チップ３２の反りによって、特に半導体チップの外周部分に対向する他方の半導体チップ３１の封止接着樹脂４１が引っ張られ、半導体チップの回路形成面との間で剥離が発生し、電気的な性能に悪影響を及ぼすことが考えられる。   In general, the thermal expansion coefficients of the semiconductor chips 31 and 32 are extremely small compared to the thermal expansion coefficients of the sealing adhesive resin 41 used for bonding to the circuit board 2 and the circuit board 2 itself, and semiconductor chips of different sizes are shifted and arranged. In this case, since the warp tendency is different between the upper and lower sides of the circuit board 2, the entire circuit board 2 as shown in FIG. Greatly warps. Due to the deviation, the entire circuit board 2 becomes wavy. At this time, the warping of one semiconductor chip 32 causes the sealing adhesive resin 41 of the other semiconductor chip 31 facing the outer peripheral portion of the semiconductor chip to be pulled, and peeling occurs between the semiconductor chip and the circuit formation surface. It is considered that the electrical performance is adversely affected.

本発明は、このような従来技術の課題を解決するためになされたもので、回路基板の両面上に複数の半導体チップを配置して接合する半導体チップの両面実装構造において、チップと封止樹脂への負荷を低減し、半導体チップの配置制約なしに、所望の構造を実現することを目的としている。   The present invention has been made to solve the above-described problems of the prior art. In a double-sided mounting structure of a semiconductor chip in which a plurality of semiconductor chips are arranged and bonded on both sides of a circuit board, the chip and the sealing resin are provided. An object of the present invention is to realize a desired structure without reducing the load on the semiconductor chip and without placing restrictions on the placement of the semiconductor chip.

本発明の請求項１記載の半導体装置は、回路基板と、前記回路基板の第１面に複数の第１バンプを介して実装され、封止接着樹脂によって樹脂封止された直方体の第１半導体チップと、前記回路基板の第２面に複数の第２バンプを介して実装され、樹脂封止された直方体の第２半導体チップと、からなる半導体装置であって、前記回路基板上面から見た場合に、前記第１，第２半導体チップは、重なり部分を有するとともにその重心位置を互いにずらしてあり、前記重なり部分を含み、かつ、前記複数の第１バンプ間の領域の前記第１面に形成された凹部を有し、前記凹部に前記封止接着樹脂が充填されていることを特徴とする。
また、本発明の請求項２記載の半導体装置は、回路基板と、前記回路基板の第１面に複数の第１バンプを介して実装され、封止接着樹脂によって樹脂封止された直方体の第１半導体チップと、前記回路基板の第２面に複数の第２バンプを介して実装され、樹脂封止された直方体の第２半導体チップと、からなる半導体装置であって、前記回路基板上面から見た場合に、前記第１，第２半導体チップは、重なり部分を有するとともにその重心位置を互いにずらしてあり、前記重なり部分を含み、かつ、前記複数の第１バンプ間の領域の前記第１面に形成され、前記封止接着樹脂よりも弾性率の高い凸部を有することを特徴とする。 According to a first aspect of the present invention, there is provided a semiconductor device including a circuit board and a rectangular parallelepiped first semiconductor mounted on a first surface of the circuit board via a plurality of first bumps and sealed with a sealing adhesive resin. A semiconductor device comprising a chip and a second semiconductor chip that is mounted on the second surface of the circuit board via a plurality of second bumps and sealed with a resin, as viewed from the upper surface of the circuit board In this case, the first and second semiconductor chips have overlapping portions and their gravity centers are shifted from each other, include the overlapping portions, and are formed on the first surface in a region between the plurality of first bumps. It has a formed recess, and the recess is filled with the sealing adhesive resin.
According to a second aspect of the present invention, there is provided a semiconductor device comprising: a circuit board; a rectangular parallelepiped which is mounted on a first surface of the circuit board via a plurality of first bumps and sealed with a sealing adhesive resin. A semiconductor device comprising: a semiconductor chip; and a second rectangular semiconductor chip mounted on the second surface of the circuit board via a plurality of second bumps and sealed with a resin, from the upper surface of the circuit board When viewed, the first and second semiconductor chips have overlapping portions and the positions of their centers of gravity are shifted from each other, include the overlapping portions, and the first region in the region between the plurality of first bumps. It has a convex part formed on the surface and having a higher elastic modulus than the sealing adhesive resin .

本発明の請求項３記載の半導体装置は、回路基板と、前記回路基板の第１面に複数の第１バンプを介して実装され、封止接着樹脂によって樹脂封止された直方体の第１半導体チップと、前記回路基板の第２面に複数の第２バンプを介して実装され、樹脂封止された直方体の第２半導体チップと、からなる半導体装置であって、前記回路基板上面から見た場合に、前記第１，第２半導体チップは、重なり部分を有するとともにその重心位置を互いにずらしてあり、前記回路基板上面から見た場合の前記第１，第２半導体チップの全体の領域で、前記第１面の前記第２半導体チップの投影領域の外周に対応する位置に沿って鍵型の形状に形成された凹部を有し、前記凹部に前記封止接着樹脂が充填されていることを特徴とする。 According to a third aspect of the present invention, there is provided a semiconductor device including a circuit board and a rectangular parallelepiped first semiconductor mounted on the first surface of the circuit board via a plurality of first bumps and sealed with a sealing adhesive resin. A semiconductor device comprising a chip and a second semiconductor chip that is mounted on the second surface of the circuit board via a plurality of second bumps and sealed with a resin, as viewed from the upper surface of the circuit board In this case, the first and second semiconductor chips have overlapping portions and the positions of the centers of gravity are shifted from each other, and the entire area of the first and second semiconductor chips when viewed from the upper surface of the circuit board, Having a recess formed in a key shape along a position corresponding to the outer periphery of the projection area of the second semiconductor chip on the first surface, and the recess is filled with the sealing adhesive resin. Features.

この構成によれば、サイズの異なる半導体チップがずれていることによって生じる局所的なうねり、およびそれに起因する封止接着樹脂の引張り力を低減することができ、半導体チップと封止接着樹脂の間に生じる剥離現象を回避できる。   According to this configuration, it is possible to reduce local undulation caused by the shift of semiconductor chips of different sizes, and the tensile force of the sealing adhesive resin resulting therefrom, and between the semiconductor chip and the sealing adhesive resin. Can be avoided.

以下、本発明を各実施の形態を示す図１〜図９に基づいて説明する。
なお、同様の作用を成すものには同一の符号を付けて説明する。
（実施の形態１）
図１（ａ）（ｂ）は本発明の実施の形態１を示す。 Hereinafter, the present invention will be described with reference to FIGS.
In addition, the same code | symbol is attached | subjected and demonstrated to what comprises the same effect | action.
(Embodiment 1)
1A and 1B show Embodiment 1 of the present invention.

回路基板２の上面に半導体チップ３１がフェイスダウンでフリップフロップ実装され、回路基板２の下面に半導体チップ３２がフェイスダウンでフリップフロップ実装されている。   The semiconductor chip 31 is flip-flop mounted on the upper surface of the circuit board 2 face down, and the semiconductor chip 32 is flip-flop mounted on the lower surface of the circuit board 2 face down.

詳しくは、回路基板２の上面に封止接着樹脂４１が形成され、その上に半導体チップ３１が搭載されている。半導体チップ３１の外形は、システムＬＳＩにおける寸法の一例であるが、ここでは縦３ｍｍ×横３ｍｍ、厚みは２００μｍとする。   Specifically, a sealing adhesive resin 41 is formed on the upper surface of the circuit board 2, and the semiconductor chip 31 is mounted thereon. The outer shape of the semiconductor chip 31 is an example of dimensions in the system LSI, but here, it is assumed that the length is 3 mm × width 3 mm and the thickness is 200 μm.

回路基板２の外形は縦６ｍｍ×６ｍｍ、厚みは３００μｍであり、６層構成の両面回路基板である。詳細に図示はしていないが、回路基板２の表面の電極と、半導体チップ３１の表面のパッドはバンプ５１を介して電気的に接合されている。バンプ５１の高さは約２０μｍであり、その直径は約５０μｍである。回路基板２の表面の電極の高さは約２０μｍであるため、回路基板２と半導体チップ３１の間に介在する封止接着樹脂４１の総高さは約４０μｍである。   The external shape of the circuit board 2 is 6 mm × 6 mm in length and the thickness is 300 μm, and it is a double-sided circuit board having a 6-layer structure. Although not shown in detail, the electrodes on the surface of the circuit board 2 and the pads on the surface of the semiconductor chip 31 are electrically joined via bumps 51. The bump 51 has a height of about 20 μm and a diameter of about 50 μm. Since the height of the electrode on the surface of the circuit board 2 is about 20 μm, the total height of the sealing adhesive resin 41 interposed between the circuit board 2 and the semiconductor chip 31 is about 40 μm.

封止接着樹脂４１には、金属フィラーが混入された導電性の接着樹脂や、絶縁性の接着樹脂などが用いられ、半導体チップ３１の周辺部においてフィレットを形成している。
バンプ５１は、半田および金などの金属または導電性の樹脂ボールおよびそれらの組合せなどで形成されている。バンプ５１の中心は、半導体チップ３１のエッジから約１５０μｍ程度内側にくるように形成されている。 As the sealing adhesive resin 41, a conductive adhesive resin mixed with a metal filler, an insulating adhesive resin, or the like is used, and a fillet is formed in the periphery of the semiconductor chip 31.
The bump 51 is formed of a metal such as solder and gold or a conductive resin ball and a combination thereof. The center of the bump 51 is formed so as to be about 150 μm inside from the edge of the semiconductor chip 31.

これら構造は、先にシート状態の封止接着樹脂４１を回路基板２の上に貼り付けて半導体チップ３１を搭載し、半導体チップ３１の上面から加熱・加圧することにより形成する場合や、先に半導体チップ３１をバンプ５１のみで接合した後にペースト状の封止接着樹脂４１を注入して接着することにより形成する場合などがある。   These structures are formed when the sealing adhesive resin 41 in a sheet state is first pasted on the circuit board 2 to mount the semiconductor chip 31 and heated / pressed from the upper surface of the semiconductor chip 31. In some cases, the semiconductor chip 31 is formed by bonding only the bumps 51 and then injecting and bonding a paste-like sealing adhesive resin 41.

回路基板２のもう下面には同様に封止接着樹脂４２が形成され、その上に半導体チップ３２が搭載されており、バンプ５２を介して電気的接合がなされている。半導体チップ３２の外形サイズは上記半導体チップ３１と同様、その接合方法、バンプ形状等も全て上記半導体チップ３１側と同様である。   Similarly, a sealing adhesive resin 42 is formed on the other lower surface of the circuit board 2, and a semiconductor chip 32 is mounted on the sealing adhesive resin 42, and is electrically connected via bumps 52. The external size of the semiconductor chip 32 is the same as that of the semiconductor chip 31, and the bonding method, bump shape, etc. are all the same as those of the semiconductor chip 31.

図１（ｂ）に示すように、半導体チップ３１と半導体チップ３２は上面から見た場合に、対称的に配置されているのではなく、半導体チップ３１の重心Ｇ１に対し、半導体チップ３２の重心Ｇ２は、縦方向に１ｍｍ、そして横方向に１ｍｍずれて配置されている。   As shown in FIG. 1B, the semiconductor chip 31 and the semiconductor chip 32 are not arranged symmetrically when viewed from above, but the center of gravity of the semiconductor chip 32 with respect to the center of gravity G1 of the semiconductor chip 31. G2 is arranged 1 mm in the vertical direction and 1 mm in the horizontal direction.

回路基板２の半導体チップ３１が搭載される上面には、図１（ａ）（ｂ）に示すように、半導体チップ３２と半導体チップ３１が重なりあう領域に凹部２１が形成されている。その凹部２１の深さは約３０μｍであり、封止接着樹脂４１は凹部２１の中にも充填され、封止接着樹脂４１の高さ、すなわち半導体チップ３１から回路基板２までの距離は、凹部２１において、７０μｍと最も高く形成されている。この回路基板２に設けられた凹部２１は、回路基板２の製造時に、表面よりエッチング等の加工処理を施すことによって形成されたものである。   On the top surface of the circuit board 2 on which the semiconductor chip 31 is mounted, as shown in FIGS. 1A and 1B, a recess 21 is formed in a region where the semiconductor chip 32 and the semiconductor chip 31 overlap. The depth of the recess 21 is about 30 μm, and the sealing adhesive resin 41 is also filled in the recess 21. The height of the sealing adhesive resin 41, that is, the distance from the semiconductor chip 31 to the circuit board 2 is In No. 21, the height is as high as 70 μm. The recess 21 provided in the circuit board 2 is formed by performing processing such as etching from the surface when the circuit board 2 is manufactured.

凹部２１を形成する領域の詳細な寸法事例を以下に示す。
半導体チップ３２と半導体チップ３１が重なりあう全領域としているが、半導体チップ３１に形成されるバンプ５１の配置制約に応じてその領域は制限される。 Detailed dimension examples of the region where the recess 21 is formed will be shown below.
Although the entire area where the semiconductor chip 32 and the semiconductor chip 31 overlap each other, the area is limited according to the arrangement restriction of the bumps 51 formed on the semiconductor chip 31.

凹部２１の平面的な位置は、図１（ｂ）に示すように、半導体チップ３１に形成されているバンプ５１より、その周辺の封止接着樹脂の充填に必要な領域として、少なくともＤ１＝１００μｍ以上内側に存在するものとする。   As shown in FIG. 1B, the planar position of the recess 21 is at least D1 = 100 μm as a region necessary for filling the sealing adhesive resin around the bump 51 formed on the semiconductor chip 31. It is assumed that it exists inside.

また、半導体チップ３２の側の反りによって半導体チップ３１の側の封止接着樹脂４１が受ける引張り力は、半導体チップ３２のエッジよりも外側で最大になる可能性があることから、凹部２１は、半導体チップ３２のエッジよりも外側の領域まで広げて形成する方が好適である。ここではＤ２＝１００μｍ以上はみだして形成されているとする。   Further, since the tensile force received by the sealing adhesive resin 41 on the semiconductor chip 31 side due to the warp on the semiconductor chip 32 side may be maximized outside the edge of the semiconductor chip 32, the recess 21 is It is preferable to form the semiconductor chip 32 so as to extend to a region outside the edge. Here, it is assumed that D2 = 100 μm or more is formed.

このようにして、凹部２１と半導体チップ３１の間の封止接着樹脂４１が高く形成されていることにより、回路基板２のもう一方に搭載されている半導体チップ３２の側が反ることによって、特に半導体チップ３２の外周部分に相当する回路基板２のうねりの影響を、ある一定量の高さを持った凹部２１の封止接着樹脂４１が緩和し、当該部分の半導体チップ３１と封止接着樹脂４１の界面に生じる引張り力を低減できる。   In this way, since the sealing adhesive resin 41 between the recess 21 and the semiconductor chip 31 is formed high, the side of the semiconductor chip 32 mounted on the other side of the circuit board 2 is warped. The influence of the undulation of the circuit board 2 corresponding to the outer peripheral portion of the semiconductor chip 32 is alleviated by the sealing adhesive resin 41 of the concave portion 21 having a certain amount of height, and the semiconductor chip 31 and the sealing adhesive resin of the portion concerned. The tensile force generated at the interface of 41 can be reduced.

（実施の形態２）
図２，図３は本発明の実施の形態２を示す。
実施の形態１では、回路基板２の上面に形成されている凹部２１の全部を、半導体チップ３１と半導体チップ３２が重なり合う領域に形成するとしているが、回路基板２の電気配線の制約により困難な場合は、図２に示すように、引張り力が最も大きくなる領域である半導体チップ３２の外周に相当する位置に沿って鍵型の領域に限定して形成しても同様の効果が得られる。この時、鍵型の凹部２１の幅は、半導体チップ３２に外側に１００μｍ以上、内側に１００μｍ以上、合計２００μｍ以上の幅を持って形成されているとする。 (Embodiment 2)
2 and 3 show a second embodiment of the present invention.
In the first embodiment, all of the recesses 21 formed on the upper surface of the circuit board 2 are formed in a region where the semiconductor chip 31 and the semiconductor chip 32 overlap, but this is difficult due to restrictions on the electrical wiring of the circuit board 2. In this case, as shown in FIG. 2, the same effect can be obtained even if the formation is limited to the key-shaped region along the position corresponding to the outer periphery of the semiconductor chip 32, which is the region where the tensile force is maximized. At this time, it is assumed that the width of the key-shaped recess 21 is formed in the semiconductor chip 32 with a width of 100 μm or more on the outside and 100 μm or more on the inside, and a total of 200 μm or more.

また、図１に示した方形の凹部２１または図２に示した鍵型の領域に配置された凹部２１は、半導体チップ３１の内で連続的に形成するとしているが、実際には、半導体チップ３１の内には、バンプ５１以外にも、回路基板２の表面上に電極以外の銅パターンが形成されている場合が多いため、必ずしも連続的に形成できるとは限らない。このようなパターンの影響により凹部２１の形成が困難な場合には、例えば図３にその一例を示すように、半導体チップ３１に形成されるバンプ５１のレイアウトやその他の制約に応じて、断続的に形成された凹部２１ａ，２１ｂ，２１ｃで構成していてもかまわない。   Further, the rectangular recesses 21 shown in FIG. 1 or the recesses 21 arranged in the key-shaped region shown in FIG. 2 are supposed to be formed continuously in the semiconductor chip 31. In addition to the bumps 51, a copper pattern other than the electrodes is often formed on the surface of the circuit board 2 in 31, so that it cannot always be formed continuously. When it is difficult to form the recesses 21 due to the influence of such a pattern, for example, as shown in FIG. 3, for example, intermittently according to the layout of the bumps 51 formed on the semiconductor chip 31 and other restrictions. You may comprise by the recessed part 21a, 21b, 21c formed in this.

また実施の形態１，実施の形態２において、前記凹部２１，２１ａ，２１ｂ，２１ｃは、説明の簡略化のため回路基板２の半導体チップ３１と対向する表面にのみ形成しているが、各半導体チップが他方に与えるうねりの影響は同様であるため、回路基板２の半導体チップ３２と対向する表面にのみ形成したり、回路基板２の半導体チップ３１と対向する表面ならびに回路基板２の半導体チップ３２と対向する表面に同様に凹部２１，２１ａ，２１ｂ，２１ｃを形成することが考えられる。   In the first and second embodiments, the recesses 21, 21a, 21b, and 21c are formed only on the surface of the circuit board 2 that faces the semiconductor chip 31 for the sake of simplification. Since the influence of the undulation on the other side of the chip is the same, it is formed only on the surface of the circuit board 2 facing the semiconductor chip 32, or the surface of the circuit board 2 facing the semiconductor chip 31 and the semiconductor chip 32 of the circuit board 2. It is conceivable to form recesses 21, 21 a, 21 b, and 21 c in the same manner on the surface facing each other.

（実施の形態３）
図４（ａ）（ｂ）は本発明の実施の形態３を示す。
この実施の形態３では、図４（ａ）（ｂ）に示すように回路基板２の半導体チップ３１が搭載される面に凸部２２が形成されている。この凸部２２の高さは約３０μｍである。凸部２２を構成する材料は、ガラスクロス入りのエポキシ樹脂など、いずれも封止接着樹脂よりも弾性率の高い材料である。具体的には、封止接着樹脂の弾性率は約５ＧＰａであるのに対し、ガラスクロス入りのエポキシ樹脂は、その弾性率は１０ＧＰａ以上である。 (Embodiment 3)
4 (a) and 4 (b) show Embodiment 3 of the present invention.
In the third embodiment, as shown in FIGS. 4A and 4B, the convex portion 22 is formed on the surface of the circuit board 2 on which the semiconductor chip 31 is mounted. The height of the convex portion 22 is about 30 μm. The material constituting the convex portion 22 is a material having a higher elastic modulus than the sealing adhesive resin, such as an epoxy resin containing glass cloth. Specifically, the elastic modulus of the sealing adhesive resin is about 5 GPa, whereas the epoxy resin with glass cloth has an elastic modulus of 10 GPa or more.

このような硬い材料が回路基板２の上に形成されていることによって、それを含む当該領域の回路基板の厚みを局所的に厚くでき、回路基板２のもう一方に搭載されている半導体チップ３２側が反ることによる影響を半導体チップ３１の側に与えないようにすることができ、半導体チップ３１と封止接着樹脂５１の界面に生じる引張り力を低減できる。   By forming such a hard material on the circuit board 2, the thickness of the circuit board in the region including the hard material can be locally increased, and the semiconductor chip 32 mounted on the other side of the circuit board 2. The effect of warping the side can be prevented from being exerted on the semiconductor chip 31 side, and the tensile force generated at the interface between the semiconductor chip 31 and the sealing adhesive resin 51 can be reduced.

凸部２２を形成する領域の詳細な寸法事例を以下に示す。
半導体チップ３２と半導体チップ３１が重なりあう全領域としているが、半導体チップ３１に形成されるバンプ５１の配置制約に応じてその領域は制限される。例えば図４（ｂ）の場合、凸部２２の平面的な領域の外形は、半導体チップ３１の上に形成されているバンプ５１より、その周辺の封止接着樹脂の充填に必要な領域として、図４（ｂ）中の記号Ｄ３で示すように少なくとも１００μｍ以上内側に存在するものとする。また、半導体チップ３２の側の反りによって半導体チップ３１の側の封止接着樹脂４１が受ける引張り力は、半導体チップ３２のエッジよりも外側で最大になる可能性があることから、凸部２２は、図４（ｂ）中の記号Ｄ４で示すように、半導体チップ３２のエッジよりも外側の領域まで広げて形成する方が好適である。ここではＤ４を半導体チップ３２よりも１００μｍ以上はみだして形成している。 Detailed dimension examples of the region where the convex portion 22 is formed will be shown below.
Although the entire area where the semiconductor chip 32 and the semiconductor chip 31 overlap each other, the area is limited according to the arrangement restriction of the bumps 51 formed on the semiconductor chip 31. For example, in the case of FIG. 4B, the outer shape of the planar region of the convex portion 22 is a region necessary for filling the sealing adhesive resin around the bump 51 formed on the semiconductor chip 31. As shown by the symbol D3 in FIG. 4B, it is assumed that it exists at least 100 μm or more inside. In addition, since the tensile force received by the sealing adhesive resin 41 on the semiconductor chip 31 side due to the warp on the semiconductor chip 32 side may be maximum outside the edge of the semiconductor chip 32, the convex portion 22 is As shown by the symbol D4 in FIG. 4B, it is preferable that the semiconductor chip 32 is formed so as to extend to the region outside the edge. Here, D4 is formed to protrude 100 μm or more from the semiconductor chip 32.

（実施の形態４）
図５，図６は本発明の実施の形態４を示す。
実施の形態３では、回路基板２の上面に形成されている凹部２２の全部を、半導体チップ３１と半導体チップ３２が重なり合う領域に形成するとしているが、この実施の形態４では図５に示すように、引張り力の最も大きくなる領域である半導体チップ３２の外周に相当する位置に沿って鍵型の領域に限定して形成しても同様の効果が得られる。この時の鍵型の凸部２２の幅は、具体的には半導体チップ３２に外側に１００μｍ以上、内側に１００μｍ以上、合計２００μｍ以上の幅を持って形成されている。 (Embodiment 4)
5 and 6 show a fourth embodiment of the present invention.
In the third embodiment, all of the recesses 22 formed on the upper surface of the circuit board 2 are formed in a region where the semiconductor chip 31 and the semiconductor chip 32 overlap. In this fourth embodiment, as shown in FIG. In addition, the same effect can be obtained by forming only the key-shaped region along the position corresponding to the outer periphery of the semiconductor chip 32, which is the region where the tensile force is maximized. The width of the key-shaped convex portion 22 at this time is specifically formed in the semiconductor chip 32 with a width of 100 μm or more on the outside and 100 μm or more on the inside, with a total width of 200 μm or more.

また、前に示した方形または鍵型の領域に配置された凸部２２は、半導体チップ３１の内で連続的に形成するとしているが、実際には、半導体チップ３１の内には、バンプ５１以外にも、回路基板２の表面上に電極以外の銅パターンが形成されている場合が多いため、必ずしも連続的に形成できるとは限らない。このようなパターンの影響により凸部２２の形成が困難な場合には、例えば図６にその一例を示すように、半導体チップ３１に形成されるバンプ５１のレイアウトやその他制約に応じて、断続的に凸部２２ａ，２２ｂ，２２ｃを形成してもかまわない。   Further, the convex portions 22 arranged in the square or key-shaped region shown above are continuously formed in the semiconductor chip 31, but actually, the bumps 51 are formed in the semiconductor chip 31. In addition, since a copper pattern other than an electrode is often formed on the surface of the circuit board 2, it cannot always be formed continuously. When it is difficult to form the convex portion 22 due to the influence of such a pattern, for example, as shown in FIG. 6 for example, intermittently according to the layout of the bump 51 formed on the semiconductor chip 31 and other restrictions. Alternatively, the convex portions 22a, 22b, and 22c may be formed.

また実施の形態３とこの実施の形態４における凸部２２，２２ａ，２２ｂ，２２ｃは、銅などの金属材料を用いて形成することで、上記とは別の効果も得られる。具体的には、一般に、エポキシ系の樹脂は、金属材料とは密着性が低いため、封止接着樹脂４１と凸部２２は、外的な負荷に対し容易に分離される。半導体チップ３２が搭載される側の反りによって、封止接着樹脂４１と凸部２２を先行的に分離させることによって、封止接着樹脂４１と半導体チップ３１との界面の引張り力を生じなくさせることが期待できる。この場合には、凸部２２の最表面にフッ素系、シリコン系などの離型剤を塗布したり、有機薄膜などの離型処理を施すなどを行うことで封止接着樹脂４１との離型性を高める方が効果的である。   In addition, the convex portions 22, 22a, 22b, and 22c in the third embodiment and the fourth embodiment are formed using a metal material such as copper, so that an effect different from the above can be obtained. Specifically, in general, since the epoxy resin has low adhesion to the metal material, the sealing adhesive resin 41 and the convex portion 22 are easily separated from an external load. By preliminarily separating the sealing adhesive resin 41 and the convex portion 22 by the warp on the side on which the semiconductor chip 32 is mounted, the tensile force at the interface between the sealing adhesive resin 41 and the semiconductor chip 31 is prevented from being generated. Can be expected. In this case, the release from the sealing adhesive resin 41 is performed by applying a release agent such as fluorine or silicon on the outermost surface of the convex portion 22 or performing a release treatment such as an organic thin film. It is more effective to increase the sex.

また実施の形態３，実施の形態４において、前記凸部２２，２２ａ，２２ｂ，２２ｃは、説明の簡略化のため回路基板２の半導体チップ３１と対向する表面にのみ形成しているが、各半導体チップが他方に与えるうねりの影響は同様であるため、回路基板２の半導体チップ３２と対向する表面にのみ形成したり、回路基板２の半導体チップ３１と対向する表面ならびに回路基板２の半導体チップ３２と対向する表面に同様に凸部２２，２２ａ，２２ｂ，２２ｃを形成することが考えられる。   In the third and fourth embodiments, the protrusions 22, 22a, 22b, and 22c are formed only on the surface of the circuit board 2 that faces the semiconductor chip 31 for simplicity of explanation. Since the influence of the swell on the other of the semiconductor chip is the same, it is formed only on the surface of the circuit board 2 facing the semiconductor chip 32, or the surface of the circuit board 2 facing the semiconductor chip 31 and the semiconductor chip of the circuit board 2. Similarly, it is conceivable to form convex portions 22, 22 a, 22 b and 22 c on the surface facing 32.

（実施の形態５）
図７〜図９は本発明の実施の形態５を示す。
この実施の形態５では、図７（ａ）（ｂ）に示すように、回路基板２に半導体チップ３１が搭載されている領域の内、その裏側の半導体チップ３２と重なり合っていない領域には、当該回路基板２の半導体チップ３２が搭載される側の面に、弾性体２３が形成されている。図８は図７（ｂ）の背面図を示し、弾性体２３が半導体チップ３２の外周に沿って鍵型に形成されていることが分かる。 (Embodiment 5)
7 to 9 show a fifth embodiment of the present invention.
In the fifth embodiment, as shown in FIGS. 7A and 7B, in the region where the semiconductor chip 31 is mounted on the circuit board 2, the region that does not overlap with the semiconductor chip 32 on the back side thereof, An elastic body 23 is formed on the surface of the circuit board 2 on which the semiconductor chip 32 is mounted. FIG. 8 is a rear view of FIG. 7B, and it can be seen that the elastic body 23 is formed in a key shape along the outer periphery of the semiconductor chip 32.

このように半導体チップ３２の側面を鍵型に覆うように形成されている弾性体２３は、回路基板３２の基材料よりも線膨張が小さいもしくは弾性率の高い材料でできている。具体的には、弾性体２３として線膨張係数は２０ｐｐｍ／℃、そして弾性率が８ＧＰａであるものを用いた。そのような材料の代表的な例として、一般にフィラー濃度の大きいエポキシ樹脂などが挙げられる。このような弾性体を当該領域に形成することによって、図８に示すような回路基板２の全体のうねりを弾性体２３が抑制し、そのうねりに起因して半導体チップの封止接着樹脂が引張られることを回避することができる。   Thus, the elastic body 23 formed so as to cover the side surface of the semiconductor chip 32 in a key shape is made of a material having a smaller linear expansion or a higher elastic modulus than the base material of the circuit board 32. Specifically, an elastic body 23 having a linear expansion coefficient of 20 ppm / ° C. and an elastic modulus of 8 GPa was used. As a typical example of such a material, there is generally an epoxy resin having a high filler concentration. By forming such an elastic body in the region, the elastic body 23 suppresses the entire waviness of the circuit board 2 as shown in FIG. 8, and the sealing adhesive resin of the semiconductor chip is pulled by the waviness. Can be avoided.

弾性体２３が配置される領域の具体寸法について以下に示す。
弾性体２３が配置されるのは、その効果を最大にするため、半導体チップ３１と半導体チップ３２が重ならない領域全域としている。半導体チップ３１と半導体チップ３２のズレは、前述した通り、縦方向に１ｍｍ、そして横方向に１ｍｍであることから、半導体チップ３２の側面に形成される弾性体２３は、図７（ｂ）中に記号Ｄ５で示すように、半導体チップ３２のエッジより、１ｍｍ程度の幅を持って形成される。弾性体２３の高さは、封止接着樹脂４２の高さ４０μｍ、そして半導体チップ３２の厚み２００μｍを合計し、２４０μｍ程度であるとする。 Specific dimensions of the region where the elastic body 23 is disposed will be described below.
The elastic body 23 is disposed over the entire region where the semiconductor chip 31 and the semiconductor chip 32 do not overlap in order to maximize the effect. As described above, the deviation between the semiconductor chip 31 and the semiconductor chip 32 is 1 mm in the vertical direction and 1 mm in the horizontal direction. Therefore, the elastic body 23 formed on the side surface of the semiconductor chip 32 is shown in FIG. As shown by symbol D5, the semiconductor chip 32 is formed with a width of about 1 mm from the edge. The height of the elastic body 23 is about 240 μm, which is the sum of the height of the sealing adhesive resin 42 of 40 μm and the thickness of the semiconductor chip 32 of 200 μm.

上記では、半導体チップ周辺に存在するその他受動部品の配置制約に応じて、断続的に配置されていてもかまわない。またその高さも半導体チップ３２の上面までとしているが、必要量に応じてその高さを低くしてもかまわない。   In the above, it may be intermittently arranged according to the arrangement restrictions of other passive components existing around the semiconductor chip. The height is also up to the upper surface of the semiconductor chip 32, but the height may be lowered according to the required amount.

弾性体２３は、説明の簡略化のため回路基板２の半導体チップ３２の搭載されている面にのみ形成しているが、各半導体チップが他方に与えるうねりの影響は同様であるため、半導体チップ３１が搭載されている面にも同様に形成することも考えられる。   The elastic body 23 is formed only on the surface of the circuit board 2 on which the semiconductor chip 32 is mounted for the sake of simplicity of explanation. It is also conceivable to form the same on the surface on which 31 is mounted.

本発明の半導体チップの両面実装構造は、サイズの異なる半導体チップがずれていることによって生じる局所的なうねり、およびそれに起因する封止接着樹脂の引張り力を低減することができ、半導体チップと封止接着樹脂の間に生じる剥離現象を回避することができる。またそれにより、回路基板や半導体チップをさらに薄くすることができ、半導体実装構造の小型・低背化を実現することができる。   The double-sided mounting structure of the semiconductor chip of the present invention can reduce local undulation caused by misalignment of semiconductor chips of different sizes, and the tensile force of the sealing adhesive resin resulting therefrom. Peeling phenomenon that occurs between the adhesive resins can be avoided. Thereby, the circuit board and the semiconductor chip can be made thinner, and the semiconductor mounting structure can be reduced in size and height.

本発明の実施の形態１における半導体装置の断面図と平面図Sectional drawing and top view of the semiconductor device in Embodiment 1 of this invention 本発明の実施の形態２における半導体装置の平面図The top view of the semiconductor device in Embodiment 2 of this invention 同実施の形態における半導体装置の別の平面図Another plan view of the semiconductor device according to the embodiment 本発明の実施の形態３における半導体装置の断面図と平面図Sectional drawing and top view of the semiconductor device in Embodiment 3 of this invention 発明の実施の形態４における半導体装置の平面図Plan view of a semiconductor device in a fourth embodiment of the invention 同実施の形態における半導体装置の別の平面図Another plan view of the semiconductor device according to the embodiment 本発明の実施の形態５における半導体装置の断面図と平面図Sectional drawing and top view of the semiconductor device in Embodiment 5 of this invention 同実施の形態における背面図Rear view in the same embodiment 同実施の形態の適用効果を示す概要図Schematic diagram showing the application effect of the same embodiment 半導体チップの一般的な両面実装構造を説明する概要図Outline diagram explaining general double-sided mounting structure of semiconductor chip 半導体チップの両面実装構造における問題点を説明する概要図Outline diagram explaining problems in the double-sided mounting structure of semiconductor chips

符号の説明Explanation of symbols

２ 回路基板
２１，２１ａ，２１ｂ，２１ｃ 凹部
２２，２２ａ，２２ｂ，２２ｃ 凸部
２３ 弾性体
３１，３２ 半導体チップ
４１，４２ 封止接着樹脂
５１，５２ バンプ 2 Circuit boards 21, 21a, 21b, 21c Recesses 22, 22a, 22b, 22c Protrusions 23 Elastic bodies 31, 32 Semiconductor chips 41, 42 Sealing adhesive resins 51, 52 Bumps

Claims (3)

回路基板と、
前記回路基板の第１面に複数の第１バンプを介して実装され、封止接着樹脂によって樹脂封止された直方体の第１半導体チップと、
前記回路基板の第２面に複数の第２バンプを介して実装され、樹脂封止された直方体の第２半導体チップと、からなる半導体装置であって、
前記回路基板上面から見た場合に、前記第１，第２半導体チップは、重なり部分を有するとともにその重心位置を互いにずらしてあり、
前記重なり部分を含み、かつ、前記複数の第１バンプ間の領域の前記第１面に形成された凹部を有し、前記凹部に前記封止接着樹脂が充填されている
半導体装置。 A circuit board;
A rectangular parallelepiped first semiconductor chip mounted on the first surface of the circuit board via a plurality of first bumps and sealed with a sealing adhesive resin;
A rectangular parallelepiped second semiconductor chip mounted on the second surface of the circuit board via a plurality of second bumps and sealed with a resin,
When viewed from the upper surface of the circuit board, the first and second semiconductor chips have overlapping portions and their gravity positions are shifted from each other.
A semiconductor device having a recess including the overlapping portion and formed in the first surface in a region between the plurality of first bumps, and the recess is filled with the sealing adhesive resin. . 回路基板と、
前記回路基板の第１面に複数の第１バンプを介して実装され、封止接着樹脂によって樹脂封止された直方体の第１半導体チップと、
前記回路基板の第２面に複数の第２バンプを介して実装され、樹脂封止された直方体の第２半導体チップと、からなる半導体装置であって、
前記回路基板上面から見た場合に、前記第１，第２半導体チップは、重なり部分を有するとともにその重心位置を互いにずらしてあり、
前記重なり部分を含み、かつ、前記複数の第１バンプ間の領域の前記第１面に形成され、前記封止接着樹脂よりも弾性率の高い凸部を有する
半導体装置。 A circuit board;
A rectangular parallelepiped first semiconductor chip mounted on the first surface of the circuit board via a plurality of first bumps and sealed with a sealing adhesive resin;
A rectangular parallelepiped second semiconductor chip mounted on the second surface of the circuit board via a plurality of second bumps and sealed with a resin,
When viewed from the upper surface of the circuit board, the first and second semiconductor chips have overlapping portions and their gravity positions are shifted from each other.
A semiconductor device including a convex portion including the overlapping portion and formed on the first surface in a region between the plurality of first bumps and having a higher elastic modulus than the sealing adhesive resin . 回路基板と、
前記回路基板の第１面に複数の第１バンプを介して実装され、封止接着樹脂によって樹脂封止された直方体の第１半導体チップと、
前記回路基板の第２面に複数の第２バンプを介して実装され、樹脂封止された直方体の第２半導体チップと、からなる半導体装置であって、
前記回路基板上面から見た場合に、前記第１，第２半導体チップは、重なり部分を有するとともにその重心位置を互いにずらしてあり、
前記回路基板上面から見た場合の前記第１，第２半導体チップの全体の領域で、前記第１面の前記第２半導体チップの投影領域の外周に対応する位置に沿って鍵型の形状に形成された凹部を有し、前記凹部に前記封止接着樹脂が充填されている
半導体装置。 A circuit board;
A rectangular parallelepiped first semiconductor chip mounted on the first surface of the circuit board via a plurality of first bumps and sealed with a sealing adhesive resin;
A rectangular parallelepiped second semiconductor chip mounted on the second surface of the circuit board via a plurality of second bumps and sealed with a resin,
When viewed from the upper surface of the circuit board, the first and second semiconductor chips have overlapping portions and their gravity positions are shifted from each other.
In the entire area of the first and second semiconductor chips when viewed from the upper surface of the circuit board, a key shape is formed along a position corresponding to the outer periphery of the projection area of the second semiconductor chip on the first surface. A semiconductor device having a recessed portion formed and filled with the sealing adhesive resin .
JP2008006341A 2008-01-16 2008-01-16 Semiconductor device Expired - Fee Related JP5078631B2 (en)

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