JP2008153699A - Semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can prevent external noises from entering the semiconductor device and has a robustness and reliability by adopting a simple arrangement structure for passive elements without enlarging the mounting area on a wiring board. <P>SOLUTION: The semiconductor device 20 has a board 25, a semiconductor element 27 disposed on one principle surface of the board 25, and a plurality of the passive elements 23 and 24. The passive elements contain a plurality of the first passive elements 23 having a first height and a plurality of the second passive elements 24 having a second height lower than that of the first passive elements 23. The semiconductor element 27 is supported on the plurality of the first passive elements 23; and electrodes of the semiconductor element 27 and electrodes of the board 25 are connected with wires. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically to a semiconductor device in which a semiconductor chip (semiconductor element) and a passive element are mounted on one main surface of a substrate and a manufacturing method thereof.

  In a semiconductor device, a passive element such as a capacitor is often inserted and connected between a power supply terminal and a ground terminal in order to reduce or suppress the entry of external noise that causes a malfunction during use.

  As the degree of integration increases and the number of the above-mentioned terminals increases, noise is likely to be introduced due to the increased distance between the power supply terminal and the ground terminal, so the passive elements are placed as close to the semiconductor chip as possible. It is desirable to perform (refer patent document 1).

  As a mode in which passive elements are arranged in the vicinity of a semiconductor chip, the structure shown in FIG. 1 has been proposed. 1A and 1B are diagrams illustrating a structure of an electronic component on which the semiconductor device is mounted. FIG. 1A is a plan view and FIG. 1B is a cross-sectional view. Referring to FIG. 1, in an electronic component 10, a semiconductor device 3 is mounted on one main surface of a substrate 1 via a solder ball 2. A plurality of passive elements 4 such as capacitors are mounted around the semiconductor device 3 on one main surface of the substrate 1.

  As another mode in which the passive element is arranged in the vicinity of the semiconductor chip, a structure shown in FIG. 2 has also been proposed. 2A and 2B are diagrams illustrating a structure of the semiconductor device, in which FIG. 2A is a cross-sectional view and FIG. 2B is a rear view. Referring to FIG. 2, in the configuration in which a large number of solder balls 2 are provided as external connection terminals on the back surface of the wiring substrate 5 of the semiconductor device 3, that is, the surface opposite to the mounting surface of the semiconductor chip 11, the solder A passive element 4 such as a capacitor is mounted in a portion where the ball 2 is not provided, that is, in a substantially central portion of the wiring board 5.

  Further, as another mode in which the passive element is arranged in the vicinity of the semiconductor chip, a structure shown in FIG. 3 has been proposed (see Patent Document 2). FIG. 3 is a cross-sectional view illustrating the structure of the semiconductor device. Referring to FIG. 3, a plurality of passive elements 4 such as capacitors are mounted on one main surface of the wiring board 5, and a semiconductor chip 17 is mounted on the passive elements 4. The electrodes of the semiconductor chip 17 and the electrodes of the wiring substrate 5 are connected by bonding wires 18. These capacitive element 4, semiconductor chip 17, and bonding wire 18 are sealed with a sealing resin 16. A plurality of external connection solder balls 2 are disposed on the other main surface of the wiring board 5.

  In addition, a structure in which a passive element is mounted on one main surface of a wiring board, a base member is fixed to the wiring board so as to cover the passive element, and a semiconductor chip is mounted on the base member is also proposed. (See Patent Document 3). In such a structure, a gap is formed between the passive element disposed on the wiring board and the base member covering the passive element.

Similarly to Patent Document 2, a configuration is proposed in which a plurality of passive elements such as capacitors are mounted on one main surface of a wiring board, and a semiconductor chip is mounted by flip chip mounting so as to cover the passive elements. (See Patent Document 4). In such a configuration, a solder bump having a thickness (height) exceeding the height of the passive element having the largest external dimension among the plurality of passive elements is applied to the semiconductor chip, and flip chip mounting is performed. Has been.
JP 61-35544 A JP 2005-12199 A JP 2004-214579 A Japanese Patent Application Laid-Open No. 2004-247637

  However, in the structure shown in FIG. 1, it is necessary to provide both the region for mounting and arranging the semiconductor device 3 and the region for arranging the passive element 4 on one main surface of the substrate 1. Therefore, the substrate 1 having a large mounting area is required.

  Similarly, in the structure shown in FIG. 2, both the area for arranging the solder balls 2 and the area for arranging the passive elements 4 must be provided on the main surface of the wiring board 5. Therefore, the wiring board 5 having a large mounting area is required even in such a configuration.

  As semiconductor chips (semiconductor elements) such as LSIs (Large Scale Integrated Circuits) become highly integrated and highly functional, the number of power supply terminals and ground terminals required for the semiconductor chips is increasing. Along with this, the number of passive elements required is also increasing. Therefore, the structure shown in FIGS. 1 and 2 requires a substrate having a larger mounting area, and cannot cope with the downsizing of a semiconductor device that has been required in recent years.

  Further, in the structure shown in FIG. 3, the height of each passive element 4 must be the same so as not to cause variations. That is, all the passive elements 4 are in contact with the semiconductor chip 17 and the semiconductor chip 17 and the wiring board 5 must be parallel. For this reason, in the configuration shown in Patent Document 2, in order to make the variation in the height of the passive element 4 on the wiring substrate 5 caused by the variation in mounting uniform, the passive element 4 is wired via the solder paste. It has been proposed that after mounting on the substrate 5, the upper surface of the passive element 4 is polished and flattened.

  However, since the amount of solder paste between the wiring board 5 and the passive element 4 is small, it is difficult to make the height of all the passive elements 4 uniform, and the passive element 4 is destroyed by the polishing process. There is a high risk of being done.

Further, in the structure shown in FIG. 3, the passive element 4 is disposed between the semiconductor chip 17 and the wiring substrate 5, and the outer periphery is covered with the sealing resin 16. In general, the passive element 4 is configured using ceramic or silicon (Si) as a base material, and has a thermal expansion coefficient different from that of the wiring board 5 or the sealing resin 16. Specifically, the thermal expansion coefficient of the ceramic capacitor as the passive element 4 is 9 × 10 ⁻⁶ / ° C., the thermal expansion coefficient of the sealing resin is 8 × 10 ⁻⁶ / ° C., and the thermal expansion of the wiring board. coefficient is 20 × ^{10 -6} / ℃. As in the example shown in FIG. 3, in the structure in which the passive element 4 is disposed between the semiconductor chip 17 and the wiring substrate 5 and the outer periphery is simply covered with the sealing resin 16, thermal expansion is performed on the semiconductor chip 17. Under the semiconductor chip 17 is the sealing element 16 having a small coefficient, and the passive element 4 having a large coefficient of thermal expansion exists. Therefore, under an environment where there is a temperature change, each member may expand or contract due to heat due to the difference in thermal expansion coefficient of each member, and stress may be generated, and the semiconductor chip 17 may be destroyed.

  On the other hand, in the structure proposed in Patent Document 3, that is, in the structure in which a gap is formed between the passive element disposed on the wiring board and the base member covering the passive element, the semiconductor package When heat is applied to the package in a solder reflow process or the like for mounting the circuit board on the wiring board, stress is generated due to a difference in thermal expansion coefficient between the semiconductor chip and the base member. As a result, for example, when a force is applied to the semiconductor chip and the base member from above, there is a gap between the base member and the passive element, so that the semiconductor chip disposed on the base member is deformed and destroyed. There is a risk of being.

  In the structure proposed in Patent Document 4, the semiconductor chip is flip-chip mounted, and the height of the solder bumps at this time exceeds (absorbs) the maximum height of a plurality of passive elements. Is set. Therefore, there are few restrictions on the arrangement of passive elements.

  However, such a configuration cannot be applied to a structure in which the electrode pads of the semiconductor chip and the electrodes of the wiring substrate are connected by a wire bonding method. That is, as shown in FIG. 4A, the semiconductor chip 17 is arranged via a plurality of capacitive elements arranged on the wiring board 5 and having different external dimensions, and the electrode pads of the semiconductor chip 17 and the wiring board 5 are arranged. When the electrode pads of the semiconductor chip 17 are connected by the wire bonding method, the external dimensions of the capacitive element 4-1 disposed almost immediately below the electrode pads of the semiconductor chip 17 are small, and the lower surface of the semiconductor chip 17 and the capacitive element 4 -1 and a gap G exists, when wire bonding processing is performed on the electrode pad, the semiconductor chip 17 is inclined at an angle θ as shown in FIG. There is a great risk of 17 destruction. It is also difficult to increase the reliability of the wire bonding connection.

  The present invention has been made in view of the above points, and it is possible to connect lead wires between a semiconductor chip and a wiring board without increasing the mounting area of the wiring board on which the semiconductor chip and the passive element are mounted. An object of the present invention is to provide a robust and reliable semiconductor device that can facilitate (wire bonding) and prevent external noise from entering the semiconductor device, and a method for manufacturing the same.

  According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element provided above the substrate, and a plurality of passive elements provided on the substrate, wherein the passive element is A semiconductor device is provided, wherein the semiconductor device is sealed with resin, and the semiconductor element is mounted on the resin substantially parallel to the substrate.

  According to still another aspect of the present invention, a step of mounting a plurality of passive elements on a substrate, a step of disposing a resin on the substrate so as to cover the passive elements, and mounting a semiconductor element on the resin A semiconductor device comprising: a step of connecting the electrode of the semiconductor element and the electrode of the substrate with a wire; and a step of resin-sealing the semiconductor element, the passive element, and the wire A manufacturing method is provided.

  According to the present invention, a robust and highly reliable semiconductor device capable of preventing external noise from being mixed into a semiconductor device with a simple passive element arrangement structure without increasing the mounting area of the wiring board, and its A manufacturing method can be provided.

  Hereinafter, embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described.

[Embodiment of Semiconductor Device]
First, a first embodiment of a semiconductor device of the present invention will be described with reference to FIGS. FIG. 5 shows a first embodiment of the semiconductor device of the present invention, FIG. 5- (A) is a cross-sectional view, and FIG. 5- (B) is a plan view. For convenience of explanation, in FIG. 5B, the bonding wire 28 illustrated in FIG.

  Referring to FIG. 5, in the semiconductor device 20 according to the present embodiment, a semiconductor chip 27 and a plurality of passive elements 24 are mounted on one main surface (upper surface) of the wiring substrate 25, and the other of the wiring body substrate 25. A plurality of solder balls 22 serving as external connection terminals are disposed on the main surface (lower surface).

  The wiring board 25 has, for example, a multilayer wiring structure composed of a glass epoxy resin layer and a wiring layer, or a double-sided wiring structure, and is also referred to as a circuit board or an interposer.

  In the present embodiment, four first passive elements 23-1 to 23-4 and twelve second passive elements 24-1 to 24-24 are provided on one main surface of the wiring board 25. -12 is installed. In FIG. 5B, the hatched portions at both ends of each of the passive elements 23 and 24 are external connection terminal (electrode) portions of the passive elements, and are formed on one main surface of the wiring board 25. It is fixed and connected to the provided electrode pad. Here, the first passive elements 23-1 to 23-4 and the second passive elements 24-1 to 24-12 are all for reducing the mixing of external noise that causes malfunctions when the semiconductor device is used. For example, a capacitor (capacitance element), a resistor, a coil, or the like is provided.

  The capacitance of the passive element, for example, a capacitor (capacitance element) is selected in accordance with a current value handled in the connected electronic circuit. Therefore, since capacitive elements having different capacitance values are required in accordance with the scale and function of the electronic circuit in the semiconductor chip 27, at least two types (groups) of capacitive elements are required.

  In the present embodiment, the capacitive elements (chip capacitors) that are the first passive elements 23-1 to 23-4 are arranged corresponding to an electronic circuit that handles a relatively large current, while the second Capacitance elements (chip capacitors) that are the passive elements 24-1 to 24-12 are arranged corresponding to electronic circuits that handle a relatively small current.

  Therefore, the first passive element has a larger outer dimension than the second passive element. For this reason, the height of the first passive element when it is connected and fixed to the electrode pad on the wiring board 25 is high. (Thickness), that is, the height from one main surface of the wiring board 25 is higher than the height of the second passive element. The capacitor element (chip capacitor) is generally formed using ceramic as a dielectric.

  In the present embodiment, the semiconductor chip 27, the wiring board 25, the first passive elements 23-1 to 23-4, and the second passive elements 24-1 to 24-12 are electrically connected to each other. Thus, the semiconductor device 20 is configured. In such an embodiment, the first passive elements 23-1 to 23-4 correspond to a region on one main surface of the wiring board 25 on which the semiconductor chip 27 is placed, corresponding to the semiconductor. The chip 27 is mounted and fixed at positions corresponding to the four corners. The four corners of the semiconductor chip 27 are fixed on the first passive elements 23-1 to 23-4, that is, supported by the four first passive elements and mounted on the wiring board 25. Yes. In this configuration, the four first passive elements (23-1 to 23-4) having the same outer dimensions are selected, and the surface of the semiconductor chip 27 to be placed, that is, for external connection. The surface on which the electrode pad is disposed and one main surface of the circuit board 25 are substantially parallel to each other.

  The four first passive elements (23-1 to 23-4) arranged corresponding to the four corners of the semiconductor chip 27 correspond to the four corners and also correspond to the electronic circuits in the semiconductor chip 27. The location is selected to be as close as possible to the electronic circuit. The second passive elements 24-1 to 24-12 are all mounted and fixed on the surface of the wiring board 25 located immediately below the semiconductor chip 27. Since the second passive element has a smaller external dimension than the first passive element, there is a gap between the semiconductor chip 27 and the second passive elements 24-1 to 24-12. These second passive elements are also arranged as close as possible to the corresponding electronic circuits in the semiconductor chip 27.

  According to such an embodiment, the plurality of passive elements, that is, the first passive elements 23-1 to 23-4 and the second passive elements 24-1 to 24-12 are directly below the portion where the semiconductor chip 17 is located. Therefore, there is no need to separately provide a region for mounting the passive elements, and the area of the wiring board 25 is not increased. Therefore, the semiconductor device can be miniaturized.

  In addition, as compared with the conventional structure shown in FIGS. 1 and 2, the semiconductor chip 17, the first passive elements 23-1 to 23-4, and the second passive elements 24-1 to 24-12. The wiring length can be shortened, and mixing of external noise can be reduced more effectively.

  Further, the first passive elements 23-1 to 23-4 and the second passive elements 24-1 to 24-12, the semiconductor chip 27, and the bonding wires 28 are sealed with a sealing resin 26. That is, the sealing resin 26 is not only above the semiconductor chip 27 but also the first passive elements 23-1 to 23-4 and the second passive elements 24-1 to 24-disposed below the semiconductor chip 27. Between 12 is also filled. Accordingly, the front and back surfaces of the semiconductor chip 27 are covered with the sealing resin 26. Therefore, the semiconductor chip 27 is less affected by the generation of stress due to the difference in thermal expansion coefficient between the front and back surfaces, and a highly reliable semiconductor device 20 can be obtained.

  Note that, as described above, in the present embodiment, the first passive elements 23-1 to 23-4 are mounted and fixed on portions corresponding to the four corners of the semiconductor chip 27 on the wiring substrate 25. More specifically, the first passive elements 23-1 to 23-4 are arranged so that the end portions thereof coincide with the side edges (end portions) of the semiconductor chip 27.

  However, the present invention is not limited to this embodiment, and may be the embodiment shown in FIG. 6 or FIG. Here, FIG. 6 is a diagram (part 1) for illustrating a modified example of the arrangement of the first passive elements 23-1 to 23-4. More specifically, FIG. FIG. 6 (A) is an enlarged view of a portion surrounded by a dotted line, and FIG. 6 (D) is an enlarged view of a portion surrounded by a dotted line in FIG. 6 (C). FIG. 7 is a diagram (No. 2) for illustrating a modification of the arrangement of the first passive elements 23-1 to 23-4. 7- (B) is an enlarged view of a portion surrounded by a dotted line in FIG. 7- (A), and FIG. 7- (D) is an enlarged view of a portion surrounded by a dotted line in FIG. 7- (C). is there.

  Referring to FIG. 6, the first passive elements 23-1 to 23-4 and the second passive element 24 are arranged on the wiring board 25, and the first passive elements 23-1 to 23-4 and the second passive elements 24 are arranged. When the semiconductor chip 27 is placed (die-attached) on the two passive elements 24, a so-called die collet 30 may be used. In this case, pressure is applied to the semiconductor chip 27 by the die collet 30. At this time, as shown in FIGS. 6A and 6B, the outer end portions of the first passive elements 23-1 to 23-4 are inside the side end surface of the die collet 30. Then, the die collet 30 may cause a bending moment around the ends of the first passive elements 23-1 to 23-4 to break the semiconductor chip 27. On the other hand, as shown in FIG. 6- (C) and FIG. 6- (D), the outer ends of the first passive elements 23-1 to 23-4 are at least at the same position as the side end face of the die collet 30. Alternatively, when the die collet 30 is located outside the side end face, it is possible to prevent the above-described bending moment from being generated around the ends of the first passive elements 23-1 to 23-4, and thus the semiconductor chip 27. Can be prevented. Therefore, as shown in FIGS. 5, 6 -C, and 6 -D, the end portions of the first passive elements 23-1 to 23-4 are at least the same position as the side end face of the die collet 30. Or on the outside of the side end face of the die collet 30 and at the same position as the side of the semiconductor chip 27 or on the inside of the side of the semiconductor chip 27.

  Further, referring to FIG. 7, the first passive elements 23-1 to 23-4 and the second passive element 24 are arranged on the wiring board 25, and the first passive elements 23-1 to 23- are arranged. A capillary 31 is used to wire bond the electrode pads 32 of the semiconductor chip 27 placed on the fourth and second passive elements 24. At this time, as shown in FIG. 7- (A) and FIG. 7- (B), the end portions of the first passive elements 23-1 to 23-4 are inside the electrode pads 32 of the semiconductor chip 27. When wire bonding is performed, a bending moment about the ends of the first passive elements 23-1 to 23-4 acts and the semiconductor chip 27 may be destroyed. On the other hand, as shown in FIG. 7- (C) and FIG. 7- (D), the end portions of the first passive elements 23-1 to 23-4 are at least at the same position as the side end surfaces of the electrode pads 32, or When it is outside the side end face of the electrode pad 32, it is possible to prevent the bending moment from being generated around the ends of the first passive elements 23-1 to 23-4 and to prevent the semiconductor chip 27 from being destroyed. can do.

  Accordingly, as shown in FIGS. 5, 7 -C, and 7 -D, the end portions of the first passive elements 23-1 to 23-4 are at least at the same position as the wire bonding portion 32. Alternatively, it is desirable to be outside the wire bonding portion 32 and at the same position as the side of the semiconductor chip 27 or inside the side of the semiconductor chip 27.

  Referring to FIG. 5 again, as described above, the second passive elements 24-1 to 24-12 are placed on the wiring board 25 at substantially equal intervals. This arrangement structure will be described with reference to FIG.

  Here, FIG. 8 is a plan view of the wiring board 25 for explaining the arrangement structure of the second passive elements 24-1 to 24-12. In FIG. 8, illustration of the semiconductor chip 17, the bonding wire 28, the sealing resin 26, and the first passive elements 23-1 to 23-4 shown in FIG. 2 is omitted for convenience of explanation. For convenience of explanation, FIGS. 8A and 8B show an example in which nine second passive elements 24-1 to 24-9 are arranged on the wiring board 25, and FIG. -(C) shows an example in which seven second passive elements 24-1 to 24-7 are arranged on the wiring board 25.

  In order to exhibit the characteristics of the semiconductor chip 27 satisfactorily, it is necessary to shorten the wiring length between the semiconductor chip 27 and the passive elements (second passive elements 24-1 to 24-9 in the example shown in FIG. 8). There is. As a result of paying attention to shortening of the wiring length, as shown by a dotted line A in FIG. 8A, passive elements (passive elements 24-1 to 24-5 in the example of FIG. 8A) are formed on the wiring board 25. As shown by the dotted line B, a region where the passive elements are not arranged is formed, and the position and quantity of the passive elements arranged on the wiring board 25 may be biased.

As described above, the passive element is generally configured using ceramic or silicon as a base material, and has a thermal expansion coefficient different from that of the wiring board or the sealing resin. Specifically, the thermal expansion coefficient of the ceramic capacitor as the passive element is 9 × 10 ⁻⁶ / ° C., the thermal expansion coefficient of the sealing resin is 8 × 10 ⁻⁶ / ° C., and the thermal expansion coefficient of the wiring board. Is 20 × 10 ⁻⁶ / ° C. As shown in FIG. 5, the sealing resin 26 is also formed between the passive elements 24-1 to 24-9 on the wiring board 25, but the portion surrounded by the dotted line A in FIG. Since the passive elements 24-1 to 24-5 are densely arranged, the amount of sealing resin formed is smaller than the portion surrounded by the dotted line B where no passive elements are arranged. Therefore, the portion surrounded by the dotted line A is a region having a smaller thermal expansion coefficient than the portion surrounded by the dotted line B.

  Thus, in the wiring board 25, a region where the number of mounted passive elements is large, that is, a region where the thermal expansion coefficient is small, and a region where the number of passive elements mounted is small, that is, a large thermal expansion coefficient. If the region exists, the entire semiconductor device, the semiconductor chip 27, or the wiring substrate 25 may be damaged due to the stress due to the difference in thermal expansion coefficient.

  Therefore, as shown in FIG. 8B, it is desirable that the second passive elements 24-1 to 24-9 are arranged at substantially equal intervals in the semiconductor device 20 as a whole. That is, it is desirable to dispose the passive elements 24-1 to 24-9 with a substantially uniform density without the density of the arrangement on the wiring board 25. As described above, by arranging the arrangement density of the passive elements 24-1 to 24-9 in the wiring board 25 evenly, the entire semiconductor device 20, the semiconductor chip 27, or the wiring board 25 shown in FIG. It becomes a structure which is hard to be influenced by the stress due to the difference in thermal expansion coefficient.

  For the same reason, not only the structure illustrated in FIG. 8B but also the structure illustrated in FIG. That is, in the wiring board 25, in order to avoid a region having a small thermal expansion coefficient and a region having a large thermal expansion coefficient as a result of forming a region having a large number and a small number of passive elements to be mounted. Alternatively, dummy elements 21-1 to 21-4 having substantially the same thermal expansion coefficient as the passive elements 24-1 to 24-7 may be disposed on the wiring board 25. More specifically, each of the dummy elements 21-1 to 21-4 is preferably made of substantially the same material as the passive elements 24-1 to 24-7. If each of the dummy elements 21-1 to 21-4 has substantially the same thermal expansion coefficient as the passive elements 24-1 to 24-7, the generation of stress due to the difference in the thermal expansion coefficients is prevented. Can do. In the structure shown in FIG. 8C, in the entire semiconductor device 20, the dummy elements 21-1 to 21-4 are coupled to the second passive elements 24-1 to 24-7 in the wiring substrate 25. They are arranged with a substantially uniform density by eliminating the difference in arrangement density. As described above, by arranging the arrangement density of the passive elements 24-1 to 24-7 and the dummy elements 21-1 to 21-4 in the wiring board 25 evenly, the entire semiconductor device 20 shown in FIG. The semiconductor chip 27 or the wiring board 25 is not easily affected by the stress due to the difference in thermal expansion coefficient between them.

  Further, the first passive elements 23-1 to 23-4 and the second passive elements 24-1 to 24-12 shown in FIG. 5 are arranged in consideration of the inflow of the sealing resin 26. This will be described with reference to FIGS. FIG. 9 is a diagram for explaining the relationship between the arrangement of passive elements (in the example shown in FIG. 9, the second passive elements 24-1 to 24-3 for convenience of explanation) and the inflow of the sealing resin 26 (part 1). FIG. 10 is a diagram (part 2) for explaining the relationship between the arrangement of the passive elements 40 to 48 and the inflow of the sealing resin 26.

  As shown in FIG. 5, the first passive elements 23-1 to 23-4 and the second passive elements 24-1 to 24-12, the semiconductor chip 27, and the bonding wires 28 are hermetically sealed with a sealing resin 26. Stopped. During the resin sealing, the passive elements 23-1 to 23-4 and 24-1 to 24-12 hinder the inflow of the sealing resin, and the sealing resin becomes the passive elements 23-1 to 23-4 and There is a risk that it will not flow properly between 24-1 and 24-12. In the present embodiment, the orientation of the passive elements 23-1 to 23-4 and 24-1 to 24-12 is set in consideration of the inflow direction of the sealing resin 26.

  That is, as shown in FIG. 9- (A), the passive element 24 such as a capacitor (capacitance element) has a substantially rectangular parallelepiped shape. In the figure, electrodes E1 and E2 are provided at both ends of the rectangular parallelepiped. 9A, a plan view when the sealing resin flows in the direction indicated by the arrow b with respect to the passive element 24 is shown in FIG. 9B, and the sealing resin is indicated by the arrow c. A plan view when flowing in the direction is shown in FIG.

  In this embodiment, as shown in FIG. 9- (B), the passive elements 24-1 to 24-3 are passive so that the longitudinal direction thereof is parallel to the inflow direction of the sealing resin. The elements 24-1 to 24-3 are arranged so that the distance between them is substantially equal.

  The interval L2 between the passive elements 24-1 to 24-3 shown in FIG. 9B is provided by the passive elements 24-1 to 24-3 so that the longitudinal direction is perpendicular to the inflow direction of the sealing resin. This is wider than the distance L1 between the passive elements 24-1 to 24-3 in the case shown in FIG. 9- (C). Accordingly, in the case shown in FIG. 9- (B), the sealing resin can easily flow between the passive elements 24-1 to 24-3 as compared to the case shown in FIG. 9- (C). The generation of voids in the sealing resin can be reliably prevented. In the structure shown in FIG. 5, the inflow direction of the sealing resin is, for example, the direction from the passive element 24-9 to the passive element 24-1 in FIG. Of course, the direction from the passive element 24-1 to the automatic element 24-9 is also possible.

  Further, the intervals between the passive elements 24-1 to 24-3 shown in FIG. 9- (B) are all equal intervals of length L2, and the interval between the passive elements 24-1 and 24-2. This is different from the case shown in FIG. 9- (D) in which the distance L4 between L3, the passive element 24-2, and the passive element 24-3 is different. In the case shown in FIG. 9- (B), the intervals L2 between the passive elements 24-1 to 24-3 are equal, so that the passive elements 24-1 to 24-24 are compared to the case shown in FIG. 9- (D). The rate and amount of resin inflow between -3 can be equalized. Therefore, the resin can be appropriately flown, and the occurrence of a portion where the resin is not flown can be prevented.

  FIG. 10 shows an example in which the concept shown in FIG. 9- (B) is made more specific. FIG. 10- (A) is a plan view of the wiring board 25 on which six semiconductor chips 27 are mounted, and FIG. 10- (B) is a sectional view taken along line aa in FIG. 10- (A). is there. Each of the semiconductor chips 27 and the passive elements 40 to 48 arranged between the semiconductor chip 27 and the wiring board 25 are arranged so that the longitudinal direction thereof is parallel to the inflow direction of the sealing resin. . In FIG. 10A, the reference numbers are given to the passive elements for only one semiconductor chip, but the passive elements are similarly arranged under the other five semiconductor chips. .

  According to such a configuration, the sealing resin can easily flow between the passive elements 40 (41, 42), 43 (44, 45) and 46 (47, 48), and the generation of voids is reliably prevented. be able to. Further, the passive element 43 (44, 45) is disposed at the approximate center between the passive elements 40 (41, 42) and 46 (47, 48). That is, the passive elements 40 (41, 42), 43 (44, 45) and 46 (47, 48) are arranged at substantially equal intervals. Accordingly, the speed and amount of resin flow between the passive elements 40 (41, 42) and 43 (44, 45) and between the passive elements 43 (44, 45) and 46 (47, 48) can be equalized. The resin can appropriately flow between the passive elements 40 (41, 42), 43 (44, 45) and 46 (47, 48), and the formation of a portion where the resin does not flow is prevented. be able to.

  Incidentally, in the example shown in FIG. 5, four first passive elements 23-1 to 23-4 and twelve second passive elements 24-1 to 24-12 are provided on the wiring substrate 25. It is placed. However, the number of the first passive elements that support the semiconductor chip 27 on the wiring board 25 so as to be substantially parallel to the wiring board 25 is not necessarily four, and if it is plural, the number is particularly limited. There is no limitation. That is, for example, the structure shown in FIG. 11 or 12 may be used. Here, FIG. 11 is a plan view showing a modification (No. 1) of the first embodiment of the semiconductor device of the present invention, and FIG. 12 shows the first embodiment of the semiconductor device of the present invention. It is the top view which showed the modification (the 2). For convenience of explanation, the bonding wire 28 (see FIG. 5- (A)) is not shown in FIGS.

  Referring to FIG. 11, in the first modification of the semiconductor device according to the first embodiment of the present invention (part 1), the height is higher than those of the second passive elements 24-1 to 24-12, and the semiconductor chip. Three first passive elements 23-1 to 23-3 that support 27 are arranged at locations corresponding to three of the four corners of the semiconductor chip 27.

  Referring to FIG. 12, also in the modification (No. 2) of the first embodiment of the semiconductor device of the present invention, the height is higher than those of the second passive elements 24-1 to 24-12. The first passive elements 23-1 to 23-3 that support the semiconductor chip 27 are disposed at positions corresponding to two corners of the four corners of the semiconductor chip 27, and the first passive element 23-3 is Of the four corners of the semiconductor chip 27, the sides of the semiconductor chip 27 connecting the two corners where the first passive elements 23-1 and 23-2 are not disposed (the passive elements 23-1 and 23-2 are disposed). It is arranged at a location corresponding to a substantially midpoint of the side facing the other side.

  A modification (No. 3) of the first embodiment of the semiconductor device of the present invention is shown in FIG. FIG. 13- (A) is a plan view of the wiring board in a state where dummy elements to be described later are not disposed, and FIG. 13- (B) is a side view when viewed in the direction of the arrow in FIG. 13- (A). is there. Further, FIG. 13- (C) is a plan view of the wiring board in a state where dummy elements to be described later are arranged, and FIG. 13- (D) is a side view when viewed in the direction of the arrow in FIG. 13- (C). It is.

As described above, the passive element has various sizes depending on its purpose and application. For example, if capacitor 0603 type or area of 0.6 × 0.3 [mm ^2], include 1608 type or the like of 1.6 × 0.8 [mm ^2]. A passive element having a height higher than other types of passive elements (second passive elements 24-1 to 24-12 in the example shown in FIG. 5) (first passive elements 23-1 to 23-1 in the example shown in FIG. 5). Although it is only necessary that the semiconductor chip 27 can be supported using only 23-4), in practice, the wiring length between the semiconductor chip 27 and the passive element may become long.

  Referring to FIG. 13- (A) and FIG. 13- (B), the semiconductor chip 27 is supported by three first passive elements 23-1 to 23-3. Of the locations corresponding to the four corners of the chip 27, nothing is provided at locations corresponding to the corners corresponding to the portion P in FIG. Therefore, when viewed in the direction of the arrow in FIG. 13- (A), as shown in FIG. 13- (B), there is a gap between the semiconductor chip 27 and the second passive elements 24-4 and 24-5. Exists. In this case, it is conceivable to arrange passive elements having a height equivalent to that of the first passive elements 23-1 to 23-3 at the corners corresponding to the portion P in FIG. 13- (A). However, it may not be necessary in the circuit, and when the distance / wiring length from the electronic circuit in the semiconductor chip 27 becomes long, it is difficult to reduce the mixing of external noise.

  Therefore, in the present modification, as shown in FIGS. 13- (C) and 13- (D), a dummy element 21 having a height equivalent to that of the first passive elements 23-1 to 23-3. -5 is arranged at a position corresponding to the portion P in FIG. Thereby, the semiconductor chip 27 is supported.

  Note that such a dummy element can also be disposed at a substantially central portion of one side of the semiconductor chip 27, like the dummy element 21-6. Further, depending on the configuration of the electronic circuit of the semiconductor chip 27, some of the passive elements that are arranged corresponding to the four corners of the semiconductor chip 27 and support the semiconductor element can be changed to the dummy elements. It is.

  As described above, the dummy element is preferably made of substantially the same material as that of the first passive elements 23-1 to 23-3, or substantially the same material as that of the semiconductor chip 27. If the dummy element has substantially the same thermal expansion coefficient as the first passive elements 23-1 to 23-3 or the semiconductor chip 27, it is possible to prevent the generation of stress due to the difference in the thermal expansion coefficient.

  Next, a second embodiment of the semiconductor device of the present invention will be described with reference to FIGS. In the first embodiment of the semiconductor device of the present invention, a semiconductor chip is mounted on a wiring board with a plurality of passive elements as a support, and other passive elements are placed in the wiring board region immediately below the semiconductor chip. It was installed.

  In the second embodiment of the semiconductor device of the present invention, a predetermined resin layer is formed in advance on the surface of the wiring board where the passive element is placed, and the semiconductor chip is fixed on the resin layer ( (With dice).

  FIG. 14 is a cross-sectional view for explaining a first example of the second embodiment of the present invention together with its manufacturing process. 14A, after a predetermined number of passive elements 51 are mounted and arranged on one main surface (upper surface) of the wiring board 25, an adhesive for semiconductor elements having insulating properties such as epoxy resin ( A die attach resin 55 is formed so as to cover the passive element 51. Next, the semiconductor chip 27 is pressed against the surface of the die attach resin 55 using the die collet 30 that holds the semiconductor chip 27 by suction, and the surface of the die attach resin 55 is applied as shown in FIG. The semiconductor chip 27 is fixed (die-attached) on the die attach resin 55 while being flattened.

  Note that, after the semiconductor chip 27 is fixed to the surface of the die attach resin 55, wire bonding is performed between the electrode pads 57 on the wiring substrate 25 and the electrode pads of the semiconductor chip 27. This is well known. Yes, illustration is omitted here for convenience of explanation.

  FIG. 15 is a cross-sectional view for explaining a second example of the second embodiment of the semiconductor device of the present invention together with its manufacturing process. Referring to FIG. 15- (A), after mounting and arranging a predetermined number of passive elements 51 on one main surface (upper surface) of the wiring board 25, for bonding semiconductor elements having insulating properties such as epoxy resin ( A die attach resin 55 is formed so as to cover the passive element 51. Next, as shown in FIG. 15B, the surface of the die attach resin 55 is flattened using a jig 53. Thereafter, as shown in FIG. 15C, the semiconductor chip 27 is fixed to the surface of the flattened die attach resin 55. Note that after the semiconductor chip 27 is diced onto the die attach resin 55, wire bonding is performed between the electrode pads 57 of the wiring board 25 and the electrode pads of the semiconductor chip 27. Similarly, illustration is omitted.

  In general, the surface of a passive element such as a chip capacitor is not necessarily flat. Moreover, there are various sizes and shapes of passive elements, and when a semiconductor chip is diced on the passive elements, the surface of the semiconductor chip may not be parallel to the surface of the wiring board. Further, in places where passive elements smaller than the surrounding passive elements are disposed, a gap may be formed between the wiring board and the semiconductor chip, that is, the semiconductor chip may be in a floating state.

  When the semiconductor chip is not mounted in parallel to the wiring board, when wire bonding is performed between the wiring board and the semiconductor chip, the force is not properly transmitted from the capillary, and the electrode pad of the semiconductor chip and the bonding wire are not connected. Connectivity may be degraded.

  However, according to the example shown in FIG. 14 or FIG. 15, since the semiconductor chip 27 is placed on the flat die attach resin 55, the surface of the semiconductor chip 27 and the surface of the wiring substrate 25 are parallel to each other. can do. Accordingly, when wire bonding is performed between the electrode pad 57 of the wiring board 25 and the electrode pad of the semiconductor chip 27, the force from the capillary is appropriately transmitted, and the electrode pad of the semiconductor chip 27 and the electrode pad 57 of the wiring board 25 are The connection by the bonding wire can be reliably performed with high reliability.

  In the example shown in FIG. 15, a pressing method using a jig 53 is used to flatten the surface of the die attach resin 55. However, the present invention is not limited to this. For example, a screen printing method may be applied to form a resin layer having a thickness that covers the passive element 51. According to such a screen printing method, a resin layer having a flat surface can be formed.

  As will be described later, each member and die attach resin 55 disposed on the wiring board 25 are finally sealed with a sealing resin. Accordingly, by making the thermal expansion coefficient of the die attach resin 55 substantially the same as the thermal expansion coefficient of the sealing resin, it is possible to reduce the occurrence of stress based on the difference between the two thermal expansion coefficients.

  As described above, in the example shown in FIGS. 14 and 15, the die attach resin 55 is formed so as to cover the passive element 51 disposed on the wiring substrate 25, and then the semiconductor chip 27 ( The die attach resin 55 is pressurized using a jig 53 (see FIG. 14) or the jig 53 (see FIG. 15), and the surface of the die attach resin 55 is flattened. At this time, due to the pressurization, the die attach resin 55 may flow out to the electrode pad 57 portion of the wiring board 25, which may hinder wire bonding between the wiring board 25 and the semiconductor chip 27.

  Therefore, in order to prevent this, the structure shown in FIG. 16 may be adopted. Here, FIG. 16 is an enlarged view of a portion surrounded by a dotted line in FIG. 14 or FIG. In the example shown in FIG. 16- (A), in the wiring board 25, a groove portion is formed in the vicinity of the electrode pad 57 and on the inner side (center side of the wiring board 25) than the position where the electrode pad 57 is disposed. 58 is provided. In the example shown in FIG. 16- (B), in the wiring board 25, the wiring board is in the vicinity of the electrode pad 57 and inside the position where the electrode pad 57 is provided (center side of the wiring board 25). A dam portion 59 is provided at 25 portion.

  By disposing the groove 58 or the dam 59, it is possible to prevent the die attach resin 55 from flowing out to the electrode pad 57 portion of the wiring substrate 25. The die attach resin 55 is connected to the wiring substrate 25 and the semiconductor chip. It is possible to avoid obstructing wire bonding with the terminal 27.

  In the example shown in FIG. 14 or FIG. 15, the passive element 51 is arranged in a region below the portion where the semiconductor chip 27 is located on the wiring substrate 25, that is, in a region overlapping the semiconductor chip 27 in plan view. It is installed. Therefore, the required area of the wiring board 25 can be reduced, and the semiconductor device can be reduced in size. Further, compared to the conventional structure shown in FIGS. 1 and 2, the wiring length between the semiconductor chip 27 and the passive element 51 can be shortened, and mixing of external noise can be reduced more effectively.

  Next, a third embodiment of the semiconductor device of the present invention will be described with reference to FIGS. FIG. 17 is a view for explaining a first example of the third embodiment of the semiconductor device of the present invention, and FIGS. 17- (A) and 17- (B) are sectional views. 17- (C) is a plan view of FIG. 17- (B). FIG. 18 is a view for explaining a second example of the third embodiment of the semiconductor device according to the present invention together with the manufacturing process, and FIGS. 18-A and 18-B are cross-sectional views. FIG. 18- (C) is a plan view of FIG. 18- (B).

  Referring to FIG. 17- (A), the wiring board 60 is provided with a cavity 61 on one main surface thereof. The depth of the cavity 61 (the length in the vertical direction in FIG. 17A) is deeper than the height of the passive element 51.

  Further, as shown in FIG. 17C, the opening area of the cavity 61 when viewed in plan is smaller than the area of the main surface of the semiconductor chip 27. More specifically, the opening of the cavity portion 61 when seen in a plan view is located on the inner side (center side) where the electrode pad 70 formed on the semiconductor chip 27 is located, and the area thereof is the semiconductor chip 27. It is formed smaller than.

  The passive element 51 is mounted and fixed on the bottom main surface in the cavity 61.

  A die collet that fills the cavity part 61 with an insulating (die attach) resin 65 having an insulating property, such as an epoxy resin, that is larger than the capacity of the cavity part 61, and then holds the semiconductor chip 27 by suction. 30, the surface to be bonded of the semiconductor chip 27 is pressed against the surface of the die attach resin 65, that is, pressed from above, to flatten the surface of the die attach resin 65 and to attach the semiconductor chip 27 to the die attach. The resin 65 is fixed to the wiring substrate 60.

  Therefore, the surface of the semiconductor chip 27 and the surface of the wiring board 60 are substantially parallel, and when the wire bonding is performed between the electrode pad of the wiring board 60 and the electrode pad 70 of the semiconductor chip 27, a force from the capillary is generated. Properly transmitted, the connection by the bonding wire between the electrode pad of the semiconductor chip and the electrode pad of the wiring board can be reliably performed with high reliability.

  When the electrode pads of the semiconductor chip 27 and the electrode pads of the wiring substrate 60 are connected by the bonding wires 28, the states shown in FIGS. 17- (B) and 17- (C) are obtained.

  As described above, the cavity 61 when viewed in plan is smaller in area than the semiconductor chip 27 on the inner side (center side) than the position where the electrode pad 70 formed on the semiconductor chip 27 is located. Thus, when the wiring board 60 and the semiconductor chip 27 are wire-bonded, the heat conduction from the wiring board 60 is improved, and the bonding property is improved.

  As described above, the surface of the die attach resin 65 accommodated and disposed in the cavity forming portion 61 is pressurized from above by the semiconductor chip 27 adsorbed and held on the die collet 30, so that the surface of the die attach resin 65 is pressed. The die attach resin 65 may flow out to the bonding pad portion formed on the wiring board 60 due to the pressurization. Therefore, in order to prevent this, the groove 58 shown in FIG. 16- (A) or the dam shown in FIG. 16- (B) is formed around the cavity 61 of the wiring board 60 as in the above embodiment. A portion 59 may be provided.

  In the example shown in FIG. 17, an electrode pad (not shown) on the wiring board 60 and the electrode pad 70 of the semiconductor chip 27 are connected by a wire bonding method, but instead of wire bonding, As shown in FIG. 18, the semiconductor chip 27 may be connected to the electrode pads on the wiring board 60 by a flip chip bonding method.

  Referring to FIG. 18- (A), the wiring board 60 is provided with a cavity forming portion 61 as in the example shown in FIG. The depth of the cavity forming portion 61 (the length in the vertical direction in FIG. 17A) is deeper than the height of the passive element 51.

  Further, as shown in FIG. 18C, the opening area of the cavity 61 when viewed in plan is smaller than the area of the main surface of the semiconductor chip 27.

  The passive element 51 is mounted and fixed on the bottom main surface of the cavity portion 61.

  An amount of die attach resin 65 larger than the volume of the cavity portion 61 is filled in the cavity portion 61, and the semiconductor chip 27 is attached to the die attach resin 65 by a known flip chip tool 75 provided with the semiconductor chip 27. Flip chip bonding is performed from above.

  In the present embodiment, the passive element 51 is provided in a region below the portion where the semiconductor chip 27 is located, that is, in a region overlapping the semiconductor chip 27 in plan view. The mounting area can be reduced and the size of the semiconductor device can be reduced. Further, compared to the conventional structure shown in FIGS. 1 and 2, the wiring length between the semiconductor chip 27 and the passive element 51 can be shortened, and mixing of external noise can be reduced more effectively.

[Embodiment of Semiconductor Device Manufacturing Method]
Next, an embodiment of a method for manufacturing a semiconductor device of the present invention will be described.

  First, a method for manufacturing the semiconductor device 20 (see FIG. 5 and the like) according to the first embodiment of the semiconductor device of the present invention will be described with reference to FIGS. 19 and 20 are process cross-sectional views for explaining a method of manufacturing the semiconductor device 20 (see FIG. 5 and the like) according to the first embodiment of the semiconductor device of the present invention. The manufacturing process shown here shows a process in which a large-sized wiring board is applied, a plurality of semiconductor devices are collectively formed on the wiring board, and the individual semiconductor devices are separated after resin coating. . In the illustrated process, three semiconductor devices are formed on a large wiring board.

  Referring to FIGS. 19 and 20, in manufacturing the semiconductor device 20 according to the first embodiment of the semiconductor device of the present invention shown in FIG. 5, first, the semiconductor device 20 is arranged on the wiring substrate 25. A solder paste 81 is applied and formed on the electrode pad 80 (FIG. 19- (A)). In this case, the material applied to the electrode pad 80 may be a conductive adhesive, and may be formed by a printing method or a dispensing method in addition to a coating method.

  Next, the first passive element 23 and the second passive element 24 are mounted on the electrode pad 80 to which the solder paste 81 is applied, and the solder is collectively reflowed and cured to be cured. And the electrode of the 2nd passive element 24 is fixed to the electrode pad 80 (FIG. 19- (B)).

  As described above, the first passive element 23 has a larger outer dimension than the second passive element 24, and the plurality of first passive elements 23 have the same outer dimension.

  The plurality of first passive elements 23-1, 23-2, etc., correspond to the region where the semiconductor chip 27 is arranged, at the corner of the semiconductor chip and / or each side of the semiconductor chip. Correspondingly, they are arranged separately. On the other hand, the second passive elements 24-1 to 24-3 and the like are arranged directly below the semiconductor chip 27 and separated from the first passive elements.

  Next, the semiconductor chip 27 having the die bonding film 29 attached to the back surface (non-formation surface of the electronic circuit element / electronic circuit) is mounted on the first passive element 23 using the die bonding film 29. It adheres (FIG. 19- (C)).

  At this time, since the heights of the plurality of first passive elements 23 are equal, the semiconductor chip 27 is supported by the first passive elements 23-1 to 23-4 so as to be substantially parallel to the wiring board 25. The On the other hand, a gap is formed between the semiconductor chip 27 and the second passive element 24.

  Next, the electrode pads of the semiconductor chip 27 and the electrode pads of the wiring board 25 are wire-bonded and connected using the bonding wires 28 (FIG. 19- (D)).

  Next, the first passive element 23 and the second passive element 24, the semiconductor chip 27, the bonding wire 28, and the like are sealed with a sealing resin 26 (FIG. 20- (E)).

  At this time, a plurality of semiconductor chips, passive elements, bonding wires and the like mounted and fixed on the wiring board 25 are collectively sealed with resin.

  In the resin sealing, as described with reference to FIGS. 9 and 10, the orientation of the passive elements 23-1 to 23-2 and 24-1 to 24-3 is determined by the sealing resin. Therefore, the sealing resin 26 easily flows between the passive elements 23-1 to 23-2 and 24-1 to 24-3. Therefore, the generation of voids in the sealing resin 26 is reliably prevented.

  The sealing resin 26 is not only above the semiconductor chip 27 but also below the semiconductor chip 27. The first passive elements 23-1 to 23-2 and the second passive elements 24-1 to 24 are disposed below the semiconductor chip 27. -3, the semiconductor chip 27 has a structure in which the upper surface and the lower surface of the semiconductor chip 27 are covered with the sealing resin 26. Therefore, the semiconductor chip 27 is not easily affected by the generation of stress due to the difference in thermal expansion coefficient between the upper surface and the lower surface of the semiconductor chip 27, and the highly reliable semiconductor device 20 can be obtained.

Thereafter, a plurality of solder balls 22 functioning as external connection terminals are formed on the other main surface of the wiring board 25 (FIG. 20- (F)).
Thereafter, the semiconductor chip 27 on one main surface of the wiring board 25 and the wiring board 25 and sealed with a sealing resin 26 and the passive elements 23 and 24 electrically connected to the semiconductor element 27. In addition, the bonding wire 28 and the like as one unit are separated into pieces by dicing using a dicing saw or the like to form individual semiconductor devices 20 (FIG. 20- (G)).

  Next, a method for manufacturing a semiconductor device (see FIG. 14 or FIG. 15 etc.) according to the second embodiment of the semiconductor device of the present invention will be described with reference to FIGS. 21 and 22 are process cross-sectional views for explaining a method for manufacturing a semiconductor device (see FIG. 14 or FIG. 15) according to the second embodiment of the semiconductor device of the present invention. Even in the manufacturing process shown here, a process is shown in which a large-sized wiring board is applied, a plurality of semiconductor devices are collectively formed on the wiring board, and the individual semiconductor devices are separated after resin coating. . In the illustrated process, three semiconductor devices are formed on a large wiring board.

  Referring to FIGS. 21 and 22, even in the manufacture of the semiconductor device according to the second embodiment of the semiconductor device of the present invention, first, a solder paste is applied to the electrode pad 80 arranged on the wiring board 25. 81 is applied and formed (FIG. 21- (A)). In this case, the material applied to the electrode pad 80 may be a conductive adhesive, and may be formed by a printing method, a dispensing method, or the like in addition to the coating method.

  Next, the passive element 51 is mounted on the soldering pad 80 to which the solder paste 81 is applied, the solder is collectively reflowed and cured, and the electrode of the passive element 51 is fixed to the electrode pad 80 (FIG. 21). -(B)).

  Next, an insulating semiconductor element fixing (die attach) resin 55 such as an epoxy resin is coated so as to cover the passive element 51 disposed on the wiring board 25 (FIG. 21- (C)). As will be described later, each member and die attach resin 55 finally disposed on the wiring board 25 are sealed with a sealing resin 26. Thus, by making the thermal expansion coefficient of the die attach resin 55 substantially the same as the thermal expansion coefficient of the sealing resin, it is possible to reduce the occurrence of stress based on the difference between the two thermal expansion coefficients.

  Next, the semiconductor chip 27 is mounted and fixed on the passive element 51 using the die attach resin 55 (FIG. 21- (D)). At this time, as described with reference to FIG. 14, the semiconductor chip 27 may flatten the surface of the die attach resin 55 using the die collet 30, and the semiconductor chip 27 may be diced on the surface. Alternatively, as described with reference to FIG. 15, after the surface of the die attach resin 55 is flattened using the jig 53, the semiconductor chip 27 may be diced on the flattened resin surface. .

  In any case, the semiconductor chip 27 can be mounted on the wiring substrate 25 via the die attach resin 55 so that the lower surface of the semiconductor chip 27 and the surface of the wiring substrate 25 are parallel to each other by a simple process. it can. By mounting the semiconductor chip 27 so as to be parallel to the wiring substrate 25, when wire bonding is performed between the wiring substrate 25 and the semiconductor chip 27, which will be described later, the force from the bonding capillary is appropriately transmitted, and the semiconductor chip The connection by the bonding wire between 27 electrode pads and the electrode pad on the wiring board 25 can be reliably performed with high reliability.

  It should be noted that the amount of die attach resin 55 and the amount of die attach resin 55 and the amount of die attach resin 55 are such that no void is generated in the die attach resin 55 disposed between the wiring substrate 25, the passive element 51, and the semiconductor chip 27. The pressurizing force when mounting 27 is appropriately set. Further, as described with reference to FIG. 16, the wiring board 25 is provided with the groove 58 or the dam part 59, and the die attach resin 55 flows out onto the bonding pad disposed on the surface of the wiring board 25. To prevent.

  Next, the electrodes of the semiconductor chip 27 and the bonding pads disposed on the surface of the wiring board 25 are connected using the bonding wires 28, and both are electrically connected (FIG. 21- (E)). Next, the passive element 51, the semiconductor chip 27, the bonding wire 28, and the like are sealed with a sealing resin 26 such as an epoxy resin (FIG. 22- (F)).

  Next, a plurality of solder balls 22 functioning as external connection terminals are formed on the lower surface (the other main surface) of the wiring board 25 (FIG. 22- (G)).

  Thereafter, a wiring substrate 25, a semiconductor chip 27 on one main surface of the wiring substrate 25 and sealed with a sealing resin 26, a passive element 51 electrically connected to the semiconductor element 27, and Using the bonding wire 28 and the like as a unit, the semiconductor device 20 is divided into individual pieces by dicing using a dicing saw to form individual semiconductor devices 20 (FIG. 22- (H)).

  Although the embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes are within the scope of the gist of the present invention described in the claims. It can be changed.

Regarding the above description, the following items are further disclosed.
(Appendix 1)
A semiconductor device having a substrate, a semiconductor element disposed on one main surface of the substrate, and a plurality of passive elements,
The plurality of passive elements include a plurality of first passive elements having a first height, and a plurality of second passive elements having a second height lower than the first passive element. Including
The semiconductor device is supported on the plurality of first passive elements, and an electrode of the semiconductor element and an electrode of the substrate are wire-connected.
(Appendix 2)
The plurality of passive elements provided between the semiconductor element and the substrate are sealed with a sealing resin made of the same material as the sealing resin provided above the semiconductor element. The semiconductor device according to appendix 1.
(Appendix 3)
The semiconductor device according to claim 2, wherein the passive element is provided so that a longitudinal direction of the passive element is substantially parallel to an inflow direction of the sealing resin.
(Appendix 4)
4. The semiconductor device according to claim 1, wherein the first passive element is provided in a portion corresponding to four corners of the main surface of the semiconductor element having a substantially rectangular shape on the substrate. .
(Appendix 5)
The semiconductor device according to any one of appendices 1 to 4, wherein the passive elements are provided at substantially equal intervals.
(Appendix 6)
Note that a dummy element having substantially the same thermal expansion coefficient as that of the passive element is provided between the semiconductor element and the substrate in a region overlapping the main surface of the semiconductor element of the substrate. The semiconductor device according to any one of 1 to 5.
(Appendix 7)
A semiconductor device comprising a substrate, a semiconductor element provided above the substrate, and a plurality of passive elements provided on the substrate,
The passive element is sealed with resin;
The semiconductor device is mounted on the resin substantially parallel to the substrate.
(Appendix 8)
The semiconductor device according to appendix 7, wherein the resin has the same thermal expansion coefficient as that of a sealing resin provided above the semiconductor chip.
(Appendix 9)
A groove portion is provided in the vicinity of the bonding pad provided on the substrate and at a position of the substrate located on the center side of the substrate from the position where the bonding pad is provided. The semiconductor device according to appendix 7 or 8.
(Appendix 10)
A dam portion is provided in the vicinity of the bonding pad provided on the substrate and at a position of the substrate located on the center side of the substrate from the position where the bonding pad is provided. The semiconductor device according to appendix 7 or 8,
(Appendix 11)
The semiconductor device according to claim 7, wherein the substrate has a cavity forming portion, and the passive element is mounted on a main surface of the cavity forming portion.
(Appendix 12)
Mounting a plurality of first passive elements and a plurality of second passive elements having a height lower than the height of the first passive elements on a substrate;
Mounting a semiconductor element with an adhesive film on the back surface on the upper surface of the first passive element;
Connecting the electrode of the semiconductor element and the electrode of the substrate with a wire;
A method of manufacturing a semiconductor device, comprising: sealing the semiconductor element, the passive element, and the wire with resin.
(Appendix 13)
Mounting a plurality of passive elements on a substrate;
Disposing a resin on the substrate so as to cover the passive element;
Mounting a semiconductor element on the resin;
Connecting the electrode of the semiconductor element and the electrode of the substrate with a wire;
A method of manufacturing a semiconductor device, comprising: sealing the semiconductor element, the passive element, and the wire with resin.

It is a figure which shows the structure of the electronic component carrying the conventional semiconductor device. It is a figure which shows the structure (the 1) of the conventional semiconductor device. It is sectional drawing which shows the structure (the 2) of the conventional semiconductor device. It is a fragmentary sectional view of the conventional semiconductor device which shows one of the problems of a prior art. 1 is a diagram showing a first embodiment of a semiconductor device of the present invention. It is FIG. (1) for demonstrating the modification of arrangement | positioning of a 1st passive element. It is FIG. (2) for demonstrating the modification of arrangement | positioning of a 1st passive element. It is a top view of the wiring board for demonstrating the arrangement structure of a 2nd passive element. It is FIG. (1) for demonstrating the relationship between arrangement | positioning of a passive element, and inflow of sealing resin. It is FIG. (2) for demonstrating the relationship between arrangement | positioning of a passive element, and inflow of sealing resin. It is the top view which showed the modification (the 1) of 1st Embodiment of the semiconductor device of this invention. It is the top view which showed the modification (the 2) of 1st Embodiment of the semiconductor device of this invention. It is a figure for demonstrating the modification (the 3) of 1st Embodiment of the semiconductor device of this invention. It is sectional drawing for demonstrating the 1st example of 2nd Embodiment of the semiconductor device of this invention. It is sectional drawing for demonstrating the 2nd example of 2nd Embodiment of the semiconductor device of this invention. It is a figure for demonstrating the structure for preventing the outflow of resin. It is a figure for demonstrating the 1st example of 3rd Embodiment of the semiconductor device of this invention. It is a figure for demonstrating the 2nd example of 3rd Embodiment of the semiconductor device of this invention. FIG. 3 is a first view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the semiconductor device of the present invention; FIG. 3 is a second view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the semiconductor device of the present invention; It is FIG. 1 for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of the semiconductor device of this invention. It is FIG. 2 for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of the semiconductor device of this invention.

Explanation of symbols

20 Semiconductor devices 23-1 to 23-4 First passive elements 24-1 to 24-12 Second passive elements 25, 60 Wiring substrate 27 Semiconductor chip 29 Adhesive film 55, 65 Die attach resin 61 Cavity forming part

Claims (3)

A semiconductor device comprising a substrate, a semiconductor element provided above the substrate, and a plurality of passive elements provided on the substrate,
The passive element is sealed with resin;
The semiconductor device is mounted on the resin substantially parallel to the substrate.   The semiconductor device according to claim 1, wherein the substrate has a cavity forming portion, and the passive element is mounted on a main surface of the cavity forming portion. Mounting a plurality of passive elements on a substrate;
Disposing a resin on the substrate so as to cover the passive element;
Mounting a semiconductor element on the resin;
Connecting the electrode of the semiconductor element and the electrode of the substrate with a wire;
A method of manufacturing a semiconductor device, comprising: sealing the semiconductor element, the passive element, and the wire with resin.

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