JP4435187B2 - Multilayer semiconductor device - Google Patents

Multilayer semiconductor device Download PDF

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JP4435187B2
JP4435187B2 JP2007025544A JP2007025544A JP4435187B2 JP 4435187 B2 JP4435187 B2 JP 4435187B2 JP 2007025544 A JP2007025544 A JP 2007025544A JP 2007025544 A JP2007025544 A JP 2007025544A JP 4435187 B2 JP4435187 B2 JP 4435187B2
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semiconductor element
region
connection
semiconductor device
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JP2008192815A (en
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昌利 福田
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Toshiba Corp
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は複数の半導体素子を積層した積層型半導体装置に関する。   The present invention relates to a stacked semiconductor device in which a plurality of semiconductor elements are stacked.

半導体装置の小型化や高機能化等を実現するために、１つのパッケージ内に複数の半導体素子を積層して封止したパッケージ構造（ＣＯＣ（Ｃｈｉｐ ｏｎ Ｃｈｉｐ）構造）が実用化されている。ＣＯＣパッケージはメモリ素子とプロセッサ素子とを積層した構造にも応用されており、ＳＩＰ（Ｓｙｓｔｅｍ ｉｎ Ｐａｃｋａｇｅ）型の半導体装置として実用化が進められている。ＣＯＣパッケージでＳＩＰを構成する場合、上下の半導体素子間の接続にはフリップチップ接続の適用が検討されている（特許文献１参照）。   In order to realize miniaturization and high functionality of a semiconductor device, a package structure (COC (Chip on Chip) structure) in which a plurality of semiconductor elements are stacked and sealed in one package has been put into practical use. The COC package is also applied to a structure in which a memory element and a processor element are stacked, and is practically used as a SIP (System in Package) type semiconductor device. When a SIP is configured with a COC package, application of flip-chip connection is being studied for connection between upper and lower semiconductor elements (see Patent Document 1).

ＣＯＣパッケージの素子間接続にフリップチップ接続を適用する場合には、まず外部接続端子等を有する配線基板上に第１の半導体素子（下段側半導体素子）を搭載する。次いで、第２の半導体素子（上段側半導体素子）を第１の半導体素子に対してフリップチップ接続する。すなわち、第１の半導体素子の上面に設けられたバンプ電極と第２の半導体素子の下面に設けられたバンプ電極とを接続することによって、素子間を電気的および機械的に接続する。さらに、上下の半導体素子間の隙間には、接続信頼性等を高めるためにアンダーフィル樹脂が充填される。   When flip-chip connection is applied to the connection between elements of the COC package, first, a first semiconductor element (lower semiconductor element) is mounted on a wiring board having external connection terminals and the like. Next, the second semiconductor element (upper stage side semiconductor element) is flip-chip connected to the first semiconductor element. That is, by connecting the bump electrode provided on the upper surface of the first semiconductor element and the bump electrode provided on the lower surface of the second semiconductor element, the elements are electrically and mechanically connected. Further, the gap between the upper and lower semiconductor elements is filled with an underfill resin in order to improve connection reliability and the like.

フリップチップ接続を適用した場合のバンプ電極による接続体の高さ、すなわち上下の半導体素子間の隙間は一般的に４０μｍ以下程度であり、１５〜３０μｍ程度であることが多い。このような隙間に液状のアンダーフィル樹脂を充填する場合、バンプ電極の有無によりアンダーフィル樹脂の充填速度に差が生じることによって、ボイドが発生しやすいという問題がある。すなわち、バンプ電極は第２の半導体素子の形状に対応する隙間領域の内側に設定された設定された接続領域に形成される。従って、隙間領域内の接続領域より外側の領域には樹脂流動時の抵抗となるものが存在しない。   When the flip chip connection is applied, the height of the connection body by the bump electrode, that is, the gap between the upper and lower semiconductor elements is generally about 40 μm or less, and often about 15 to 30 μm. When such a gap is filled with a liquid underfill resin, there is a problem that voids are likely to occur due to a difference in the filling rate of the underfill resin depending on the presence or absence of bump electrodes. That is, the bump electrode is formed in the set connection region set inside the gap region corresponding to the shape of the second semiconductor element. Accordingly, there is no resistance in the resin flow in the region outside the connection region in the gap region.

このような隙間に液状のアンダーフィル樹脂を充填すると、バンプ電極が存在する部分（接続領域内）とバンプ電極が存在しない部分（接続領域より外側の領域）との間で樹脂の充填速度に差が生じる。バンプ電極が存在しない部分では、樹脂流動時の抵抗となるものが存在しないために充填速度が速くなる。このため、バンプ電極が存在する接続領域の外側からの樹脂の回り込みが早くなり、遅延して樹脂が流れる接続領域を巻き込む形となる。その結果、接続領域に巻き込みボイドが発生しやすくなる。   If liquid underfill resin is filled in such a gap, there is a difference in the resin filling speed between the portion where the bump electrode exists (in the connection region) and the portion where the bump electrode does not exist (the region outside the connection region). Occurs. In the portion where no bump electrode is present, the filling speed is increased because there is no resistance that acts when the resin flows. For this reason, the wraparound of the resin from the outside of the connection region where the bump electrode is present is accelerated, and the connection region where the resin flows with a delay is involved. As a result, entrainment voids are likely to occur in the connection region.

アンダーフィル樹脂に生じたボイドは樹脂剥離の起点となったり、またボイド内のバンプ電極は溶融してショートしやすいことから、素子間接続にフリップチップ接続を適用したＣＯＣパッケージ（積層型半導体装置）の信頼性や製造歩留り等を低下させる要因となっている。さらに、アンダーフィル樹脂の充填速度差に基づいて、隙間の外側へのアンダーフィル樹脂のはみ出し量が多くなりやすい。第１の半導体素子と配線基板との接続にワイヤボンディングを適用した場合、はみ出し量が多いとアンダーフィル樹脂がボンディングパッド上まで広がり、ボンディング不良が発生するおそれもある。   The void generated in the underfill resin becomes the starting point of resin peeling, and the bump electrode in the void is easily melted and short-circuited. Therefore, a COC package (laminated semiconductor device) using flip-chip connection for inter-element connection This is a factor that lowers the reliability and manufacturing yield. Furthermore, the amount of the underfill resin protruding to the outside of the gap tends to increase based on the difference in filling speed of the underfill resin. When wire bonding is applied to the connection between the first semiconductor element and the wiring board, if the amount of protrusion is large, the underfill resin spreads over the bonding pad, which may cause bonding failure.

なお、特許文献１には積層する半導体素子のバンプ電極の周囲に補強用バンプを設けることが記載されている。補強用バンプは上下の半導体素子の対向面にそれぞれ設けられており、これらはバンプ電極同士の当接と同時に当接される。ここでは半導体素子間に配置される樹脂を、予め上段側半導体素子の電極形成面に供給しており、余剰の樹脂を樹脂流動通路で外部に排出している。特許文献１ではバンプ接続後にアンダーフィル樹脂を充填しておらず、アンダーフィル樹脂の充填速度差については何等考慮されていない。
特開２００６−０２４７５２号公報 Patent Document 1 describes that reinforcing bumps are provided around bump electrodes of semiconductor elements to be stacked. Reinforcing bumps are provided on the opposing surfaces of the upper and lower semiconductor elements, respectively, which are in contact with the bump electrodes at the same time. Here, the resin disposed between the semiconductor elements is supplied in advance to the electrode forming surface of the upper semiconductor element, and excess resin is discharged to the outside through the resin flow passage. In Patent Document 1, underfill resin is not filled after bump connection, and no consideration is given to the difference in filling speed of the underfill resin.
JP 2006-024752 A

本発明の目的は、積層する半導体素子間の接続にフリップチップ接続を適用するにあたって、素子間の隙間への樹脂の充填性を高めることによって、接続信頼性や製造歩留り等の向上を図った積層型半導体装置を提供することにある。   An object of the present invention is to improve the connection reliability, the manufacturing yield, and the like by improving the resin filling property in the gap between the elements when applying the flip chip connection to the connection between the semiconductor elements to be stacked. It is to provide a type semiconductor device.

本発明の態様に係る積層型半導体装置は、素子搭載部と接続部とを有する配線基板と、前記接続部と電気的に接続された電極部と、素子積層領域と、前記素子積層領域の内側に設定された第１の接続領域とを有し、前記配線基板の素子搭載部に搭載された第１の半導体素子と、前記第１の半導体素子の素子積層領域上に積層され、かつ前記第１の接続領域と対応するように前記第１の半導体素子と対向する面に設定された第２の接続領域を有する第２の半導体素子と、前記第１の接続領域および前記第２の接続領域の少なくとも一方に設けられたバンプ電極を有し、前記第１の半導体素子と前記第２の半導体素子との間の隙間の間隔が１５μｍ以上４０μｍ以下となるように、前記第１の半導体素子と前記第２の半導体素子とを接続するバンプ接続部と、前記第１の半導体素子と前記第２の半導体素子との対向面の少なくとも一方から他方に向けて突出させると共に、前記第１の半導体素子と前記第２の半導体素子との間の隙間の高さ方向の一部を少なくとも占有するように設けられ、前記第１および第２の接続領域より外側の領域に配置された突起を有する空隙調整部と、前記第１の半導体素子と前記第２の半導体素子との間の隙間に充填された樹脂とを具備することを特徴としている。 A stacked semiconductor device according to an aspect of the present invention includes a wiring board having an element mounting portion and a connection portion, an electrode portion electrically connected to the connection portion, an element stack region, and an inner side of the element stack region. A first connection region set on the wiring substrate, stacked on the device stacking region of the first semiconductor device, and stacked on the device stacking region of the first semiconductor device, A second semiconductor element having a second connection region set on a surface facing the first semiconductor element so as to correspond to the first connection region; the first connection region; and the second connection region A bump electrode provided on at least one of the first semiconductor element and the first semiconductor element so that a gap between the first semiconductor element and the second semiconductor element is 15 μm or more and 40 μm or less. Bump for connecting to the second semiconductor element The connecting portion and at least one of the facing surfaces of the first semiconductor element and the second semiconductor element protrude from the other side toward the other, and between the first semiconductor element and the second semiconductor element A gap adjusting portion provided so as to occupy at least a part in the height direction of the gap and having a protrusion disposed in a region outside the first and second connection regions; the first semiconductor element; And a resin filled in a gap between the second semiconductor element and the second semiconductor element.

本発明の態様に係る積層型半導体装置によれば、第１の半導体素子と第２の半導体素子との隙間に樹脂を充填する際の充填速度差が空隙調整部により緩和される。このため、樹脂の充填性を高めてボイドの発生を抑制することができる。従って、信頼性や製造歩留り等の向上を図った積層型半導体装置を提供することが可能となる。   According to the stacked semiconductor device according to the aspect of the present invention, the gap adjusting portion relieves the filling speed difference when filling the gap between the first semiconductor element and the second semiconductor element with the resin. For this reason, the filling property of resin can be improved and generation | occurrence | production of a void can be suppressed. Therefore, it is possible to provide a stacked semiconductor device with improved reliability and manufacturing yield.

以下、本発明を実施するための形態について、図面を参照して説明する。図１、図２および図３は本発明の第１の実施形態によるＣＯＣパッケージ構造の積層型半導体装置の構成を示している。これらの図に示す積層型半導体装置１は、素子搭載用の配線基板２を有している。配線基板２は半導体素子の搭載部と回路部とを有するものであればよく、絶縁基板や半導体基板等の表面や内部に配線網を形成した配線基板２が用いられる。配線基板２を構成する基板には、樹脂基板、セラミックス基板、ガラス基板等の絶縁基板、あるいは半導体基板等、各種の材料からなる基板を適用することができる。   Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. 1, 2 and 3 show the configuration of a stacked semiconductor device having a COC package structure according to the first embodiment of the present invention. The stacked semiconductor device 1 shown in these drawings has a wiring board 2 for mounting elements. The wiring substrate 2 may be any substrate having a semiconductor element mounting portion and a circuit portion, and a wiring substrate 2 having a wiring network formed on the surface or inside of an insulating substrate, a semiconductor substrate, or the like is used. As the substrate constituting the wiring substrate 2, substrates made of various materials such as an insulating substrate such as a resin substrate, a ceramic substrate, and a glass substrate, or a semiconductor substrate can be applied.

例えば、多層プリント配線板（多層銅張積層板）等からなる配線基板（インターポーザ）２の下面側には、半田バンプ等の外部接続端子３が設けられている。配線基板２の上面側には素子搭載部が設けられている。配線基板２の素子搭載部の周囲には、外部接続端子３と配線網（図示せず）を介して電気的に接続された接続パッド４が設けられている。接続パッド４は接続部として機能し、かつワイヤボンディング部となるものである。   For example, external connection terminals 3 such as solder bumps are provided on the lower surface side of a wiring board (interposer) 2 made of a multilayer printed wiring board (multilayer copper-clad laminate) or the like. An element mounting portion is provided on the upper surface side of the wiring board 2. A connection pad 4 electrically connected to the external connection terminal 3 via a wiring network (not shown) is provided around the element mounting portion of the wiring board 2. The connection pad 4 functions as a connection part and becomes a wire bonding part.

配線基板２の素子搭載部には、第１の半導体素子５がダイアタッチ材等の接着剤層６を介して接着されている。第１の半導体素子５の上面の外周側には電極パッド７が設けられている。電極パッド７はボンディングワイヤ８を介して配線基板２の接続パッド４と電気的に接続されている。第１の半導体素子５上には第２の半導体素子９が積層され、これら半導体素子５、９間の接続にはフリップチップ接続が適用される。半導体素子５、６は特に限定されるものではないが、例えば第１および第２の半導体素子５、９の一方がメモリ素子で他方がプロセッサ素子（論理ＬＳＩ）等の組合せが例示される。   The first semiconductor element 5 is bonded to the element mounting portion of the wiring board 2 via an adhesive layer 6 such as a die attach material. An electrode pad 7 is provided on the outer peripheral side of the upper surface of the first semiconductor element 5. The electrode pad 7 is electrically connected to the connection pad 4 of the wiring board 2 through the bonding wire 8. A second semiconductor element 9 is stacked on the first semiconductor element 5, and flip chip connection is applied to the connection between the semiconductor elements 5 and 9. The semiconductor elements 5 and 6 are not particularly limited. For example, one of the first and second semiconductor elements 5 and 9 is a memory element and the other is a combination of a processor element (logic LSI).

第１および第２の半導体素子５、９の対向面には、それぞれバンプ電極が設けられている。これらバンプ電極同士を接続してバンプ接続体１０を形成することによって、第１の半導体素子５と第２の半導体素子９とが接続されている。バンプ接続体１０を形成するバンプ電極は第１および第２の半導体素子５、９の少なくとも一方に形成されていればよいが、両方に形成することが一般的である。第１および第２の半導体素子５、９の両方の対向面にバンプ電極を形成する場合、半田／半田、Ａｕ／半田、半田／Ａｕ等の組合せが適用される。このようなバンプ電極はバンプ接続部を構成するものである。   Bump electrodes are provided on the opposing surfaces of the first and second semiconductor elements 5 and 9, respectively. The first semiconductor element 5 and the second semiconductor element 9 are connected by connecting the bump electrodes to form the bump connector 10. The bump electrode for forming the bump connector 10 may be formed on at least one of the first and second semiconductor elements 5 and 9, but is generally formed on both. When bump electrodes are formed on the opposing surfaces of both the first and second semiconductor elements 5 and 9, a combination of solder / solder, Au / solder, solder / Au, or the like is applied. Such a bump electrode constitutes a bump connection part.

第１の半導体素子５と第２の半導体素子９との間の隙間には、アンダーフィル剤として樹脂１１が充填されている。アンダーフィル樹脂１１には、例えばエポキシ樹脂、アクリル樹脂、シリコーン樹脂、ポリイミド樹脂等が用いられ、例えばシリカ粉末等のフィラーを含むエポキシ樹脂が一般的である。配線基板２上に積層、配置された第１および第２の半導体素子５、９は、例えばエポキシ樹脂のような封止樹脂１２でボンディングワイヤ８等と共に封止されており、これらによって積層型半導体装置１が構成されている。   A gap between the first semiconductor element 5 and the second semiconductor element 9 is filled with a resin 11 as an underfill agent. For the underfill resin 11, for example, an epoxy resin, an acrylic resin, a silicone resin, a polyimide resin, or the like is used. For example, an epoxy resin containing a filler such as silica powder is generally used. The first and second semiconductor elements 5 and 9 stacked and arranged on the wiring substrate 2 are sealed together with the bonding wires 8 and the like with a sealing resin 12 such as an epoxy resin, and thereby a stacked semiconductor. A device 1 is configured.

上述した積層型半導体装置１の構成並びに製造工程の詳細について、図２および図３を参照して説明する。図２は積層型半導体装置１の第１の半導体素子５と第２の半導体素子９との積層部分を拡大して示す平面図、図３は図２のＡ−Ａ線に沿った断面図である。配線基板２上に搭載される第１の半導体素子５の上面（第２の半導体素子９と対向する面）５ａには、第２の半導体素子９の形状に対応する素子積層領域１３が設定されており、この素子積層領域１３上に第２の半導体素子９が積層されている。   The configuration of the stacked semiconductor device 1 and the details of the manufacturing process will be described with reference to FIGS. FIG. 2 is an enlarged plan view showing a stacked portion of the first semiconductor element 5 and the second semiconductor element 9 of the stacked semiconductor device 1, and FIG. 3 is a cross-sectional view taken along the line AA of FIG. is there. On the upper surface (the surface facing the second semiconductor element 9) 5a of the first semiconductor element 5 mounted on the wiring board 2, an element stacking region 13 corresponding to the shape of the second semiconductor element 9 is set. The second semiconductor element 9 is laminated on the element lamination region 13.

第１の半導体素子５の素子積層領域１３の内側には、第１の接続領域１４Ａが設定されている。第１の接続領域１４Ａ内には、バンプ接続体１０を形成する一方のバンプ電極（第１のバンプ電極）が形成されている。一方、第１の半導体素子５上に積層される第２の半導体素子９の下面（第１の半導体素子５と対向する面）９ａには、第１の接続領域１４Ａに対応する部分に第２の接続領域１４Ｂが設定されている。第２の接続領域１４Ｂ内には、バンプ接続体１０を形成する他方のバンプ電極（第２のバンプ電極）が形成されている。これらバンプ電極は熱圧着やリフロー等により接続される。   A first connection region 14 </ b> A is set inside the element stack region 13 of the first semiconductor element 5. One bump electrode (first bump electrode) forming the bump connection body 10 is formed in the first connection region 14A. On the other hand, the second semiconductor element 9 stacked on the first semiconductor element 5 has a lower surface (a surface facing the first semiconductor element 5) 9a in a portion corresponding to the first connection region 14A. The connection area 14B is set. In the second connection region 14B, the other bump electrode (second bump electrode) forming the bump connection body 10 is formed. These bump electrodes are connected by thermocompression bonding or reflow.

第１の半導体素子５のバンプ電極と第２の半導体素子９のバンプ電極とを接続した後、これら半導体素子５、９間の隙間Ｓに液状のアンダーフィル樹脂１１を充填する。隙間Ｓの間隔（バンプ接続体１０の高さ）は１５μｍ以上４０μｍ以下とされており、１５〜３０μｍの範囲であることが一般的である。アンダーフィル樹脂１１の充填は、まず第１の半導体素子５の上面５ａの第２の半導体素子９の一辺に沿った部分に液状樹脂を塗布する。図２において、符号１１ａは液状樹脂の当初の辺状（長尺状）の塗布部を示している。第１の半導体素子５に塗布された液状樹脂１１ａは毛管現象で隙間Ｓ内を流動して充填される。これを熱キュアして熱硬化させることによって、アンダーフィル樹脂１１が形成される。 After connecting the bump electrode of the first semiconductor element 5 and the bump electrode of the second semiconductor element 9, a liquid underfill resin 11 is filled in the gap S between the semiconductor elements 5 and 9. The gap S (the height of the bump connection body 10) is 15 μm or more and 40 μm or less, and is generally in the range of 15 to 30 μm. In filling the underfill resin 11, first, a liquid resin is applied to a portion along one side of the second semiconductor element 9 on the upper surface 5 a of the first semiconductor element 5. In FIG. 2, the code | symbol 11a has shown the application | coating part of the initial side shape (elongate shape) of liquid resin. The liquid resin 11a applied to the first semiconductor element 5 flows and fills the gap S by capillary action. The underfill resin 11 is formed by thermally curing and thermosetting this.

この際、バンプ接続体１０を有する接続領域１４は、第１の半導体素子５の素子積層領域１３と第２の半導体素子９との隙間Ｓに対して部分的に設けられている。従って、このままの状態で液状樹脂１１ａを塗布すると、バンプ接続体１０を有する接続領域１４とその外側の領域（隙間Ｓ内の接続領域１４より外側の非接続領域１５）との間で液状樹脂１１ａの充填速度に差が生じ、その結果としてアンダーフィル樹脂１１にボイド（巻き込みボイド等）が発生しやすくなる。そこで、この実施形態では少なくとも隙間Ｓ内における接続領域１４より外側の非接続領域１５に空隙調整用の突起１６を複数設けている。   At this time, the connection region 14 having the bump connection body 10 is partially provided with respect to the gap S between the element stacked region 13 of the first semiconductor element 5 and the second semiconductor element 9. Accordingly, when the liquid resin 11a is applied in this state, the liquid resin 11a is connected between the connection region 14 having the bump connection body 10 and the outer region (the non-connection region 15 outside the connection region 14 in the gap S). As a result, voids (such as entrainment voids) are likely to occur in the underfill resin 11. Therefore, in this embodiment, a plurality of gap adjustment protrusions 16 are provided at least in the non-connection region 15 outside the connection region 14 in the gap S.

第１の半導体素子５の上面５ａには、第１の接続領域１４Ａより外側に複数の突起（第１の突起）１６Ａが設けられている。第１の突起１６Ａは、素子積層領域１３内の第１の接続領域１４Ａより外側の非接続領域１５から、素子積層領域１３よりさらに外側の外周領域１７にかけて形成されている。第２の半導体素子９の下面９ａにも、第２の接続領域１４Ｂより外側の非接続領域１５に複数の突起（第２の突起）１６Ｂが設けられている。突起１６は第１および第２の半導体素子５、９の対向面５ａ、９ａの一方から他方に向けて突出させると共に、隙間Ｓの高さ方向の一部を占有するように設けられている。これら複数の突起１６は空隙調整部を構成するものである。   On the upper surface 5a of the first semiconductor element 5, a plurality of protrusions (first protrusions) 16A are provided outside the first connection region 14A. The first protrusion 16 </ b> A is formed from the non-connection region 15 outside the first connection region 14 </ b> A in the element stacking region 13 to the outer peripheral region 17 further outside the device stacking region 13. Also on the lower surface 9a of the second semiconductor element 9, a plurality of protrusions (second protrusions) 16B are provided in the non-connection region 15 outside the second connection region 14B. The protrusion 16 is provided so as to protrude from one of the facing surfaces 5a and 9a of the first and second semiconductor elements 5 and 9 toward the other and to occupy a part of the gap S in the height direction. The plurality of protrusions 16 constitute a gap adjusting portion.

このように、隙間Ｓ内の非接続領域１５に配置された突起１６は、液状樹脂１１ａの流動時に抵抗として作用する。従って、バンプ接続体１０を有する接続領域１４とその外側の非接続領域１５との間の流動抵抗の差が小さくなり、隙間Ｓの面内方向における液状樹脂１１ａの流動速度（充填速度）が均一化される方向になる。その結果として、液状樹脂１１ａの流動速度差に基づく巻き込みボイド等の発生を低減することができる。アンダーフィル樹脂１１内のボイド発生を抑制することによって、第１の半導体素子５と第２の半導体素子９との接続信頼性、ひいては積層型半導体装置１の信頼性を向上させることが可能となる。また、ボイド発生に起因する製造歩留りの低下も抑制することができる。   As described above, the protrusion 16 disposed in the non-connection region 15 in the gap S acts as a resistance when the liquid resin 11a flows. Accordingly, the difference in flow resistance between the connection region 14 having the bump connection body 10 and the non-connection region 15 outside thereof is reduced, and the flow rate (filling rate) of the liquid resin 11a in the in-plane direction of the gap S is uniform. It becomes the direction to be. As a result, it is possible to reduce the occurrence of entrainment voids and the like based on the flow rate difference of the liquid resin 11a. By suppressing the generation of voids in the underfill resin 11, it is possible to improve the connection reliability between the first semiconductor element 5 and the second semiconductor element 9 and thus the reliability of the stacked semiconductor device 1. . In addition, it is possible to suppress a decrease in manufacturing yield due to the generation of voids.

さらに、突起１６で液状樹脂１１ａの流動速度差が抑えられことに加えて、液状樹脂１１ａが突起１６と接触することで、アンダーフィル樹脂１１の隙間Ｓからのはみ出し量を低減することができる。アンダーフィル樹脂１１のはみ出し量に関しては、素子積層領域１３より外側の外周領域１７にも突起１６を配置することで、より一層はみ出し量を低減することができる。すなわち、外周領域１７に配置された突起１６は液状樹脂１１ａに対してダムとして機能するため、アンダーフィル樹脂１１のはみ出し量がより一層低減される。これによって、例えば電極パッド７や接続パッド４上まで液状樹脂１１ａが広がることに起因するボンディング不良の発生等を抑制することが可能となる。   Furthermore, in addition to the flow rate difference of the liquid resin 11 a being suppressed by the protrusions 16, the amount of protrusion of the underfill resin 11 from the gaps S can be reduced by the liquid resin 11 a coming into contact with the protrusions 16. Regarding the amount of protrusion of the underfill resin 11, the protrusion amount can be further reduced by disposing the protrusions 16 in the outer peripheral region 17 outside the element lamination region 13. That is, since the protrusion 16 disposed in the outer peripheral region 17 functions as a dam with respect to the liquid resin 11a, the amount of the underfill resin 11 protruding further is further reduced. As a result, for example, it is possible to suppress the occurrence of bonding failure caused by the liquid resin 11a spreading to the electrode pads 7 and the connection pads 4.

液状樹脂１１ａの流動速度差の低減は、アンダーフィル樹脂１１の特性の均一化等に対しても有効に作用する。すなわち、流動速度が小さい部分では液状樹脂１１ａ自体に加えて、液状樹脂１１ａに添加したシリカ粉末等のフィラーも流れにくくなる。このため、アンダーフィル樹脂１１にフィラー含有量が設定量より少ない部分が発生する。シリカ粉末等のフィラーはアンダーフィル樹脂１１の熱膨張係数等を半導体素子５、９に近づけて、熱サイクル等による剥離を抑制するものである。従って、部分的にフィラー含有量が少ないとその部分から剥離等が生じやすくなる。   The reduction in the flow rate difference of the liquid resin 11a effectively acts on the uniformity of the characteristics of the underfill resin 11 and the like. That is, fillers such as silica powder added to the liquid resin 11a are difficult to flow in addition to the liquid resin 11a itself at a portion where the flow rate is low. For this reason, a portion where the filler content is less than the set amount occurs in the underfill resin 11. A filler such as silica powder brings the thermal expansion coefficient of the underfill resin 11 close to the semiconductor elements 5 and 9 and suppresses peeling due to a thermal cycle or the like. Therefore, if the filler content is partially small, peeling or the like is likely to occur from that portion.

このような点に対して、突起１６で液状樹脂１１ａの流動速度差を低減することによって、液状樹脂１１ａ自体の流れに加えて、液状樹脂１１ａに添加されたシリカ粉末等のフィラーも流れも均一化される方向に働く。従って、アンダーフィル樹脂１１内のフィラー含有量が均一化され、アンダーフィル樹脂１１の本来の特性を良好に発揮させることができる。これによって、例えば熱サイクルの付加によるアンダーフィル樹脂１１の剥離、それに伴うバンプ接続部の接続不良等の発生を抑制することが可能となる。   In contrast to this, by reducing the flow rate difference of the liquid resin 11a with the protrusions 16, in addition to the flow of the liquid resin 11a itself, the flow of filler such as silica powder added to the liquid resin 11a is uniform. Work in the direction of Therefore, the filler content in the underfill resin 11 is made uniform, and the original characteristics of the underfill resin 11 can be exhibited well. As a result, for example, it is possible to suppress the peeling of the underfill resin 11 due to the addition of a thermal cycle, the occurrence of a connection failure of the bump connection portion, and the like.

空隙調整部を構成する突起１６は、例えばバンプ電極の形成と同時に電極材料（半田やＡｕ等の金属材料）で形成することができる。また、バンプ電極の形成工程とは別に、樹脂やリソグラフィ工程等で形成してもよい。突起１６の形状は図３等に示すようにバンプ電極と同形状であってもよいし、また図４および図５に示すような土手形状を有していてもよい。さらに、突起１６は第１および第２の半導体素子５、９の対向面５ａ、９ａの少なくとも一方に設けられていればよい。   The protrusion 16 constituting the gap adjusting portion can be formed of, for example, an electrode material (a metal material such as solder or Au) simultaneously with the formation of the bump electrode. In addition to the bump electrode formation process, the bump electrode may be formed by a resin or lithography process. The shape of the protrusion 16 may be the same as the bump electrode as shown in FIG. 3 or the like, or may have a bank shape as shown in FIGS. Furthermore, the protrusion 16 may be provided on at least one of the opposing surfaces 5a and 9a of the first and second semiconductor elements 5 and 9.

図２および図３では第１および第２の半導体素子５、９の対向面５ａ、９ａの両方に突起１６を設けた構造を示したが、例えば図６ないし図９に示すように、第１の半導体素子５の第２の半導体素子９と対向する面（上面）９ａのみに突起１６を配置してもよい。図６および図７に示すように、第１の半導体素子５の上面５ａのみに突起１６を設けた場合、デザインや製造工程をあまり変更することなく、非接続領域１５と外周領域１７の両方に突起１６を配置することができる。従って、製造コストの増加等を抑制した上で、ボイドの抑制効果と樹脂はみ出し量の低減効果を有効に得ることが可能となる。   FIGS. 2 and 3 show the structure in which the protrusions 16 are provided on both the opposing surfaces 5a and 9a of the first and second semiconductor elements 5 and 9. For example, as shown in FIGS. The protrusion 16 may be disposed only on the surface (upper surface) 9 a of the semiconductor element 5 facing the second semiconductor element 9. As shown in FIGS. 6 and 7, when the protrusion 16 is provided only on the upper surface 5 a of the first semiconductor element 5, both the non-connection region 15 and the outer peripheral region 17 can be formed without significantly changing the design and manufacturing process. The protrusion 16 can be arranged. Accordingly, it is possible to effectively obtain the effect of suppressing voids and the effect of reducing the amount of protruding resin while suppressing an increase in manufacturing cost and the like.

第１の半導体素子５の第２の半導体素子９と対向する面（上面）９ａに突起１６を配置する場合、図８および図９に示すように、非接続領域１５のみに突起１６を配置してもよい。この場合にも、上述したようにボイドの抑制効果と樹脂はみ出し量の低減効果を得ることができる。さらに、アンダーフィル樹脂１１の特性の均一化効果等についても同様である。このように、突起１６は少なくとも非接続領域１５に配置されていればよい。第２の半導体素子９の下面９ａのみに突起１６を配置してもよいが、この場合には当然ながら第２の半導体素子９の外側まで突起１６を配置することはできない。   When the protrusion 16 is disposed on the surface (upper surface) 9a of the first semiconductor element 5 facing the second semiconductor element 9, the protrusion 16 is disposed only in the non-connection region 15 as shown in FIGS. May be. Also in this case, as described above, the effect of suppressing voids and the effect of reducing the amount of protruding resin can be obtained. The same applies to the effect of uniformizing the characteristics of the underfill resin 11. As described above, the protrusion 16 may be disposed at least in the non-connection region 15. The protrusions 16 may be disposed only on the lower surface 9 a of the second semiconductor element 9. In this case, however, the protrusions 16 cannot naturally be disposed outside the second semiconductor element 9.

突起１６は上述したように隙間Ｓの高さ方向の一部を占有するように設けられている。すなわち、突起１６は隙間Ｓの間隔より低い高さを有し、かつ第１の突起１６Ａと第２の突起１６Ｂとが当接することがないように配置されている。突起１６Ａ、１６Ｂ同士が当接して接続されてしまうと、液状樹脂１１ａを隙間Ｓ内に充填した際に、バンプ接続体１０を有する接続領域１４からのエアーの抜けが悪くなり、これがボイドの発生原因となるおそれがある。このため、この実施形態では隙間Ｓの間隔より高さが低く、かつ隙間Ｓ内で接続されることがない突起１６を適用している。   As described above, the protrusion 16 is provided so as to occupy a part of the gap S in the height direction. That is, the protrusion 16 has a height lower than the gap S, and is arranged so that the first protrusion 16A and the second protrusion 16B do not contact each other. If the protrusions 16A and 16B are in contact with each other and connected, when the liquid resin 11a is filled in the gap S, the escape of air from the connection region 14 having the bump connection body 10 becomes worse, which causes the generation of voids. May cause this. For this reason, in this embodiment, the projection 16 is applied which is lower than the gap S and is not connected in the gap S.

突起１６の具体的な高さは、突起１６の形成位置や形成密度等にもよるが、隙間Ｓの間隔の５０％以上７５％以下の範囲であることが好ましい。突起１６の高さが隙間Ｓの間隔の５０％未満であると、液状樹脂１１ａに対する流動抵抗として機能が不十分となり、粒度速度差を均一化する効果が低下する。一方、突起１６の高さが隙間Ｓの間隔の７５％を超えると、隙間Ｓに対する占有率が高くなりすぎて、上述したエアーの抜け性の低下によるボイドが発生しやすくなる。   The specific height of the protrusions 16 is preferably in the range of 50% or more and 75% or less of the gap S interval although it depends on the formation position and formation density of the protrusions 16. When the height of the protrusion 16 is less than 50% of the gap S, the function as the flow resistance against the liquid resin 11a becomes insufficient, and the effect of equalizing the particle size rate difference decreases. On the other hand, if the height of the protrusion 16 exceeds 75% of the gap S, the occupation ratio with respect to the gap S becomes too high, and voids due to the above-described decrease in air detachability tend to occur.

次に、本発明の第２の実施形態による積層型半導体装置について、図１０ないし図１３を参照して説明する。図１０は第２の実施形態による積層型半導体装置の第１の半導体素子５と第２の半導体素子９との積層部分を拡大して示す平面図、図１１は図１０のＡ−Ａ線に沿った断面図である。なお、前述した第１の実施形態と同一部分には同一符号を付し、その説明を一部省略する。また、積層型半導体装置の全体構成は第１の実施形態と同様であり、図１の積層型半導体装置１に示した通りである。   Next, a stacked semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 10 is an enlarged plan view showing a stacked portion of the first semiconductor element 5 and the second semiconductor element 9 of the stacked semiconductor device according to the second embodiment, and FIG. 11 is a line AA in FIG. FIG. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is partially omitted. The overall configuration of the stacked semiconductor device is the same as that of the first embodiment, as shown in the stacked semiconductor device 1 of FIG.

図１０および図１１に示す積層型半導体装置において、第２の半導体素子９の下面９ａには液状樹脂１１ａの流動抵抗として作用する突起１６Ｂが形成されている。突起１６Ｂは液状樹脂１１ａの塗布辺となる第２の半導体素子９の一辺に沿った部分の形成体積が第２の半導体素子９の他の辺に沿った部分の形成体積より少なくなるように配置されている。ここで、同一体積の突起１６Ｂを適用する場合には、突起１６Ｂの形成密度に基づいて形成体積を調整する。また、突起１６Ｂの各体積で形成体積を調整してもよい。   In the stacked semiconductor device shown in FIGS. 10 and 11, a protrusion 16 </ b> B that acts as a flow resistance of the liquid resin 11 a is formed on the lower surface 9 a of the second semiconductor element 9. The protrusions 16B are arranged so that the formation volume of a portion along one side of the second semiconductor element 9 serving as the application side of the liquid resin 11a is smaller than the formation volume of a portion along the other side of the second semiconductor element 9. Has been. Here, when applying the protrusions 16B having the same volume, the formation volume is adjusted based on the formation density of the protrusions 16B. Further, the formation volume may be adjusted by each volume of the protrusion 16B.

このような突起１６Ｂの配置を適用することによって、第２の半導体素子９の中央付近に設けられているバンプ接続体１０の周囲に液状樹脂１１ａをより早く到達させることができる。さらに、液状樹脂１１ａの塗布辺となる第２の半導体素子９の一辺に沿った部分は、突起１６Ｂの未形成領域を有することが好ましい。これによって、液状樹脂１１ａの充填速度をより均一化方向にすることができる。この際、液状樹脂１１ａの塗布長さａに対する突起１６Ｂの未形成領域の長さｂの比（ｂ／ａ）を０．５以上とすることが好ましい。なお、ｂ／ａ比が１を超えると突起１６Ｂによる本来の流動抵抗の増加効果が低減するため、ｂ／ａ比は０．５〜１の範囲とすることが好ましい。   By applying such an arrangement of the protrusions 16 </ b> B, the liquid resin 11 a can reach the periphery of the bump connection body 10 provided near the center of the second semiconductor element 9 earlier. Furthermore, it is preferable that a portion along one side of the second semiconductor element 9 serving as the application side of the liquid resin 11a has a region where the protrusion 16B is not formed. Thereby, the filling speed of the liquid resin 11a can be made more uniform. At this time, the ratio (b / a) of the length b of the unformed region of the protrusion 16B to the application length a of the liquid resin 11a is preferably 0.5 or more. If the b / a ratio exceeds 1, the effect of increasing the inherent flow resistance by the protrusions 16B is reduced, so the b / a ratio is preferably in the range of 0.5-1.

上述したように、突起１６Ｂの配置（形成密度）を調整することによって、バンプ接続体１０の周囲に発生するボイドをより有効に抑制することが可能となる。図１０および図１１では突起１６Ｂを第２の半導体素子９の下面９ａに設けているが、図８および図９に示すように第１の半導体素子５の上面５ａに設ける突起１６Ａでも同様な配置を適用することができる。図８および図９において、突起１６Ａは液状樹脂１１ａの塗布辺に沿った部分の形成体積が他の辺に沿った部分の形成体積より少なくなるように配置されており、さらに塗布辺に沿って未形成領域を有している。   As described above, by adjusting the arrangement (formation density) of the protrusions 16B, voids generated around the bump connector 10 can be more effectively suppressed. 10 and 11, the protrusion 16B is provided on the lower surface 9a of the second semiconductor element 9. However, the protrusion 16A provided on the upper surface 5a of the first semiconductor element 5 has the same arrangement as shown in FIGS. Can be applied. 8 and 9, the protrusion 16A is arranged so that the formation volume of the portion along the application side of the liquid resin 11a is smaller than the formation volume of the portion along the other side, and further along the application side. Has an unformed region.

さらに、図１２および図１３に示すように、第２の半導体素子９の面内に接続領域１４Ｂが複数設定されていると共に、これら接続領域１４Ｂ間にバンプ接続体１０を有しない領域１８が存在している場合には、各接続領域１４Ｂに対応させて突起１６Ｂの未形成領域を設けることが好ましい。さらに、液状樹脂１１ａも各接続領域１４Ｂに対応させて分割して塗布することが好ましい。この場合、液状樹脂１１ａの塗布長さａは各部の合計長さ、突起１６Ｂの未形成領域の長さｂも各領域の合計長さとなり、それらの比を０．５〜１の範囲とすることが好ましい。バンプ接続体１０を有しない領域１８には突起１６Ａを配置してもよい。突起１６は素子中央付近の非接続領域にも配置することができる。   Further, as shown in FIGS. 12 and 13, a plurality of connection regions 14B are set in the plane of the second semiconductor element 9, and a region 18 having no bump connection body 10 exists between these connection regions 14B. In this case, it is preferable to provide a region where the protrusion 16B is not formed so as to correspond to each connection region 14B. Furthermore, it is preferable that the liquid resin 11a is also divided and applied corresponding to each connection region 14B. In this case, the application length a of the liquid resin 11a is the total length of each portion, and the length b of the unformed region of the protrusion 16B is also the total length of each region, and the ratio thereof is in the range of 0.5 to 1. It is preferable. A protrusion 16 </ b> A may be disposed in the region 18 that does not have the bump connection body 10. The protrusion 16 can also be disposed in a non-connection region near the center of the element.

次に、空隙調整部としての突起を適用した他の半導体装置について、図１４および図１５を参照して説明する。図１４および図１５に示す半導体装置２０は、外部接続端子２１を有する配線基板２２上にフリップチップ接続された半導体素子２３を具備している。配線基板２２と半導体素子２３とはバンプ接続体２４を介して接続されており、さらにそれらの隙間にはアンダーフィル樹脂２５が充填されている。この場合の接続高さ（隙間）は一般的に１００μｍ程度以下であり、４０〜７０μｍの範囲であることが多い。   Next, another semiconductor device to which the protrusion as the gap adjusting portion is applied will be described with reference to FIGS. A semiconductor device 20 shown in FIGS. 14 and 15 includes a semiconductor element 23 flip-chip connected on a wiring board 22 having external connection terminals 21. The wiring board 22 and the semiconductor element 23 are connected via a bump connection body 24, and an underfill resin 25 is filled in the gap between them. In this case, the connection height (gap) is generally about 100 μm or less, and often in the range of 40 to 70 μm.

近年、半導体装置の高密度化、高機能化、高速化等を図るために、機械的に脆弱な層（低誘電率絶縁膜（Ｌｏｗ−ｋ膜）等）を有する半導体素子２３が実用化されている。脆弱な層は半導体装置にかかる応力によって、同層のチップコーナ側が破壊の起点となることが知られている。そこで、破壊の進展を防ぐために、レーザダイシング等で幅１０〜５０μｍ、深さ５〜２５μｍ程度の溝２６を設けることがある。   In recent years, a semiconductor element 23 having a mechanically fragile layer (a low dielectric constant insulating film (Low-k film) or the like) has been put into practical use in order to increase the density, functionality, and speed of a semiconductor device. ing. It is known that a weak layer is a failure start point on the chip corner side of the same layer due to stress applied to the semiconductor device. Therefore, in order to prevent the progress of destruction, a groove 26 having a width of about 10 to 50 μm and a depth of about 5 to 25 μm may be provided by laser dicing or the like.

上述したような半導体素子２３を適用した半導体装置２０においては、配線基板２２の溝２６に対向する位置に突起２７を配置し、樹脂２５の流動抵抗が低い溝部周辺の流動抵抗を上げることによって、樹脂２５の充填速度差を低減することが有効である。このように、空隙調整部を構成する突起２７は配線基板２２と半導体素子２３との隙間にアンダーフィル樹脂２５を充填する場合にも有効に機能する場合がある。この場合の突起２７も前述した各実施形態の突起１６と同様な構成を有することが好ましい。   In the semiconductor device 20 to which the semiconductor element 23 as described above is applied, the protrusion 27 is disposed at a position facing the groove 26 of the wiring board 22 and the flow resistance around the groove portion where the flow resistance of the resin 25 is low is increased. It is effective to reduce the difference in filling speed of the resin 25. As described above, the protrusion 27 constituting the gap adjustment portion may function effectively even when the underfill resin 25 is filled in the gap between the wiring board 22 and the semiconductor element 23. In this case, the projection 27 preferably has the same configuration as the projection 16 of each embodiment described above.

なお、本発明は上記した各実施形態に限定されるものではなく、複数の半導体素子間をフリップチップ接続する各種の積層型半導体装置に適用することができる。また、半導体素子の積層数も２個に限られるものではなく、３個もくしはそれ以上であってもよい。そのような積層型半導体装置についても、本発明に含まれるものである。さらに、本発明の実施形態は本発明の技術的思想の範囲内で拡張もしくは変更することができ、この拡張、変更した実施形態も本発明の技術的範囲に含まれるものである。   The present invention is not limited to the above-described embodiments, and can be applied to various types of stacked semiconductor devices in which a plurality of semiconductor elements are flip-chip connected. Further, the number of stacked semiconductor elements is not limited to two, and three or more may be used. Such a stacked semiconductor device is also included in the present invention. Furthermore, the embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and these expanded and modified embodiments are also included in the technical scope of the present invention.

本発明の第１の実施形態による積層型半導体装置の断面図である。1 is a cross-sectional view of a stacked semiconductor device according to a first embodiment of the present invention. 図１に示す積層型半導体装置の第１の半導体素子と第２の半導体素子との積層部分を拡大して示す平面図である。FIG. 2 is an enlarged plan view illustrating a stacked portion of a first semiconductor element and a second semiconductor element of the stacked semiconductor device illustrated in FIG. 1. 図２のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 図２に示す積層型半導体装置の変形例を示す平面図である。FIG. 10 is a plan view illustrating a modification of the stacked semiconductor device illustrated in FIG. 2. 図４のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 図２に示す積層型半導体装置の他の変形例を示す平面図である。FIG. 10 is a plan view illustrating another modification of the stacked semiconductor device illustrated in FIG. 2. 図６のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 図２に示す積層型半導体装置のさらに他の変形例を示す平面図である。FIG. 10 is a plan view illustrating still another modification of the stacked semiconductor device illustrated in FIG. 2. 図８のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 本発明の第２の実施形態による積層型半導体装置の第１の半導体素子と第２の半導体素子との積層部分を拡大して示す平面図である。It is a top view which expands and shows the lamination | stacking part of the 1st semiconductor element of the lamination type semiconductor device by the 2nd Embodiment of this invention, and a 2nd semiconductor element. 図１０のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 図１０に示す積層型半導体装置の変形例を示す平面図である。FIG. 11 is a plan view illustrating a modification of the stacked semiconductor device illustrated in FIG. 10. 図１２のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 空隙調整部を適用した他の半導体装置の構成を示す平面図である。It is a top view which shows the structure of the other semiconductor device to which the space | gap adjustment part is applied. 図１４のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG.

符号の説明Explanation of symbols

１…積層型半導体装置、２…配線基板、５…第１の半導体素子、５ａ…上面（第１の半導体素子の第２の半導体素子と対向する面）、９…第２の半導体素子、９ａ…下面（第２の半導体素子の第１の半導体素子と対向する面）、１０…バンプ接続体、１１…アンダーフィル樹脂、１１ａ…液状樹脂の塗布部、１３…素子積層領域、１４Ａ…第１の接続領域、１４Ｂ…第２の接続領域、１５，１８…非接続領域、１６Ａ，１６Ｂ…突起、１７…外周領域。   DESCRIPTION OF SYMBOLS 1 ... Multilayer semiconductor device, 2 ... Wiring board, 5 ... 1st semiconductor element, 5a ... Upper surface (surface facing 2nd semiconductor element of 1st semiconductor element), 9 ... 2nd semiconductor element, 9a ... Lower surface (surface of second semiconductor element facing first semiconductor element), 10... Bump connector, 11... Underfill resin, 11a... Liquid resin coating section, 13. 14B ... second connection region, 15, 18 ... non-connection region, 16A, 16B ... projection, 17 ... outer peripheral region.

Claims (4)

素子搭載部と接続部とを有する配線基板と、
前記接続部と電気的に接続された電極部と、素子積層領域と、前記素子積層領域の内側に設定された第１の接続領域とを有し、前記配線基板の素子搭載部に搭載された第１の半導体素子と、
前記第１の半導体素子の素子積層領域上に積層され、かつ前記第１の接続領域と対応するように前記第１の半導体素子と対向する面に設定された第２の接続領域を有する第２の半導体素子と、
前記第１の接続領域および前記第２の接続領域の少なくとも一方に設けられたバンプ電極を有し、前記第１の半導体素子と前記第２の半導体素子との間の隙間の間隔が１５μｍ以上４０μｍ以下となるように、前記第１の半導体素子と前記第２の半導体素子とを接続するバンプ接続部と、
前記第１の半導体素子と前記第２の半導体素子との対向面の少なくとも一方から他方に向けて突出させると共に、前記第１の半導体素子と前記第２の半導体素子との間の隙間の高さ方向の一部を少なくとも占有するように設けられ、前記第１および第２の接続領域より外側の領域に配置された突起を有する空隙調整部と、
前記第１の半導体素子と前記第２の半導体素子との間の隙間に充填された樹脂と
を具備することを特徴とする積層型半導体装置。 A wiring board having an element mounting portion and a connection portion;
The electrode portion electrically connected to the connection portion, an element stacking region, and a first connection region set inside the element stacking region are mounted on the element mounting portion of the wiring board. A first semiconductor element;
A second connection region stacked on the device stack region of the first semiconductor element and having a second connection region set on a surface facing the first semiconductor device so as to correspond to the first connection region; A semiconductor element of
A bump electrode is provided in at least one of the first connection region and the second connection region, and a gap between the first semiconductor element and the second semiconductor element is 15 μm or more and 40 μm. to be equal to or less than, the bump connecting portion for connecting the first semiconductor element and the second semiconductor element,
The height of the gap between the first semiconductor element and the second semiconductor element is made to protrude from at least one of the opposing surfaces of the first semiconductor element and the second semiconductor element toward the other. A gap adjusting portion provided to occupy at least a part of the direction, and having a protrusion disposed in a region outside the first and second connection regions;
A stacked semiconductor device comprising: a resin filled in a gap between the first semiconductor element and the second semiconductor element. 請求項１記載の積層型半導体装置において、
前記突起は前記隙間の間隔の５０％以上７５％以下の範囲の高さを有することを特徴とする積層型半導体装置。 The stacked semiconductor device according to claim 1,
2. The stacked semiconductor device according to claim 1, wherein the protrusion has a height in a range of 50% to 75% of the gap interval. 請求項１または請求項２記載の積層型半導体装置において、
前記突起は前記第１の半導体素子の前記第２の半導体素子と対向する面に設けられており、かつ前記素子搭載領域内の前記第１の接続領域を除く領域と前記素子搭載領域より外側の領域とに配置されていることを特徴とする積層型半導体装置。 The stacked semiconductor device according to claim 1 or 2 ,
The protrusion is provided on a surface of the first semiconductor element facing the second semiconductor element, and a region excluding the first connection region in the element mounting region and an outer side of the element mounting region. A stacked semiconductor device, wherein the stacked semiconductor device is disposed in a region. 請求項１ないし請求項３のいずれか１項記載の積層型半導体装置において、
前記突起は前記樹脂の注入辺となる前記第２の半導体素子の一辺に沿った部分の形成体積が前記第２の半導体素子の他の辺に沿った部分の形成体積より少なくなるように配置されていることを特徴とする積層型半導体装置。 In the stacked semiconductor device according to any one of claims 1 to 3,
The protrusions are arranged such that the formation volume of a portion along one side of the second semiconductor element serving as the resin injection side is smaller than the formation volume of a portion along the other side of the second semiconductor element. A stacked semiconductor device characterized by comprising:
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