US7723839B2 - Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device - Google Patents

Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device Download PDF

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US7723839B2
US7723839B2 US11/446,189 US44618906A US7723839B2 US 7723839 B2 US7723839 B2 US 7723839B2 US 44618906 A US44618906 A US 44618906A US 7723839 B2 US7723839 B2 US 7723839B2
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semiconductor device
external connection
base substrate
semiconductor chip
semiconductor
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US20060278970A1 (en
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Yuji Yano
Seiji Ishihara
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III Holdings 10 LLC
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Sharp Corp
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Definitions

  • the present application discloses technology relating to: (i) a semiconductor device having thereon a semiconductor chip; (ii) a stacked semiconductor device in which a plurality of semiconductor devices are stacked; and (iii) a manufacturing method for a semiconductor device.
  • FIG. 15 is a cross sectional view illustrating a stack of two conventional semiconductor devices.
  • a semiconductor device 200 is stacked on a semiconductor device 100 .
  • the semiconductor device 100 includes: a base substrate 101 ; a semiconductor chip 103 mounted on the base substrate 101 ; external connection terminals 107 provided on a bottom surface of the base substrate 101 ; and external connection terminals 108 provided on an upper surface of the base substrate 101 .
  • the semiconductor chip 103 and the base substrate 101 are electrically connected with each other via a wire 104 . Further, the semiconductor chip 103 and the wire 104 are covered with a resin layer 106 .
  • a region, of the base substrate 101 , where the external connection terminals 108 are provided is not covered by the resin layer 106 , and is exposed.
  • the semiconductor device 200 has the same configuration as that of the semiconductor device 100 , except in that a resin layer 106 covers the entire region above a base substrate 101 , instead of covering regions other than a region where a semiconductor chip 103 and a wiring 104 are formed.
  • the following problems may take place in a case where the two semiconductor devices 100 and 200 are stacked as illustrated in FIG. 15 . Namely, if a height “s” of each of the external connection terminals 107 of the semiconductor device 200 is lower than a height “t” of the resin layer 106 of the semiconductor device 100 , there will be a gap “u” between the external connection terminal 107 of the semiconductor device 200 and one of the external connection terminals 108 of the semiconductor device 100 . Due to this gap “u”, it is unable to connect the semiconductor device 100 with the semiconductor device 200 .
  • the height “t” of the external connection terminal 107 of the semiconductor device 200 is reduced, the height “t” of the resin layer 106 of the semiconductor device 100 also has to be reduced.
  • reduction of the high “t” of the resin layer 106 of the semiconductor device 100 requires a technology for reducing the thickness of the semiconductor device 100 : e.g., a technology for reducing the thickness of the semiconductor chip 103 , or a technology for lowering the height of the loop formed by the wiring 104 . This causes technical difficulty in the production of the semiconductor device 100 .
  • a similar problem occurs in a case of stacking semiconductor devices illustrated in FIG. 16 .
  • FIG. 16 is a cross sectional view illustrating a stack of two conventional semiconductor devices.
  • a semiconductor device 400 is stacked on the semiconductor device 300 .
  • the semiconductor device 300 has an external connection terminal 108 formed on a semiconductor chip 103 .
  • a region where the external connection terminal 108 is formed is not covered by a resin layer 106 , and the region therefore is exposed.
  • the configuration of the semiconductor device 300 is the same as that of the foregoing semiconductor device 100 .
  • the configuration of the semiconductor device 400 is similar to that of the foregoing semiconductor device 200 .
  • FIG. 17 is a cross sectional view illustrating a resin-sealing process carried out in a manufacturing process of a conventional semiconductor device.
  • the following problem occurs in the resin-sealing process. Namely, for example, if a transfer mold is used for carrying out the resin-sealing process for covering, with a resin 106 , the semiconductor chip 103 except for the region where the external connection terminal 108 is formed, a mold 50 directly presses the wiring layer 108 on the semiconductor chip 103 , which layer includes conductive layer x and an insulation layer y (See FIG. 17 ).
  • the thickness of the wiring layer 108 is approximately 50 ⁇ m and is thin. Further, the material of the wiring layer 108 is hardly deformed. As such, the wiring layer 108 will not be able to absorb the stress applied by the mold 50 . As a result, a strong stress is applied to the semiconductor chip 103 , and this strong stress may cause damage to the semiconductor chip 103 .
  • the technology was made, and it is one of objects of the present technology to contribute to realization of higher density packaging of semiconductor devices, by providing a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.
  • the semiconductor device includes: a base substrate; a semiconductor chip electrically connected to the base substrate; a resin layer covering at least a portion of the semiconductor chip; and a first external connection terminal electrically connected to the base substrate, wherein the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
  • the first external connection terminal has the exposed surface which is exposed from the surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane. Therefore, at a time of stacking another semiconductor device on the semiconductor device of the present technology, the first external connection terminal is connected with an external connection terminal of the upper semiconductor device, even if the external connection terminal of the upper semiconductor device is low. Incidentally, in a case where external connection terminals of the upper semiconductor device are arranged at a narrow pitch, the height of each of the external connection terminals is low. However, with the configuration, the resin layer does not block the external connection terminal from reaching the first external connection terminal. Thus, it is not necessary to lower the resin layer for the purpose of acquiring a connection between the external connection terminals.
  • the semiconductor device is high in its connection reliability, and is easily manufactured without a need for a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
  • the above described first external connection terminal is used for acquiring the connection with the upper semiconductor device. This reduces damage to the semiconductor chip even if the semiconductor device is sealed with a resin by using a transfer mold or the like.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including (i) a base substrate, (ii) a semiconductor chip electrically connected to the base substrate, (iii) a resin layer covering at least a portion of the semiconductor chip, and (iv) a first external connection terminal electrically connected to the base substrate, the method comprising the step of: (A) sealing with a resin such that (a) the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and (b) the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
  • the configuration it is possible to manufacture a semiconductor device in which (i) a first external connection terminal having the exposed surface which is exposed from a surface of the resin layer, and (ii) the exposed surface and the surface of the resin layer form a single plane.
  • the semiconductor devices are connected with each other, even if an external connection terminal of the upper semiconductor device is low.
  • the height of each of the external connection terminals is low.
  • the resin layer does not block the external connection terminal from reaching the first external connection terminal.
  • the method allows easy manufacturing of a semiconductor device which is high in its connection reliability, and the method does not require a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
  • damage to the semiconductor chip is reduced by (i) forming and deforming the external connection terminal, and then (ii) carrying out the resin-sealing process, instead of exposing the wiring layer formed on the surface of the semiconductor chip for the purpose of acquiring the connection with the upper semiconductor device.
  • the method may be so adapted that the step (A) includes the sub steps of: pressing a mold against the first external connection terminal to flatten a surface of the first external connection terminal; and sealing with the resin such that (a) the first external connection terminal has the exposed surface which is exposed from the surface of the resin layer, and (b) the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
  • the sub step of sealing is carried out after the external connection terminal is deformed by pressing the mold against the external connection terminal.
  • FIG. 1 is a cross sectional view illustrating a configuration of a semiconductor device of an embodiment.
  • FIG. 2 is a plane view illustrating the semiconductor device of FIG. 1 viewed from above.
  • FIG. 3( a ) is a cross sectional view illustrating a semiconductor device manufacturing process of an embodiment.
  • FIG. 3( b ) is a cross sectional view illustrating a semiconductor device manufacturing process of an embodiment.
  • FIG. 3( c ) is a cross sectional view illustrating a semiconductor device manufacturing process of an embodiment.
  • FIG. 4 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 1.
  • FIG. 5 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 2.
  • FIG. 6 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 3.
  • FIG. 7 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 4.
  • FIG. 8 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 5.
  • FIG. 9 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 6.
  • FIG. 10 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 7.
  • FIG. 11 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 8.
  • FIG. 12 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 9.
  • FIG. 13 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 10.
  • FIG. 14 is a cross sectional view illustrating a configuration of a stacked semiconductor device.
  • FIG. 15 is a cross sectional view illustrating a stack of two conventional semiconductor devices.
  • FIG. 16 is a cross sectional view illustrating a stack of two conventional semiconductor devices.
  • FIG. 17 is a cross sectional view illustrating a resin-sealing step carried out in a conventional manufacturing process of a semiconductor device.
  • FIG. 1 is a cross sectional view illustrating a configuration of a semiconductor device.
  • FIG. 2 is a plane view illustrating the semiconductor device of FIG. 1 which is viewed from above.
  • a wiring layer 9 is formed, and external connection terminals (first external connection terminals) 8 which are electrically conductive projections formed on the wiring layer 9 . As illustrated in FIG. 2 , these external connection terminals 8 are arranged in an area-array manner. Further, The wiring layer 9 and the base substrate 1 are connected with each other via the wire 4 .
  • the semiconductor device 20 is sealed by a resin layer 6 .
  • the resin layer 6 covers: the upper surface of the base substrate 1 , the adhesive layer 2 , the semiconductor chip 3 , the wire 4 , and the wiring layer 9 .
  • a suitable material of the resin layer 6 may be: epoxy resin, silicone resin, or the like.
  • the material of the resin layer 6 is not particularly limited.
  • a characteristic of the semiconductor device 20 of the present embodiment is that each of the external connection terminals 8 is in the same plane as the surface of the resin layer 6 , and is exposed from the surface of the resin layer 6 .
  • a surface (exposed surface) of the external connection terminal 8 and the surface of the resin layer 6 form a single plane. This is also rephrased as the surface of the external connection terminal 8 and the surface of the resin layer 6 are at the same height.
  • the wording “in the same plane” does not mean “exactly in the same plane”. That is, the external connection terminal 8 can be substantially in the same plane as the surface of the resin layer 6 , and yet the following effect is obtained.
  • the surface of the external connection terminal 8 is exposed from the resin layer 6 , so that the external connection terminal 8 is formed on the surface of the semiconductor device 20 .
  • the external connection terminal 8 of the semiconductor device 20 is connected with an external connection terminal of the upper semiconductor device.
  • the resin layer 6 does not block the external connection terminal of the upper semiconductor device from reaching the external connection terminal 8 , even if the height of the external connection terminal of the upper semiconductor device is lowered for the purpose of achieving a higher density integration.
  • the semiconductor device 20 of the present embodiment is high in its connection reliability, and is easily manufactured without a need for a technology to reduce the thickness of the semiconductor device 20 , such a technology being a technology for reducing the thickness of the semiconductor chip 3 , a technology for lowering the loop of the wire 4 , or the like.
  • the wiring layer 9 formed on the surface of the semiconductor chip 3 is not exposed from the resin layer 6 ; i.e., the wiring layer 9 is covered with the resin layer 6 .
  • the wiring layer 9 formed on the surface of the semiconductor chip 3 does not have to be covered with a mold during a resin-sealing process. This reduces damage to the semiconductor chip 3 , which occurs during the resin-sealing process.
  • each of the external connection terminals 8 of the semiconductor device 20 is electrically connected to the base substrate 1 via the wiring layer 9 .
  • the wiring layer 9 is formed on the upper surface of the semiconductor chip 3 . This allows reduction of the thickness of the semiconductor device 20 .
  • FIG. 3( a ) to FIG. 3( c ) are cross sectional views illustrating a manufacturing process of the semiconductor device of the present embodiment.
  • a semiconductor chip 3 is mounted on an adhesive layer 2 which is provided on a base substrate 1 .
  • the semiconductor chip 3 has thereon a wiring layer 9 and external connection terminals 8 which are formed prior to the mounting of the semiconductor chip 3 . Note that it is possible to mount, on the base substrate 1 , the semiconductor chip 3 on which the wiring layer 9 has been formed beforehand, and then mount the external connection terminal 8 . Then, the semiconductor chip 3 and wiring layer 9 are electrically connected with the base substrate 1 via the wire 4 .
  • a resin-sealing process is carried out in such a manner that the external connection terminal 8 is in the same plane as the surface of the resin layer 6 , and is exposed from the surface of the resin layer 6 (sealing process).
  • a mold 50 is pressed as illustrated in FIG. 3( b ) so as to deform the external connection terminal 8 . More specifically, a surface, of the mold 50 , which touches the external connection terminal 8 is flat. By pressing such a mold 50 , the upper surface of the external connection terminal 8 is flattened.
  • the external connection terminal 8 be made of a material which is easily deformed, so that the process is easily carried out. For example, such a material may be solder or copper.
  • solder As the material of the external connection terminal 8 , the solder will be melted and become flowable, if a mold temperature surpasses the melting point of the solder, at the time of carrying out the resin-sealing process.
  • the mold temperature during the resin-sealing process is between 150° C. and 200° C.
  • solder having a melting point of 200° C. or higher it is preferable to adopt solder having a melting point of 200° C. or higher.
  • the resin-sealing process is carried out in such a manner that the external connection terminal 8 is in the same plane as the surface of the resin layer 6 , and is exposed from the surface of the resin layer 6 .
  • an external connection terminal 7 is formed on the bottom surface of the base substrate 1 .
  • the external connection terminal 7 does not necessarily have to be formed after the resin-sealing process, and it is possible to form the external connection terminal 7 prior to the resin-sealing process.
  • the manufacturing method for the semiconductor device 20 of the present embodiment includes the resin-sealing process, and the sealing process is carried out by using the mold 50 .
  • This manufacturing method easily realizes the external connection terminal 8 , of the semiconductor device 20 , which terminal is (i) in the same plane as the surface of the resin layer 6 , and (ii) exposed from the surface of the resin layer 6 .
  • the manufacturing method uses the mold 50 .
  • the manufacturing method is not particularly limited to the method using the mold 50 , provided that the external connection terminal 8 is exposed from the resin layer 6 : i.e., the external connection terminal 8 is formed on the surface of the semiconductor device 20 .
  • FIG. 4 is a cross sectional view illustrating a configuration of a semiconductor device 20 a of Alternative Example 1. As illustrated in FIG. 4 , a semiconductor chip 3 in the semiconductor device 20 a is connected to a base substrate 1 by a flip-chip bonding using a bump 10 , instead of connecting the semiconductor chip 3 and the base substrate 1 via a wire 4 .
  • the semiconductor device 20 a has the same configuration as that of the foregoing semiconductor device 20 , except for the above described point.
  • the flip-chip bonding technique is used in the semiconductor device 20 a of the present alternative example, so that the semiconductor chip 3 is mounted on the base substrate 1 at a higher density.
  • a method for manufacturing this semiconductor device 20 a is the same as the foregoing manufacturing method for the semiconductor device 20 , except in that a flip-chip bonding is carried out for connecting the semiconductor chip 3 with the base substrate 1 .
  • FIG. 5 is a cross sectional view illustrating a configuration of a semiconductor device 20 b of Alternative Example 2.
  • the wiring layer 9 is directly formed on the semiconductor chip 3 .
  • a wiring layer 9 is formed on a supporting member 11 .
  • This wiring layer 9 on the supporting member 11 is mounted on an adhesive layer 12 which is provided on a semiconductor chip 3 .
  • the wiring layer 9 is formed on the supporting member 11
  • the wiring layer 9 on the supporting member 11 is mounted on the adhesive layer 12 on the semiconductor chip 3 .
  • the supporting member 11 and the adhesive layer 12 are insulative members. By adopting, for these members, a material whose elasticity is low, the members further absorb the stress applied to the semiconductor chip 3 , thus reducing the damage to the semiconductor chip 3 .
  • Respective areas of the supporting member 11 and the wiring layer 9 formed on the supporting member 11 may be larger than the area of the semiconductor chip 3 .
  • the size of the wiring layer 9 may be larger than that of the semiconductor chip 3 .
  • the semiconductor chip 3 is connected with a base substrate 1 via a wire 4 .
  • the wiring layer 9 and the base substrate 1 are connected via a wire 5 .
  • the wire 4 Since there is no sufficient space for providing the wire 4 between the semiconductor chip 3 and the adhesive layer 12 , the wire 4 is extended through the inside of the adhesive layer 12 . In other words, the wire 4 is wrapped by the adhesive layer 12 . Since the wire 4 is wrapped by the adhesive layer 12 , a wire deformation which occurs in the resin-sealing process is restrained.
  • the semiconductor device 20 b has the same configuration as the foregoing semiconductor device 20 , except for the above described point. Accordingly, the above described manufacturing method for the semiconductor device 20 can be used as to: (i) forming and deforming external connection terminals 8 , and (ii) carrying out the resin-sealing process.
  • FIG. 6 is a cross sectional view illustrating a configuration of a semiconductor device 20 c of Alternative Example 3.
  • the configuration of the semiconductor device 20 c is substantially the same as the semiconductor device 20 b of Alternative Example 2.
  • the configuration of the semiconductor device 20 c differs from the semiconductor device 20 b in that a spacer layer 13 is provided on an adhesive layer 18 which is provided on a semiconductor chip 3 .
  • the spacer layer 13 With the provision of the spacer layer 13 , a sufficient space for a wire 4 is acquired between the semiconductor chip 3 and an adhesive layer 12 . Accordingly, in the semiconductor device 20 c of the present alternative example, the wire 4 is not extended through the adhesive layer 12 . This improves the reliability of the connection between the semiconductor chip 3 and the wire 4 . Further, the supporting member 11 and the spacer layer 13 can be made of a heat conductive material. In this case, a heat dissipating characteristic is improved.
  • the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 c as to: (i) forming and deforming the external connection terminals 8 , and (ii) carrying out the resin-sealing process.
  • FIG. 7 is a cross sectional view illustrating a configuration of a semiconductor device 20 d of Alternative Example 4. Unlike the semiconductor device 20 b of Alternative Example 2, a semiconductor chip 3 and a base substrate 1 in the semiconductor device 20 d are connected by a flip-chip boding using a bump 10 , as illustrated in FIG. 7 . Other than that, the configuration of the semiconductor device 20 d is the same as the semiconductor 20 b of Alternative Example 2.
  • the flip-chip bonding technique is used in the semiconductor device 20 d of the present alternative example, so that the semiconductor chip 3 is mounted on the base substrate 1 at a higher density.
  • This semiconductor device 20 d does not require its adhesive layer 12 to be thickened, as is the case of Alternative Example 2, nor does it require a spacer layer 13 as is required in Alternative Example 3. Thus, it is possible to reduce the thickness of the semiconductor device.
  • a method for manufacturing this semiconductor device 20 b is the same as the foregoing manufacturing method for the semiconductor device 20 , except in that a flip-chip bonding is carried out for connecting the semiconductor chip 3 with the base substrate 1 .
  • FIG. 8 is a cross sectional view illustrating a configuration of a semiconductor device 20 e of Alternative Example 5.
  • the external connection terminals 8 are provided on the semiconductor chip 3 via the wiring layer 9 .
  • external connection terminals 8 are directly provided on a base substrate 1 , and are electrically connected with the base substrate 1 , as illustrated in FIG. 8 .
  • the semiconductor device 20 e has the same configuration as the semiconductor device 20 , except for the above described point.
  • each of the external connection terminals 8 is formed on the base substrate 1 , and not above a semiconductor chip 3 . Accordingly, a stress applied to the external connection terminal 8 by a mold used in a resin-sealing process is not applied to the semiconductor chip 3 . This further reduces damage to the semiconductor chip 3 . Further, this is also advantageous in that the height of the semiconductor device is lowered.
  • the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 e as to: (i) forming and deforming the external connection terminals 8 , and (ii) carrying out the resin-sealing process.
  • FIG. 9 is a cross sectional view illustrating a configuration of a semiconductor device 20 f of Alternative Example 6. As in the semiconductor device 20 e of Alternative Example 5, external connection terminals 8 in the semiconductor device 20 f are directly provided on a base substrate 1 , and are electrically connected to the base substrate 1 .
  • the semiconductor device 20 f differs from the semiconductor device 20 e , in that (1) a semiconductor chip 3 is provided in an opening portion 16 of the base substrate 1 , and (2) another semiconductor chip 3 is stacked on the semiconductor chip 3 , and both of the semiconductor chips 3 are electrically connected to the base substrate 1 via a wire 4 and a wiring layer 9 , respectively.
  • the semiconductor device 20 f has the same configuration as the semiconductor device 20 e of Alternative Example 5, except for the above described point.
  • the semiconductor device 20 f of the present alternative example includes two semiconductor chips 3 provided in the aperture section 16 of the base substrate 1 , so that the semiconductor chips 3 are mounted at a higher density than a case where the semiconductor chips 3 are provided on the base substrate 1 .
  • the present alternative example deals with a case where the number of the semiconductor chips 3 is two.
  • the number of the semiconductor chips 3 being mounted is not limited to two.
  • the semiconductor chips are mounted at a higher density than a case of mounting the same number of semiconductor chips on the base substrate 1 .
  • the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 f as to: (i) forming and deforming the external connection terminals 8 , and (ii) carrying out the resin-sealing process.
  • FIG. 10 is a cross sectional view illustrating a configuration of a semiconductor device 20 g of Alternative Example 7. As in the semiconductor device 20 e of Alternative Example 5, external connection terminals 8 in the semiconductor device 20 g are directly provided on a base substrate 1 , and are electrically connected to the base substrate 1 .
  • the semiconductor device 20 g differs from the semiconductor device 20 e , in that (1) a semiconductor chip 3 is provided in a depressed portion 17 of the base substrate 1 , and (2) another semiconductor chip 3 is stacked on the semiconductor chip 3 , and both of the semiconductor chips 3 are electrically connected to the base substrate 1 via a wire 4 .
  • the lower semiconductor chip 3 and the base substrate 1 are directly connected via the wire 4 , and not via the wiring layer 9 .
  • the lower semiconductor chip 3 may be connected via the wiring layer 9 .
  • the upper semiconductor chip 3 and the base substrate 1 are directly connected via the wire 4 and the wiring layer 9 .
  • the semiconductor device 20 g has the same configuration as the semiconductor device 20 e of Alternative Example 5, except for the above described point.
  • the semiconductor device 20 g of the present alternative example includes the semiconductor chips 3 which are provided in the depressed portion 17 of the base substrate 1 .
  • This configuration allows the semiconductor chips 3 to be mounted at a higher density than a case where the semiconductor chips 3 are provided on a portion of the base substrate 1 other than the depressed portion 17 of the base substrate 1 .
  • a provision of the depressed portion 17 on the base substrate 1 causes less deterioration in the mechanical strength of the semiconductor device, when compared with the configuration of Alternative Example 6, in which the base substrate 1 is provided with the opening portion 16 .
  • the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 g as to: (i) forming and deforming the external connection terminals 8 , and (ii) carrying out the resin-sealing process.
  • FIG. 11 is a cross sectional view illustrating a configuration of a semiconductor device 20 h of Alternative Example 8.
  • the surface of a resin layer 6 of the semiconductor device 20 h is not flat.
  • the surface of the resin layer 6 in a region 14 having external connection terminals 8 is lower (i.e., depressed toward a base substrate 1 ) than the surface of the resin layer 6 in a region 15 which is a region other than the region 14 .
  • the configuration of the semiconductor device 20 h is the same as the semiconductor device 20 .
  • each external connection terminal of a semiconductor device laminated above the semiconductor device 20 h is partially housed in the depressed portion. This configuration allows for an even higher density packaging.
  • the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 h as to: (i) forming and deforming the external connection terminals 8 , and (ii) carrying out the resin-sealing process.
  • a mold 50 to be used is preferably a mold illustrated in FIG. 17 , or the like, whose portion corresponding to the depressed portion of the surface of the resin layer 6 is projected.
  • FIG. 12 is a cross sectional view illustrating a configuration of a semiconductor device 20 i of Alternative Example 9.
  • the surface of a resin layer 6 in a region 14 having external connection terminals 8 is lower (i.e., depressed toward a base substrate 1 ) than the surface of the resin layer 6 in a region 15 which is a region other than the region 14 , as in the case of the foregoing semiconductor device 20 h.
  • Each of the external connection terminal 8 in the semiconductor device 20 i is directly formed on the base substrate 1 , and is electrically connected. Accordingly, in the semiconductor device 20 i , a region 14 having the external connection terminals 8 is arranged on both sides of the region 15 which is a region other than the region 14 , while the region 15 is arranged on both sides of the region 14 having the external connection terminals 8 , in the semiconductor device 20 h.
  • the configuration of the semiconductor device 20 i is the same as the semiconductor device 20 h of Alternative Example 8, other than the above described point.
  • each of the external connection terminal 8 is formed on the base substrate 1 , and not above the semiconductor chip 3 .
  • the stress applied to the external connection terminal 8 by the mold used in the resin-sealing process is prevented from being applied to the semiconductor chip 3 .
  • damage to the semiconductor chip 3 is further reduced.
  • each external connection terminal of a semiconductor device laminated above the semiconductor device 20 i is partially housed in the depressed portion. This configuration allows for an even higher density packaging.
  • the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 i as to: (i) forming and deforming the external connection terminals 8 , and (ii) carrying out the resin-sealing process.
  • a mold 50 to be used is preferably a mold illustrated in FIG. 17 or the like whose portion corresponding to the depressed portion of the surface of the resin layer 6 is projected.
  • FIG. 13 is a cross sectional view illustrating a configuration of a semiconductor device 20 j of Alternative Example 10.
  • the semiconductor device 20 j includes: a base substrate 1 ; three semiconductor chips 3 a to 3 c which are stacked on the base substrate 1 ; and external connection terminals (second external connection terminals) 7 provided on the bottom surface of the base substrate 1 .
  • An adhesive layer is provided on the base substrate 1 , and the lower semiconductor chip 3 a is provided on the adhesive layer on the base substrate 1 .
  • This semiconductor device 3 a is electrically connected with the base substrate 1 by a flip-chip bonding using a bump 10 .
  • an adhesive layer is formed on the lower semiconductor chip 3 a , and the middle semiconductor chip 3 b is provided on the adhesive layer on the lower semiconductor chip 3 a .
  • This semiconductor chip 3 b is electrically connected with the base substrate 1 via a wire 4 .
  • the wire 4 connecting the middle semiconductor chip 3 b with the base substrate 1 is extended through the inside of an adhesive layer provided on the middle semiconductor chip 3 b.
  • the upper semiconductor chip 3 c is provided on the adhesive layer which is provided on the middle semiconductor chip 3 b .
  • This upper semiconductor chip 3 c is electrically connected to the base substrate 1 via a wire 4 .
  • an adhesive layer is provided, and a spacer layer 13 is provided on the adhesive layer on the semiconductor chip 3 c . Therefore, the wire 4 which connects the upper semiconductor chip 3 c with the base substrate 1 is not extended through the inside of the adhesive layer.
  • the spacer layer 13 has thereon an adhesive layer, and a supporting member 11 is provided on the adhesive layer on the spacer layer 13 . Further, the supporting member 11 has thereon a wiring layer 9 , and an external connection terminals (first external connection terminals) 8 which are electrically conductive projections formed on the wiring layer 9 . As is the case of the configuration of FIG. 2 , these external communication terminals 8 are arranged in an area-array manner.
  • the wiring layer 9 and the base substrate 1 are connected via a wire 5 .
  • the semiconductor device 20 j is sealed by a resin layer 6 . More specifically, the resin layer 6 entirely covers the members formed on the upper surface of the base substrate 1 , except for the external connection terminals 8 .
  • each of the external connection terminals 8 in the semiconductor device 20 j is in the same plane as the surface of the resin layer 6 , and is exposed from the surface of the resin layer 6 .
  • the surface of the external connection terminal 8 and the surface of the resin layer 6 form a single surface.
  • the surface of the external connection terminal 8 and the surface of the resin layer 6 are at the same height.
  • the description reading “in the same plane as the surface of the resin layer 6 ” does not mean that the surface of the external connection terminal 8 has to be exactly in the same plane as the surface of the resin layer 6 , and the surface of the external connection terminal 8 may be substantially in the same plane as the surface of the resin layer 6 .
  • three semiconductor chips 3 a to 3 c are mounted in the semiconductor device 20 j of the present alternative example.
  • the present alternative example deals with a case where three semiconductor chips 3 are stacked, however, the number of the semiconductor chips 3 is not limited to three. It is possible to stack two semiconductor chips 3 , or stack four or more semiconductor chips 3 . Further, how the semiconductor chips 3 are mounted is not particularly limited.
  • the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 j as to: (i) forming and deforming the external connection terminals 8 , and (ii) carrying out the resin-sealing process.
  • FIG. 14 is a cross sectional view illustrating the configuration of a stacked semiconductor device 40 .
  • the foregoing semiconductor 20 i is stacked on the foregoing semiconductor device 20
  • another semiconductor device 30 is stacked on the semiconductor 20 i.
  • the external connection terminals 8 of the semiconductor device 20 are respectively jointed to the external connection terminals 7 of the semiconductor device 20 i , so that the semiconductor devices 20 and 20 i are electrically connected with each other.
  • the semiconductor device 30 has on its bottom surface external connection terminals 7 .
  • the external connection terminals 8 of the semiconductor device 20 i are respectively jointed to the external connection terminals 7 of the semiconductor device 30 , so that the semiconductor devices 20 i and 30 are electrically connected with each other.
  • the external connection terminals 8 of the semiconductor device 20 are in the same plane as the surface of the resin layer 6 , and are exposed from the surface of the resin layer 6 . Accordingly, even if the respective heights of the external connection terminals 7 of the semiconductor device 20 i is low, the external connection terminals 8 of the semiconductor device 20 and the external connection terminal 7 of the semiconductor device 20 i are respectively connected with each other. Similarly, the external connection terminals 8 of the semiconductor device 20 i are also in the same plane as the surface of the resin layer 6 , and are exposed from the surface of the resin layer 6 . Accordingly, even if the respective heights of the external connection terminals 7 of the semiconductor device 30 are low, the external connection terminals 8 of the semiconductor device 20 i and the external connection terminals 7 of the semiconductor device 30 are respectively connected with each other.
  • the semiconductor device 40 is formed by stacking the semiconductor devices 20 , 20 i , and 30 , and electrically connecting them with one another. This configuration allows lowering of the external connection terminals 7 while avoiding deterioration in the connection stability. As a result, a high density packaging of semiconductor devices is possible.
  • the above explanation deals with a case where the number of semiconductor devices to be stacked is three.
  • the number of the semiconductor devices to be stacked is not limited to this, and it is possible to stack two semiconductor devices, or stack four or more semiconductor devices.
  • the above explanation deals with a case where the semiconductor devices 20 , 20 i , and 30 are stacked.
  • the semiconductor device 30 can be stacked on any one of or more than one of the semiconductor devices 20 , and 20 a to 20 j .
  • a semiconductor device includes: a base substrate; a semiconductor chip electrically connected to the base substrate; a resin layer covering at least a portion of the semiconductor chip; and a first external connection terminal electrically connected to the base substrate, wherein the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
  • the first external connection terminal has the exposed surface which is exposed from the surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane. Therefore, at a time of stacking another semiconductor device on the semiconductor device as disclosed, the first external connection terminal is connected with an external connection terminal of the upper semiconductor device, even if the external connection terminal of the upper semiconductor device is low. Incidentally, in a case where external connection terminals of the upper semiconductor device are arranged at a narrow pitch, the height of each of the external connection terminals is low. However, with the configuration, the resin layer does not block the external connection terminal from reaching the first external connection terminal. Thus, it is not necessary to lower the resin layer for the purpose of acquiring a connection between the external connection terminals.
  • the semiconductor device is high in its connection reliability, and is easily manufactured without a need for a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
  • the above described first external connection terminal is used for acquiring the connection with the upper semiconductor device. This reduces damage to the semiconductor chip even if the semiconductor device is sealed with a resin by using a transfer mold or the like.
  • the semiconductor device may be adapted so that said first external connection terminal is electrically connected with the base substrate via a wiring layer.
  • the semiconductor device may be adapted so that said wiring layer is formed on a surface, of the semiconductor chip, on a side of the external connection terminal.
  • the wiring layer is formed on the surface, of the semiconductor chip, on the side of the first external connection terminal. This is more advantageous in terms of reducing the thickness of a semiconductor device, when compared to a later described case where supporting member and/or an adhesive layer is/are interposed.
  • the semiconductor device may be adapted so that said wiring layer is formed on a supporting member, and is mounted on the semiconductor chip.
  • the semiconductor device may be adapted so that an area of a region in which the wiring layer is provided is larger than an area of the semiconductor chip.
  • the wiring layer may be larger than the semiconductor chip.
  • the upper and lower semiconductor devices can be stacked even if the upper semiconductor device has a larger area of an external connection terminal array than the lower semiconductor chip.
  • the semiconductor device may be adapted so that said first external connection terminal is formed on the base substrate.
  • the first external connection terminal is formed on the base substrate, and not above the semiconductor chip.
  • the stress applied to the first external connection terminal by the mold used in a resin-sealing process is prevented from being applied to the semiconductor chip.
  • damage to the semiconductor chip is further reduced.
  • this is also advantageous in that the height of the semiconductor device is lowered.
  • the semiconductor device may be adapted so that said semiconductor chip is provided in an aperture section of the base substrate.
  • the semiconductor chip By providing the semiconductor chip in the aperture section of the base substrate, it is possible to package semiconductor chips at a higher density than a case where the semiconductor chip is provided on the base substrate.
  • the semiconductor device may be adapted so that said semiconductor chip is provided in a depressed portion of the base substrate.
  • the semiconductor chip By providing the semiconductor chip in the depressed portion of the base substrate, it is possible to package semiconductor chips at a higher density than a case where the semiconductor chip is provided on the base substrate.
  • the semiconductor device may be adapted so that a first surface of the resin layer is depressed towards the base substrate so that the first surface is closer to the base substrate than a second surface of the resin layer is to the base substrate, the first surface being a surface of the resin layer in a region where the first external connection terminal is provided, and the second surface being a surface of the resin layer other than the first surface.
  • the resin surface (first surface) of the region in which the first external connection terminal is provided may be lower than the resin surface (second surface) of the other region.
  • the external connection terminal of a semiconductor device stacked above the semiconductor device of the present technology is partially housed in the depressed portion. This configuration allows for an even higher density packaging.
  • the semiconductor device may be adapted so that said first external connection terminal is made of a solder.
  • the first external connection terminal By using, as a material of the first external connection terminal, a solder which is easily deformable, the first external connection terminal is easily deformed. Further, it becomes easy to expose, from the resin layer, the exposed surface of the first external connection terminal, and form a single plane including the exposed surface and the surface of the resin layer.
  • the semiconductor device may be adapted so that said solder has a melting point of 200° C. or higher.
  • the mold temperature during the resin-sealing process in general, is between 150° C. to 200° C. Accordingly, if the solder has the melting point of 200° C. or higher, it is possible to reduce the risk that the mold temperature surpasses the melting point of solder, and that the solder is melted and becomes flowable.
  • the semiconductor device may be adapted so that said first external connection terminal is made of copper.
  • the first external connection terminal By using, as a material of the first external connection terminal, copper which is easily deformable, the first external connection terminal is easily deformed. Further, it becomes easy to expose, from the resin layer, the exposed surface of the first external connection terminal, and form a single plane including the exposed surface and the surface of the resin layer.
  • a semiconductor may include: a base substrate; a plurality of semiconductor chips each electrically connected to the base substrate; a resin layer covering at least a portion of the semiconductor chip; and a first external connection terminal electrically connected to the base substrate, wherein the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
  • a stacked semiconductor device includes: any one of the above described semiconductor devices, and another one of the above described semiconductor devices further including a second external connection terminal, wherein the above semiconductor device is electrically connected with the another one of the above semiconductor devices, by jointing the first external connection terminal of the above semiconductor device with the second external connection terminal of the another one of the above semiconductor devices.
  • the semiconductor devices are electrically connected with each other by jointing the first external connection terminal to the second external connection terminal. This configuration allows for even higher density packaging.
  • a stacked semiconductor device includes: any one of the above described semiconductor devices, and another semiconductor device further including a second external connection terminal, wherein the above semiconductor device is electrically connected with the another semiconductor device, by jointing the first external connection terminal of the above semiconductor device with the second external connection terminal of the another semiconductor device.
  • the semiconductor devices are electrically connected with each other by jointing the first external connection terminal to the second external connection terminal. This configuration allows for even higher density packaging.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including (i) a base substrate, (ii) a semiconductor chip electrically connected to the base substrate, (iii) a resin layer covering at least a portion of the semiconductor chip, and (iv) a first external connection terminal electrically connected to the base substrate, the method comprising the step of: (A) sealing with a resin such that (a) the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and (b) the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
  • the configuration it is possible to manufacture a semiconductor device in which (i) a first external connection terminal having the exposed surface which is exposed from a surface of the resin layer, and (ii) the exposed surface and the surface of the resin layer form a single plane.
  • the semiconductor devices are connected with each other, even if an external connection terminal of the upper semiconductor device is low.
  • the height of each of the external connection terminals is low.
  • the resin layer does not block the external connection terminal from reaching the first external connection terminal. Thus, it is not necessary to lower the resin layer for the purpose of acquiring a connection with the upper semiconductor device.
  • the method allows easy manufacturing of a semiconductor device which is high in its connection reliability, and the method does not require a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
  • damage to the semiconductor chip is reduced by (i) forming and deforming the external connection terminal, and then (ii) carrying out the resin-sealing process, instead of exposing the wiring layer formed on the surface of the semiconductor chip for the purpose of acquiring the connection with the upper semiconductor device.
  • the method may be adapted so that the step (A) includes the sub steps of: pressing a mold against the first external connection terminal to flatten a surface of the first external connection terminal; and sealing with the resin such that (a) the first external connection terminal has the exposed surface which is exposed from the surface of the resin layer, and (b) the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
  • the sub step of sealing is carried out after the external connection terminal is deformed by pressing the mold against the external connection terminal.
  • the method may further include the step of heating the mold to a temperature of not more than a melting point of the first external connection terminal.
  • the first external connection terminal has the exposed surface, and the exposed surface of the first connection terminal and the resin layer form a single plane. Therefore, at a time of stacking another semiconductor device on the semiconductor device of the present technology, the first external connection terminal is connected with an external connection terminal of the upper semiconductor device, even if the external connection terminal of the upper semiconductor device is low. Thus, it is not necessary to lower the resin layer for the purpose of acquiring a connection between the external connection terminals. As a result, the semiconductor device of the present invention is high in its connection reliability, and is easily manufactured without a need for a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
  • the above described first external connection terminal is used for acquiring the connection with the upper semiconductor device. This reduces damage to the semiconductor chip even if the semiconductor device is sealed with a resin by using a transfer mold or the like.

Abstract

A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.

Description

This Nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 171730/2005 filed in Japan on Jun. 10, 2005, the entire contents of which are hereby incorporated by reference.
FIELD OF THE TECHNOLOGY
The present application discloses technology relating to: (i) a semiconductor device having thereon a semiconductor chip; (ii) a stacked semiconductor device in which a plurality of semiconductor devices are stacked; and (iii) a manufacturing method for a semiconductor device.
BACKGROUND OF THE TECHNOLOGY
Smaller and lighter electronic devices having more advanced functions have been developed. Under such circumstances, it is required that semiconductor devices be more densely packaged. In response to such a requirement, for example, Japanese Unexamined Patent Publications No. 135267/1998 (Tokukaihei 10-135267; published on May 22, 1998) and No. 172157/2004 (Tokukai 2004-172157; Published on Jun. 17, 2004) suggest a method which allows higher density packaging of semiconductor devices by stacking the semiconductor devices.
Incidentally, in stacking of the semiconductor devices having a conventional configuration, a relationship between (i) a height of a connecting terminal of an upper semiconductor device and (ii) a height of sealing resin of a lower semiconductor device is important.
The following describes about this point, with reference to FIG. 15 to FIG. 17. FIG. 15 is a cross sectional view illustrating a stack of two conventional semiconductor devices.
In FIG. 15, a semiconductor device 200 is stacked on a semiconductor device 100. Of the two semiconductor devices, the semiconductor device 100 includes: a base substrate 101; a semiconductor chip 103 mounted on the base substrate 101; external connection terminals 107 provided on a bottom surface of the base substrate 101; and external connection terminals 108 provided on an upper surface of the base substrate 101. The semiconductor chip 103 and the base substrate 101 are electrically connected with each other via a wire 104. Further, the semiconductor chip 103 and the wire 104 are covered with a resin layer 106. On the other hand, a region, of the base substrate 101, where the external connection terminals 108 are provided is not covered by the resin layer 106, and is exposed.
The semiconductor device 200 has the same configuration as that of the semiconductor device 100, except in that a resin layer 106 covers the entire region above a base substrate 101, instead of covering regions other than a region where a semiconductor chip 103 and a wiring 104 are formed.
For example, the following problems may take place in a case where the two semiconductor devices 100 and 200 are stacked as illustrated in FIG. 15. Namely, if a height “s” of each of the external connection terminals 107 of the semiconductor device 200 is lower than a height “t” of the resin layer 106 of the semiconductor device 100, there will be a gap “u” between the external connection terminal 107 of the semiconductor device 200 and one of the external connection terminals 108 of the semiconductor device 100. Due to this gap “u”, it is unable to connect the semiconductor device 100 with the semiconductor device 200. Accordingly, in order to connect the semiconductor device 100 and the semiconductor device 200, it is necessary to satisfy the relationship of “s”>“t”, where “s” is the height of the external connection terminal 107 of the semiconductor device 200, and the “t” is the height of the resin layer 106 of the semiconductor device 100.
If the height “t” of the external connection terminal 107 of the semiconductor device 200 is reduced, the height “t” of the resin layer 106 of the semiconductor device 100 also has to be reduced. However, reduction of the high “t” of the resin layer 106 of the semiconductor device 100 requires a technology for reducing the thickness of the semiconductor device 100: e.g., a technology for reducing the thickness of the semiconductor chip 103, or a technology for lowering the height of the loop formed by the wiring 104. This causes technical difficulty in the production of the semiconductor device 100. A similar problem occurs in a case of stacking semiconductor devices illustrated in FIG. 16.
FIG. 16 is a cross sectional view illustrating a stack of two conventional semiconductor devices. In FIG. 16, a semiconductor device 400 is stacked on the semiconductor device 300. The semiconductor device 300 has an external connection terminal 108 formed on a semiconductor chip 103. A region where the external connection terminal 108 is formed is not covered by a resin layer 106, and the region therefore is exposed. Other than what mentioned above, the configuration of the semiconductor device 300 is the same as that of the foregoing semiconductor device 100. Further, the configuration of the semiconductor device 400 is similar to that of the foregoing semiconductor device 200.
FIG. 17 is a cross sectional view illustrating a resin-sealing process carried out in a manufacturing process of a conventional semiconductor device. In manufacturing of the above mentioned semiconductor device 300, the following problem occurs in the resin-sealing process. Namely, for example, if a transfer mold is used for carrying out the resin-sealing process for covering, with a resin 106, the semiconductor chip 103 except for the region where the external connection terminal 108 is formed, a mold 50 directly presses the wiring layer 108 on the semiconductor chip 103, which layer includes conductive layer x and an insulation layer y (See FIG. 17). The thickness of the wiring layer 108 is approximately 50 μm and is thin. Further, the material of the wiring layer 108 is hardly deformed. As such, the wiring layer 108 will not be able to absorb the stress applied by the mold 50. As a result, a strong stress is applied to the semiconductor chip 103, and this strong stress may cause damage to the semiconductor chip 103.
SUMMARY OF THE TECHNOLOGY
In view of the foregoing problems, the technology was made, and it is one of objects of the present technology to contribute to realization of higher density packaging of semiconductor devices, by providing a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.
Further, it reduces, through a simple process, damage to a semiconductor chip or the like in such a configuration that an external connection terminal is exposed from a resin layer.
In order to achieve the objects, the semiconductor device includes: a base substrate; a semiconductor chip electrically connected to the base substrate; a resin layer covering at least a portion of the semiconductor chip; and a first external connection terminal electrically connected to the base substrate, wherein the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
In the configuration, the first external connection terminal has the exposed surface which is exposed from the surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane. Therefore, at a time of stacking another semiconductor device on the semiconductor device of the present technology, the first external connection terminal is connected with an external connection terminal of the upper semiconductor device, even if the external connection terminal of the upper semiconductor device is low. Incidentally, in a case where external connection terminals of the upper semiconductor device are arranged at a narrow pitch, the height of each of the external connection terminals is low. However, with the configuration, the resin layer does not block the external connection terminal from reaching the first external connection terminal. Thus, it is not necessary to lower the resin layer for the purpose of acquiring a connection between the external connection terminals. As a result, the semiconductor device is high in its connection reliability, and is easily manufactured without a need for a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
Further, instead of exposing the wiring layer formed on the semiconductor chip, the above described first external connection terminal is used for acquiring the connection with the upper semiconductor device. This reduces damage to the semiconductor chip even if the semiconductor device is sealed with a resin by using a transfer mold or the like.
In order to achieve the objects, a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including (i) a base substrate, (ii) a semiconductor chip electrically connected to the base substrate, (iii) a resin layer covering at least a portion of the semiconductor chip, and (iv) a first external connection terminal electrically connected to the base substrate, the method comprising the step of: (A) sealing with a resin such that (a) the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and (b) the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
With the configuration, it is possible to manufacture a semiconductor device in which (i) a first external connection terminal having the exposed surface which is exposed from a surface of the resin layer, and (ii) the exposed surface and the surface of the resin layer form a single plane. Thus, at a time of stacking another semiconductor device on the semiconductor device, the semiconductor devices are connected with each other, even if an external connection terminal of the upper semiconductor device is low. Incidentally, in a case where external connection terminals of the upper semiconductor device are arranged at a narrow pitch, the height of each of the external connection terminals is low. However, with the configuration, the resin layer does not block the external connection terminal from reaching the first external connection terminal. Thus, with this manufacturing method, it is not necessary to lower the resin layer for the purpose of acquiring a connection with the upper semiconductor device. As a result, the method allows easy manufacturing of a semiconductor device which is high in its connection reliability, and the method does not require a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
Further, damage to the semiconductor chip is reduced by (i) forming and deforming the external connection terminal, and then (ii) carrying out the resin-sealing process, instead of exposing the wiring layer formed on the surface of the semiconductor chip for the purpose of acquiring the connection with the upper semiconductor device.
Further, in order to achieve the objects, the method may be so adapted that the step (A) includes the sub steps of: pressing a mold against the first external connection terminal to flatten a surface of the first external connection terminal; and sealing with the resin such that (a) the first external connection terminal has the exposed surface which is exposed from the surface of the resin layer, and (b) the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
In the configuration, the sub step of sealing is carried out after the external connection terminal is deformed by pressing the mold against the external connection terminal. With this simple process, it is possible to expose, from the resin layer, the exposed surface of the external connection terminal, and to form a single plane including the exposed surface and the surface of the resin layer. Thus, a semiconductor device is easily manufactured.
Additional objects, features, and strengths of the present technology will be made clear by the description below. Further, the advantages will be evident from the following explanation in reference to the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross sectional view illustrating a configuration of a semiconductor device of an embodiment.
FIG. 2 is a plane view illustrating the semiconductor device of FIG. 1 viewed from above.
FIG. 3( a) is a cross sectional view illustrating a semiconductor device manufacturing process of an embodiment.
FIG. 3( b) is a cross sectional view illustrating a semiconductor device manufacturing process of an embodiment.
FIG. 3( c) is a cross sectional view illustrating a semiconductor device manufacturing process of an embodiment.
FIG. 4 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 1.
FIG. 5 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 2.
FIG. 6 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 3.
FIG. 7 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 4.
FIG. 8 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 5.
FIG. 9 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 6.
FIG. 10 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 7.
FIG. 11 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 8.
FIG. 12 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 9.
FIG. 13 is a cross sectional view illustrating a configuration of a semiconductor device of Alternative Example 10.
FIG. 14 is a cross sectional view illustrating a configuration of a stacked semiconductor device.
FIG. 15 is a cross sectional view illustrating a stack of two conventional semiconductor devices.
FIG. 16 is a cross sectional view illustrating a stack of two conventional semiconductor devices.
FIG. 17 is a cross sectional view illustrating a resin-sealing step carried out in a conventional manufacturing process of a semiconductor device.
 DESCRIPTION OF THE EMBODIMENTS
The following describes an embodiment with reference to FIG. 1 through FIG. 14. Note that the following explanation contains expressions such as “upper surface”, “lower surface”, “above”, and “below”, each of which is based on top and bottom of the drawings. However, these expressions are used for the sake of simple explanation, and are not meant to limit which one of surfaces faces upward (or downward).
FIG. 1 is a cross sectional view illustrating a configuration of a semiconductor device. FIG. 2 is a plane view illustrating the semiconductor device of FIG. 1 which is viewed from above.
As illustrated in FIG. 1, a semiconductor device 20 of the present embodiment includes: a base substrate 1; a semiconductor chip 3 mounted on an adhesive layer 2 on the base substrate 1; and external connection terminals (second external connection terminals) 7 provided on the bottom surface of the base substrate 1. The base substrate 1 and the semiconductor chip 3 are electrically connected with each other via a wire 4.
On the upper surface of the semiconductor chip 3, a wiring layer 9 is formed, and external connection terminals (first external connection terminals) 8 which are electrically conductive projections formed on the wiring layer 9. As illustrated in FIG. 2, these external connection terminals 8 are arranged in an area-array manner. Further, The wiring layer 9 and the base substrate 1 are connected with each other via the wire 4.
Further, the semiconductor device 20 is sealed by a resin layer 6. More specifically, the resin layer 6 covers: the upper surface of the base substrate 1, the adhesive layer 2, the semiconductor chip 3, the wire 4, and the wiring layer 9. For example, a suitable material of the resin layer 6 may be: epoxy resin, silicone resin, or the like. However, the material of the resin layer 6 is not particularly limited.
A characteristic of the semiconductor device 20 of the present embodiment is that each of the external connection terminals 8 is in the same plane as the surface of the resin layer 6, and is exposed from the surface of the resin layer 6. In other words, a surface (exposed surface) of the external connection terminal 8 and the surface of the resin layer 6 form a single plane. This is also rephrased as the surface of the external connection terminal 8 and the surface of the resin layer 6 are at the same height.
Here, the wording “in the same plane” does not mean “exactly in the same plane”. That is, the external connection terminal 8 can be substantially in the same plane as the surface of the resin layer 6, and yet the following effect is obtained.
As described above, the surface of the external connection terminal 8 is exposed from the resin layer 6, so that the external connection terminal 8 is formed on the surface of the semiconductor device 20. Thus, at the time of stacking, on the semiconductor device 20, another semiconductor device whose external connection terminal is low, the external connection terminal 8 of the semiconductor device 20 is connected with an external connection terminal of the upper semiconductor device. In other words, the resin layer 6 does not block the external connection terminal of the upper semiconductor device from reaching the external connection terminal 8, even if the height of the external connection terminal of the upper semiconductor device is lowered for the purpose of achieving a higher density integration. Since the height of the resin layer 6 does not need to be reduced for acquiring a connection between the semiconductor device 20 and the upper semiconductor device, the semiconductor device 20 of the present embodiment is high in its connection reliability, and is easily manufactured without a need for a technology to reduce the thickness of the semiconductor device 20, such a technology being a technology for reducing the thickness of the semiconductor chip 3, a technology for lowering the loop of the wire 4, or the like.
Further, in the semiconductor device 20 of the present embodiment, the wiring layer 9 formed on the surface of the semiconductor chip 3 is not exposed from the resin layer 6; i.e., the wiring layer 9 is covered with the resin layer 6. As such, the wiring layer 9 formed on the surface of the semiconductor chip 3 does not have to be covered with a mold during a resin-sealing process. This reduces damage to the semiconductor chip 3, which occurs during the resin-sealing process.
Further, it is easy to electrically connect the semiconductor device 20 of the present embodiment with the upper semiconductor device. This is because each of the external connection terminals 8 of the semiconductor device 20 is electrically connected to the base substrate 1 via the wiring layer 9.
Further, in the semiconductor device 20 of the present embodiment, the wiring layer 9 is formed on the upper surface of the semiconductor chip 3. This allows reduction of the thickness of the semiconductor device 20.
Next described is a manufacturing method for the semiconductor device 20 of the present embodiment. FIG. 3( a) to FIG. 3( c) are cross sectional views illustrating a manufacturing process of the semiconductor device of the present embodiment.
First, as illustrated in FIG. 3( a), a semiconductor chip 3 is mounted on an adhesive layer 2 which is provided on a base substrate 1. The semiconductor chip 3 has thereon a wiring layer 9 and external connection terminals 8 which are formed prior to the mounting of the semiconductor chip 3. Note that it is possible to mount, on the base substrate 1, the semiconductor chip 3 on which the wiring layer 9 has been formed beforehand, and then mount the external connection terminal 8. Then, the semiconductor chip 3 and wiring layer 9 are electrically connected with the base substrate 1 via the wire 4.
Next, a resin-sealing process is carried out in such a manner that the external connection terminal 8 is in the same plane as the surface of the resin layer 6, and is exposed from the surface of the resin layer 6 (sealing process). Here, a mold 50 is pressed as illustrated in FIG. 3( b) so as to deform the external connection terminal 8. More specifically, a surface, of the mold 50, which touches the external connection terminal 8 is flat. By pressing such a mold 50, the upper surface of the external connection terminal 8 is flattened. It is preferable that the external connection terminal 8 be made of a material which is easily deformed, so that the process is easily carried out. For example, such a material may be solder or copper.
In a case of using solder as the material of the external connection terminal 8, the solder will be melted and become flowable, if a mold temperature surpasses the melting point of the solder, at the time of carrying out the resin-sealing process. In general, the mold temperature during the resin-sealing process is between 150° C. and 200° C. On this account, it is preferable to adopt solder having a melting point of 200° C. or higher.
Then, as illustrated in FIG. 3( c), the resin-sealing process is carried out in such a manner that the external connection terminal 8 is in the same plane as the surface of the resin layer 6, and is exposed from the surface of the resin layer 6.
Lastly, an external connection terminal 7 is formed on the bottom surface of the base substrate 1. Note that the external connection terminal 7 does not necessarily have to be formed after the resin-sealing process, and it is possible to form the external connection terminal 7 prior to the resin-sealing process.
As described, the manufacturing method for the semiconductor device 20 of the present embodiment includes the resin-sealing process, and the sealing process is carried out by using the mold 50. This manufacturing method easily realizes the external connection terminal 8, of the semiconductor device 20, which terminal is (i) in the same plane as the surface of the resin layer 6, and (ii) exposed from the surface of the resin layer 6. Thus, the semiconductor device 20 is easily manufactured. According to the above explanation, the manufacturing method uses the mold 50. However, the manufacturing method is not particularly limited to the method using the mold 50, provided that the external connection terminal 8 is exposed from the resin layer 6: i.e., the external connection terminal 8 is formed on the surface of the semiconductor device 20.
The following describes alternative examples of the semiconductor device 20. Note that the same symbols are given for members having the same functions as those described hereinabove, and the explanations therefor are omitted.
Alternative Example 1
FIG. 4 is a cross sectional view illustrating a configuration of a semiconductor device 20 a of Alternative Example 1. As illustrated in FIG. 4, a semiconductor chip 3 in the semiconductor device 20 a is connected to a base substrate 1 by a flip-chip bonding using a bump 10, instead of connecting the semiconductor chip 3 and the base substrate 1 via a wire 4.
The semiconductor device 20 a has the same configuration as that of the foregoing semiconductor device 20, except for the above described point.
As described, the flip-chip bonding technique is used in the semiconductor device 20 a of the present alternative example, so that the semiconductor chip 3 is mounted on the base substrate 1 at a higher density.
A method for manufacturing this semiconductor device 20 a is the same as the foregoing manufacturing method for the semiconductor device 20, except in that a flip-chip bonding is carried out for connecting the semiconductor chip 3 with the base substrate 1.
Alternative Example 2
FIG. 5 is a cross sectional view illustrating a configuration of a semiconductor device 20 b of Alternative Example 2. In the foregoing semiconductor devices 20 and 20 a, the wiring layer 9 is directly formed on the semiconductor chip 3. However, in the semiconductor device 20 b, a wiring layer 9 is formed on a supporting member 11. This wiring layer 9 on the supporting member 11 is mounted on an adhesive layer 12 which is provided on a semiconductor chip 3. As described, the wiring layer 9 is formed on the supporting member 11, and the wiring layer 9 on the supporting member 11 is mounted on the adhesive layer 12 on the semiconductor chip 3. With this configuration, a stress applied to the semiconductor chip is reduced by the supporting member 11 and the adhesive layer 12. Thus, damage to the semiconductor chip 3 is reduced. The supporting member 11 and the adhesive layer 12 are insulative members. By adopting, for these members, a material whose elasticity is low, the members further absorb the stress applied to the semiconductor chip 3, thus reducing the damage to the semiconductor chip 3.
Respective areas of the supporting member 11 and the wiring layer 9 formed on the supporting member 11 may be larger than the area of the semiconductor chip 3. In other words, the size of the wiring layer 9 may be larger than that of the semiconductor chip 3. By forming the wiring layer 9 through a broader region than the semiconductor chip 3, upper and lower semiconductor devices can be stacked even if the upper semiconductor device has a larger area of an external connection terminal array than the lower semiconductor chip.
The semiconductor chip 3 is connected with a base substrate 1 via a wire 4. On the other hand, the wiring layer 9 and the base substrate 1 are connected via a wire 5.
Since there is no sufficient space for providing the wire 4 between the semiconductor chip 3 and the adhesive layer 12, the wire 4 is extended through the inside of the adhesive layer 12. In other words, the wire 4 is wrapped by the adhesive layer 12. Since the wire 4 is wrapped by the adhesive layer 12, a wire deformation which occurs in the resin-sealing process is restrained.
The semiconductor device 20 b has the same configuration as the foregoing semiconductor device 20, except for the above described point. Accordingly, the above described manufacturing method for the semiconductor device 20 can be used as to: (i) forming and deforming external connection terminals 8, and (ii) carrying out the resin-sealing process.
Alternative Example 3
FIG. 6 is a cross sectional view illustrating a configuration of a semiconductor device 20 c of Alternative Example 3. The configuration of the semiconductor device 20 c is substantially the same as the semiconductor device 20 b of Alternative Example 2. However, as illustrated in FIG. 6, the configuration of the semiconductor device 20 c differs from the semiconductor device 20 b in that a spacer layer 13 is provided on an adhesive layer 18 which is provided on a semiconductor chip 3.
With the provision of the spacer layer 13, a sufficient space for a wire 4 is acquired between the semiconductor chip 3 and an adhesive layer 12. Accordingly, in the semiconductor device 20 c of the present alternative example, the wire 4 is not extended through the adhesive layer 12. This improves the reliability of the connection between the semiconductor chip 3 and the wire 4. Further, the supporting member 11 and the spacer layer 13 can be made of a heat conductive material. In this case, a heat dissipating characteristic is improved.
The above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 c as to: (i) forming and deforming the external connection terminals 8, and (ii) carrying out the resin-sealing process.
Alternative Example 4
FIG. 7 is a cross sectional view illustrating a configuration of a semiconductor device 20 d of Alternative Example 4. Unlike the semiconductor device 20 b of Alternative Example 2, a semiconductor chip 3 and a base substrate 1 in the semiconductor device 20 d are connected by a flip-chip boding using a bump 10, as illustrated in FIG. 7. Other than that, the configuration of the semiconductor device 20 d is the same as the semiconductor 20 b of Alternative Example 2.
As described, the flip-chip bonding technique is used in the semiconductor device 20 d of the present alternative example, so that the semiconductor chip 3 is mounted on the base substrate 1 at a higher density. This semiconductor device 20 d does not require its adhesive layer 12 to be thickened, as is the case of Alternative Example 2, nor does it require a spacer layer 13 as is required in Alternative Example 3. Thus, it is possible to reduce the thickness of the semiconductor device.
A method for manufacturing this semiconductor device 20 b is the same as the foregoing manufacturing method for the semiconductor device 20, except in that a flip-chip bonding is carried out for connecting the semiconductor chip 3 with the base substrate 1.
Alternative Example 5
FIG. 8 is a cross sectional view illustrating a configuration of a semiconductor device 20 e of Alternative Example 5. In the foregoing semiconductor devices 20, and 20 a to 20 d, the external connection terminals 8 are provided on the semiconductor chip 3 via the wiring layer 9. On the other hand, in the semiconductor device 20 e, external connection terminals 8 are directly provided on a base substrate 1, and are electrically connected with the base substrate 1, as illustrated in FIG. 8.
The semiconductor device 20 e has the same configuration as the semiconductor device 20, except for the above described point.
As described, in the semiconductor device 20 e of the present alternative example, each of the external connection terminals 8 is formed on the base substrate 1, and not above a semiconductor chip 3. Accordingly, a stress applied to the external connection terminal 8 by a mold used in a resin-sealing process is not applied to the semiconductor chip 3. This further reduces damage to the semiconductor chip 3. Further, this is also advantageous in that the height of the semiconductor device is lowered.
The above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 e as to: (i) forming and deforming the external connection terminals 8, and (ii) carrying out the resin-sealing process.
Alternative Example 6
FIG. 9 is a cross sectional view illustrating a configuration of a semiconductor device 20 f of Alternative Example 6. As in the semiconductor device 20 e of Alternative Example 5, external connection terminals 8 in the semiconductor device 20 f are directly provided on a base substrate 1, and are electrically connected to the base substrate 1.
As illustrated in FIG. 9, the semiconductor device 20 f differs from the semiconductor device 20 e, in that (1) a semiconductor chip 3 is provided in an opening portion 16 of the base substrate 1, and (2) another semiconductor chip 3 is stacked on the semiconductor chip 3, and both of the semiconductor chips 3 are electrically connected to the base substrate 1 via a wire 4 and a wiring layer 9, respectively.
The semiconductor device 20 f has the same configuration as the semiconductor device 20 e of Alternative Example 5, except for the above described point.
As described, the semiconductor device 20 f of the present alternative example includes two semiconductor chips 3 provided in the aperture section 16 of the base substrate 1, so that the semiconductor chips 3 are mounted at a higher density than a case where the semiconductor chips 3 are provided on the base substrate 1.
Note that the present alternative example deals with a case where the number of the semiconductor chips 3 is two. However, the number of the semiconductor chips 3 being mounted is not limited to two. In a case where a single semiconductor chip 3 is mounted, it is possible to realize a thinner semiconductor device than a case of providing a semiconductor chip 3 on the base substrate 1. Accordingly, a higher density packaging is achieved in such a case as well. Further, in a case of stacking three or more semiconductor chips 3, the semiconductor chips are mounted at a higher density than a case of mounting the same number of semiconductor chips on the base substrate 1.
The above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 f as to: (i) forming and deforming the external connection terminals 8, and (ii) carrying out the resin-sealing process.
Alternative Example 7
FIG. 10 is a cross sectional view illustrating a configuration of a semiconductor device 20 g of Alternative Example 7. As in the semiconductor device 20 e of Alternative Example 5, external connection terminals 8 in the semiconductor device 20 g are directly provided on a base substrate 1, and are electrically connected to the base substrate 1.
As illustrated in FIG. 10, the semiconductor device 20 g differs from the semiconductor device 20 e, in that (1) a semiconductor chip 3 is provided in a depressed portion 17 of the base substrate 1, and (2) another semiconductor chip 3 is stacked on the semiconductor chip 3, and both of the semiconductor chips 3 are electrically connected to the base substrate 1 via a wire 4. In the present alternative example, the lower semiconductor chip 3 and the base substrate 1 are directly connected via the wire 4, and not via the wiring layer 9. However, the lower semiconductor chip 3 may be connected via the wiring layer 9. Further, the upper semiconductor chip 3 and the base substrate 1 are directly connected via the wire 4 and the wiring layer 9. However, it is not necessary to connect the upper semiconductor chip 3 via the wiring layer 9, and the upper semiconductor chip 3 may be directly connected to the base substrate 1.
The semiconductor device 20 g has the same configuration as the semiconductor device 20 e of Alternative Example 5, except for the above described point.
As described, the semiconductor device 20 g of the present alternative example includes the semiconductor chips 3 which are provided in the depressed portion 17 of the base substrate 1. This configuration allows the semiconductor chips 3 to be mounted at a higher density than a case where the semiconductor chips 3 are provided on a portion of the base substrate 1 other than the depressed portion 17 of the base substrate 1.
Further, a provision of the depressed portion 17 on the base substrate 1 causes less deterioration in the mechanical strength of the semiconductor device, when compared with the configuration of Alternative Example 6, in which the base substrate 1 is provided with the opening portion 16.
As in Alternative Example 2, the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 g as to: (i) forming and deforming the external connection terminals 8, and (ii) carrying out the resin-sealing process.
Alternative Example 8
FIG. 11 is a cross sectional view illustrating a configuration of a semiconductor device 20 h of Alternative Example 8. As illustrated in FIG. 11, the surface of a resin layer 6 of the semiconductor device 20 h is not flat. The surface of the resin layer 6 in a region 14 having external connection terminals 8 is lower (i.e., depressed toward a base substrate 1) than the surface of the resin layer 6 in a region 15 which is a region other than the region 14. Other than that, the configuration of the semiconductor device 20 h is the same as the semiconductor device 20.
As described, by depressing the surface of the resin layer 6 in the region having the external connection terminals 8, each external connection terminal of a semiconductor device laminated above the semiconductor device 20 h is partially housed in the depressed portion. This configuration allows for an even higher density packaging.
As in Alternative Example 2, the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 h as to: (i) forming and deforming the external connection terminals 8, and (ii) carrying out the resin-sealing process. Note, however, that a mold 50 to be used is preferably a mold illustrated in FIG. 17, or the like, whose portion corresponding to the depressed portion of the surface of the resin layer 6 is projected.
Alternative Example 9
FIG. 12 is a cross sectional view illustrating a configuration of a semiconductor device 20 i of Alternative Example 9. As illustrated in FIG. 12, in the semiconductor device 20 i, the surface of a resin layer 6 in a region 14 having external connection terminals 8 is lower (i.e., depressed toward a base substrate 1) than the surface of the resin layer 6 in a region 15 which is a region other than the region 14, as in the case of the foregoing semiconductor device 20 h.
Each of the external connection terminal 8 in the semiconductor device 20 i is directly formed on the base substrate 1, and is electrically connected. Accordingly, in the semiconductor device 20 i, a region 14 having the external connection terminals 8 is arranged on both sides of the region 15 which is a region other than the region 14, while the region 15 is arranged on both sides of the region 14 having the external connection terminals 8, in the semiconductor device 20 h.
The configuration of the semiconductor device 20 i is the same as the semiconductor device 20 h of Alternative Example 8, other than the above described point.
As described, each of the external connection terminal 8 is formed on the base substrate 1, and not above the semiconductor chip 3. With this configuration, the stress applied to the external connection terminal 8 by the mold used in the resin-sealing process is prevented from being applied to the semiconductor chip 3. Thus, damage to the semiconductor chip 3 is further reduced.
Further, by depressing the surface of the resin layer 6 in the region having the external connection terminals 8, each external connection terminal of a semiconductor device laminated above the semiconductor device 20 i is partially housed in the depressed portion. This configuration allows for an even higher density packaging.
As in Alternative Example 2, the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 i as to: (i) forming and deforming the external connection terminals 8, and (ii) carrying out the resin-sealing process. Note, however, that a mold 50 to be used is preferably a mold illustrated in FIG. 17 or the like whose portion corresponding to the depressed portion of the surface of the resin layer 6 is projected.
Alternative Example 10
FIG. 13 is a cross sectional view illustrating a configuration of a semiconductor device 20 j of Alternative Example 10. As illustrated in FIG. 13, the semiconductor device 20 j includes: a base substrate 1; three semiconductor chips 3 a to 3 c which are stacked on the base substrate 1; and external connection terminals (second external connection terminals) 7 provided on the bottom surface of the base substrate 1.
An adhesive layer is provided on the base substrate 1, and the lower semiconductor chip 3 a is provided on the adhesive layer on the base substrate 1. This semiconductor device 3 a is electrically connected with the base substrate 1 by a flip-chip bonding using a bump 10.
Further, an adhesive layer is formed on the lower semiconductor chip 3 a, and the middle semiconductor chip 3 b is provided on the adhesive layer on the lower semiconductor chip 3 a. This semiconductor chip 3 b is electrically connected with the base substrate 1 via a wire 4. The wire 4 connecting the middle semiconductor chip 3 b with the base substrate 1 is extended through the inside of an adhesive layer provided on the middle semiconductor chip 3 b.
The upper semiconductor chip 3 c is provided on the adhesive layer which is provided on the middle semiconductor chip 3 b. This upper semiconductor chip 3 c is electrically connected to the base substrate 1 via a wire 4. On this upper semiconductor chip 3 c, an adhesive layer is provided, and a spacer layer 13 is provided on the adhesive layer on the semiconductor chip 3 c. Therefore, the wire 4 which connects the upper semiconductor chip 3 c with the base substrate 1 is not extended through the inside of the adhesive layer.
The spacer layer 13 has thereon an adhesive layer, and a supporting member 11 is provided on the adhesive layer on the spacer layer 13. Further, the supporting member 11 has thereon a wiring layer 9, and an external connection terminals (first external connection terminals) 8 which are electrically conductive projections formed on the wiring layer 9. As is the case of the configuration of FIG. 2, these external communication terminals 8 are arranged in an area-array manner. The wiring layer 9 and the base substrate 1 are connected via a wire 5.
Further, the semiconductor device 20 j is sealed by a resin layer 6. More specifically, the resin layer 6 entirely covers the members formed on the upper surface of the base substrate 1, except for the external connection terminals 8.
As in the foregoing semiconductor device 20, each of the external connection terminals 8 in the semiconductor device 20 j is in the same plane as the surface of the resin layer 6, and is exposed from the surface of the resin layer 6. In other words, the surface of the external connection terminal 8 and the surface of the resin layer 6 form a single surface. This is also rephrased as the surface of the external connection terminal 8 and the surface of the resin layer 6 are at the same height. Here, the description reading “in the same plane as the surface of the resin layer 6” does not mean that the surface of the external connection terminal 8 has to be exactly in the same plane as the surface of the resin layer 6, and the surface of the external connection terminal 8 may be substantially in the same plane as the surface of the resin layer 6.
As described, three semiconductor chips 3 a to 3 c are mounted in the semiconductor device 20 j of the present alternative example. Thus, it is possible to achieve an even higher density packaging.
Note that the present alternative example deals with a case where three semiconductor chips 3 are stacked, however, the number of the semiconductor chips 3 is not limited to three. It is possible to stack two semiconductor chips 3, or stack four or more semiconductor chips 3. Further, how the semiconductor chips 3 are mounted is not particularly limited.
As in Alternative Example 2, the above described manufacturing method for the semiconductor device 20 can be used for the semiconductor device 20 j as to: (i) forming and deforming the external connection terminals 8, and (ii) carrying out the resin-sealing process.
Next described is a stacked semiconductor device. FIG. 14 is a cross sectional view illustrating the configuration of a stacked semiconductor device 40.
As illustrated in FIG. 14, the foregoing semiconductor 20 i is stacked on the foregoing semiconductor device 20, and another semiconductor device 30 is stacked on the semiconductor 20 i.
The external connection terminals 8 of the semiconductor device 20 are respectively jointed to the external connection terminals 7 of the semiconductor device 20 i, so that the semiconductor devices 20 and 20 i are electrically connected with each other.
The semiconductor device 30 has on its bottom surface external connection terminals 7. The external connection terminals 8 of the semiconductor device 20 i are respectively jointed to the external connection terminals 7 of the semiconductor device 30, so that the semiconductor devices 20 i and 30 are electrically connected with each other.
As described, the external connection terminals 8 of the semiconductor device 20 are in the same plane as the surface of the resin layer 6, and are exposed from the surface of the resin layer 6. Accordingly, even if the respective heights of the external connection terminals 7 of the semiconductor device 20 i is low, the external connection terminals 8 of the semiconductor device 20 and the external connection terminal 7 of the semiconductor device 20 i are respectively connected with each other. Similarly, the external connection terminals 8 of the semiconductor device 20 i are also in the same plane as the surface of the resin layer 6, and are exposed from the surface of the resin layer 6. Accordingly, even if the respective heights of the external connection terminals 7 of the semiconductor device 30 are low, the external connection terminals 8 of the semiconductor device 20 i and the external connection terminals 7 of the semiconductor device 30 are respectively connected with each other.
As described above, the semiconductor device 40 is formed by stacking the semiconductor devices 20, 20 i, and 30, and electrically connecting them with one another. This configuration allows lowering of the external connection terminals 7 while avoiding deterioration in the connection stability. As a result, a high density packaging of semiconductor devices is possible.
Note that the above explanation deals with a case where the number of semiconductor devices to be stacked is three. However, the number of the semiconductor devices to be stacked is not limited to this, and it is possible to stack two semiconductor devices, or stack four or more semiconductor devices.
Further, the above explanation deals with a case where the semiconductor devices 20, 20 i, and 30 are stacked. However, the semiconductor device 30 can be stacked on any one of or more than one of the semiconductor devices 20, and 20 a to 20 j. Alternatively, it is possible to stack a plurality of semiconductor devices selected from the semiconductor devices 20, and 20 a to 20 j.
It will be obvious that the above-described devices and methods may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the disclosure, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
As described, a semiconductor device includes: a base substrate; a semiconductor chip electrically connected to the base substrate; a resin layer covering at least a portion of the semiconductor chip; and a first external connection terminal electrically connected to the base substrate, wherein the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
In the configuration, the first external connection terminal has the exposed surface which is exposed from the surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane. Therefore, at a time of stacking another semiconductor device on the semiconductor device as disclosed, the first external connection terminal is connected with an external connection terminal of the upper semiconductor device, even if the external connection terminal of the upper semiconductor device is low. Incidentally, in a case where external connection terminals of the upper semiconductor device are arranged at a narrow pitch, the height of each of the external connection terminals is low. However, with the configuration, the resin layer does not block the external connection terminal from reaching the first external connection terminal. Thus, it is not necessary to lower the resin layer for the purpose of acquiring a connection between the external connection terminals. As a result, the semiconductor device is high in its connection reliability, and is easily manufactured without a need for a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
Further, instead of exposing the wiring layer formed on the semiconductor chip, the above described first external connection terminal is used for acquiring the connection with the upper semiconductor device. This reduces damage to the semiconductor chip even if the semiconductor device is sealed with a resin by using a transfer mold or the like.
The semiconductor device may be adapted so that said first external connection terminal is electrically connected with the base substrate via a wiring layer.
By electrically connecting the first external connection terminal with the base substrate via the wiring layer as described above, an electrical connection between the semiconductor device of the present technology and the upper semiconductor device is easily acquired.
The semiconductor device may be adapted so that said wiring layer is formed on a surface, of the semiconductor chip, on a side of the external connection terminal.
In the configuration, the wiring layer is formed on the surface, of the semiconductor chip, on the side of the first external connection terminal. This is more advantageous in terms of reducing the thickness of a semiconductor device, when compared to a later described case where supporting member and/or an adhesive layer is/are interposed.
The semiconductor device may be adapted so that said wiring layer is formed on a supporting member, and is mounted on the semiconductor chip.
By forming the wiring layer on the supporting member, and by mounting the wiring layer on an adhesive layer on the semiconductor chip, a stress to be applied to the semiconductor chip is reduced by the supporting member and the adhesive layer. Thus, damage to the semiconductor chip is further reduced.
The semiconductor device may be adapted so that an area of a region in which the wiring layer is provided is larger than an area of the semiconductor chip. In short, the wiring layer may be larger than the semiconductor chip.
As described, by forming the wiring layer through a broader region than the semiconductor chip, the upper and lower semiconductor devices can be stacked even if the upper semiconductor device has a larger area of an external connection terminal array than the lower semiconductor chip.
The semiconductor device may be adapted so that said first external connection terminal is formed on the base substrate.
As described, the first external connection terminal is formed on the base substrate, and not above the semiconductor chip. With this configuration, the stress applied to the first external connection terminal by the mold used in a resin-sealing process is prevented from being applied to the semiconductor chip. Thus, damage to the semiconductor chip is further reduced. Further, this is also advantageous in that the height of the semiconductor device is lowered.
The semiconductor device may be adapted so that said semiconductor chip is provided in an aperture section of the base substrate.
By providing the semiconductor chip in the aperture section of the base substrate, it is possible to package semiconductor chips at a higher density than a case where the semiconductor chip is provided on the base substrate.
The semiconductor device may be adapted so that said semiconductor chip is provided in a depressed portion of the base substrate.
By providing the semiconductor chip in the depressed portion of the base substrate, it is possible to package semiconductor chips at a higher density than a case where the semiconductor chip is provided on the base substrate.
The semiconductor device may be adapted so that a first surface of the resin layer is depressed towards the base substrate so that the first surface is closer to the base substrate than a second surface of the resin layer is to the base substrate, the first surface being a surface of the resin layer in a region where the first external connection terminal is provided, and the second surface being a surface of the resin layer other than the first surface. In other words, the resin surface (first surface) of the region in which the first external connection terminal is provided may be lower than the resin surface (second surface) of the other region.
As described, by depressing the surface of the resin layer in the region having the first external connection terminal, the external connection terminal of a semiconductor device stacked above the semiconductor device of the present technology is partially housed in the depressed portion. This configuration allows for an even higher density packaging.
The semiconductor device may be adapted so that said first external connection terminal is made of a solder.
By using, as a material of the first external connection terminal, a solder which is easily deformable, the first external connection terminal is easily deformed. Further, it becomes easy to expose, from the resin layer, the exposed surface of the first external connection terminal, and form a single plane including the exposed surface and the surface of the resin layer.
The semiconductor device may be adapted so that said solder has a melting point of 200° C. or higher.
The mold temperature during the resin-sealing process, in general, is between 150° C. to 200° C. Accordingly, if the solder has the melting point of 200° C. or higher, it is possible to reduce the risk that the mold temperature surpasses the melting point of solder, and that the solder is melted and becomes flowable.
The semiconductor device may be adapted so that said first external connection terminal is made of copper.
By using, as a material of the first external connection terminal, copper which is easily deformable, the first external connection terminal is easily deformed. Further, it becomes easy to expose, from the resin layer, the exposed surface of the first external connection terminal, and form a single plane including the exposed surface and the surface of the resin layer.
Further, a semiconductor may include: a base substrate; a plurality of semiconductor chips each electrically connected to the base substrate; a resin layer covering at least a portion of the semiconductor chip; and a first external connection terminal electrically connected to the base substrate, wherein the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
It is possible to achieve a higher density packaging, by mounting a plurality of the semiconductor chips within the resin layer.
Further, as described, a stacked semiconductor device includes: any one of the above described semiconductor devices, and another one of the above described semiconductor devices further including a second external connection terminal, wherein the above semiconductor device is electrically connected with the another one of the above semiconductor devices, by jointing the first external connection terminal of the above semiconductor device with the second external connection terminal of the another one of the above semiconductor devices.
In the configuration, the semiconductor devices are electrically connected with each other by jointing the first external connection terminal to the second external connection terminal. This configuration allows for even higher density packaging.
Further, as described, a stacked semiconductor device includes: any one of the above described semiconductor devices, and another semiconductor device further including a second external connection terminal, wherein the above semiconductor device is electrically connected with the another semiconductor device, by jointing the first external connection terminal of the above semiconductor device with the second external connection terminal of the another semiconductor device.
In the configuration, the semiconductor devices are electrically connected with each other by jointing the first external connection terminal to the second external connection terminal. This configuration allows for even higher density packaging.
Further a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including (i) a base substrate, (ii) a semiconductor chip electrically connected to the base substrate, (iii) a resin layer covering at least a portion of the semiconductor chip, and (iv) a first external connection terminal electrically connected to the base substrate, the method comprising the step of: (A) sealing with a resin such that (a) the first external connection terminal has an exposed surface which is exposed from a surface of the resin layer, and (b) the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
With the configuration, it is possible to manufacture a semiconductor device in which (i) a first external connection terminal having the exposed surface which is exposed from a surface of the resin layer, and (ii) the exposed surface and the surface of the resin layer form a single plane. Thus, at a time of stacking another semiconductor device on the semiconductor device, the semiconductor devices are connected with each other, even if an external connection terminal of the upper semiconductor device is low. Incidentally, in a case where external connection terminals of the upper semiconductor device are arranged at a narrow pitch, the height of each of the external connection terminals is low. However, with the configuration, the resin layer does not block the external connection terminal from reaching the first external connection terminal. Thus, it is not necessary to lower the resin layer for the purpose of acquiring a connection with the upper semiconductor device. As a result, the method allows easy manufacturing of a semiconductor device which is high in its connection reliability, and the method does not require a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
Further, damage to the semiconductor chip is reduced by (i) forming and deforming the external connection terminal, and then (ii) carrying out the resin-sealing process, instead of exposing the wiring layer formed on the surface of the semiconductor chip for the purpose of acquiring the connection with the upper semiconductor device.
Further, the method may be adapted so that the step (A) includes the sub steps of: pressing a mold against the first external connection terminal to flatten a surface of the first external connection terminal; and sealing with the resin such that (a) the first external connection terminal has the exposed surface which is exposed from the surface of the resin layer, and (b) the exposed surface of the first external connection terminal and the surface of the resin layer form a single plane.
In the configuration, the sub step of sealing is carried out after the external connection terminal is deformed by pressing the mold against the external connection terminal. With this simple process, it is possible to expose, from the resin layer, the exposed surface of the external connection terminal, and to form a single plane including the exposed surface and the surface of the resin layer. Thus, a semiconductor device is easily manufactured.
Further, the method may further include the step of heating the mold to a temperature of not more than a melting point of the first external connection terminal.
By heating the mold to a temperature which is not more than the melting point of the external connection terminal, it is possible to reduce the risk that the mold temperature surpasses the melting point of solder, and that the solder is melted and becomes flowable.
In the semiconductor device, the first external connection terminal has the exposed surface, and the exposed surface of the first connection terminal and the resin layer form a single plane. Therefore, at a time of stacking another semiconductor device on the semiconductor device of the present technology, the first external connection terminal is connected with an external connection terminal of the upper semiconductor device, even if the external connection terminal of the upper semiconductor device is low. Thus, it is not necessary to lower the resin layer for the purpose of acquiring a connection between the external connection terminals. As a result, the semiconductor device of the present invention is high in its connection reliability, and is easily manufactured without a need for a technology to reduce the thickness of the semiconductor device, such a technology being a technology for reducing the thickness of the semiconductor chip, a technology for lowering the loop of the wire, or the like.
Further, instead of exposing the wiring layer formed on the semiconductor chip, the above described first external connection terminal is used for acquiring the connection with the upper semiconductor device. This reduces damage to the semiconductor chip even if the semiconductor device is sealed with a resin by using a transfer mold or the like.
The embodiments and concrete examples of implementation discussed in the foregoing detailed explanation serve solely to illustrate the technical details of the present technology, which should not be narrowly interpreted within the limits of such embodiments and concrete examples, but rather may be applied in many variations within the spirit of the present technology, provided such variations do not exceed the scope of the patent claims set forth below.

Claims (11)

1. A semiconductor device, comprising:
a base substrate;
a semiconductor chip electrically coupled to the base substrate;
a supporting member attached to the semiconductor chip, wherein a wiring layer is formed on a surface of the supporting member opposite the semiconductor chip;
a resin layer covering at least portions of the semiconductor chip and the supporting member; and
a plurality of external connection terminals that are electrically coupled to the wiring layer, wherein surfaces of the external connection terminals are exposed from the resin layer, and wherein the exposed surfaces of the external connection terminals are substantially co-planer with an exterior surface of the resin layer.
2. The semiconductor device as set forth in claim 1, wherein bonding wires electrically couple the wiring layer to the base substrate.
3. The semiconductor device as set forth in claim 1, wherein:
a first surface of the resin layer is depressed towards the base substrate so that the first surface is closer to the base substrate than a second surface of the resin layer is to the base substrate,
the first surface being a surface of the resin layer in a region where the external connection terminals are provided, and
the second surface being a surface of the resin layer other than the first surface.
4. The semiconductor device as set forth in claim 1, wherein said external connection terminals are made of a solder.
5. The semiconductor device as set forth in claim 1, wherein said external connection terminals are made of copper.
6. The semiconductor device as set forth in claim 2, wherein the bonding wires are encapsulated in the resin layer.
7. The semiconductor device as set forth in claim 2, wherein a plurality of solder bumps electrically couple the semiconductor chip to the base substrate.
8. The semiconductor device as set forth in claim 2, wherein bonding wires also electrically couple the semiconductor chip to the base substrate.
9. The semiconductor device as set forth in claim 4, wherein said solder has a melting point of 200° C. or higher.
10. The semiconductor device as set forth in claim 8, further comprising an adhesive layer that couples the supporting member to the semiconductor chip, wherein the bonding wires that electrically couple the semiconductor chip to the base substrate pass through the adhesive layer.
11. The semiconductor device as set forth in claim 8, further comprising a spacer position between the semiconductor chip and the supporting member, wherein the spacer provides sufficient space between the semiconductor chip and the supporting member to allow the bonding wires to pass, unobstructed, between the semiconductor chip and the base substrate.
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Cited By (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210435A1 (en) * 2000-08-23 2007-09-13 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
US20080169544A1 (en) * 2006-01-17 2008-07-17 Junji Tanaka Semiconductor device and method of fabricating the same
US20080230887A1 (en) * 2007-03-23 2008-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
US20090146301A1 (en) * 2007-12-11 2009-06-11 Panasonic Corporation Semiconductor device and method of manufacturing the same
US20100000775A1 (en) * 2008-07-03 2010-01-07 Advanced Semiconductor Engineering, Inc. Circuit substrate and method of fabricating the same and chip package structure
US20100171207A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Shen Stackable semiconductor device packages
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US20100171205A1 (en) * 2009-01-07 2010-07-08 Kuang-Hsiung Chen Stackable Semiconductor Device Packages
US20100181660A1 (en) * 2009-01-20 2010-07-22 Monolito Galera Multi-Chip Semiconductor Package
US20110049704A1 (en) * 2009-08-31 2011-03-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with integrated heatsinks
US20110117700A1 (en) * 2009-11-18 2011-05-19 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US20110156251A1 (en) * 2009-12-31 2011-06-30 Chi-Chih Chu Semiconductor Package
US20110193205A1 (en) * 2010-02-10 2011-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having stacking functionality and including interposer
US20110298129A1 (en) * 2010-06-08 2011-12-08 Samsung Electronics Co., Ltd. Stacked package
US20120205795A1 (en) * 2011-02-15 2012-08-16 Samsung Electronics Co., Ltd. Stacked package and method of manufacturing the same
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8569885B2 (en) 2010-10-29 2013-10-29 Advanced Semiconductor Engineering, Inc. Stacked semiconductor packages and related methods
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8643167B2 (en) 2011-01-06 2014-02-04 Advanced Semiconductor Engineering, Inc. Semiconductor package with through silicon vias and method for making the same
US20140117562A1 (en) * 2005-02-18 2014-05-01 Fujitsu Semiconductor Limited Semiconductor device
US20150111318A1 (en) * 2012-12-06 2015-04-23 Texas Instruments Incorporated Heterogeneous Integration of Memory and Split-Architecture Processor
US9123764B2 (en) 2012-08-24 2015-09-01 Infineon Technologies Ag Method of manufacturing a component comprising cutting a carrier
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US9196597B2 (en) 2010-01-13 2015-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101053079A (en) 2004-11-03 2007-10-10 德塞拉股份有限公司 Stacked packaging improvements
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP2008198916A (en) * 2007-02-15 2008-08-28 Spansion Llc Semiconductor device and manufacturing method thereof
JP5025443B2 (en) * 2007-12-11 2012-09-12 パナソニック株式会社 Semiconductor device manufacturing method and semiconductor device
JP2008205518A (en) * 2008-06-02 2008-09-04 Sharp Corp Method for manufacturing semiconductor device
KR20090130702A (en) * 2008-06-16 2009-12-24 삼성전자주식회사 Semiconductor package and method for manufacturing the same
TW201007924A (en) * 2008-08-07 2010-02-16 Advanced Semiconductor Eng Chip package structure
JP5340718B2 (en) * 2008-12-24 2013-11-13 新光電気工業株式会社 Manufacturing method of electronic device
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US8476750B2 (en) * 2009-12-10 2013-07-02 Qualcomm Incorporated Printed circuit board having embedded dies and method of forming same
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
KR101075241B1 (en) * 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US8421204B2 (en) * 2011-05-18 2013-04-16 Fairchild Semiconductor Corporation Embedded semiconductor power modules and packages
EP2535926A3 (en) * 2011-06-17 2015-08-05 BIOTRONIK SE & Co. KG Semiconductor package
KR101883152B1 (en) * 2011-08-04 2018-08-01 삼성전자 주식회사 Semiconductor device
CN102931169A (en) * 2011-08-10 2013-02-13 快捷半导体(苏州)有限公司 Embedded semiconductor power module and package thereof
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
JP2013225638A (en) * 2012-03-23 2013-10-31 Toshiba Corp Semiconductor device
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8906743B2 (en) * 2013-01-11 2014-12-09 Micron Technology, Inc. Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
KR102448238B1 (en) * 2018-07-10 2022-09-27 삼성전자주식회사 Semiconductor package
WO2023248606A1 (en) * 2022-06-20 2023-12-28 ソニーセミコンダクタソリューションズ株式会社 Package, semiconductor device, and method for producing package

Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06291221A (en) 1993-04-05 1994-10-18 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH08236665A (en) 1995-02-28 1996-09-13 Citizen Watch Co Ltd Resin sealed semiconductor device and manufacture thereof
JPH09330992A (en) 1996-06-10 1997-12-22 Ricoh Co Ltd Semiconductor device mounting body and its manufacture
JPH10135267A (en) 1996-10-30 1998-05-22 Oki Electric Ind Co Ltd Structure of mounting board and its manufacture
JPH10289923A (en) 1997-02-17 1998-10-27 Nittetsu Semiconductor Kk Manufacture of semiconductor package
US5831441A (en) * 1995-06-30 1998-11-03 Fujitsu Limited Test board for testing a semiconductor device, method of testing the semiconductor device, contact device, test method using the contact device, and test jig for testing the semiconductor device
JPH11186492A (en) 1997-12-22 1999-07-09 Toshiba Corp Semiconductor package and its mounting structure
US6105245A (en) 1997-02-17 2000-08-22 Nippon Steel Semiconductor Corporation Method of manufacturing a resin-encapsulated semiconductor package
KR20010070217A (en) 1999-11-16 2001-07-25 가네꼬 히사시 Semiconductor device and manufacturing method of the same
US20010020739A1 (en) 2000-03-09 2001-09-13 Nec Corporation Flip chip type semiconductor device and method for manufacturing the same
JP2001298115A (en) 2000-04-13 2001-10-26 Seiko Epson Corp Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment
JP2002359350A (en) 2001-05-31 2002-12-13 Denso Corp Method of manufacturing stacked circuit module
CN2558078Y (en) 2002-04-15 2003-06-25 威盛电子股份有限公司 Embedded ball lattice array package structure
US20030133274A1 (en) * 2002-01-16 2003-07-17 Kuo-Tso Chen Integrated circuit package and method of manufacture
US20030137045A1 (en) 2002-01-23 2003-07-24 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method of manufacturing the same
US6603198B2 (en) * 1998-08-28 2003-08-05 Micron Technology, Inc. Semiconductor structure having stacked semiconductor devices
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6750547B2 (en) * 2001-12-26 2004-06-15 Micron Technology, Inc. Multi-substrate microelectronic packages and methods for manufacture
JP2004172157A (en) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd Semiconductor package and package stack semiconductor device
US20040164411A1 (en) * 1999-05-07 2004-08-26 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
JP2004319892A (en) 2003-04-18 2004-11-11 Renesas Technology Corp Manufacturing method of semiconductor device
US20050008525A1 (en) 2001-12-15 2005-01-13 Roland Pfarr Lead-free soft solder
US20050012195A1 (en) 2003-07-18 2005-01-20 Jun-Young Go BGA package with stacked semiconductor chips and method of manufacturing the same
US6853078B2 (en) * 2002-02-22 2005-02-08 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US20050040529A1 (en) 2003-08-20 2005-02-24 Kyu-Jin Lee Ball grid array package, stacked semiconductor package and method for manufacturing the same
US6956296B2 (en) * 2001-06-15 2005-10-18 International Business Machines Corporation Transfer molding of integrated circuit packages
US7230329B2 (en) * 2003-02-07 2007-06-12 Seiko Epson Corporation Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device
US7372151B1 (en) * 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050004059A1 (en) * 2003-04-15 2005-01-06 Tularik Inc. Gene amplification and overexpression in cancer

Patent Citations (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06291221A (en) 1993-04-05 1994-10-18 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH08236665A (en) 1995-02-28 1996-09-13 Citizen Watch Co Ltd Resin sealed semiconductor device and manufacture thereof
US5831441A (en) * 1995-06-30 1998-11-03 Fujitsu Limited Test board for testing a semiconductor device, method of testing the semiconductor device, contact device, test method using the contact device, and test jig for testing the semiconductor device
JPH09330992A (en) 1996-06-10 1997-12-22 Ricoh Co Ltd Semiconductor device mounting body and its manufacture
JPH10135267A (en) 1996-10-30 1998-05-22 Oki Electric Ind Co Ltd Structure of mounting board and its manufacture
JPH10289923A (en) 1997-02-17 1998-10-27 Nittetsu Semiconductor Kk Manufacture of semiconductor package
US6105245A (en) 1997-02-17 2000-08-22 Nippon Steel Semiconductor Corporation Method of manufacturing a resin-encapsulated semiconductor package
JPH11186492A (en) 1997-12-22 1999-07-09 Toshiba Corp Semiconductor package and its mounting structure
US6603198B2 (en) * 1998-08-28 2003-08-05 Micron Technology, Inc. Semiconductor structure having stacked semiconductor devices
US20040164411A1 (en) * 1999-05-07 2004-08-26 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US20020064935A1 (en) 1999-11-16 2002-05-30 Hirokazu Honda Semiconductor device and manufacturing method the same
KR20010070217A (en) 1999-11-16 2001-07-25 가네꼬 히사시 Semiconductor device and manufacturing method of the same
KR20010089209A (en) 2000-03-09 2001-09-29 가네꼬 히사시 Flip chip type semiconductor device and method for manufacturing the same
US20020121689A1 (en) 2000-03-09 2002-09-05 Nec Corporation Flip chip type semiconductor device and method for manufacturing the same
US20010020739A1 (en) 2000-03-09 2001-09-13 Nec Corporation Flip chip type semiconductor device and method for manufacturing the same
JP2001298115A (en) 2000-04-13 2001-10-26 Seiko Epson Corp Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment
JP2002359350A (en) 2001-05-31 2002-12-13 Denso Corp Method of manufacturing stacked circuit module
US6956296B2 (en) * 2001-06-15 2005-10-18 International Business Machines Corporation Transfer molding of integrated circuit packages
US20050008525A1 (en) 2001-12-15 2005-01-13 Roland Pfarr Lead-free soft solder
US6750547B2 (en) * 2001-12-26 2004-06-15 Micron Technology, Inc. Multi-substrate microelectronic packages and methods for manufacture
US20030133274A1 (en) * 2002-01-16 2003-07-17 Kuo-Tso Chen Integrated circuit package and method of manufacture
US20030137045A1 (en) 2002-01-23 2003-07-24 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method of manufacturing the same
CN1449232A (en) 2002-01-23 2003-10-15 松下电器产业株式会社 Circuit component built-in module and method of manufacturing the same
US20040145044A1 (en) 2002-01-23 2004-07-29 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module with embedded semiconductor chip and method of manufacturing
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US6853078B2 (en) * 2002-02-22 2005-02-08 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
CN2558078Y (en) 2002-04-15 2003-06-25 威盛电子股份有限公司 Embedded ball lattice array package structure
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
JP2004172157A (en) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd Semiconductor package and package stack semiconductor device
US7230329B2 (en) * 2003-02-07 2007-06-12 Seiko Epson Corporation Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device
JP2004319892A (en) 2003-04-18 2004-11-11 Renesas Technology Corp Manufacturing method of semiconductor device
US20050012195A1 (en) 2003-07-18 2005-01-20 Jun-Young Go BGA package with stacked semiconductor chips and method of manufacturing the same
JP2005072587A (en) 2003-08-20 2005-03-17 Samsung Electronics Co Ltd Bga package, package stacking structure and manufacturing method therefor
US20050040529A1 (en) 2003-08-20 2005-02-24 Kyu-Jin Lee Ball grid array package, stacked semiconductor package and method for manufacturing the same
US7372151B1 (en) * 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same

Cited By (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8587109B2 (en) 2000-08-23 2013-11-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
US8067827B2 (en) * 2000-08-23 2011-11-29 Micron Technology, Inc. Stacked microelectronic device assemblies
US20070210435A1 (en) * 2000-08-23 2007-09-13 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
US9076789B2 (en) * 2005-02-18 2015-07-07 Socionext Inc. Semiconductor device having a high frequency external connection electrode positioned within a via hole
US20140117562A1 (en) * 2005-02-18 2014-05-01 Fujitsu Semiconductor Limited Semiconductor device
US20080169544A1 (en) * 2006-01-17 2008-07-17 Junji Tanaka Semiconductor device and method of fabricating the same
US7968990B2 (en) * 2006-01-17 2011-06-28 Spansion Llc Semiconductor device and method of fabricating the same
US20080230887A1 (en) * 2007-03-23 2008-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
US8143101B2 (en) 2007-03-23 2012-03-27 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
US20090146301A1 (en) * 2007-12-11 2009-06-11 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8841772B2 (en) 2007-12-11 2014-09-23 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US20100000775A1 (en) * 2008-07-03 2010-01-07 Advanced Semiconductor Engineering, Inc. Circuit substrate and method of fabricating the same and chip package structure
US8158888B2 (en) 2008-07-03 2012-04-17 Advanced Semiconductor Engineering, Inc. Circuit substrate and method of fabricating the same and chip package structure
US8076765B2 (en) 2009-01-07 2011-12-13 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors
US20100171205A1 (en) * 2009-01-07 2010-07-08 Kuang-Hsiung Chen Stackable Semiconductor Device Packages
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US20100171207A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Shen Stackable semiconductor device packages
US20100181660A1 (en) * 2009-01-20 2010-07-22 Monolito Galera Multi-Chip Semiconductor Package
US7846773B2 (en) * 2009-01-20 2010-12-07 Fairchild Semiconductor Corporation Multi-chip semiconductor package
US20100308461A1 (en) * 2009-01-20 2010-12-09 Manolito Galera Multi-chip semiconductor package
US20110049704A1 (en) * 2009-08-31 2011-03-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with integrated heatsinks
US20110117700A1 (en) * 2009-11-18 2011-05-19 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US8198131B2 (en) 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US8405212B2 (en) 2009-12-31 2013-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor package
US20110156251A1 (en) * 2009-12-31 2011-06-30 Chi-Chih Chu Semiconductor Package
US9196597B2 (en) 2010-01-13 2015-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US20110193205A1 (en) * 2010-02-10 2011-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having stacking functionality and including interposer
US8823156B2 (en) 2010-02-10 2014-09-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having stacking functionality and including interposer
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8872317B2 (en) * 2010-06-08 2014-10-28 Samsung Electronics Co., Ltd. Stacked package
US20110298129A1 (en) * 2010-06-08 2011-12-08 Samsung Electronics Co., Ltd. Stacked package
US8569885B2 (en) 2010-10-29 2013-10-29 Advanced Semiconductor Engineering, Inc. Stacked semiconductor packages and related methods
US8643167B2 (en) 2011-01-06 2014-02-04 Advanced Semiconductor Engineering, Inc. Semiconductor package with through silicon vias and method for making the same
US8546938B2 (en) * 2011-02-15 2013-10-01 Samsung Electronics Co., Ltd. Stacked package including spacers and method of manufacturing the same
US20120205795A1 (en) * 2011-02-15 2012-08-16 Samsung Electronics Co., Ltd. Stacked package and method of manufacturing the same
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
US11735563B2 (en) 2011-10-17 2023-08-22 Invensas Llc Package-on-package assembly with wire bond vias
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US10510659B2 (en) 2012-05-22 2019-12-17 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9123764B2 (en) 2012-08-24 2015-09-01 Infineon Technologies Ag Method of manufacturing a component comprising cutting a carrier
US9312253B2 (en) * 2012-12-06 2016-04-12 Texas Instruments Incorporated Heterogeneous integration of memory and split-architecture processor
US20150111318A1 (en) * 2012-12-06 2015-04-23 Texas Instruments Incorporated Heterogeneous Integration of Memory and Split-Architecture Processor
US10629567B2 (en) 2013-11-22 2020-04-21 Invensas Corporation Multiple plated via arrays of different wire heights on same substrate
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US11462483B2 (en) 2015-10-12 2022-10-04 Invensas Llc Wire bond wires for interference shielding
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10658302B2 (en) 2016-07-29 2020-05-19 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
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US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor

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