JPH11186492A - Semiconductor package and its mounting structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package wherein, even when semiconductor packages of the same structure are laminated for mounting, specified terminals or the IC connected in the packages are separately inputted/outputted. SOLUTION: Rear surface terminals 14a-14g provided at a package main body 11 of a resin sealing a memory IC16, and surface terminals 12a and 12g are provided. The rear surface terminals 14a and 14b are electrically connected, as pair, to the surface terminals 12a and 12b through the memory IC18 to constitute a first signal circuit, the rear surface terminal 14d is electrically connected, as pair, to the surface terminal 12c with no memory IC16 inbetween to constitute a second signal circuit, and the rear surface terminal 14c except for the first and second signal circuits is electrically connected to the memory IC16 to constitute a third signal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package mounted on information equipment and the like and a semiconductor package mounting structure in which semiconductor packages are stacked in multiple stages and mounted at a high density, and more particularly to a structure which can be miniaturized.

[0002]

2. Description of the Related Art In recent information devices and the like, the proportion of the area of a motherboard (substrate) occupied by a semiconductor IC such as a memory IC using a large number of semiconductor ICs of the same type in order to achieve high functionality is large, and the substrate area is large. It is a factor.

[0003] For this reason, as shown in FIG. 6, these semiconductor ICs are used in a desktop personal computer or a workstation.
1 was mounted on a small daughter board 2, and a method of mounting the daughter board 2 vertically on the motherboard 3 was devised. The area of the motherboard 3 was reduced, and the size of the device was reduced. .

[0004] On the other hand, among information devices used for carrying such as mobile phones and notebook computers, the above-described method cannot be used in order to improve portability. For this reason, for example, as shown in FIG. 7, semiconductor packages having the same structure having terminals on the front and back surfaces are stacked and mounted. That is, since the terminals 4b on the back surface of the upper semiconductor package 4 and the terminals 5a on the front surface of the lower semiconductor package 5 are connected, the semiconductor packages 4 and 5 are connected at the shortest distance without using a substrate. be able to. The terminals 4a and 4b and the terminals 5a and 5b are connected inside the semiconductor package. In FIG. 7, reference numeral 6 denotes a semiconductor IC such as a memory IC.

[0005]

The mounting structure using the conventional semiconductor packages 4 and 5 has the following problems. For example, when the terminal 4b of the semiconductor package 4 is a terminal for controlling the memory IC 6 inside the package, if the semiconductor packages 5 having the same structure are mounted on top of each other, the control signal of the upper semiconductor package 4 and the lower semiconductor The control signal A of the package 5 is both terminals 5a
Will be connected. For this reason, if the two semiconductor packages 4 and 5 are simply mounted on top of each other, the control signals, which should be independent, are connected to each other and do not function.

Therefore, the terminal 4 of the semiconductor package 4
b has to be connected to the substrate via a jumper line without connecting to the terminal 5a of the semiconductor package 5, or to manufacture several kinds of semiconductor chips in which the same memory IC 6 is used but the terminal position of the control signal is changed. For this reason, there were problems such as an increase in cost and difficulty in downsizing.

Accordingly, the present invention provides a semiconductor package which can independently input and output predetermined terminals of an IC connected in each package, even when semiconductor packages having the same structure are stacked and mounted. And a semiconductor package mounting structure.

[0008]

In order to solve the above-mentioned problems and to achieve the object, an invention according to claim 1 comprises a semiconductor chip, a main body made of resin for sealing the semiconductor chip, and A plurality of first terminals provided on one main surface of the main body, and a plurality of second terminals provided on the other main surface of the main body; At least one selected first terminal is electrically connected to the second terminal via the semiconductor chip in pairs, forming a first signal circuit, and a first signal circuit other than the first signal circuit. A plurality of first terminals selected from one terminal are electrically connected to the second terminals one by one without interposing the semiconductor chip to form a second signal circuit, and
At least one of the first terminals other than the signal circuit and the second signal circuit is electrically connected to the semiconductor chip to form a third signal circuit.

According to a second aspect of the present invention, in the first aspect, the second signal circuit is formed of a flexible substrate. According to a third aspect of the present invention, in the first aspect of the invention, the second signal circuit is formed by a lead frame.

According to a fourth aspect of the present invention, in the first aspect, the third signal circuit is for applying a control signal to the semiconductor chip. In the invention described in claim 5, in the invention described in claim 1, the second terminal is a first terminal forming the first signal circuit and a first terminal forming the second signal circuit. Both are electrically connected.

According to a sixth aspect of the present invention, in the first aspect of the invention, the first terminal is a bump electrode protruding from a substrate, and the bump electrode of the substrate is protruding from the substrate. The semiconductor chip is attached to the surface opposite to the surface.

According to a seventh aspect of the present invention, in the first aspect, the first terminal and the second terminal forming each of the first signal circuits are connected to a main surface of the main body. When viewed through in a direction perpendicular to the direction, it is arranged at an overlapping position.

According to an eighth aspect of the present invention, in the first aspect, the first terminal and the second terminal forming each of the second signal circuits are connected to a main surface of the main body. Are arranged at positions not overlapping each other when viewed in a direction perpendicular to the direction.

According to a ninth aspect of the present invention, in the semiconductor package mounting structure, a plurality of semiconductor packages each including a semiconductor chip and a main body made of a resin sealing the semiconductor chip are stacked. The semiconductor package includes a plurality of first terminals provided on one main surface of the main body, and a plurality of second terminals provided on the other main surface of the main body. At least one first terminal selected from the first terminals is electrically connected to the second terminal via the semiconductor chip one by one to form a first signal circuit, and the first signal The plurality of first terminals selected from the first terminals other than the circuit are electrically connected to the second terminals one by one without interposing the semiconductor chip to form a second signal circuit, and A first signal circuit and the second signal circuit; At least one of the first terminals other than the signal circuit is electrically connected to the semiconductor chip to form a third signal circuit, and the plurality of stacked semiconductor packages are adjacent to each other in the first signal path. Terminal and the second
And the first signal circuit and the second signal circuit of each semiconductor package are electrically connected to each other, and at least one of the second signal circuits of each semiconductor package is adjacent to the first signal circuit and the second signal circuit of each semiconductor package. Electrically connected to the third signal circuit of the semiconductor package.

The invention described in claim 10 is the ninth invention.
In the invention described in (1), the first signal circuit is a conduction path for a common signal input / output simultaneously with each of the semiconductor packages.

The invention described in claim 11 is the ninth invention.
In the invention described in (1), the second signal circuit is a conduction path for a signal selectively input / output to / from each of the semiconductor packages via the third signal circuit.

[0017]

FIG. 1 is a diagram schematically showing a mounting structure of a semiconductor package according to an embodiment of the present invention. In FIG. 1, 10A to 10D denote the same type of semiconductor package, 20 denotes another type of semiconductor package, and 30 denotes a printed circuit board.

Since the semiconductor packages 10A to 10D have the same structure, only the semiconductor package 10A will be described, and the other semiconductor packages 10B to 10D will be given the same reference numerals for the same functional portions and will not be described in detail. The semiconductor package 10A includes a memory IC described later.
A package body 11 made of, for example, epoxy resin or the like for sealing the package body 16, front terminals 12a to 12g provided on the surface of the package body 11, and back terminals 14a to 14g forming bump electrodes provided on the back surface. ing.
The front terminals 12a to 12g and the rear terminals 14a to 14g are arranged at positions overlapping each other when the package body 11 is seen through in the stacking direction.

The front terminal 12a and the back terminal 14a are connected to each other and to the terminal 16a of the memory IC 16. The front terminal 12b and the back terminal 14b are connected to each other, and are connected to the data signal terminal 16b of the memory IC 16. The front terminals 12a, 12b and the back terminals 14a, 14b form a first signal circuit.

Further, the surface terminal 12c is connected to the memory IC 1
6 to form a third signal circuit. Similarly, the front terminal 12d and the back terminal 14e, the front terminal 12e and the back terminal 14f, and the front terminal 12f and the back terminal 14g are connected to form a second signal circuit, and the package body 11 is seen through in the stacking direction. It is placed in a position that does not overlap when it is done.

FIG. 2 shows a semiconductor package 10A (10B to 10B).
It is a figure which shows the internal structure of 10D). That is, a wiring board 15, a memory IC (semiconductor IC) 16, and a flexible board 17 are arranged in the package body 11.

For example, a wiring board 1 made of glass epoxy resin
5 has terminals 15a to 15g on the front surface and rear terminals 14a to 14g, which are the above-described bump electrodes, on the rear surface. The terminals 15 a to 15 b are connected to the terminals 14 a to 1 via vias (Via) 19 provided on the substrate 15.
4c. In addition, a connection portion 15p is provided on the surface of the wiring board 15. Terminal 15c and terminal 14c
Are connected inside the wiring board 15. The connection portion 15p and the terminal 14d are connected to the via 15 inside the wiring board 15.
are connected via t.

The memory IC 16 is provided with terminals 16a to 16g, which are bump electrodes, on the back surface, and has an adhesive (not shown) on the back surface of a flexible substrate 17 described later.
Is glued through. The terminals 16a to 16b are connected to each semiconductor package 10 such as a logic signal and a data signal.
A terminal for common signals required in A to 10D and a terminal 16C are terminals for control signals for selecting an IC.

In this embodiment, the terminals 16d to 16g are idle terminals (arbitrarily, the terminal 1
6a to 16c can have the same function).
The flexible substrate 17 has the surface terminal 1 described above on the surface.
2a to 12g are formed, and the connection portions 17p respectively connected to the connection portions 15p of the wiring board 15 are formed on the back surface.
Is provided. The flexible substrate 17 connects the front terminals 12c to 12f to the rear terminals 14d via the connection portions 17p.
~ 14g. The terminals 14a and 14b constituting the first signal circuit are directly connected to the surface terminals 12a and 12b via the inside of the memory IC 16 and the flexible substrate 17.
It is connected to the. FIG. 1 shows only the connection between the front terminal 12d and the rear terminal 14d.

The terminals 16a to 16g of the memory IC 16 and the terminals 15a to 15g of the wiring board 15 are connected. The printed circuit board 30 is connected to terminals 31a to 31g, a logic circuit 32 connected to the terminal 31a, a data circuit 33 connected to the terminal 31b, and a control circuit 34 connected to the terminals 31c to 31g. .

Back terminal 14a of semiconductor package 10A
To 14 g are connected to terminals 31 a to 31 g of the printed circuit board 30, and the surface terminals 12 a to 12 g are connected to the semiconductor package 1.
0B are connected to the back terminals 14a to 14g.

Similarly, front terminals 12a to 12g of semiconductor package 10B are connected to rear terminals 1 of semiconductor package 10C.
4a to 14g, and front terminals 12a to 12g of the semiconductor package 10C are connected to rear terminals 14a to 14g of the semiconductor package 10D.

On the other hand, front terminals 12a to 12g of semiconductor package 10D are connected to rear terminals 22a of semiconductor package 20.
a to 22g. The semiconductor packages 10A to 10D and 20 configured as described above are
The signal flow when the components are stacked and mounted on 0 is as follows. That is, the signal of the logic IC of the semiconductor package 20 is transmitted from the back surface terminal 22 a to the semiconductor package 10.
D front terminal 12a, back terminal 14a, front terminal 12a, back terminal 14a of semiconductor package 10C, front terminal 12a, back terminal 14a of semiconductor package 10B, front terminal 12a of semiconductor package 10A, back terminal 14
a, and reaches the logic circuit 32 via the terminal 31 a of the printed circuit board 30. Of course, logic circuit 3
2 are also applied along the same path.

The memory I of the semiconductor package 10D
The data signal of C16 is transmitted from the back terminal 14b to the front terminal 12b, the back terminal 14b of the semiconductor package 10C, the front terminal 12b of the semiconductor package 10B, and the back terminal 14.
b, pass through the front terminal 12b and the rear terminal 14b of the semiconductor package 10A, and reach the data circuit 33 via the terminal 31b of the printed circuit board 30. Of course, the output signal from the data circuit 33 is applied along the same route. Also,
The data signal of the memory IC 16 of the semiconductor package 10C is transmitted from the back terminal 14b to the front terminal 12b, the back terminal 14b of the semiconductor package 10B, and the semiconductor package 10A.
, And reaches the data circuit 33 via the terminal 31 b of the printed circuit board 30. Similarly, the data signal of each memory IC 16 of the semiconductor packages 10B and 10A also reaches the data circuit 33. Of course, the output signal from the data circuit 33 is applied along the same route.

On the other hand, a control signal for selecting the semiconductor package 10A is sent from the control circuit 34 to the terminals 31c and 31c.
The voltage is applied to the memory IC 16 via the terminals 14c and 16c. Further, a control signal for selecting the semiconductor package 10B is transmitted from the control circuit 34 via the terminal 31d and the terminals 15p and 12c of the semiconductor package 10A.
The data is input to the terminal 14c of the semiconductor package 10B, and the memory IC 16 of the semiconductor package 10B is selected.
Further, a control signal of the semiconductor package 10C is input from the control circuit 34 to the terminal 14c of the semiconductor package 10C via the terminal 31e, the terminals 14e, 15p, 12d of the semiconductor package 10A and the terminals 14d, 15p, 12c of the semiconductor package 10B. Then, the IC memory 16 of the semiconductor package 10C is selected. Furthermore, a control signal for selecting the semiconductor package 10D is:
From the control circuit 34, the terminal 31f, the semiconductor package 10
A terminal 14f, 15p, 12e of terminal A, terminal 14e, 15p, 12d of semiconductor package 10B and terminal 14d, 15p, 12c of semiconductor package 10C are input to terminal 14c of semiconductor package 10D, and IC of this semiconductor package 10D The memory 16 is selected. Similarly, the IC memory 16 of the semiconductor package 20 is selected.

That is, when the same type of signal may be input / output to / from the terminal 16b of the different memory IC 16 like a data signal, the back terminals 14b of the semiconductor packages 10A to 10D are connected to the same terminal 31b of the printed circuit board 30. Will be connected.

On the other hand, in the case of a control signal for selecting each memory IC, the back terminal 14c is transferred from the back terminal 14c to the back terminal 14d in the adjacent semiconductor package.
From the back terminal 14e to the back terminal 14e.
4f. For this reason,
The control signals of the respective memory ICs 16 of the semiconductor packages 10A to 10D are transmitted to the terminals 31c to 3c of the printed circuit board 30, respectively.
A different signal can be input / output from the print control circuit 34 to 1f.

Therefore, it is possible to prevent the control signals that should be independent from each other from being connected to each other and not functioning. For this reason, it can be dealt with simply by mounting semiconductor packages having the same structure in an overlapping manner.

FIGS. 3 and 4 are views showing modifications of the structure of a semiconductor package for shifting terminals. As shown in FIG. 3, a semiconductor package 40 has the same basic wiring structure as that of FIG. 2, and a semiconductor IC 42 is mounted on a rigid substrate 41 made of glass epoxy resin or ceramic.
Are flip-chip connected. On the rigid substrate 41, lower surface input / output terminals 43a to 43e are formed. A flexible substrate 45 on which upper surface input / output terminals 44a to 44e are formed is connected to the rigid substrate 41 at an outer peripheral portion of the semiconductor IC 42. The other end of the flexible board 45 is fixed on the semiconductor IC 42. In FIG. 3, reference numeral 46 denotes a wiring on the rigid substrate 41. The upper input / output terminals 44b to 44e are connected to the lower input / output terminals 43a to 43f via a flexible board 45 and a wiring 46 provided on the surface of the flexible board 45.
The lower surface input / output terminals 43 a to 43 f are electrically connected to the wiring 46 via vias (Via) 49 provided inside the substrate 41. The lower surface input / output terminals 43a to 43
e may be a bump electrode.

The semiconductor package 4 configured as described above
0 is connected via the wiring 46 provided on the surface, and therefore has an advantage that the manufacturing is easier and the manufacturing cost is lower than that of the semiconductor package of FIG.

Further, as shown in FIG. 4, the semiconductor package 50 has the same basic wiring structure as that of FIG. 2, and has a rigid substrate 51 made of glass epoxy resin or ceramic.
The semiconductor IC 52 is wire-bonded. Lower surface input / output terminals 53a to 53e are formed on the rigid substrate 51, and a semiconductor IC 5 including wire bonding is provided.
Lead frames 54a-5 formed higher than the height 2
4e (54b is not shown) are connected to lower surface input / output terminals 53a to 53e via vias (Via) 59 provided inside the rigid substrate 51, respectively. Note that the lower surface input / output terminals 53a to 53e may be bump electrodes.

The tips of the lead frames 54a to 54e
For example, upper surface input / output terminals 56a to 56e are exposed on the upper surface of the package body 55 formed by potting.

The semiconductor package 5 configured as described above
By stacking and mounting 0s, the same effect as in the above-described embodiment can be obtained. FIG. 5 is a conceptual diagram showing a modification of the connection between the front terminal and the rear terminal. That is, the semiconductor package 60 includes the package body 61, and has the front terminals 62a to 62f and the rear terminals 63a to 63f.
f is provided. Front terminal 62a and back terminal 63
a, front terminal 62b and back terminal 63b, front terminal 62c
And the back terminals 63c and 63d, the front terminal 62e and the back terminal 63f, and the front terminal 62f and the back terminal 63f, respectively. That is, by stacking and mounting such semiconductor packages 60, the same effect as in the above-described embodiment can be obtained.

That is, the stacked semiconductor packages 6
At 0, data signals and the like commonly input and output use the terminals 62a and 63a and the terminals 62b and 63b, and use the terminals 62c and 63c and the terminals 62f and 63f when the terminals are insufficient. On the other hand, when a control signal such as a chip selection signal is applied only to a desired package 60, terminals 62c and 63d
And terminals 62e and 63f. In this modification, even if the terminal is used for a common signal or for each control signal,
It has the advantage that it can be shared.

Further, the number of the first terminal and the number of the second terminal constituting the first signal circuit may be one, and the number of the first terminals constituting the third signal circuit may be plural. Still further, the pair of first and second terminals forming the first signal circuit are:
The condition that the pair of first and second terminals constituting the second signal circuit are located at positions where they do not overlap in the stacking direction, and the condition that the pair of first and second terminals forming the second signal circuit are located at positions that do not overlap in the stacking direction.
It can be changed as long as one of the signal circuits of the above satisfies the condition of being connected to the third signal circuit of the adjacent semiconductor package.

The present invention is not limited to the above embodiment. That is, in the above embodiment, the connection with the semiconductor IC has been described using a typical connection method, but a connection method other than the embodiment may be used. Further, a flexible substrate may be used instead of the rigid substrate. In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0042]

According to the semiconductor package of the present invention, even if the semiconductor packages are stacked in multiple stages, even if they are simply stacked in multiple stages without using jumper wires or using several types of semiconductor packages with changed terminal positions. Signals can be input and output for each of the stacked semiconductor packages. As a result, the area occupied by the substrate can be significantly reduced, which greatly contributes to high-density mounting.

On the other hand, according to the mounting structure of the semiconductor package of the present invention, each semiconductor package is simply laminated without using a jumper wire or several types of semiconductor packages whose terminal positions are changed. Signal input / output is possible for each package. This allows
The area occupied by the substrate can be greatly reduced, which is a significant factor contributing to high-density mounting.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a mounting structure of a semiconductor package according to an embodiment of the present invention.

FIG. 2 is a sectional view showing the semiconductor package.

FIG. 3 is a sectional view showing a first modification of the semiconductor package.

FIG. 4 is a sectional view showing a second modification of the semiconductor package.

FIG. 5 is a view schematically showing a third modification of the semiconductor package.

FIG. 6 is a diagram showing a high-density mounting structure of a semiconductor package in a conventional tabletop information device.

FIG. 7 is a diagram schematically showing a conventional semiconductor package.

[Explanation of symbols]

 10A to 10D: Semiconductor package 11: Package body 12a to 12g: Front terminals 14a to 14g: Back terminals 16: Memory IC 20: Semiconductor package 30: Printed circuit board

Claims (11)

[Claims] 1. A semiconductor chip, a main body made of a resin for sealing the semiconductor chip, a plurality of first terminals provided on one main surface of the main body, and another main terminal of the main body. A plurality of second terminals provided on a surface, and at least one first terminal selected from the plurality of first terminals is paired with the second terminal via the semiconductor chip. And a plurality of first terminals selected from first terminals other than the first signal circuit are electrically connected to each other without passing through the semiconductor chip. A pair of terminals is electrically connected to each other to form a second signal circuit, and at least one of the first terminals other than the first signal circuit and the second signal circuit is electrically connected to the semiconductor chip. Being connected to form a third signal circuit. Conductor package. 2. The semiconductor package according to claim 1, wherein said second signal circuit is formed of a flexible substrate. 3. The semiconductor package according to claim 1, wherein said second signal circuit is formed by a lead frame. 4. The semiconductor package according to claim 1, wherein said third signal circuit is for applying a control signal to said semiconductor chip. 5. The semiconductor device according to claim 1, wherein the second terminal is electrically connected to both the first terminal forming the first signal circuit and the first terminal forming the second signal circuit. The semiconductor package according to claim 1. 6. The semiconductor device according to claim 1, wherein the first terminal is a bump electrode protruding from a substrate, and the semiconductor chip is attached to a surface of the substrate opposite to the surface from which the bump electrode protrudes. The semiconductor package according to claim 1, wherein: 7. The apparatus according to claim 1, wherein the first terminal and the second terminal forming each of the first signal circuits are arranged at overlapping positions when viewed through the main surface of the main body in a direction perpendicular to the main surface. The semiconductor package according to claim 1, wherein: 8. The first terminal and the second terminal constituting each of the second signal circuits are arranged at positions that do not overlap with each other when viewed in a direction perpendicular to the main surface of the main body. The semiconductor package according to claim 1, wherein: 9. A semiconductor package mounting structure in which a plurality of semiconductor packages each including a semiconductor chip and a resin body encapsulating the semiconductor chip are stacked, wherein the semiconductor package comprises: A plurality of first terminals provided on one main surface; and a plurality of second terminals provided on the other main surface of the main body, wherein the plurality of first terminals are selected from the plurality of first terminals. At least one first terminal is electrically connected to the second terminal via the semiconductor chip one by one to form a first signal circuit, and from a first terminal other than the first signal circuit. The selected plurality of first terminals are electrically connected to the second terminals one by one without interposing the semiconductor chip to form a second signal circuit, and the first signal circuit and the second signal circuit are connected to each other. The first circuit other than the signal circuit At least one of the semiconductor chips is electrically connected to the semiconductor chip to form a third signal circuit; and the plurality of stacked semiconductor packages are adjacent to the first terminal and the second terminal. And the first signal circuit and the second signal circuit of each of the semiconductor packages are electrically connected to each other,
At least one of the second signal circuits of each of the semiconductor packages is electrically connected to the third signal circuit of an adjacent semiconductor package. 10. The semiconductor package mounting structure according to claim 9, wherein said first signal circuit is a conduction path for a common signal input / output simultaneously with each of said semiconductor packages. 11. The semiconductor device according to claim 11, wherein the second signal circuit is a conduction path for a signal selectively input / output to / from each of the semiconductor packages via the third signal circuit. 10. The mounting structure of the semiconductor package according to 9.