JPH05160333A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To supply a stable power source to an integrated circuit without affecting a chip area of the integrated circuit, by electrically connecting a semiconductor chip having a terminal for power source on a corner part with a package having an inner lead part for power source on the position corresponding to the corner part. CONSTITUTION:A layout of a power source pattern 11a necessary to be enhanced is located on a corner part of a semiconductor chip 11, and bonding pads 12a for power source terminal are provided. Then, both the bonding pads 12a for power source and an inner lead part 13a for power source which is located on the position of die pad 13 corresponding to the corner part are bonded with wires 16a. Therefore, a power source can be stably supplied to the power pattern 11a of the semiconductor chip 11 through the wires 16a and the bonding pads 12a for power source.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having an IC (integrated circuit) or LSI (large scale integrated circuit) semiconductor chip enclosed in a package. It is about.

[0002]

2. Description of the Related Art Generally, in this type of semiconductor integrated circuit device, a large number of terminals for various power sources are formed on a semiconductor chip. Therefore, by increasing the number of terminals in the package and allocating a large number of terminals for such power supply relationship, these power supply terminals can be electrically connected inside the package and the power supply capability to the semiconductor chip is secured. I am trying to do it.

FIG. 5 shows an example of such a conventional semiconductor integrated circuit device.

In the semiconductor integrated circuit device of FIG. 5, in order to improve the power supply capability and stability, the semiconductor chip
Bonding pads including power supply bonding pads that are terminals for 51 power supplies (VCC, VDD, VSS, GND, etc.)
The number of arrays of 52 is increased, and the number of inner terminals 55, which are terminals on the package side, is also increased, and each is electrically connected (inner bonding) to each other by wires 56. I try to increase the number of terminals.

[0005]

Generally, in this type of semiconductor integrated circuit device, from the viewpoint of high integration, high functionality and simplification of manufacturing process of the device, limited terminals are effectively utilized, It is desired to increase the number of terminals of the package and not increase the chip area. In addition, even in a semiconductor integrated circuit that operates at high speed and has a large output current and a large current consumption, even if the packages have the same number of terminals, power supplies (for example, VCC, VDD, VSS, GN)
It is desired to increase the supply capacity of (D etc.) and to supply a stable power supply to the power supply noise and the simultaneous switching noise in the high speed operation to suppress the malfunction.

However, according to the above-mentioned conventional semiconductor integrated circuit device, as the number of terminals increases, the miniaturization of the frame patterns of various packages, screen printing, patterns such as vapor deposition, and multilayer wiring technology are required, and in terms of cost. It becomes a problem. Further, due to the increase and miniaturization of the wiring patterns of various packages, it becomes difficult to wire bond particularly at the corners of the semiconductor chip. Furthermore, by miniaturizing various patterns, power supplies (VCC, VDD, VS
(S, GND, etc.) and the influence of noise due to impedance of signal lines such as normal input, output, and input / output, inductance, coupling between lines, etc. are also problems.

That is, according to such a conventional semiconductor integrated circuit device, the area of the semiconductor chip, the number of terminals of the package are increased in proportion to the number of power supply terminals for enhancing the power supply capability, and in various packages. In addition, the number of lead frames, vapor deposition, and pattern wiring such as multi-layer wiring also increases, and the cost also increases. Also, the wire bonding itself becomes difficult in proportion to the increase in the wiring pattern of the terminals on the semiconductor chip and the package. Furthermore, as the amount of wiring in the package frame or pattern increases, sophisticated wiring pattern miniaturization technology is also required, which may result in insufficient power supply capability or impedance to other signal lines. And inductance may affect it.

The present invention has been made in view of the above-mentioned conventional problems, and suppresses an increase in manufacturing cost as much as possible.
An object of the present invention is to provide a semiconductor integrated circuit device with high reliability and stability of operation.

[0009]

In order to achieve the above-mentioned object, a semiconductor integrated circuit device of the present invention includes a semiconductor integrated circuit composed of a semiconductor chip having a power supply terminal at a corner, and the semiconductor integrated circuit. A package having a power supply inner lead portion at a position corresponding to the corner portion of the semiconductor chip and a connecting means for electrically connecting the power supply terminal and the power supply inner lead portion. Characterize.

[0010]

According to the semiconductor integrated circuit device of the present invention, the semiconductor integrated circuit is composed of a semiconductor chip having a power supply terminal such as a bonding pad in the corner portion, while the semiconductor integrated circuit is enclosed. The package has a power supply inner lead portion at a position corresponding to the corner portion of the semiconductor chip. Since the power supply terminals and the power supply inner lead portions are electrically connected to each other by the connecting means, which is a wire for wire bonding, for example, even if the same package has the same number of terminals, the semiconductor chip It is possible to provide a sufficient power supply to the package, and it is not necessary to increase the number of terminals of the package, a complicated and fine package frame or pattern, and an advanced wire bonding technique. Further, it does not affect the chip area of the integrated circuit, and does not adversely affect signals other than power-related signals. As a result, it is possible to supply a stable power as much as possible even in an integrated circuit that requires high-speed operation while suppressing an increase in manufacturing cost to a minimum, and therefore, the reliability and stability of device operation are improved. improves.

The action of the present invention will be more apparent from the following examples of the present invention, and other actions of the present invention will be further clarified.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic view of a layout when a semiconductor chip is wire-bonded in a semiconductor integrated circuit device according to an embodiment of the present invention.

In FIG. 1, the semiconductor integrated circuit device constitutes a semiconductor integrated circuit and has a bonding pad on the upper surface.
A semiconductor chip 11 in which 12 are formed in an array, a die pad 13 provided on a package substrate 14 to which the semiconductor chip 11 is die-bonded, and an inner lead portion 15a provided on the substrate 14 are included. Configured wiring pattern 1
5, and a wire 16 for electrically connecting (wire bonding) the inner lead portion 15a and the bonding pad 12 to each other. The bonding pad 12 constitutes a signal input / output terminal.

In the present embodiment, the VCC, VDD, and
Even if the number of terminals of power supplies such as VSS and GND (hereinafter, the power supply also refers to VCC, VDD, VSS, GND, etc.) is increased, the number of terminals of the package is not increased and the semiconductor chip 11 is connected to the semiconductor chip 11. In order to improve the power supply capability of the semiconductor chip 11, the corner portion of the semiconductor chip 11 and the package portion corresponding to this corner portion have various measures described below.

That is, in a normal semiconductor integrated circuit, buffers for input, output, input / output, etc. are arranged on the periphery of a semiconductor chip, and in particular, a corner portion of the semiconductor chip constitutes an integrated circuit including a transistor. Each element, and also various power sources and signal lines are vacant areas (dead areas) in which the wiring is not arranged. In the present embodiment, first, the corners of the semiconductor chip 11, which are the vacant areas, should be strengthened. The layout of the required power supply pattern 11a is arranged, and the power supply bonding pad 12a as an example of the power supply terminal is arranged.
Is provided. And the position corresponding to this corner portion of the die pad 13 is defined as the power supply inner lead portion 13a,
The power source bonding pad 12a and the power source inner lead portion 13a are configured to be wire-bonded by a wire 16a which is an example of a connecting means. That is, the power source is the wire 16a and the power source bonding pad 12
It can be supplied to the power supply pattern 11a of the semiconductor chip 11 via a.

Here, in particular, in this embodiment, the semiconductor chip
Die pad (island) for taking 11 substrate potential 13
And a power source (for example, GND) are commonly used, a stable back bias and power source can be supplied to the semiconductor chip 11, and the power source pattern on the substrate 14 is wider than that of a normal signal line to be more stable. It is configured to be able to supply power.

Thus, by arranging the power supply bonding pad 12a for strengthening the power supply in the corner portion of the semiconductor chip 11 and utilizing the vacant area, the area of the semiconductor chip 11 is not particularly increased. Furthermore, by providing a power supply wiring pattern at the corners of the package, there is no need for advanced wire bonding technology at the corners unlike the conventional package, and wire bonding and package This is extremely advantageous because it allows a margin for pattern formation and ensures the reliability of packaging.

When the number of power supply terminals required is small, the conventional method can be applied, but it is also possible to provide the power supply terminals only at the corners of the semiconductor chip and the package as in the embodiment shown in FIG. It is possible. In addition, in the case of a multi-pin chip or package having a large number of terminals, a power supply terminal can be newly added to a corner portion in addition to a semiconductor chip or a power supply terminal on an arbitrary side of the package in order to strengthen the power supply. Even when it is not necessary to strengthen the power supply, the power supply pattern on any side can be placed in the corner to reduce the number of pins and prevent the power supply from adversely affecting other signals. Is also possible.

As described above, according to the first embodiment, the width, pitch, etc. of the signal wiring of the package can be increased without increasing the number of terminals of the package regardless of the number of terminals on the semiconductor chip 11. It does not require fine processing technology, new multilayer wiring layer or wiring technology, and does not use advanced wire bonding technology at the corners of the semiconductor chip 11, and further, impedance between signal lines, inductance, coupling, etc. Without being affected by the noise of
Sufficient power supply can be realized.

Next, a second embodiment of the present invention will be described with reference to FIG. The second embodiment is an embodiment in which the power supply potential to be strengthened is not the same as the substrate potential of the semiconductor chip, or is compatible with a power supply of a system different from the substrate potential.

In FIG. 2, the semiconductor integrated circuit device includes a semiconductor chip 21 having a bonding pad 22 constituting a signal input / output terminal, a power supply pattern 21a, and a power supply bonding pad 22a arranged on the upper surface, and a package. Die pad 23 provided on the substrate 24 of the semiconductor chip 21 to which the semiconductor chip 21 is die-bonded, a wiring pattern 25 including an inner power source inner portion 25a, and an inner power source inner portion 25a. And power supply bonding pad 22
It has a wire 26a for electrically connecting with a. That is,
The second embodiment is similar to the first embodiment in that the semiconductor chip and the corner portion of the package are used. However, in the second embodiment, the pattern on the die pad 23 is not electrically connected to the power supply bonding pad 22a, and instead, the power supply bonding pad 22a is used.
22a is connected to an inner lead portion 25a provided on the corner portion by a wire 26a. As a result, in the second embodiment as well, it is possible to realize stable power supply without increasing the number of terminals of the package as much as possible, and without requiring fine processing technology, new multilayer wiring technology, or advanced bonding technology. You can

Next, a third embodiment of the present invention will be described with reference to FIG.

In FIG. 3, the semiconductor integrated circuit device is provided on a semiconductor chip 31 on which a power source pattern 31a and power source bonding pads 32a are arrayed and formed, and on a package substrate 34. 31 is die-bonded, and includes a die pad 33 including an inner power source portion 33a, a wiring pattern 35 including an inner power source portion 35a, and these inner power source portions.
Wires 36a for electrically connecting the power supply bonding pads 32a to the power supply bonding pads 32a. That is, in the third embodiment, the power source having the same potential as the substrate potential is commonly used as in the first embodiment to strengthen the power source, and the bonding with another power source as in the second embodiment is also possible. This is an example. Therefore, also in the third embodiment, the first and second
Similar to the embodiment, it is possible to realize stable power supply without increasing the number of terminals of the package as much as possible, and without requiring fine processing technology, new multilayer wiring technology, or advanced bonding technology.

Next, a fourth embodiment of the present invention will be described with reference to FIG. The fourth embodiment is similar to the first to third embodiments in that the corner portion of the chip is utilized, and in addition to that, the wiring pattern on the package side is devised. ..

In FIG. 4, the semiconductor integrated circuit device is provided on a semiconductor chip 41 having a bonding pad 42a for power supply and bonding pads 42 for signal input / output arranged on the upper surface thereof, and a substrate 44 of a package. The semiconductor chip 41 is die-bonded and the power supply inner
The die pad 43 including the power source inner portion 43a, the wiring pattern 45 including the power source inner portion 45a, and the power source inner layer portions 43a and 45a and the power source bonding pad 42a are electrically connected. It has a wire 46a for That is, in the fourth embodiment, the power source common to the substrate bias is such that the die pad 43 can be bonded from any position on the semiconductor chip 41.
By slightly expanding the exposed area of 43 and extending parallel to each side of the die pad 43 for another power supply, it is also possible to bond with the power supply bonding pad 42a at any position on the semiconductor chip 41 by the wire 46a. In this embodiment, the power supply capacity is further improved.

According to the embodiment shown in FIGS. 1 to 4,
Utilizing an empty area which is a corner portion on the semiconductor chip and forming a power source pattern on the package portion corresponding to this corner portion, or forming a power source for the substrate bias of the semiconductor chip and another power source pattern around it. The number of terminals of the package is increased regardless of an increase in the number of terminals on the semiconductor chip by arranging and bonding the necessary number of wires directly to the die pad pattern and other power source patterns from the bonding pads of the semiconductor chip by wires. In addition, it does not require special fine technology such as the pitch of the signal line wiring of the package or multi-layer wiring technology, and is not affected by noise such as impedance between signal lines, inductance and coupling as much as possible. It is possible to realize various power supplies.

The package of this embodiment as described above includes a plastic (mold) type package, a ceramic type (sardip, sark, etc.) package, and a printed circuit board type package. , TCP (tape carrier package), COG (chip on glass), COB (chip on board) type packages, etc. can be used.
As the bonding method, in addition to the wire bonding method described above, a wireless bonding method such as TAB (tape automated mating) or flip chip bonding can be adopted.

[0029]

As described in detail above, according to the present invention, a semiconductor integrated circuit composed of a semiconductor chip having a power supply terminal at a corner portion and a power supply at a position corresponding to a corner portion of the semiconductor chip. Since it has a package having an inner inner portion and a connecting means for electrically connecting the power source terminal and the power inner portion, it is possible to form a semiconductor chip with the same number of terminals in the same package. Sufficient power supply can be provided, and an increase in the number of package terminals, a complicated and fine package frame or pattern, and an advanced wire bonding technique are not required. In addition, the chip area of the integrated circuit is not affected, and the power supply can be increased by increasing the number of power supply terminals by the conventional technique, and signals other than power supply related signals are not adversely affected. Therefore, even in an integrated circuit that requires high-speed operation, it is possible to supply a stable power supply as much as possible.

As described above, it becomes possible to supply a stable power as much as possible even in an integrated circuit requiring a high-speed operation while suppressing an increase in manufacturing cost to a minimum, and therefore, reliability and stability of operation of the device. The property is extremely improved.

As a result of the above, according to the present invention, it is possible to provide a semiconductor integrated circuit device which meets the demands for manufacturing cost reduction, high integration, and high functionality, and which is highly reliable and can operate at high speed.

[Brief description of drawings]

FIG. 1 is a partially enlarged plan view showing a wiring state of a corner portion of a semiconductor chip and a package portion corresponding to the corner portion in a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a partially enlarged plan view showing a wiring state of a corner portion of a semiconductor chip and a package portion corresponding to the corner portion in a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a partially enlarged plan view showing a wiring state of a corner portion of a semiconductor chip and a package portion corresponding to the corner portion in a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 4 is a partial plan view showing a wiring state of a semiconductor chip and a package in a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 5 is a partial plan view showing a wiring state of a semiconductor chip and a package in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

11, 21, 31, 41 Semiconductor chip 12a, 22a, 32a, 42a Power supply bonding pad 13a, 25a, 33a, 35a, 43a, 45a Power supply inner portion 16a, 26a, 36a, 46a Wire

Claims (3)

[Claims] 1. A semiconductor integrated circuit comprising a semiconductor chip having a power supply terminal at a corner portion, and a power supply inner lead portion at a position where the semiconductor integrated circuit is enclosed and corresponds to a corner portion of the semiconductor chip. And a connecting means for electrically connecting the power supply terminal and the power supply inner lead portion. 2. The semiconductor chip comprises a die pad die-bonded thereto, and a portion of the die pad corresponding to a corner portion of the semiconductor chip is the power supply terminal as a part of the power supply inner lead portion. 2. The semiconductor integrated circuit device according to claim 1, which is electrically connected to. 3. The connection means comprises a wire for wire-bonding the power supply terminal and the power supply inner lead portion.
The semiconductor integrated circuit device described.