JP2541532B2 - Semiconductor module - Google Patents

Semiconductor module

Info

Publication number
JP2541532B2
JP2541532B2 JP596587A JP596587A JP2541532B2 JP 2541532 B2 JP2541532 B2 JP 2541532B2 JP 596587 A JP596587 A JP 596587A JP 596587 A JP596587 A JP 596587A JP 2541532 B2 JP2541532 B2 JP 2541532B2
Authority
JP
Japan
Prior art keywords
semiconductor device
package
lead
semiconductor
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP596587A
Other languages
Japanese (ja)
Other versions
JPS63175454A (en
Inventor
鈴木  茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP596587A priority Critical patent/JP2541532B2/en
Publication of JPS63175454A publication Critical patent/JPS63175454A/en
Application granted granted Critical
Publication of JP2541532B2 publication Critical patent/JP2541532B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、樹脂封止型半導体装置及びそれを使用した
電子装置に関し、特に、シングル・インライン・パッケ
ージ型モジュール及びそれに使用される樹脂封止型半導
体装置に適用して有効な技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device and an electronic device using the same, and more particularly, to a single in-line package type module and a resin-sealed resin used therein. The present invention relates to a technology effective when applied to a semiconductor device of the type.

〔従来技術〕[Prior art]

一般に、樹脂封止型(レジンモールド型)半導体装置
の全体構造は、タブの上に半導体チップが搭載され、こ
の半導体チップの電極(パッド)とリードの内部リード
部とがワイヤで電気的接続された後、レジンでモールド
されたものである。
Generally, in the entire structure of a resin-sealed type (resin mold type) semiconductor device, a semiconductor chip is mounted on a tab, and an electrode (pad) of this semiconductor chip and an internal lead portion of a lead are electrically connected by a wire. After that, it is molded with resin.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

このようなレジンモールド型半導体装置を配線基板の
両面に複数個実装してシングル・インライン・パッケー
ジ(以下、SIPという)型モジュールを構成する場合、
前記配線基板上の配線レイアウトが、その表と裏で半導
体装置の信号端子が反対になっているため、複雑とな
り、配線層数も増加する。そこで、基板の表面と裏面で
同じ信号端子を配設し、レジンモールド型半導体装置の
リードを逆曲げにして表裏両面のリード端子(パッド)
の位置を同じにすることが考えられる。この考えを適用
した半導体モジュールとしては、たとえば、特開昭60−
200559号公報に記載されるようなものがある。
When a plurality of such resin mold type semiconductor devices are mounted on both sides of a wiring board to form a single in-line package (hereinafter referred to as SIP) type module,
The wiring layout on the wiring board becomes complicated because the signal terminals of the semiconductor device are opposite to each other on the front and back sides, and the number of wiring layers increases. Therefore, the same signal terminals are arranged on the front and back surfaces of the board, and the leads of the resin mold type semiconductor device are bent in reverse to form lead terminals (pads) on both the front and back sides.
It is possible to make the positions of the same. A semiconductor module to which this idea is applied is disclosed in, for example, JP-A-60-
There is one as described in 200559.

しかしながら、例えば、プラスチック・リーディッド
・チップ・キャリア型パッケージ(以下、PLCCという)
の半導体装置を実装する場合には、前記パッケージはリ
ードを基準として厚さ方向の上下が対称になっておら
ず、つまり外部リードが折り曲げられた側のパッケージ
の裏面と内部リードとの間の厚み寸法が、外部リードを
一方側に折り曲げたパッケージと逆方向に折り曲げたパ
ッケージとで相違することになる。したがって、外部リ
ードが折り曲げられる方向に合わせてリードフレームの
寸法を相違させる必要がある。また、前記配線基板のPL
CC型半導体装置の下にチップコンデンサ(デカップリン
グ用)等の他の電子素子の部品を搭載するようになって
いるため、リードを単純に逆曲げしただけでは、電子素
子にパッケージが接触して実装することができないとい
う問題点を発明者が見い出した。いわゆるPLCC(Plasti
c Leaded Chip Carrier)型の半導体装置については、
例えば、日経マグロウヒル社、1984年6月11日発行、
「日経エレクトロニクス別冊・マイクロデバイセズ」
(P148〜P153)に記載がある。
However, for example, plastic lead chip carrier type package (hereinafter referred to as PLCC)
In the case of mounting the semiconductor device of, the package is not symmetrical in the thickness direction with respect to the lead, that is, the thickness between the back surface of the package on the side where the external lead is bent and the internal lead. The size of the package in which the external lead is bent to one side and the package in which the external lead is bent to the opposite direction are different from each other. Therefore, it is necessary to change the dimensions of the lead frame according to the direction in which the external leads are bent. Also, the PL of the wiring board
Since other electronic element components such as chip capacitors (for decoupling) are mounted under the CC type semiconductor device, simply bending the leads backwards will cause the package to contact the electronic element. The inventor found a problem that it could not be implemented. The so-called PLCC (Plasti
c Leaded Chip Carrier) type semiconductor device,
For example, Nikkei McGraw-Hill Inc., published June 11, 1984,
"Nikkei Electronics Separate Volume, Micro Devices"
(P148 to P153)

本発明の目的は、配線基板の両面に複数の半導体装置
を実装し、各半導体装置の下部に他の電子素子を搭載し
たた電子装置に適用して有効な樹脂封止型半導体を提供
することにある。
An object of the present invention is to provide a resin-encapsulated semiconductor which is effective when applied to an electronic device in which a plurality of semiconductor devices are mounted on both surfaces of a wiring board and other electronic elements are mounted under each semiconductor device. It is in.

本発明の他の目的は、配線基板の両面に複数の半導体
装置を実装した電子装置において、スルーホール配線の
みで共通配線を構成することができる技術を提供するこ
とにある。
Another object of the present invention is to provide a technique capable of forming a common wiring with only through-hole wiring in an electronic device in which a plurality of semiconductor devices are mounted on both surfaces of a wiring board.

本発明の前記ならびにその他の目的と新規な特徴は、
本明細書の記述及び添付図面によって明らかになるであ
ろう。
The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

〔問題点を解決するための手段〕[Means for solving problems]

本願において開示される発明のうち、代表的なものの
概要を簡単に説明すれば、下記のとおりである。
The outline of a typical invention disclosed in the present application is briefly described as follows.

すなわち、本発明の半導体モジュールは、それぞれ内
部リードに連なってパッケージの外方に突出する外部リ
ードがパッケージの裏面方向に折り曲げられるととも
に、パッケージの裏面と内部リードとの間の厚さをパッ
ケージの表面と内部リードの間の厚さよりも薄く形成さ
れた第1と第2の半導体装置を有し、第1の半導体装置
は内部リードの表面側に半導体チップが搭載され、第2
の半導体装置は内部リードの裏面側に半導体チップが搭
載されている。表裏両面の同じ位置にスルーホール配線
を介して接続された信号端子を有する両面実装配線基板
の表裏両面の一方面には、第1の半導体装置と第2の半
導体装置の一方がその外部リードと信号端子とを接続し
て実装され、両面実装配線基板の表裏両面の他方面に
は、第1の半導体装置と第2の半導体装置の他方がその
外部リードと信号端子とを接続して実装されている。
That is, in the semiconductor module of the present invention, the external leads, which are respectively connected to the internal leads and project to the outside of the package, are bent toward the back surface of the package, and the thickness between the back surface of the package and the internal leads is adjusted to the surface of the package. A first semiconductor device having a thickness smaller than the thickness between the inner lead and the inner lead, and the first semiconductor device has a semiconductor chip mounted on the surface side of the inner lead,
In this semiconductor device, a semiconductor chip is mounted on the back surface side of the internal leads. One of the first semiconductor device and the second semiconductor device has an external lead on one side of the front and back surfaces of a double-sided mounting wiring board having signal terminals connected to the same position on the front and back sides through through-hole wiring. The first semiconductor device and the second semiconductor device are mounted on the other surface of the front and back surfaces of the double-sided mounting wiring board by connecting their external leads and signal terminals. ing.

〔作用〕[Action]

前記した手段によれば、表裏両面の同じ位置にスルー
ホール配線を介して接続された信号端子を有する両面実
装配線基板の一方面に第1の半導体装置を実装し、他方
面に第2の半導体装置を実装して半導体モジュールを構
成したことにより、配線基板の表裏両面の同じ位置に同
じ信号端子が配設されているため、スルーホールだけ結
線して共通配線を構成することができるので、配線基板
上の配線が簡単にできる。また、配線のための領域も少
なくできるので、配線層数も低減することができる。
According to the above-mentioned means, the first semiconductor device is mounted on one surface of the double-sided mounting wiring board having the signal terminals connected through the through-hole wiring at the same positions on the front and back surfaces, and the second semiconductor is mounted on the other surface. Since the same signal terminal is arranged at the same position on both front and back surfaces of the wiring board by mounting the device to form a semiconductor module, it is possible to connect only through holes to form a common wiring. Wiring on the board can be done easily. Further, since the area for wiring can be reduced, the number of wiring layers can be reduced.

〔発明の実施例〕Example of Invention

以下、本発明の一実施例を図面を用いて具体的に説明
する。
An embodiment of the present invention will be specifically described below with reference to the drawings.

なお、実施例を説明するための全図において、同一機
能を有するものは同一符号を付け、その繰り返しの説明
は省略する。
In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

第1図は、本発明の一実施例のPLCC型半導体装置の概
略構成を示す断面図である。
FIG. 1 is a sectional view showing a schematic configuration of a PLCC type semiconductor device according to an embodiment of the present invention.

本実施例のPLCC型半導体装置は、第1図に示すよう
に、基板(タブ基板)2の下、つまりリード3の内部リ
ード3Aの裏面側に半導体チップ1を搭載し、半導体チッ
プ1の電極(パッド)とリード3の内部リード3Aとを電
気的に接続するワイヤ4をボンディングした後、レジン
でモールドしてパッケージ5としたものである。そし
て、前記リード3の外部リード3Bを内側に折曲げたもの
である。すなわち、パッケージ5のリード3を基準にし
て厚さが薄い方に半導体チップ1を搭載した半導体装置
であり、パッケージ5の第1図における上下両面のう
ち、外部リード3Bが折り曲げられた側の面がパッケージ
5の裏面5Bとなり、その反対側の面が表面5Aとなり、内
部リード3Aの裏面側に半導体チップ1が搭載されている
ことから、第2の半導体装置となっている。
As shown in FIG. 1, the PLCC type semiconductor device of this embodiment has a semiconductor chip 1 mounted under a substrate (tab substrate) 2, that is, on the back surface side of an internal lead 3A of a lead 3, and an electrode of the semiconductor chip 1 After the wire 4 for electrically connecting the (pad) and the internal lead 3A of the lead 3 is bonded, it is molded with a resin to form a package 5. The outer lead 3B of the lead 3 is bent inward. That is, it is a semiconductor device in which the semiconductor chip 1 is mounted on the thinner side with respect to the leads 3 of the package 5, and in the upper and lower surfaces of the package 5 in FIG. Is the back surface 5B of the package 5, and the opposite surface is the front surface 5A. Since the semiconductor chip 1 is mounted on the back surface side of the internal lead 3A, it is a second semiconductor device.

また、第2図に示すPLCC型半導体装置は、通常のPLCC
型半導体装置であり、前記第1図のPLCC型半導体装置の
タブ2の上、つまり内部リードの表面側に半導体チップ
を搭載したものである。すなわち、パッケージ5のリー
ド3を基準にして厚さが厚い方に半導体チップ1を搭載
した半導体装置であり、パッケージ5の第2図における
上下両面のうち、外部リード3Bが折り曲げられた側の面
がパッケージ5の裏面5Bとなり、その反対側の面が表面
5Aとなり、内部リード3Aの表面側に半導体チップ1が搭
載されていることから、第1の半導体装置となってい
る。
Moreover, the PLCC type semiconductor device shown in FIG.
1 is a semiconductor device having a semiconductor chip mounted on the tab 2 of the PLCC semiconductor device shown in FIG. 1, that is, on the surface side of the internal lead. That is, it is a semiconductor device in which the semiconductor chip 1 is mounted on the thicker side with respect to the leads 3 of the package 5, and the surface on the side where the external lead 3B is bent, of the upper and lower surfaces of the package 5 in FIG. Is the back side 5B of the package 5, and the opposite side is the front side.
Since the semiconductor chip 1 is mounted on the front surface side of the internal lead 3A, it is a first semiconductor device.

また、第3図及び第4図(SIPモジュールのプリント
配線基板の表面及び裏面の概要構成を示す平面図)に示
すように、SIPモジュールのプリント配線基板10は、そ
の表面11及び裏面12には半導体装置の外部リードを電気
的に接続するための配線の信号端子(パッド)13、リー
ドピンを取り付けるための接続端子(パッド)14及びチ
ップコンデンサ(デカップリングコンデンサ)を搭載す
るための接続端子15がそれぞれ設けられている。そし
て、表面11に実装される半導体装置と裏面12に実装され
る半導体装置の同じ信号端子13が、プリント配線基板10
の表裏両面の同じ位置に来るように設けられている。ま
た、前記表面11と裏面12との同じ信号端子13は、表裏両
面の同じ位置にあるため、スルーホール配線(図示して
いない)だけで結線され、共通配線を構成している。
In addition, as shown in FIGS. 3 and 4 (plan views showing the schematic configuration of the front and back surfaces of the printed wiring board of the SIP module), the printed wiring board 10 of the SIP module has a front surface 11 and a back surface 12 respectively. Signal terminals (pads) 13 for wiring for electrically connecting the external leads of the semiconductor device, connection terminals (pads) 14 for attaching lead pins, and connection terminals 15 for mounting chip capacitors (decoupling capacitors) are provided. Each is provided. The same signal terminals 13 of the semiconductor device mounted on the front surface 11 and the semiconductor device mounted on the back surface 12 are connected to the printed wiring board 10.
It is provided so that it comes to the same position on both front and back sides. Further, since the same signal terminals 13 on the front surface 11 and the back surface 12 are located at the same positions on both front and back surfaces, they are connected only by through-hole wiring (not shown) to form a common wiring.

そして、第5図(SIPモジュールの要部断面図)に示
すように、このように信号端子13及び接続端子14,15が
設けられているプリント配線基板10の接続端子15にチッ
プコンデンサ16が搭載され、次にプリント配線基板10の
表面11の信号端子13上に、パッケージ5のリード3を基
準にして厚さが薄い方に半導体チップ1を搭載した第2
の半導体装置17が、裏面12の信号端子15上にパッケージ
5のリード3を基点にして厚さが厚い方に半導体チップ
1を搭載した第1の半導体装置18が実装され、SIPモジ
ュールが構成される。
Then, as shown in FIG. 5 (a cross-sectional view of the main part of the SIP module), the chip capacitor 16 is mounted on the connection terminal 15 of the printed wiring board 10 on which the signal terminal 13 and the connection terminals 14 and 15 are thus provided. Then, on the signal terminal 13 on the surface 11 of the printed wiring board 10, the semiconductor chip 1 is mounted on the signal terminal 13 on the surface 11 of the printed wiring board 10 in the thinner direction with reference to the leads 3 of the package 5.
The semiconductor device 17 is mounted with the first semiconductor device 18 in which the semiconductor chip 1 is mounted on the signal terminal 15 on the back surface 12 on the thicker side from the lead 3 of the package 5 as a base point, and the SIP module is configured. It

前述のように、パッケージ5のリード3を基準にして
厚さが薄い方に半導体チップ1を搭載した第2の半導体
装置17を作製し、この半導体装置17をプリント配線基板
10の表面11に実装し、裏面12上にパッケージ5のリード
3を基準にして厚さが厚い方に半導体チップ1を搭載し
た第1の半導体装置18を実装したSIPモジュール(電子
装置)を構成したことにより、プリント配線基板10の表
裏両面の同じ位置に同じ信号端子13が設けられているた
め、スルーホール配線だけで結線して共通配線を構成す
ることができるので、プリント配線基板10上の配線が簡
単にできる。また、配線のための領域も少なくできるの
で、配線層数も低減することができる。
As described above, the second semiconductor device 17 having the semiconductor chip 1 mounted on the thinner side of the lead 3 of the package 5 is manufactured, and the semiconductor device 17 is mounted on the printed wiring board.
A SIP module (electronic device) having a first semiconductor device 18 mounted on the front surface 11 of 10 and a semiconductor chip 1 mounted on the back surface 12 with the thicker one based on the leads 3 of the package 5 is configured. By doing so, since the same signal terminal 13 is provided at the same position on both front and back surfaces of the printed wiring board 10, it is possible to form a common wiring by connecting only through-hole wiring. Wiring is easy. Further, since the area for wiring can be reduced, the number of wiring layers can be reduced.

また、前述のように半導体チップ1をタブ2の下部側
に取り付けるだけで、通常のモールドキャビティにセッ
トし、レジンモールドする。したがって、半導体チップ
1が内部リード3Aの表面側に搭載された第1の半導体装
置18と、半導体チップ1が内部リード3Aの裏面側に搭載
された第2の半導体装置17とでは、パッケージ5全体の
サイズが同一となるとともに、それぞれのパッケージ5
の裏面と内部リード3Aとの間の厚さ寸法、つまりリード
を基準とした厚さが薄い方の厚さ寸法が相互に同一とな
り、逆の厚さが厚い方の厚さ寸法も相互に同一となる。
そのまま通常の切断,成形を行うことができるので、従
来の設備,装置,プロセスを変更せずに端子位置を反転
し、つまり相互に鏡面対称となったパッケージを作るこ
とができる。
Further, as described above, the semiconductor chip 1 is simply attached to the lower side of the tab 2 and set in a normal mold cavity for resin molding. Therefore, with the first semiconductor device 18 in which the semiconductor chip 1 is mounted on the front surface side of the internal lead 3A and the second semiconductor device 17 in which the semiconductor chip 1 is mounted on the back surface side of the internal lead 3A, the entire package 5 is Of the same size and each package 5
The thickness between the back surface of the internal lead 3A and the inner lead 3A, that is, the thickness of the thinner lead is the same, and the opposite is the same. Becomes
Since normal cutting and molding can be performed as they are, it is possible to reverse the terminal positions without changing the conventional equipment, devices, and processes, that is, to make packages that are mirror-symmetric to each other.

以上、本発明を実施例にもとづき具体的に説明した
が、本発明は、前記実施例に限定されるものではなく、
その要旨を逸脱しない範囲において種々変更可能である
ことは言うまでもない。
As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various modifications can be made without departing from the spirit of the invention.

前記実施例では、本発明をPLCC型半導体装置に適用し
た例で説明したが、本発明は、樹脂封止型半導体装置す
べてに適用することができる。
In the above embodiments, the present invention is applied to the PLCC semiconductor device, but the present invention can be applied to all resin-sealed semiconductor devices.

〔発明の効果〕〔The invention's effect〕

本願において開示される発明のうち代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。
The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application.

半導体チップが内部リードの表面側に搭載された第1
の半導体装置と、半導体チップが内部リードの裏面側に
搭載された第2の半導体装置とを作製し、それぞれのパ
ッケージの裏面方向に外部リードを折り曲げてリード端
子を構成し、スルーホールで同じ位置に信号端子が設け
られた両面実装型配線基板の一面上に前記第1の半導体
装置を実装し、他面上に第2の半導体装置を実装するよ
うに構成したことにより、両面実装型配線基板の表裏両
面の同じ位置に同じ信号端子が配設されているため、ス
ルーホール配線だけで結線して共通配線を構成すること
ができるので、配線基板上の配線が簡単にできる。ま
た、配線のための領域も少なくできるので、配線層数も
低減することができる。さらに、第1の半導体装置のリ
ードと第2の半導体装置のリードとを同種のリードフレ
ームを用いて製造することができるので、1種類のリー
ドフレームを用いて第1の半導体装置と第2の半導体装
置を製造することができ、低コストで効率良く半導体モ
ジュールを製造することが可能となる。
First semiconductor chip mounted on the surface side of the internal lead
And the second semiconductor device in which the semiconductor chip is mounted on the back surface side of the internal lead, and the external lead is bent toward the back surface of each package to form a lead terminal, and the same position is formed in the through hole. Since the first semiconductor device is mounted on one surface of the double-sided mounting type wiring board on which the signal terminals are provided, and the second semiconductor device is mounted on the other side thereof, the double-sided mounting type wiring board is formed. Since the same signal terminals are arranged at the same positions on both front and back sides, the common wiring can be configured by connecting only through-hole wiring, so that the wiring on the wiring board can be simplified. Further, since the area for wiring can be reduced, the number of wiring layers can be reduced. Furthermore, since the leads of the first semiconductor device and the leads of the second semiconductor device can be manufactured using the same type of lead frame, the first semiconductor device and the second semiconductor device can be manufactured using one type of lead frame. A semiconductor device can be manufactured, and a semiconductor module can be manufactured efficiently at low cost.

【図面の簡単な説明】 第1図は、PLCC型の第2の半導体装置の概略構成を示す
断面図、 第2図は、PLCC型の第1の半導体装置の概略構成を示す
断面図、 第3図は、SIP型の半導体モジュールのプリント配線基
板の表面を示す平面図、 第4図は、SIP型の半導体モジュールのプリント配線基
板の裏面を示す平面図、 第5図は、SIPの型半導体モジュールの要部断面図であ
る。 図中、1……半導体チップ、2……タブ、3……リー
ド、3A……内部リード、3B……外部リード、4……ワイ
ヤ、5……パッケージ、5A……パッケージの表面、5B…
…パッケージの裏面、10……プリント配線基板(両面実
装型配線基板)、11……プリント配線基板の表面、12…
…プリント配線基板の裏面、13……信号端子、14,15…
…接続端子、16……チップコンデンサ、17……第2の半
導体装置、18……第1の半導体装置である。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a schematic configuration of a PLCC type second semiconductor device, and FIG. 2 is a sectional view showing a schematic configuration of a PLCC type first semiconductor device. 3 is a plan view showing a front surface of a printed wiring board of a SIP type semiconductor module, FIG. 4 is a plan view showing a back surface of a printed wiring board of a SIP type semiconductor module, and FIG. 5 is a SIP type semiconductor. It is a principal part sectional drawing of a module. In the figure, 1 ... semiconductor chip, 2 ... tab, 3 ... lead, 3A ... internal lead, 3B ... external lead, 4 ... wire, 5 ... package, 5A ... package surface, 5B ...
… Backside of package, 10 …… Printed wiring board (double-sided mounting type wiring board), 11 …… Front surface of printed wiring board, 12…
… The back of the printed wiring board, 13 …… Signal terminals, 14,15…
... connection terminal, 16 ... chip capacitor, 17 ... second semiconductor device, 18 ... first semiconductor device.

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】内部リードに連なってパッケージの外方に
突出する外部リードが前記パッケージの裏面方向に折り
曲げられるとともに、前記パッケージの裏面と前記内部
リードとの間の厚さを前記パッケージの表面と前記内部
リードの間の厚さよりも薄く形成し、半導体チップが前
記内部リードの表面側に搭載される第1の半導体装置
と、 内部リードに連なってパッケージの外方に突出する外部
リードが前記パッケージの裏面方向に折り曲げられると
ともに、前記パッケージの裏面と前記内部リードとの間
の厚さを前記パッケージの表面と前記内部リードの間の
厚さよりも薄く形成し、半導体チップが前記内部リード
の裏面側に搭載される第2の半導体装置と、 表裏両面の同じ位置にスルーホール配線を介して接続さ
れた信号端子を有する両面実装配線基板とを有し、 前記両面実装配線基板の前記表裏両面の一方面に、前記
第1の半導体装置と第2の半導体装置の一方をその外部
リードと前記信号端子とを接続して実接する一方、前記
両面実装配線基板の前記表裏両面の他方面に、前記第1
の半導体装置と前記第2の半導体装置の他方をその外部
リードと前記信号端子とを接続して実装したことを特徴
とする半導体モジュール。
1. An outer lead, which is continuous with an inner lead and protrudes outward of a package, is bent toward a back surface of the package, and a thickness between the back surface of the package and the inner lead is set to a surface of the package. The first semiconductor device is formed to be thinner than the thickness between the inner leads, and the semiconductor chip is mounted on the front surface side of the inner leads, and the outer leads that are continuous with the inner leads and project to the outside of the package. And the semiconductor chip is formed so that the thickness between the back surface of the package and the internal lead is thinner than the thickness between the front surface of the package and the internal lead. Both the second semiconductor device mounted on the board and the signal terminal connected through through-hole wiring at the same position on both front and back surfaces. A mounting wiring board, and one of the first semiconductor device and the second semiconductor device is connected to one of the front and back surfaces of the double-sided mounting wiring board by connecting the external lead and the signal terminal. On the other hand, on the other side of the front and back surfaces of the double-sided mounting wiring board, the first
2. A semiconductor module in which the other of the semiconductor device and the second semiconductor device is mounted by connecting its external lead and the signal terminal.
【請求項2】前記それぞれの半導体装置が前記両面実装
配線基板の表裏両面にそれぞれ複数個実装したことを特
徴とする特許請求の範囲第1項に記載の半導体モジュー
ル。
2. The semiconductor module according to claim 1, wherein a plurality of the respective semiconductor devices are mounted on both front and back surfaces of the double-sided mounting wiring board.
【請求項3】前記それぞれの半導体装置は、シングル・
インライン・パッケージ型半導体装置であることを特徴
とする特許請求の範囲第1項または第2項に記載の半導
体モジュール。
3. Each of the semiconductor devices is a single
The semiconductor module according to claim 1 or 2, which is an in-line package type semiconductor device.
【請求項4】前記それぞれの半導体装置がプラスチック
・リーディッド・チップ・キャリア型半導体装置である
ことを特徴とする特許請求の範囲第1項ないし第3項の
いずれかに記載の半導体モジュール。
4. The semiconductor module according to any one of claims 1 to 3, wherein each of the semiconductor devices is a plastic read chip carrier type semiconductor device.
JP596587A 1987-01-16 1987-01-16 Semiconductor module Expired - Fee Related JP2541532B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP596587A JP2541532B2 (en) 1987-01-16 1987-01-16 Semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP596587A JP2541532B2 (en) 1987-01-16 1987-01-16 Semiconductor module

Publications (2)

Publication Number Publication Date
JPS63175454A JPS63175454A (en) 1988-07-19
JP2541532B2 true JP2541532B2 (en) 1996-10-09

Family

ID=11625589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP596587A Expired - Fee Related JP2541532B2 (en) 1987-01-16 1987-01-16 Semiconductor module

Country Status (1)

Country Link
JP (1) JP2541532B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2634516B2 (en) * 1991-10-15 1997-07-30 三菱電機株式会社 Manufacturing method of inverted IC, inverted IC, IC module
US5747874A (en) * 1994-09-20 1998-05-05 Fujitsu Limited Semiconductor device, base member for semiconductor device and semiconductor device unit
US9230890B2 (en) 2012-04-27 2016-01-05 Lapis Semiconductor Co., Ltd. Semiconductor device and measurement device
JP6116817B2 (en) * 2012-04-27 2017-04-19 ラピスセミコンダクタ株式会社 Resin sealing method and semiconductor device manufacturing method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5879739A (en) * 1981-11-05 1983-05-13 Toshiba Corp Sheath for semiconductor
JPS58140141A (en) * 1982-02-16 1983-08-19 Nec Corp Resin sealed type semiconductor device

Also Published As

Publication number Publication date
JPS63175454A (en) 1988-07-19

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