JPS58140141A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPS58140141A JPS58140141A JP2320282A JP2320282A JPS58140141A JP S58140141 A JPS58140141 A JP S58140141A JP 2320282 A JP2320282 A JP 2320282A JP 2320282 A JP2320282 A JP 2320282A JP S58140141 A JPS58140141 A JP S58140141A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- thickness
- wall thickness
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
本発明は樹脂封止型半導体装置にかかシ、内部リードの
平面に対して半導体ベレットが載置されるアイランドの
平面が下方に位置されている構造（以下ディンプル構造
と称す）の薄型樹脂封止半導体装置に関する。Detailed Description of the Invention The present invention provides a resin-sealed semiconductor device having a structure (hereinafter referred to as a dimple structure) in which the plane of the island on which the semiconductor pellet is placed is located below the plane of the lid and internal leads. This invention relates to a thin resin-sealed semiconductor device.
従来、ディンプル構造でない半導体装量はボンディング
ワイヤーが半導体ベレットと接触しそうになる場合が多
く、この場合ボンティングワイヤーの引き上げ尋の修正
をしなけれはならなかったが、ディンプル構造のものは
この修正の工数をなくシ、組立工程の安定化をはかる構
造としてデ。Conventionally, in the case of semiconductor components that do not have a dimple structure, the bonding wire often comes into contact with the semiconductor pellet, and in this case, it is necessary to correct the raising width of the bonding wire. Designed as a structure that eliminates man-hours and stabilizes the assembly process.
アルインライン製樹脂封止半導体装置に使われている。Used in Alinline resin-sealed semiconductor devices.
このディンプル構造の効果は大きい。しかし、全樹脂肉
厚が１．５關程度の薄型半導体装置においては、以下の
理山でディンプル構造は実現できなかった。This dimple structure has a great effect. However, in a thin semiconductor device with a total resin wall thickness of about 1.5 degrees, a dimple structure could not be realized using the following rationale.
第１に従来の構造は内部リードから上方の樹脂肉厚と下
方の樹脂肉厚とが同じであるか、又は第１図に断面図を
示すように封止樹脂１１の上方の樹脂肉厚ｌの方が下方
の樹脂肉厚ｍよシも大きかったために、上方と下方の樹
脂肉厚の関係が従来のままでディンプル構造にすれば、
アイランド１５から下方の樹脂肉厚が＆端Ｋｌｌ＜なシ
、温度サイクル試験部の熱的環境試験でこの部分に樹脂
クラ、りが発生し、信頼性が低下した。First, in the conventional structure, the resin wall thickness above the internal lead is the same as the resin wall thickness below, or the resin wall thickness above the sealing resin 11 is l as shown in the cross-sectional view in FIG. Since the lower resin wall thickness m was larger in , if the relationship between the upper and lower resin thicknesses remains the same as before and a dimple structure is used,
When the resin wall thickness below the island 15 was less than the end Kll, resin cracking occurred in this part during the thermal environment test in the temperature cycle test section, reducing reliability.
第２に樹脂クラックが発生しないようにアイラノド１ｓ
０位飯を内部リード１４の位置よシ少しだけ下けた程度
ではディンプル構造の効果を十分に発揮できずボンディ
ングワイヤー１２の修正を完全になくすことはできなか
った。また、全樹脂肉厚を厚くすれは樹脂クラックは発
生しなくなるがｒＩＩＩ蚤という％命が損われた。尚、
第１図で１３は半導体ペレットである。Secondly, to prevent resin cracks,
Even if the 0-position metal was moved slightly lower than the position of the internal lead 14, the effect of the dimple structure could not be fully exhibited, and the need for modification of the bonding wire 12 could not be completely eliminated. Furthermore, when the total resin thickness was increased, resin cracks no longer occurred, but the life of rIII fleas was lost. still,
In FIG. 1, 13 is a semiconductor pellet.
不発もの目的は全樹脂肉厚は従来の１まで、ボンティン
グワイヤーの修正をティンプル構造によって完全になく
して組立工数の削減と組立工程の安定化をはかシ、かつ
ディンプル構造にしたことによる樹脂クラ、りの発生麹
の信頼性の低下のない＃＃型衛脂封止半導体装置を提供
することにある。The purpose of the dud is to reduce the total resin wall thickness to 1 compared to the conventional one, completely eliminate the need to modify the bonding wire by using a dimple structure, reduce assembly man-hours, and stabilize the assembly process. It is an object of the present invention to provide a ## type sanitary and grease-sealed semiconductor device that does not cause deterioration in the reliability of koji that causes cracks and rips.
上ｌじ目的を達成するため本発明は、内部リードから下
方の樹脂肉厚が内部リードから上方の樹脂肉離よりも厚
いことを％黴とする。In order to achieve the above object, the present invention determines that the resin wall thickness below the inner lead is thicker than the resin wall thickness above the inner lead.
以下、図面を用いて本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail using the drawings.
第２図は本発明の実施例を示す断面図である。FIG. 2 is a sectional view showing an embodiment of the present invention.
内部リード１４とアイランド１５との位置差（以下ディ
ンプル量と称す）をＤとすると、内部リード１４から下
方の樹脂肉厚Ｍは従来のものに比ベディンプル量りだけ
厚く、内部リード１４から上方の樹脂肉厚りはディンプ
ル量りだけ薄くなっておシ、結局、全樹脂肉厚Ｔは従来
のものと同じである。従来の半導体装置と本発明の実施
例の半導体装置との厚さの関係を表１に示す。If the positional difference between the internal lead 14 and the island 15 (hereinafter referred to as dimple amount) is D, the resin wall thickness M below the internal lead 14 is thicker than the conventional one by the amount of dimples, and the resin wall thickness M below the internal lead 14 is thicker than the conventional one. The resin wall thickness becomes thinner by the amount of dimples, and in the end, the total resin wall thickness T is the same as the conventional one. Table 1 shows the relationship in thickness between a conventional semiconductor device and a semiconductor device according to an embodiment of the present invention.
表１ 厚さの関係（単位■）
従来の半導体装ｋ（ａ）と、樹脂肉厚！９ｍは従来のも
のと同じであるがディンプル量α３關のディンプル構造
をもつ半導体装置（ｂ）と、同じディンプル量α３１１
ＢＴｈもつ本発明の実施例の半導体装置（ｃ）とのボン
ティングワイヤーの修正率および温度サイクル試験結果
を表２に示す。Table 1 Thickness relationship (unit ■) Conventional semiconductor device k(a) and resin wall thickness! 9m is the same as the conventional one, but the semiconductor device (b) has a dimple structure with a dimple amount α3, and the semiconductor device (b) has the same dimple amount α311.
Table 2 shows the modification rate and temperature cycle test results of the bonding wire with the semiconductor device (c) of the embodiment of the present invention having BTh.
半導体装＆ ：５２ビン、全樹脂肉厚１．５龍アイ
ランドサイズ：０．６Ｘ０．６■２デインプル量 ：０
，３１＋１１
樹 脂 二市販のエポキシ樹脂
試験条件 ニー６５℃〜室温〜＋１５０℃のサイク
ル
表２ 修正率と温度サイクル試験結果
＆２から明らかなように、本発明の実施例（ｃ）は従来
と簡じ樹脂肉厚で従来のものに比べて温度サイクル性を
低下させること危くボンディングワイヤーの修正が完全
になくされ、工数削減と組立工程の安定化がはかられて
いる。Semiconductor packaging &: 52 bottles, total resin wall thickness 1.5 Dragon island size: 0.6X0.6■2 Dimple amount: 0
, 31+11 Resin 2 Commercially available epoxy resin test conditions Cycle table 2 from knee 65°C to room temperature to +150°C As is clear from the correction rate and temperature cycle test results &2, the example (c) of the present invention is the same as the conventional one. This eliminates the need to modify bonding wires, which could reduce temperature cycle performance compared to conventional products due to the thick resin wall, reducing man-hours and stabilizing the assembly process.
また、本発明は下方の樹脂肉厚の増加量はディンプル量
りと同じでなくてもよい。Further, in the present invention, the amount of increase in the lower resin wall thickness does not have to be the same as the dimple measurement.
本発明の半導体装置を作製するためには、トランスファ
ー成形金型の下金型のキャビティ深さを深くシ、上金型
のキャビティ深さを浅くすれば良い０
本発明は薄型樹脂封止半導体装置に限られるものでなく
、デュアルインライン型樹脂封止半導体装置にも同様に
適用できる。In order to manufacture the semiconductor device of the present invention, the depth of the cavity in the lower mold of the transfer molding mold may be made deep, and the depth of the cavity in the upper mold may be made shallow. The present invention is not limited to, but can be similarly applied to a dual in-line resin-sealed semiconductor device.
第１図は従来の薄型樹脂封止半導体装置の断面図である
。第２図はティンプル構造をもつ本発明の実施例の薄型
樹脂封止半導体装置の断面図である。
尚、図においてｍｌｌ・・・・・・封止樹脂、１２・・
す・・ボンディングワイヤー、１３・・・・・・半！（
１ベレ、ト、１４・・・・・・内部リード、１５・・・
・・・アイランド５ｌｅＬ・・・・・・内部リードから
上方の樹脂肉厚、ｍ、Ｍ・・・・・・内部リードから下
あの樹脂肉厚、ｔ、Ｔ・・団・全樹脂肉厚、Ｄ・・・・
・・ディンプル量、ｐ、Ｐ・・・・・・半導体ベレット
の厚さくＰは図示していない）、ｆ。
Ｆ・・・・・・リードの厚さ、ｈ、Ｈ・・・・・・半導
体ベレット表面からのボンティングワイヤーの高さであ
る。
５
第１閏
第２閏FIG. 1 is a sectional view of a conventional thin resin-sealed semiconductor device. FIG. 2 is a sectional view of a thin resin-sealed semiconductor device according to an embodiment of the present invention having a timple structure. In the figure, mll... sealing resin, 12...
Su...bonding wire, 13...and a half! (
1 Bere, G, 14... Internal lead, 15...
...Island 5leL...Resin thickness above the internal lead, m, M...Resin thickness below the internal lead, t, T...Group, total resin thickness, D...
...Dimple amount, p, P... Thickness P of the semiconductor pellet (not shown), f. F: Thickness of the lead, h, H: Height of the bonding wire from the surface of the semiconductor pellet. 5 1st leap 2nd leap
Claims (1)
されるアイランドの平面が下方に位置されてなる樹脂封
止型半導体装置において、該内部リードから下方のモー
ルド肉厚が該内部リードから上方のモールド肉厚よシ厚
いことを％徴とする樹脂封止型半導体装置。In a resin-sealed semiconductor device in which the plane of the island on which the half-I body plate is placed is located below the plane of the inner lead, the thickness of the mold below the inner lead is A resin-sealed semiconductor device characterized by being thicker than the upper mold wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2320282A JPS58140141A (en) | 1982-02-16 | 1982-02-16 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2320282A JPS58140141A (en) | 1982-02-16 | 1982-02-16 | Resin sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58140141A true JPS58140141A (en) | 1983-08-19 |
Family
ID=12104077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2320282A Pending JPS58140141A (en) | 1982-02-16 | 1982-02-16 | Resin sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58140141A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63175454A (en) * | 1987-01-16 | 1988-07-19 | Hitachi Ltd | Resin sealed semiconductor device |
| JPH0283961A (en) * | 1988-09-20 | 1990-03-26 | Hitachi Ltd | Manufacture of semiconductor device, semiconductor device obtained by the method and semiconductor wafer used in the method |
-
1982
- 1982-02-16 JP JP2320282A patent/JPS58140141A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63175454A (en) * | 1987-01-16 | 1988-07-19 | Hitachi Ltd | Resin sealed semiconductor device |
| JPH0283961A (en) * | 1988-09-20 | 1990-03-26 | Hitachi Ltd | Manufacture of semiconductor device, semiconductor device obtained by the method and semiconductor wafer used in the method |
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