JPS6235545A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPS6235545A JPS6235545A JP17448185A JP17448185A JPS6235545A JP S6235545 A JPS6235545 A JP S6235545A JP 17448185 A JP17448185 A JP 17448185A JP 17448185 A JP17448185 A JP 17448185A JP S6235545 A JPS6235545 A JP S6235545A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- semiconductor chip
- stress
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止された半導体装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device.
従来の樹脂封止半導体装置の構成を第3図に示す。図に
おいて、1は半導体チップ、2はフレーム、3はモール
ド樹脂、4はビンである。なお、第3図の右半面では、
ピン及びボンディングワイヤは図示省略している。FIG. 3 shows the configuration of a conventional resin-sealed semiconductor device. In the figure, 1 is a semiconductor chip, 2 is a frame, 3 is a molding resin, and 4 is a bottle. In addition, in the right half of Figure 3,
Pins and bonding wires are not shown.
半導体チップ1はフレーム2に固定されている。A semiconductor chip 1 is fixed to a frame 2.
一方、モールド樹脂3は、高温で成形され、その後常温
にさらされるため、その体積が収縮する。On the other hand, the mold resin 3 is molded at a high temperature and then exposed to room temperature, so its volume shrinks.
半導体チップ1も同様にモールド成形時には高温にさら
され、その後常温にさらされるが上記のように半導体チ
ップ1はフレーム2に固定されており、半導体チップ1
とモールド樹脂3との熱膨張係数が異なり、一般にモー
ルド樹脂3の熱膨張係数が半導体チップ1の熱膨張係数
に比べて大きいため、第4図に矢印7で示したように半
導体チップ1とモールド樹脂3との接触面において、半
導体チップ1の表面と平行に中心に向かって応カフが印
加される。この応カフは半導体チップ1の角の部分で特
に大きい。このため、半導体チップ1上のパシベーショ
ン膜にクランクが生じる。Similarly, the semiconductor chip 1 is exposed to high temperatures during molding and then exposed to room temperature, but as described above, the semiconductor chip 1 is fixed to the frame 2, and the semiconductor chip 1
The coefficient of thermal expansion of the mold resin 3 is different from that of the semiconductor chip 1, and the coefficient of thermal expansion of the mold resin 3 is generally larger than that of the semiconductor chip 1. At the contact surface with the resin 3, a pressure cuff is applied parallel to the surface of the semiconductor chip 1 toward the center. This cuff is particularly large at the corner portions of the semiconductor chip 1. Therefore, a crank occurs in the passivation film on the semiconductor chip 1.
従来の樹脂封止半導体装置は以上のように構成されてい
るので、半導体チップとモールド樹脂との熱膨張係数の
差により半導体チップ表面に応力が印加され、この応力
によってパシベーション膜にクランクが生じる問題があ
った。Conventional resin-sealed semiconductor devices are configured as described above, so stress is applied to the surface of the semiconductor chip due to the difference in thermal expansion coefficient between the semiconductor chip and the molding resin, and this stress causes the problem of cranking of the passivation film. was there.
本発明は上記のような問題点を解消するためになされた
もので、半導体チップ表面に印加される応力を小さくし
た樹脂封止半導体装置を提供することを目的としている
。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a resin-sealed semiconductor device in which stress applied to the surface of a semiconductor chip is reduced.
〔問題点を解決するための手段〕
本発明に係る樹脂封止半導体装置は、半導体チップが固
定されるフレーム上の半導体チップの外側にその高さが
半導体チップの厚みよりも高い応力緩和部材を設けたも
のである。[Means for Solving the Problems] The resin-sealed semiconductor device according to the present invention includes a stress relaxation member whose height is higher than the thickness of the semiconductor chip on the outside of the semiconductor chip on the frame to which the semiconductor chip is fixed. It was established.
本発明においては、応力緩和部材は半導体チップ表面に
印加される応力を緩和する。In the present invention, the stress relaxation member relieves stress applied to the surface of the semiconductor chip.
以下、本発明の一実施例について、第1図を参照して説
明する。第1図は本発明の一実施例による樹脂封止半導
体装置を示し、図において、1は半導体チップ、2はフ
レーム、3はモールド樹脂、4はビン、5は応力緩和部
材である。なお、第1図の右半面ではビンおよびボンデ
ィングワイヤを図示省略している。半導体チップ1はフ
レーム2上に固定されている。また、応力緩和部材5も
フレーム2上に固定されているが、ここでは応力緩和部
材5はフレーム2に対して垂直に固定された場合を示す
。更に、応力緩和部材5の高さは半導体チップ1の厚み
よりも高(なっている。An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a resin-sealed semiconductor device according to an embodiment of the present invention. In the figure, 1 is a semiconductor chip, 2 is a frame, 3 is a molding resin, 4 is a bottle, and 5 is a stress relaxation member. Note that the bottle and bonding wire are not shown on the right half of FIG. 1. A semiconductor chip 1 is fixed on a frame 2. Further, the stress relaxation member 5 is also fixed on the frame 2, but here a case is shown in which the stress relaxation member 5 is fixed perpendicularly to the frame 2. Furthermore, the height of the stress relaxation member 5 is higher than the thickness of the semiconductor chip 1.
次に作用効果について説明する。Next, the effects will be explained.
モールド成形時、モールド樹脂3及び半導体チップ1は
共に高温にさらされる。半導体チップ1がモールド樹脂
封止された後、モールド樹脂3及び半導体チップ1は共
に常温に戻る。この時、半導体チップ1に比ベモールド
樹脂3の熱膨張係数が大きいため、半導体チップ1より
もモールド樹脂30体積収縮は大きく、また、半導体チ
ップ1はフレーム2に固定されているため、半導体チッ
プ1の表面に応力が印加されようとする。この応力は半
導体チップ1の角の部分で最も大きく作用する。しかし
、半導体チップ1の角の部分には応力緩和部材5が設け
られており、その高さが半導体チップ1の厚みよりも高
いため、半導体チップ1の中心方向に向かって収縮しよ
うとするモールド樹脂3の収縮を止める役割を果たし、
半導体チップ1に印加される応力が緩和される。よって
この応力に起因するパシベーション膜のクランクが生じ
なくなる。During molding, both the mold resin 3 and the semiconductor chip 1 are exposed to high temperatures. After the semiconductor chip 1 is sealed with the mold resin, both the mold resin 3 and the semiconductor chip 1 return to room temperature. At this time, since the thermal expansion coefficient of the molding resin 3 is larger than that of the semiconductor chip 1, the volumetric contraction of the molding resin 30 is larger than that of the semiconductor chip 1, and since the semiconductor chip 1 is fixed to the frame 2, the semiconductor chip 1 Stress is about to be applied to the surface of This stress acts most strongly at the corner portions of the semiconductor chip 1. However, since the stress relaxation members 5 are provided at the corner portions of the semiconductor chip 1 and their height is higher than the thickness of the semiconductor chip 1, the mold resin tends to contract toward the center of the semiconductor chip 1. It plays a role in stopping the contraction of 3.
The stress applied to the semiconductor chip 1 is relaxed. Therefore, cranking of the passivation film due to this stress does not occur.
なお、上記実施例では応力緩和部材がフレームに対して
垂直に固定された場合について説明したが、これは半導
体チップ側から見てフレーム表面と鋭角をなすように固
定されていてもよい。In addition, in the above embodiment, a case has been described in which the stress relaxation member is fixed perpendicularly to the frame, but it may be fixed so as to form an acute angle with the frame surface when viewed from the semiconductor chip side.
また、上記実施例では応力緩和部材が半導体チップの角
の部分にのみ設けた場合について説明したが、これは他
の部分に設けてもよく、例えば第2図に示すように半導
体チップの全周を囲む応力緩和部材6を設けてもよい。Further, in the above embodiment, the stress relaxation member is provided only at the corner portion of the semiconductor chip, but it may be provided at other portions, for example, as shown in FIG. A stress relieving member 6 may be provided to surround the.
以上のように、本発明によれば、半導体チップの外側に
半導体チップの厚みよりも高い応力緩和部材を設け、こ
れをフレームに固定したので、半導体チップ表面に印加
される応力を緩和でき、パシベーション腰にクランクが
生じるのを防ぐ効果がある。As described above, according to the present invention, a stress relaxation member that is thicker than the semiconductor chip is provided on the outside of the semiconductor chip and is fixed to the frame, so that the stress applied to the surface of the semiconductor chip can be relaxed and the passivation It has the effect of preventing cranks from forming in the lower back.
第1図は本発明の一実施例による樹脂封止半導体装置を
示す図、第2図は本発明の他の実施例による樹脂封止半
導体装置を示す図、第3図は従来の樹脂封止半導体装置
を示す図、第4図は応力の印加を示す図である。
1・・・半導体チップ、2・・・フレーム、3・・・モ
ールド樹脂、5.6・・・応力緩和部材。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 shows a resin-sealed semiconductor device according to an embodiment of the present invention, FIG. 2 shows a resin-sealed semiconductor device according to another embodiment of the invention, and FIG. 3 shows a conventional resin-sealed semiconductor device. FIG. 4 is a diagram showing the semiconductor device, and FIG. 4 is a diagram showing the application of stress. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Frame, 3... Mold resin, 5.6... Stress relaxation member. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (4)
設する樹脂封止半導体装置において、上記半導体チップ
の外側にその高さがチップの厚みよりも高い応力緩和部
材をフレーム上に固定して設けたことを特徴とする樹脂
封止半導体装置。(1) In a resin-sealed semiconductor device in which a semiconductor chip and a frame are embedded in a mold resin, a stress relaxation member whose height is higher than the thickness of the chip is fixed to the frame and provided on the outside of the semiconductor chip. A resin-sealed semiconductor device characterized by:
フレーム表面と鋭角をなすように上記フレーム上に固定
されたことを特徴とする特許請求の範囲第1項記載の樹
脂封止半導体装置。(2) The resin-sealed semiconductor device according to claim 1, wherein the stress relaxation member is fixed on the frame so as to form an acute angle with the surface of the frame when viewed from the semiconductor chip side.
の外側に設けられたことを特徴とする特許請求の範囲第
1項または第2項記載の樹脂封止半導体装置。(3) The resin-sealed semiconductor device according to claim 1 or 2, wherein the stress relaxation member is provided outside a corner portion of the semiconductor chip.
に設けられたことを特徴とする特許請求の範囲第1項ま
たは第2項記載の樹脂封止半導体装置。(4) The resin-sealed semiconductor device according to claim 1 or 2, wherein the stress relaxation member is provided on the entire outer periphery of the semiconductor chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17448185A JPS6235545A (en) | 1985-08-08 | 1985-08-08 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17448185A JPS6235545A (en) | 1985-08-08 | 1985-08-08 | Resin-sealed semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6235545A true JPS6235545A (en) | 1987-02-16 |
Family
ID=15979233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17448185A Pending JPS6235545A (en) | 1985-08-08 | 1985-08-08 | Resin-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6235545A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4928162A (en) * | 1988-02-22 | 1990-05-22 | Motorola, Inc. | Die corner design having topological configurations |
-
1985
- 1985-08-08 JP JP17448185A patent/JPS6235545A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4928162A (en) * | 1988-02-22 | 1990-05-22 | Motorola, Inc. | Die corner design having topological configurations |
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