JPH0237752A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0237752A JPH0237752A JP63188702A JP18870288A JPH0237752A JP H0237752 A JPH0237752 A JP H0237752A JP 63188702 A JP63188702 A JP 63188702A JP 18870288 A JP18870288 A JP 18870288A JP H0237752 A JPH0237752 A JP H0237752A
- Authority
- JP
- Japan
- Prior art keywords
- mold resin
- resin
- plates
- semiconductor element
- mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000011347 resin Substances 0.000 claims abstract description 50
- 229920005989 resin Polymers 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract description 3
- 230000008646 thermal stress Effects 0.000 abstract description 2
- 238000000465 moulding Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 3
- 238000005219 brazing Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000006082 mold release agent Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に樹脂封止型半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a resin-encapsulated semiconductor device.
従来、樹脂封止型半導体装置は、第４図に示、すように
、リード４１で囲まれたアイランド４２の上に半導体素
子４３をろう材等で固着し、半導体素子４３上のボンデ
ィングバット部４４とリード４１とをボンディングクイ
ヤ４５により電気的に接続した後、モールド樹脂４６に
より封止していいた。Conventionally, as shown in FIG. 4, in a resin-sealed semiconductor device, a semiconductor element 43 is fixed with a brazing material or the like on an island 42 surrounded by leads 41, and a bonding butt portion on the semiconductor element 43 is bonded to the island 42 surrounded by leads 41. 44 and the lead 41 were electrically connected by a bonding wire 45, and then sealed with a molding resin 46.
上述した従来の樹脂封止型半導体装置では、モールド樹
脂自体が水分を通す特性があるので、モールド樹脂中に
多くの水分が侵入している。最近よく使われるようにな
った表面実装のはんだ付けでは、高温に半導体装置をさ
らすなめ、モールド樹脂中の水分が気化し、その水蒸気
がモールド樹脂にクラックを生じさせる欠点がある。In the conventional resin-sealed semiconductor device described above, the molding resin itself has a property of allowing moisture to pass through, so that a large amount of moisture enters the molding resin. Surface mount soldering, which has recently become popular, has the disadvantage that the semiconductor device is exposed to high temperatures, causing moisture in the mold resin to vaporize, and the resulting water vapor to cause cracks in the mold resin.
また、モ−ルド樹脂と半導体素子の熱ｍ張係数が異なる
ため、表面実装のはんだ付けにおける高温時に、モール
ド樹脂と半導体素子間に応力が生じ、両者の間から界面
剥離、そしてクラックか生じる欠点もある。In addition, since the thermal tensile coefficients of the mold resin and the semiconductor element are different, stress is generated between the mold resin and the semiconductor element at high temperatures during surface mount soldering, resulting in interfacial delamination and cracks between the two. There is also.
本発明の目的は、モールド樹脂及びモールド樹脂と半導
体素子間にクラックが発生することのない半導体装置を
提供することにある。An object of the present invention is to provide a mold resin and a semiconductor device in which cracks do not occur between the mold resin and a semiconductor element.
本発明は、モールド樹脂により封止される半導体装置に
おいて、前記モールド樹脂内に埋め込まれる突起部を形
成した金属板を前記モールド樹脂の主表面である上面並
びに下面に配置し、前記金属板が前記モールド樹脂に挟
着されている。The present invention provides a semiconductor device sealed with a molding resin, in which a metal plate having a protrusion embedded in the molding resin is arranged on an upper surface and a lower surface which are main surfaces of the molding resin, and It is sandwiched between mold resin.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
第１図において、リード１１に囲まれたアイラ〉・ド１
２の上にろう材等で接着された半導体素子１３があり、
半導体素子１３は、ボンディングワイヤ１５で電気的に
接続される。その後、モールド樹脂１６で封入する際に
、金属板１７がモールド樹脂１６の上面部及び下面部上
に設けられ、モールド樹脂１６に挟着されている。また
、モールド樹脂１６より金属板１７が脱離しないように
ミ金属板１７には、プレスアンカによるアンカ１８が設
けられている。In FIG.
There is a semiconductor element 13 on top of 2, which is bonded with a brazing material or the like.
Semiconductor element 13 is electrically connected with bonding wire 15 . Thereafter, when enclosing with mold resin 16, metal plates 17 are provided on the upper and lower surfaces of mold resin 16 and are sandwiched between mold resin 16. Further, in order to prevent the metal plate 17 from coming off from the mold resin 16, an anchor 18 made of a press anchor is provided on the metal plate 17.
第２図は本発明の製造方法の一例のプレートモールド法
を説明する断面図である。FIG. 2 is a sectional view illustrating a plate molding method as an example of the manufacturing method of the present invention.
この半導体装置の封止方法の一例としては、第２図に示
すように、プレートモールド法を用いるのが容易である
。As an example of a method for sealing this semiconductor device, it is easy to use a plate molding method, as shown in FIG.
まず、モールド樹脂２６上の金属板２７をリードフレー
ム２つに連結しておく。次に、２つの上部金型Ａ、Ｂの
間及び２つの下部金型Ａ、Ｂの間に金属板２７を挿入し
た後、モールド樹脂２６を圧入して、金属板２７を固定
する。その後、金属板２７はリードフレーム２９と同じ
く一個ずつ切り離される。First, the metal plate 27 on the molded resin 26 is connected to two lead frames. Next, after inserting the metal plate 27 between the two upper molds A and B and between the two lower molds A and B, the mold resin 26 is press-fitted to fix the metal plate 27. Thereafter, the metal plate 27 is cut off one by one in the same way as the lead frame 29.
第３図は、本発明の第２の実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the invention.
第２の実施例は、第３図に示すように、金属板３７とモ
ールド樹脂３６の接続部は、金属板３７の両端にアンカ
３８を設けている。In the second embodiment, as shown in FIG. 3, anchors 38 are provided at both ends of the metal plate 37 to connect the metal plate 37 and the molded resin 36.
この実施例では、金属板３７の脱離を防止するアンカ３
８が封止部の端部に位置するため、第１の実施例と比べ
て、リードフレームとのショート不良を起しに＜＜、薄
型パッケージに適している利点がある。In this embodiment, the anchor 3 that prevents the metal plate 37 from coming off is
8 is located at the end of the sealing portion, it has the advantage that it is suitable for thin packages because it is less likely to cause short-circuits with the lead frame than the first embodiment.
以上説明したように本発明は、モールド樹脂の上面及び
下面に金属板を設け、モールド樹脂に挟着することによ
り、下記に・列挙する効果がある。As explained above, the present invention provides the following effects by providing metal plates on the upper and lower surfaces of the mold resin and sandwiching them between the mold resin.
１）モールド樹脂の吸湿量を大幅に低減することができ
る。その結果、はんだ実装時のモールド樹脂のクラック
を防止し、また、保存時の耐湿性の向上も図ることがで
きる。1) The amount of moisture absorbed by the mold resin can be significantly reduced. As a result, it is possible to prevent cracks in the mold resin during solder mounting, and also to improve moisture resistance during storage.
２）はんだ実装の際に用いる赤外線リフローにおいて、
赤外線反射効果がある。赤外線反射に−より、樹脂表面
が約２０〜３０℃温度が低下し、モールド樹脂と半導体
素子間の熱応力が暖和されるので、モールド樹脂と半導
体素子間のクラックを防止できる。2) In infrared reflow used during solder mounting,
Has an infrared reflective effect. Due to infrared reflection, the temperature of the resin surface is lowered by about 20 to 30° C., and the thermal stress between the mold resin and the semiconductor element is moderated, so that cracks between the mold resin and the semiconductor element can be prevented.
３）パッケージの主表面を金属板にすることにより、モ
ールド樹脂封止の際における金型汚れを低減できる。3) By making the main surface of the package a metal plate, it is possible to reduce mold contamination during mold resin sealing.
４）金型からの半導体装置の離型をよくするためにモー
ルド樹脂には離型剤が成分として含まれており、その離
型剤の影響で半導体装置表面への捺印性や捺印強度が低
下するが、表面を金属板することにより、それらの欠点
も解消できる。4) In order to improve the release of the semiconductor device from the mold, the molding resin contains a mold release agent as a component, and the effect of the mold release agent reduces the ability and strength of the imprint on the surface of the semiconductor device. However, by making the surface a metal plate, these drawbacks can be overcome.
５）パッケージ主表面を金属板にすることにより、樹脂
表面の帯電性が低減でき、半導体素子の静電破壊を防止
できる。5) By making the main surface of the package a metal plate, the chargeability of the resin surface can be reduced, and electrostatic damage to semiconductor elements can be prevented.
第１図は本発明の第１の実施例の断面図、第２図は本発
明の製造方法の一例のプレートモールド法を説明する断
面図、第３図は本発明の第２の実施例の断面図、第４図
は従来の樹脂封止型半導体装置の一例の断面図である。
１１．３１．４１・・・リード、１２，３２．４２・・
・アイランド、１３，２３．３３．４３・・・半導体素
子、１４，３４．４４・・・ボンディングバット、１５
．３５．４５・・・ボンディングワイヤ、１６゜２６゜
６゜
６・・・モールド樹脂、
７゜
２７゜
３７・・・金属板、
１８゜
２８゜
３８・・・アンカ、
・・・リードフレーム。
／ターーーホ〕ティじクワイヤFIG. 1 is a cross-sectional view of the first embodiment of the present invention, FIG. 2 is a cross-sectional view illustrating the plate molding method as an example of the manufacturing method of the present invention, and FIG. 4 is a cross-sectional view of an example of a conventional resin-sealed semiconductor device. 11.31.41...Reed, 12,32.42...
・Island, 13, 23. 33. 43... Semiconductor element, 14, 34. 44... Bonding bat, 15
．． 35.45...Bonding wire, 16゜26゜6゜6...Mold resin, 7゜27゜37...Metal plate, 18゜28゜38...Anchor, ...Lead frame. / Ta-ho] Tiji Choir
Claims (1)
記モールド樹脂内に埋め込まれる突起部を形成した金属
板を前記モールド樹脂の主表面である上面並びに下面に
配置し、前記金属板を前記モールド樹脂に挟着したこと
を特徴とする半導体装置。In a semiconductor device sealed with a mold resin, a metal plate having a protrusion embedded in the mold resin is arranged on the upper and lower main surfaces of the mold resin, and the metal plate is sandwiched between the mold resin. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63188702A JPH0237752A (en) | 1988-07-27 | 1988-07-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63188702A JPH0237752A (en) | 1988-07-27 | 1988-07-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0237752A true JPH0237752A (en) | 1990-02-07 |
Family
ID=16228318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63188702A Pending JPH0237752A (en) | 1988-07-27 | 1988-07-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0237752A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528457A (en) * | 1994-12-21 | 1996-06-18 | Gennum Corporation | Method and structure for balancing encapsulation stresses in a hybrid circuit assembly |
| WO1997042655A1 (en) * | 1996-05-06 | 1997-11-13 | Siemens Aktiengesellschaft | Carrier with at least one integrated printed circuit and process for producing the same |
| US6502926B2 (en) | 2001-01-30 | 2003-01-07 | Lexmark International, Inc. | Ink jet semiconductor chip structure |
-
1988
- 1988-07-27 JP JP63188702A patent/JPH0237752A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528457A (en) * | 1994-12-21 | 1996-06-18 | Gennum Corporation | Method and structure for balancing encapsulation stresses in a hybrid circuit assembly |
| WO1997042655A1 (en) * | 1996-05-06 | 1997-11-13 | Siemens Aktiengesellschaft | Carrier with at least one integrated printed circuit and process for producing the same |
| US6502926B2 (en) | 2001-01-30 | 2003-01-07 | Lexmark International, Inc. | Ink jet semiconductor chip structure |
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