JPH05218271A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPH05218271A JPH05218271A JP4015140A JP1514092A JPH05218271A JP H05218271 A JPH05218271 A JP H05218271A JP 4015140 A JP4015140 A JP 4015140A JP 1514092 A JP1514092 A JP 1514092A JP H05218271 A JPH05218271 A JP H05218271A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- chip
- package
- pair
- sealing portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、表面実装型のＩＣパ
ッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type IC package.
【０００２】[0002]
【従来の技術】図３は従来のＩＣパッケージの構成を示
す断面図である。図３において、１は封止材料からなる
封止部、２はチップ、３０はリードフレームに一体形成
されたリード、４は金線からなるワイヤ、５は銀ペース
ト、７はリードフレームに一体形成されたダイパッドで
ある。2. Description of the Related Art FIG. 3 is a sectional view showing the structure of a conventional IC package. In FIG. 3, 1 is a sealing portion made of a sealing material, 2 is a chip, 30 is a lead integrally formed on a lead frame, 4 is a wire made of gold wire, 5 is silver paste, and 7 is integrally formed on a lead frame. It is a die pad.
【０００３】図３に示すように、従来のＩＣパッケージ
は、封止部１内に、ダイパッド７上に銀ペースト５によ
りマウントしたチップ２と、このチップ２の所定箇所の
電極（図示せず）にワイヤ４により電気的に接続したリ
ード３０とをトランスファモールド法により封入したも
のである。このように構成されたＩＣパッケージは、基
板（図示せず）上に実装される。As shown in FIG. 3, in a conventional IC package, a chip 2 mounted on a die pad 7 with a silver paste 5 in an encapsulation portion 1 and electrodes (not shown) at predetermined locations on the chip 2 are provided. And a lead 30 electrically connected to the wire 4 by a transfer molding method. The IC package configured as described above is mounted on a substrate (not shown).
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うに構成された従来のＩＣパッケージは、実装時に半田
付けまたは赤外線リフロー等により加熱されると、封止
部１にクラック（図示せず）が生じるという問題があっ
た。このクラックが生じる原因としては、ダイパッド７
と封止部１との線膨張率の違い，ダイパッド７と封止部
１との密着性低下およびＩＣパッケージの保管中に封止
部１に侵入した水分等が挙げられる。特に、水分による
クラック発生は、ダイパッド７と封止部１との界面に溜
まった水分が、上記の加熱により気化膨張を起こすこと
によるものである。However, in the conventional IC package having such a structure, when it is heated by soldering or infrared reflow during mounting, cracks (not shown) occur in the sealing portion 1. There was a problem. The cause of this crack is the die pad 7
There is a difference in linear expansion coefficient between the sealing portion 1 and the sealing portion 1, a decrease in adhesiveness between the die pad 7 and the sealing portion 1, water entering the sealing portion 1 during storage of the IC package, and the like. In particular, the generation of cracks due to moisture is due to the moisture accumulated at the interface between the die pad 7 and the sealing portion 1 being vaporized and expanded by the above heating.
【０００５】さらに、最近のＩＣパッケージは薄形化傾
向があり、封止部１が薄形化することにより強度が低下
し、クラック発生率が高くなっている。この発明の目的
は、上記問題点に鑑み、実装時のクラック発生率を低減
し薄形化を実現したＩＣパッケージを提供することであ
る。Further, recent IC packages have a tendency to be thin, and the strength of the sealing portion 1 is reduced and the crack occurrence rate is high due to the thinning of the sealing portion 1. In view of the above problems, an object of the present invention is to provide an IC package in which the crack occurrence rate at the time of mounting is reduced and thinning is realized.
【０００６】[0006]
【課題を解決するための手段】この発明のＩＣパッケー
ジは、封止部内に、所定間隔を有して対向配置した一対
のリードの各対向端部と、この一対のリード間に掛け渡
して載置されリードに所定箇所を電気的に接続したチッ
プとを封入したものである。An IC package according to the present invention is mounted in a sealed portion so that a pair of leads facing each other with a predetermined interval are provided between the facing ends and the pair of leads. A chip that is placed and has a lead electrically connected to a predetermined portion is encapsulated.
【０００７】[0007]
【作用】この発明の構成によれば、チップを一対のリー
ド間に掛け渡して載置し封止部内に封入したため、従来
のようなチップを載置するためのダイパッドが不要とな
る。したがって、内部にクラックの原因となる水分が溜
まることがなく、また、膨張率の違いおよび密着性低下
等の不都合も生じることがない。さらに、封止部を薄く
することがなく、ダイパッドの厚みだけ全体を薄形化す
ることができる。According to the structure of the present invention, since the chip is laid over the pair of leads and mounted and enclosed in the sealing portion, the conventional die pad for mounting the chip is unnecessary. Therefore, water that causes cracks does not accumulate inside, and there is no inconvenience such as a difference in expansion coefficient and a decrease in adhesion. Further, the entire thickness can be reduced by the thickness of the die pad without reducing the thickness of the sealing portion.
【０００８】[0008]
【実施例】図１はこの発明の第１の実施例のＩＣパッケ
ージの構成を示す断面図である。図１において、１は封
止材料からなる封止部、２はチップ、３はリード、４は
金線からなるワイヤ、５は銀ペーストである。図１に示
すように、ＩＣパッケージは、封止部１内に、一対のリ
ード３の各対向端部３ａとチップ２とを封入したもので
ある。1 is a sectional view showing the structure of an IC package according to a first embodiment of the present invention. In FIG. 1, 1 is a sealing portion made of a sealing material, 2 is a chip, 3 is a lead, 4 is a wire made of a gold wire, and 5 is a silver paste. As shown in FIG. 1, the IC package is one in which a facing portion 3 a of a pair of leads 3 and a chip 2 are enclosed in a sealing portion 1.
【０００９】一対のリード３は、所定間隔を有して対向
配置したものであり、各対向端部３ａをＬ字形に屈曲さ
せたものである。また、チップ２は、一対のリード３間
に掛け渡して載置したものであり、チップ２および各リ
ード３の対向端部３ａ間は銀ペースト５により固着して
ある。そして、チップ２の上面の電極（図示せず）およ
びリード３間は、ワイヤボンディング法により、ワイヤ
４で電気的に接続してある。The pair of leads 3 are arranged so as to face each other with a predetermined spacing, and each facing end portion 3a is bent in an L shape. Further, the chip 2 is placed so as to be stretched between a pair of leads 3, and the chip 2 and the opposing end portions 3a of the leads 3 are fixed by a silver paste 5. The electrodes (not shown) on the upper surface of the chip 2 and the leads 3 are electrically connected by wires 4 by a wire bonding method.
【００１０】このようにチップ２を一対のリード３間に
掛け渡し載置したことで、従来のようなチップ２を載置
するためのダイパッド７が不要となる。次に、図２はこ
の発明の第２の実施例のＩＣパッケージの構成を示す断
面図である。図２において、６はバンプであり、図１と
同符号の部分は同様の部分を示す。Since the chip 2 is mounted by being placed between the pair of leads 3 as described above, the die pad 7 for mounting the chip 2 unlike the conventional case is unnecessary. Next, FIG. 2 is a sectional view showing the structure of an IC package according to a second embodiment of the present invention. In FIG. 2, 6 is a bump, and the same reference numerals as those in FIG. 1 denote the same parts.
【００１１】図２に示すように、ＩＣパッケージは、封
止部１内に、一対のリード３の各対向端部３ａとチップ
２とを封入したものである。一対のリード３は、所定間
隔を有して対向配置したものであり、各対向端部３ａを
Ｌ字形に屈曲させたものである。また、チップ２は、一
対のリード３間に掛け渡して載置したものであり、チッ
プ２の下面の電極（図示せず）および各リード３の対向
端部３ａ間はバンプ６を介して電気的に接続してある。As shown in FIG. 2, the IC package is one in which the opposing end portions 3a of the pair of leads 3 and the chip 2 are enclosed in the sealing portion 1. The pair of leads 3 are arranged so as to face each other with a predetermined gap, and each facing end portion 3a is bent in an L shape. Further, the chip 2 is mounted by being laid over a pair of leads 3, and an electrode (not shown) on the lower surface of the chip 2 and an opposing end portion 3 a of each lead 3 are electrically connected via a bump 6. Connected to each other.
【００１２】このようにチップ２を一対のリード３間に
掛け渡して載置したことで、従来のようなチップ２を載
置するためのダイパッド７が不要となる。以上、第１お
よび第２の実施例によれば、チップ２を一対のリード３
間に掛け渡して載置し封止部１内に封入したため、従来
のようなチップ２を載置するためのダイパッド７が不要
となる。したがって、内部にクラック発生の原因となる
水分が溜まることがなく、また、膨張率の違いおよび密
着性低下等の不都合も生じることがない。これにより、
実装時のクラック発生率を低減することができる。そし
て、さらに、従来と比較してダイパッド７の厚みだけ全
体を薄形化することができ、この薄形化は、封止部１を
薄くすることが不要であるため、強度低下を生じること
がない。By mounting the chip 2 so as to extend between the pair of leads 3 as described above, the die pad 7 for mounting the chip 2 unlike the conventional case is unnecessary. As described above, according to the first and second embodiments, the chip 2 is connected to the pair of leads 3.
Since it is laid across the space and mounted in the sealing portion 1, the die pad 7 for mounting the chip 2 unlike the conventional case is not required. Therefore, moisture that causes cracks does not accumulate inside, and there is no inconvenience such as a difference in expansion coefficient and a decrease in adhesion. This allows
It is possible to reduce the crack occurrence rate during mounting. Further, it is possible to reduce the thickness of the die pad 7 as a whole as compared with the conventional one, and this reduction in thickness may cause a decrease in strength because it is not necessary to reduce the thickness of the sealing portion 1. Absent.
【００１３】なお、第２の実施例では、各リード３の対
向端部３ａをＬ字形に折り曲げたが、必ずしも曲げる必
要はない。In the second embodiment, the opposing end portions 3a of the leads 3 are bent in an L shape, but it is not always necessary to bend them.
【００１４】[0014]
【発明の効果】この発明のＩＣパッケージによれば、チ
ップを一対のリード間に掛け渡して載置し封止部内に封
入したため、従来のようなチップを載置するためのダイ
パッドが不要となる。したがって、内部にクラックの原
因となる水分が溜まることがなく、また、膨張率の違い
および密着性低下等の不都合も生じることがない。さら
に、封止部を薄くすることがなく、ダイパッドの厚みだ
け全体を薄形化することができる。According to the IC package of the present invention, the chip is laid between the pair of leads so as to be mounted and enclosed in the sealing portion, so that the conventional die pad for mounting the chip is unnecessary. .. Therefore, water that causes cracks does not accumulate inside, and there is no inconvenience such as a difference in expansion coefficient and a decrease in adhesion. Further, the entire thickness can be reduced by the thickness of the die pad without reducing the thickness of the sealing portion.
【００１５】その結果、実装時のクラック発生率を低減
することができ、従来と比較して薄形化を実現したＩＣ
パッケージを得ることができる。As a result, it is possible to reduce the crack occurrence rate at the time of mounting, and to realize an IC thinner than the conventional one.
You can get the package.
【図１】この発明の第１の実施例のＩＣパッケージの構
成を示す断面図である。FIG. 1 is a sectional view showing a configuration of an IC package of a first embodiment of the present invention.
【図２】この発明の第２の実施例のＩＣパッケージの構
成を示す断面図である。FIG. 2 is a sectional view showing the structure of an IC package according to a second embodiment of the present invention.
【図３】従来のＩＣパッケージの構成を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a configuration of a conventional IC package.
１ 封止部 ２ チップ ３ リード 3a 対向端部 1 Sealing part 2 Chip 3 Lead 3a Opposite end
Claims (1)
した一対のリードの各対向端部と、この一対のリード間
に掛け渡して載置され前記リードに所定箇所を電気的に
接続したチップとを封入したＩＣパッケージ。1. A pair of leads, which are opposed to each other at a predetermined interval and are opposed to each other, are placed in the sealing portion, and are placed so as to extend between the pair of leads to electrically connect a predetermined portion to the leads. An IC package that encloses the connected chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4015140A JPH05218271A (en) | 1992-01-30 | 1992-01-30 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4015140A JPH05218271A (en) | 1992-01-30 | 1992-01-30 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218271A true JPH05218271A (en) | 1993-08-27 |
Family
ID=11880513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4015140A Pending JPH05218271A (en) | 1992-01-30 | 1992-01-30 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218271A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19507573A1 (en) * | 1994-03-30 | 1995-10-05 | Gold Star Electronics | Conductor structure for semiconductor housing |
| KR20000051982A (en) * | 1999-01-28 | 2000-08-16 | 유-행 치아오 | Lead frame structure having multi-segment die pad |
-
1992
- 1992-01-30 JP JP4015140A patent/JPH05218271A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19507573A1 (en) * | 1994-03-30 | 1995-10-05 | Gold Star Electronics | Conductor structure for semiconductor housing |
| DE19507573C2 (en) * | 1994-03-30 | 2002-11-21 | Gold Star Electronics | Conductor structure for a semiconductor package and semiconductor package with such a conductor structure |
| KR20000051982A (en) * | 1999-01-28 | 2000-08-16 | 유-행 치아오 | Lead frame structure having multi-segment die pad |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7008824B2 (en) | Method of fabricating mounted multiple semiconductor dies in a package | |
| US6297547B1 (en) | Mounting multiple semiconductor dies in a package | |
| JP3012816B2 (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| JP2528991B2 (en) | Resin-sealed semiconductor device and lead frame | |
| JPH06204371A (en) | Synthetic resin sealed electronic part and bending method of lead terminal thereof | |
| JP2905609B2 (en) | Resin-sealed semiconductor device | |
| JPH04158556A (en) | Reasin-sealed type semiconductor device | |
| JPH05218271A (en) | Ic package | |
| JPH02125454A (en) | Resin-sealed semiconductor device | |
| JP3153197B2 (en) | Semiconductor device | |
| JP2694871B2 (en) | Semiconductor device | |
| JP2589520B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JP3847432B2 (en) | Resin-encapsulated semiconductor device and manufacturing method thereof | |
| JP3134445B2 (en) | Resin-sealed semiconductor device | |
| KR100373891B1 (en) | Semiconductor device and method of its fabrication | |
| JPH06241889A (en) | Semiconductor device | |
| JP2003318346A (en) | Resin sealed semiconductor device and manufacturing method thereof | |
| JP3179374B2 (en) | Lead frame for semiconductor device and semiconductor device | |
| JPH0493052A (en) | Semiconductor integrated circuit device | |
| JPH01238129A (en) | Resin seal type semiconductor device | |
| JPS63152160A (en) | Laed frame for semiconductor device | |
| JPH11162998A (en) | Semiconductor device and its manufacture | |
| JPS61128551A (en) | Lead frame for semiconductor device | |
| JP2003243599A (en) | Lead frame and semiconductor device | |
| JP2715965B2 (en) | Resin-sealed semiconductor device |