JP3153197B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3153197B2
JP3153197B2 JP36787498A JP36787498A JP3153197B2 JP 3153197 B2 JP3153197 B2 JP 3153197B2 JP 36787498 A JP36787498 A JP 36787498A JP 36787498 A JP36787498 A JP 36787498A JP 3153197 B2 JP3153197 B2 JP 3153197B2
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
external terminal
semiconductor chip
terminal portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP36787498A
Other languages
Japanese (ja)
Other versions
JP2000196005A (en
Inventor
博之 小路
昌男 千田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP36787498A priority Critical patent/JP3153197B2/en
Publication of JP2000196005A publication Critical patent/JP2000196005A/en
Application granted granted Critical
Publication of JP3153197B2 publication Critical patent/JP3153197B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、樹脂封止型半導体
装置に関し、特に薄型の半導体装置を実現するSON
(Small Outline Non‐lead P
ackage)構造のように、リードの外部端子部の一
部が下面が露出しながら封止樹脂に埋め込まれ且つ外部
端子部の下面と封止樹脂底面とがほぼ平坦になっている
構造の樹脂封止型半導体装置のリードの構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to an SON for realizing a thin semiconductor device.
(Small Outline Non-lead P
As in the case of the package structure, a portion of the external terminal portion of the lead is embedded in the sealing resin while the lower surface is exposed, and the lower surface of the external terminal portion and the sealing resin bottom surface are substantially flat. The present invention relates to a structure of a lead of a fixed semiconductor device.

【0002】[0002]

【従来の技術】近年、半導体装置の小型化、薄型化に対
する要求はますます強まっている。この要求への一つの
対応策として、SON(Small Outline
Non‐lead Package)構造のように、封
止樹脂底面からリードを露出させた構造の樹脂封止型半
導体装置が提案されている。
2. Description of the Related Art In recent years, there has been an increasing demand for smaller and thinner semiconductor devices. One solution to this requirement is SON (Small Outline).
A resin-sealed semiconductor device having a structure in which leads are exposed from the bottom surface of a sealing resin like a non-lead package structure has been proposed.

【0003】図8は、この種の樹脂封止型半導体装置の
第1の従来例を模式的に示す図であり、図8(a)は、
図1のA−A’部断面に相当する第1の従来例の断面
図、図8(b)は、第1の従来例の樹脂封止半導体装置
100を裏面から見た平面図である。
FIG. 8 is a diagram schematically showing a first conventional example of this type of resin-sealed semiconductor device, and FIG.
FIG. 8B is a cross-sectional view of the first conventional example corresponding to a cross section taken along the line AA ′ of FIG. 1, and FIG. 8B is a plan view of the resin-sealed semiconductor device 100 of the first conventional example viewed from the back.

【0004】図8を参照すると、樹脂封止型半導体装置
100のデプレス曲げ加工されたリード110は、半導
体チップ140と例えばボンディング線150で電気的
に接続される内部端子部111,連結部112及び外部
端子部113を含んでなり、内部端子部111と連結部
112との接続部及び連結部112と外部端子部113
との接続部でそれぞれ曲げ加工が施されている。また半
導体チップ140はアイランド130に図示されていな
い導電性接着剤等を介して搭載・固着され、内部端子部
111,連結部112,外部端子部113の一部,アイ
ランド130及び半導体チップ140が封止樹脂120
で封止されている。更に、外部端子部113の下面は封
止樹脂120の底面とほぼ平坦になっており且つ封止樹
脂120で被覆されず、露出している。
[0004] Referring to FIG. 8, a depressed lead 110 of a resin-encapsulated semiconductor device 100 has an internal terminal portion 111, a connection portion 112 and an internal terminal 111 electrically connected to a semiconductor chip 140 by, for example, a bonding wire 150. It includes an external terminal portion 113, a connection portion between the internal terminal portion 111 and the connection portion 112, and a connection portion 112 and the external terminal portion 113.
Each of the connecting portions is bent. The semiconductor chip 140 is mounted and fixed to the island 130 via a conductive adhesive or the like (not shown), and the internal terminal portion 111, the connecting portion 112, a part of the external terminal portion 113, the island 130, and the semiconductor chip 140 are sealed. Stop resin 120
It is sealed with. Further, the lower surface of the external terminal portion 113 is substantially flat with the bottom surface of the sealing resin 120 and is not covered with the sealing resin 120 but is exposed.

【0005】また、第2の従来例として、特開平2−2
40940号公報には、この種の樹脂封止型半導体装置
が、そのの製造方法と共に開示されている。
As a second conventional example, Japanese Patent Laid-Open No.
Japanese Patent No. 40940 discloses a resin-sealed semiconductor device of this type together with a method of manufacturing the same.

【0006】図9は、特開平2−240940号公報に
開示されている製造方法を示す断面図である。図9を参
照すると、第2の従来例の半導体装置200では、平板
状の支持部271の一方の面に凸状の電極210,23
0が設けられたリードフレーム270を用い、この電極
230上に接着剤231を塗布して集積回路素子240
を搭載し、電極210と集積回路素子240とを接続体
250によって接続し、少なくとも集積回路素子240
と接続体250とを封止樹脂220で覆った後に、支持
部271の他方の面を電極210が露出するまで除去す
る(例えば、砥石290を備えた平面研削盤による研削
による)ことにより、外部接続用端子が形成されてい
る。
FIG. 9 is a sectional view showing a manufacturing method disclosed in Japanese Patent Application Laid-Open No. 2-240940. Referring to FIG. 9, in a semiconductor device 200 of the second conventional example, convex electrodes 210 and 23 are provided on one surface of a flat supporting portion 271.
The adhesive 230 is applied on the electrode 230 using the lead frame 270 provided with the
Are mounted, and the electrode 210 and the integrated circuit element 240 are connected to each other by a connector 250, and at least the integrated circuit element 240
After covering the connection member 250 with the sealing resin 220, the other surface of the support portion 271 is removed until the electrode 210 is exposed (for example, by grinding with a surface grinder provided with a grindstone 290), so that the outside is removed. A connection terminal is formed.

【0007】[0007]

【発明が解決しようとする課題】まず、第1の従来例に
おいては、図8(a)に示すようにリードのデプレス加
工の際、連結部112と外部端子部113との接続部で
の曲げ加工ではエッジ(角部)が得られず、R部(丸
み)がついてしまう。このため、樹脂封止の際に、図8
(b)に示すようにリードと封止樹脂の境界部(図8
(b)のQ部)に薄い樹脂バリが不規則に発生し、外部
端子部の露出面の形状が安定しないという欠点が有り、
この樹脂バリを低減することが求められていた。
First, in the first conventional example, as shown in FIG. 8 (a), when the lead is depressed, the bending at the connecting portion between the connecting portion 112 and the external terminal portion 113 is performed. In processing, an edge (corner) cannot be obtained, and an R portion (roundness) is formed. For this reason, FIG.
As shown in FIG. 8B, the boundary between the lead and the sealing resin (FIG. 8)
There is a drawback that thin resin burrs are irregularly generated in the (Q part) of (b) and the shape of the exposed surface of the external terminal part is not stable.
It has been required to reduce this resin burr.

【0008】また、第2の従来例のような製造方法を用
いると、電極210(リード)と封止樹脂220の境界
部での薄い樹脂バリの不規則な発生は抑制されるが、通
常の組立工程の他に裏面研磨加工という追加工程が必要
であり、組立加工費が上がってしまうという問題があっ
た。
Further, when the manufacturing method as in the second conventional example is used, irregular occurrence of thin resin burrs at the boundary between the electrode 210 (lead) and the sealing resin 220 is suppressed, In addition to the assembling step, an additional step of backside polishing is required, and there is a problem that the assembling processing cost increases.

【0009】本発明は、SON構造のように、封止樹脂
底面からリードを露出させた構造の樹脂封止型半導体装
置において、リードの外部端子部と封止樹脂との境界部
での外部端子部上への薄い樹脂バリの発生を抑制して外
部端子部露出面の形状を安定化させた封止型半導体装置
を、樹脂封止後の裏面研磨加工のような工程追加をする
ことなく、安価に提供することを目的とするものであ
る。
According to the present invention, there is provided a resin-encapsulated semiconductor device having a structure in which a lead is exposed from the bottom surface of a sealing resin, such as an SON structure, in an external terminal at a boundary between an external terminal portion of the lead and the sealing resin. A sealed semiconductor device in which the shape of the external terminal portion exposed surface is stabilized by suppressing the occurrence of thin resin burrs on the portion, without adding a process such as back surface polishing after resin sealing, The purpose is to provide it at low cost.

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置は、
半導体チップと、この半導体チップと電気的に接続され
ているリードと、前記半導体チップ及び少なくとも前記
リードの一部を封止する封止樹脂とを含む半導体装置に
おいて、前記リードは少なくとも、前記半導体チップと
電気的に接続される内部端子部と、前記半導体装置を回
路基板に実装する際にこの回路基板上の導体に接続され
る外部端子部と、前記内部端子部と前記外部端子部とを
連結する連結部とを含んでなり、この連結部の前記外部
端子部と接続している第1の端部の前記外部端子部の下
面に連続する面に前記連結部を幅方向に横断する凹部を
有するとともに少なくとも前記連結部の第1の端部でデ
プレス曲げ加工されており、少なくとも前記半導体チッ
プと前記リードの前記内部端子部と前記凹部を含む前記
連結部と前記外部端子部の一部が前記封止樹脂に封止さ
れ且つ前記外部端子部の下面は前記封止樹脂の底面に露
出しており、更に前記半導体チップと前記リードの前記
内部端子部とがバンプを介して接続されている。この半
導体チップをデプレス曲げ加工された前記リードの内部
端子部の上面側に接続したときは、前記半導体チップ裏
面に高熱伝導率材料で形成された放熱板を備えることが
できる。
According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device including a semiconductor chip, a lead electrically connected to the semiconductor chip, and a sealing resin for sealing the semiconductor chip and at least a part of the lead, the lead is at least the semiconductor chip An internal terminal portion electrically connected to the semiconductor device, an external terminal portion connected to a conductor on the circuit board when the semiconductor device is mounted on the circuit board, and connecting the internal terminal portion and the external terminal portion. And a concave portion that crosses the connecting portion in the width direction on a surface of the first end portion of the connecting portion that is connected to the external terminal portion and that is continuous with a lower surface of the external terminal portion. The connecting portion including at least the semiconductor chip, the internal terminal portion of the lead, and the recess, and the external portion, wherein the connecting portion includes at least a first end of the connecting portion and a depressed bending process. The lower surface of the portion of the terminal portion is the sealed in the sealing resin and the external terminal portions are exposed on the bottom surface of the sealing resin, further wherein said semiconductor chip and the leads
The internal terminals are connected via bumps. This half
Inside of the lead where the conductor chip is depressed and bent
When connected to the top side of the terminal,
Heat sink made of high thermal conductivity material
Can Ru.

【0011】また、本発明の他の半導体装置は、半導体
チップと、この半導体チップと電気的に接続されている
リードと、半導体チップ及び少なくともリードの一部を
封止する封止樹脂とを含み、リードは少なくとも、半導
体チップと電気的に接続される内部端子部と、半導体装
置を回路基板に実装する際にこの回路基板上の導体に接
続される外部端子部と、内部端子部と外部端子部とを連
結する連結部とを含んでなり、この連結部の厚さが外部
端子部の厚さの1/3〜3/4で且つ連結部の外部端子
部と接続している第1の端部でデプレス曲げ加工されて
おり、少なくとも半導体チップとリードの内部端子部と
連結部と外部端子部の一部が封止樹脂に封止され且つ外
部端子部の下面は封止樹脂の底面に露出している。
[0011] In addition, other semiconductor device of the present invention relates to a semiconductor
The chip is electrically connected to the semiconductor chip
Lead, semiconductor chip and at least a part of lead
And a sealing resin for sealing.
An internal terminal electrically connected to the semiconductor chip;
When mounting the device on a circuit board,
Connected external terminal, internal terminal and external terminal
And a connecting portion for connecting the connecting portion, wherein the thickness of the connecting portion is
1/3 to 3/4 of the thickness of the terminal part and the external terminal of the connecting part
Depressed at the first end connected to the semiconductor chip and at least the internal terminal of the semiconductor chip and the lead.
A part of the connecting portion and the external terminal portion is sealed with the sealing resin and
The lower surfaces of the terminal portions are exposed on the bottom surface of the sealing resin.

【0012】又、本発明の半導体装置のリード凹部は、
化学的なエッチング或いはコイニング処理により形成す
ることができる。
The lead recess of the semiconductor device of the present invention is
It can be formed by chemical etching or coining.

【0013】この時、凹部の深さは、リード強度を保持
しながら良好なデプレス曲げ加工形状を得るために、リ
ード厚さの1/4〜2/3程度であることが好ましい。
At this time, the depth of the recess is preferably about 1/4 to 2/3 of the lead thickness in order to obtain a good depressed bending shape while maintaining the lead strength.

【0014】更に、本発明の半導体装置は、この半導体
装置を回路基板に実装する際に回路基板上の導体と当接
する外部端子部の面が、封止樹脂の底面と平坦になるよ
うに、或いは連結部に形成されている凹部の深さを超え
ない範囲で封止樹脂の底面から突出させることができ
る。
Further, in the semiconductor device of the present invention, when the semiconductor device is mounted on a circuit board, the surface of the external terminal portion that contacts the conductor on the circuit board is flat with the bottom surface of the sealing resin. Alternatively, it can protrude from the bottom surface of the sealing resin within a range not exceeding the depth of the concave portion formed in the connecting portion.

【0015】[0015]

【発明の実施の形態】次に、本発明について図面を参照
して説明する。
Next, the present invention will be described with reference to the drawings.

【0016】尚、以下の説明では、半導体装置の4辺に
リードを具備している例を用いるが、向かい合う2辺の
みに具備した場合でも同様に適用できることはいうまで
もない。
In the following description, an example in which leads are provided on four sides of a semiconductor device will be used. However, it is needless to say that the same can be applied to a case in which leads are provided on only two opposite sides.

【0017】図1は、本発明の半導体装置及び本発明の
関連技術のものの模的な外観斜視図であり、図3は図
1の半導体装置を底面側から(図中B方向から)みた平
面図である。図2(a),(b)は、それぞれ本発明の
関連技術のものの図1におけるA−A’部の断面図とリ
ード10の要部を示すための拡大断面図である。
FIG. 1 shows a semiconductor device of the present invention and a semiconductor device of the present invention.
Related a schematic appearance perspective view of one technique, Figure 3 (from figure B direction) of the semiconductor device of FIG. 1 from the bottom side is a plan view. 2 (a) and 2 (b) respectively show the present invention.
FIG. 1 is a cross-sectional view and a cross-sectional view taken along line AA ′ of FIG.
FIG. 2 is an enlarged cross-sectional view illustrating a main part of a mode.

【0018】図1〜3を参照すると、本発明の関連技術
の半導体装置は、内端子部11,連結部12,外部端子
部13からなりデプレス曲げ加工されたリード10と、
アイランド30に搭載された半導体チップ40と、半導
体チップ40とリード10を電気的に接続するボンディ
ング線50とを備え、リード10の内部端子部11,連
結部12及び外部端子部13の一部,アイランド30,
半導体チップ40並びにボンディング線50が封止樹脂
20で封止されている。リード10のデプレス曲げ加工
は、第1の端部15及び第2の端部16でそれぞれ曲げ
加工が施されている。また、第1の端部15には、この
第1の端部15での曲げ方向と反対側の面(外部端子部
の下面13b側の面)に凹部14が連結部12の幅方向
全体に渡って形成されており、この凹部14も封止樹脂
20で封止されている。
Referring to FIGS. 1 to 3, a semiconductor device according to the related art of the present invention includes a depressed bent lead 10 including an inner terminal portion 11, a connecting portion 12, and an outer terminal portion 13,
The semiconductor device includes a semiconductor chip mounted on the island, a bonding wire for electrically connecting the semiconductor chip to the lead, and a part of the internal terminal portion, the connection portion and the external terminal portion of the lead, Island 30,
The semiconductor chip 40 and the bonding wires 50 are sealed with the sealing resin 20. Depress bending of the lead 10 is performed at the first end 15 and the second end 16 respectively. In the first end 15, a concave portion 14 is formed on a surface opposite to the bending direction at the first end 15 (a surface on the lower surface 13 b side of the external terminal portion) over the entire width of the connecting portion 12. The recess 14 is also sealed with the sealing resin 20.

【0019】外部端子部13の上面13a及び両側面の
一部は封止樹脂20で封止されているが、下面13bは
封止樹脂20の底面とほぼ平坦になっておりかつ封止樹
脂20で被覆されないで露出して外部電極となってい
る。
The upper surface 13a and a part of both side surfaces of the external terminal portion 13 are sealed with the sealing resin 20, while the lower surface 13b is substantially flat with the bottom surface of the sealing resin 20 and It is not covered with but exposed and serves as an external electrode.

【0020】次に、本発明の半導体装置のリードを実現
するためのリードフレームについて簡単に説明する。
Next , a lead frame for realizing the lead of the semiconductor device of the present invention will be briefly described.

【0021】図4は本発明の半導体装置の製造に用いら
れるリードフレーム70の模式的な平面図、図5は図4
のリードを中心とした部分を拡大した図であり、図5
(a)はリードを中心とした部分の拡大平面図、図5
(b)は図5(a)のX−X’部の断面図であり、図5
(c)は図5(b)を上方から見た模式的な平面図であ
る。
FIG. 4 is a schematic plan view of a lead frame 70 used for manufacturing the semiconductor device of the present invention, and FIG.
FIG. 5 is an enlarged view of a portion centered on the lead of FIG.
FIG. 5A is an enlarged plan view of a portion centered on a lead, and FIG.
FIG. 5B is a cross-sectional view taken along the line XX ′ of FIG.
FIG. 5C is a schematic plan view of FIG. 5B viewed from above.

【0022】図4,5に示されるリードフレームの製造
法の一例は次の如くである。
An example of a method for manufacturing the lead frame shown in FIGS. 4 and 5 is as follows.

【0023】まず、公知のプレス技術或いはエッチング
技術を用いてリード10、アイランド30等の形成した
後、各リード10の外部端子部13の部分と連結部12
の部分との境界部の連結部側(第1の端部15)に所定
の開口幅hの凹部14をあらかじめ形成する。この時ア
イランド30を支持している吊りリード31について
も、凹部32を形成しても良い。その後、所定のエリア
にメッキ等の表面処理を施した後、公知の曲げ加工技術
を用いてリード10のデプレス曲げ加工を行う。必要に
応じてアイランドの吊りリード31にもデプレス曲げ加
工を施す。
First, after forming the leads 10, the islands 30, etc. by using a known press technique or etching technique, the external terminal portions 13 of the respective leads 10 and the connecting portions 12 are formed.
A concave portion 14 having a predetermined opening width h is formed in advance on the connecting portion side (first end portion 15) of the boundary portion with the portion. At this time, the recess 32 may be formed also in the suspension lead 31 supporting the island 30. Then, after subjecting a predetermined area to surface treatment such as plating, the lead 10 is subjected to depress bending using a known bending technique. If necessary, the island suspension leads 31 are also depressed and bent.

【0024】以上により、本発明の半導体装置の製造に
用いられるリードフレーム70が完成する。
As described above, the lead frame 70 used for manufacturing the semiconductor device of the present invention is completed.

【0025】尚、凹部14を形成する面は、第1の端部
15でのデプレス曲げ加工方向と反対側の面、言い換え
ると外部端子部の下面13bに連続する面である。
The surface on which the recess 14 is formed is a surface opposite to the depressing bending direction at the first end 15, in other words, a surface that is continuous with the lower surface 13 b of the external terminal portion.

【0026】また、凹部14の形成手段としては、化学
的なエッチングの他に、コイニング技術による方法も可
能である。凹部14の深さd(図5(b)参照)は、曲
げ加工時の立ち上がりの急峻さとリード強度とを考慮す
ると、連結部12のリード厚さDの1/4〜2/3が好
ましい。また、凹部14の開口幅hは、0.2mm程度以
上有れば十分であり、連結部12全体の厚さを薄くし
て、凹部14とすることもできる。
As the means for forming the concave portion 14, a method based on coining technology is possible in addition to chemical etching. The depth d of the concave portion 14 (see FIG. 5B) is preferably 1 / to の of the lead thickness D of the connecting portion 12 in consideration of the steepness of the rising at the time of bending and the lead strength. Further, the opening width h of the concave portion 14 is sufficient if it is about 0.2 mm or more, and the concave portion 14 can be formed by reducing the thickness of the entire connecting portion 12.

【0027】本発明の関連技術の半導体装置1の製造
は、本発明の半導体装置のリードを実現するためのリー
ドフレームと同じリードフレーム70を用いて次のよう
に行われる。
The manufacturing of the semiconductor device 1 according to the related art of the present invention is performed by a lead for realizing the lead of the semiconductor device of the present invention.
This is performed as follows using the same lead frame 70 as the lead frame.

【0028】まず、半導体チップ40を、リードフレー
ム70のアイランド30に不図示の導電性接着剤(例え
ば銀ペースト)等を介して搭載・固着(ダイボンド)し
た後、この半導体チップ40と内部端子部11とを金線
等の金属細線によるボンディング線50にてワイヤーボ
ンディングし、封止樹脂20にてトランスファーモール
ド封止することによって、本発明の関連技術の半導体装
置1が製造できる。
First, the semiconductor chip 40 is mounted and fixed (die-bonded) to the island 30 of the lead frame 70 via a conductive adhesive (for example, silver paste) or the like (not shown). 11 is wire-bonded with a bonding wire 50 of a thin metal wire such as a gold wire, and is transfer-molded with a sealing resin 20, whereby the semiconductor device 1 according to the related art of the present invention can be manufactured.

【0029】尚、この半導体装置1の製造においては、
ダイボンド,ワイヤーボンディング,トランスファーモ
ールド封止等いずれの工程においても使用する製造装置
は従来から使用されているもので対応可能であり、特別
な新規製造装置の準備或いは既存製造装置の改造等は不
要である。
In the manufacture of the semiconductor device 1,
The manufacturing equipment used in any of the processes such as die bonding, wire bonding, and transfer mold encapsulation can be used because it has been used in the past, and there is no need to prepare special new manufacturing equipment or modify existing manufacturing equipment. is there.

【0030】次に、本発明の半導体装置の第1,第2の
実施形態について説明する。これらの実施形態におい
て、使用されるリードフレームに対する凹部の加工は、
既述のリードフレーム製造方法により施されたものが用
いられるのでその説明は省略する。
Next, first and second embodiments of the semiconductor device of the present invention will be described. In these embodiments, the processing of the recess for the lead frame used is:
Since what has been performed by the above-described lead frame manufacturing method is used, the description thereof is omitted.

【0031】図6(a),(b)は、それぞれ、第
の実施形態の半導体装置の図1におけるA−A’部
の断面を模式的に示す断面図である。これら第2,第1
の実施形態においては、いずれも内部端子部11と半導
体チップ40とがバンプ60を介して接続されている。
FIGS. 6 (a) and 6 (b) show the first and the second, respectively.
FIG. 4 is a cross-sectional view schematically illustrating a cross section taken along line AA ′ in FIG. 1 of the semiconductor device according to a second embodiment. These second and first
In each of the embodiments, the internal terminal portion 11 and the semiconductor chip 40 are connected via the bump 60.

【0032】図6(a)を参照すると、第の実施形態
の半導体装置1では、半導体チップ40はフェイスダウ
ンで樹脂封止されており、その裏面には金属等の高熱伝
導率材料で形成された放熱板80が不図示の熱伝導性接
着剤(銀ペースト等)により固着され、且つこの放熱板
80の半導体チップ40搭載面と反対側の面は、封止樹
脂20から露出しながら且つ封止樹脂20とほぼ平坦に
なっている。従って、本実施形態の半導体装置は熱放散
に優れており、消費電力が大きく発熱量の多い半導体チ
ップにより効果的である。
Referring to FIG. 6A, in the semiconductor device 1 of the first embodiment, the semiconductor chip 40 is resin-sealed face down, and the back surface thereof is formed of a high thermal conductivity material such as metal. The radiating plate 80 is fixed with a heat conductive adhesive (not shown) (not shown), and the surface of the radiating plate 80 opposite to the surface on which the semiconductor chip 40 is mounted is exposed from the sealing resin 20. It is almost flat with the sealing resin 20. Therefore, the semiconductor device of this embodiment is excellent in heat dissipation, and is more effective for a semiconductor chip which consumes a large amount of power and generates a large amount of heat.

【0033】また、図6(b)を参照すると、第の実
施形態の半導体装置1では、デプレス曲げ加工された内
部端子部11の下面側に半導体チップ40がバンプ60
を介して接続されており、半導体装置1をよりいっそう
薄型にする場合に適用してより効果的である。
Referring to FIG. 6B, in the semiconductor device 1 of the second embodiment, the semiconductor chip 40 has bumps 60 on the lower surface side of the depressed and bent internal terminal portions 11.
And is more effective when applied to make the semiconductor device 1 thinner.

【0034】次に、本発明の半導体装置の第の実施形
態について説明する。
Next, a third embodiment of the semiconductor device of the present invention will be described.

【0035】図7は、第の実施形態の半導体装置の図
1におけるA−A’部の断面を模式的に示す断面図であ
る。
FIG. 7 is a cross-sectional view schematically showing a cross section taken along the line AA ′ in FIG. 1 of the semiconductor device of the third embodiment.

【0036】図7を参照すると、第の実施形態の半導
体装置1では、この半導体装置1が回路基板に実装され
る際に、当該回路基板上の導体と当接する外部端子部3
の下面3bが、封止樹脂20の底面よりtだけ(但し、
0<t<凹部14の深さd)突出している。このように
することで、半導体装置1を回路基板に実装する際に、
回路基板上に多少の凹凸が存在しても、安定して実装す
ることが可能となる。
Referring to FIG. 7, in the semiconductor device 1 of the third embodiment, when the semiconductor device 1 is mounted on a circuit board, the external terminal portions 3 contacting the conductors on the circuit board.
Is lower than the bottom surface of the sealing resin 20 by t (however,
0 <t <depth d of recess 14) Projecting. By doing so, when mounting the semiconductor device 1 on a circuit board,
Even if there are some irregularities on the circuit board, it is possible to mount the circuit stably.

【0037】[0037]

【発明の効果】本発明の半導体装置1は、上述の通り、
リード10のデプレス曲げ加工が施される連結部12の
第1の端部15の曲げ方向に対して反対側の面に凹部1
4が形成されているので、連結部12の立ち上がりが凹
部14のない従来例に比べて極めて急峻になっている。
According to the semiconductor device 1 of the present invention, as described above,
The concave portion 1 is formed on the surface of the connecting portion 12 on which the lead 10 is subjected to the depressing bending process, on the surface opposite to the bending direction of the first end portion 15.
4, the rising of the connecting portion 12 is much steeper than in the conventional example having no concave portion 14.

【0038】これにより、本発明の半導体装置1は、外
部端子部13の端部と封止樹脂20の境界部(図3のP
部)が明瞭になり、封止樹脂20でトランスファーモー
ルド封止する際の外部端子部13での薄バリ発生を大幅
に抑制することができるという大きな効果が得られた。
As a result, the semiconductor device 1 of the present invention has a boundary portion between the end of the external terminal portion 13 and the sealing resin 20 ( P in FIG. 3 ).
Portion) became clear, and a great effect that the generation of thin burrs in the external terminal portion 13 at the time of transfer molding sealing with the sealing resin 20 can be greatly suppressed was obtained.

【0039】更に、この薄バリ発生を抑制できたことに
より、外部端子部の下面13bを安定した形状で確実に
露出させることができ、バリ取り工程を簡易化できて余
分なストレスを加えることもないのでパッケージクラッ
クを回避でき、更に実装性が向上すると云った大きな効
果が得られた。
Further, since the generation of the thin burrs can be suppressed, the lower surface 13b of the external terminal portion can be reliably exposed in a stable shape, the deburring process can be simplified, and extra stress can be applied. As a result, a package crack can be avoided, and a great effect of improving the mountability can be obtained.

【0040】また、リードフレームの製造に際しては、
凹部を形成したことにより応力が緩和され、デプレス曲
げ加工の再現性が向上するという効果も得られた。
When manufacturing the lead frame,
By forming the concave portion, the stress was relieved, and the effect of improving the reproducibility of the depressing bending was also obtained.

【0041】本発明の半導体装置は、リードフレームの
製造時に凹部を設けるという追加加工を施すのみで、従
来からの組立工程で実現可能であり、新規製造装置のた
めの設備投資或いは既存の製造装置の改造等を要するこ
となく実現できることも大きな効果である。
The semiconductor device of the present invention can be realized by a conventional assembling process simply by performing an additional process of providing a concave portion when manufacturing a lead frame, and can be realized by capital investment for a new manufacturing device or an existing manufacturing device. It is also a great effect that the present invention can be realized without requiring modification or the like.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明及び本発明の関連技術の半導体装置を模
式的に示す外観斜視図である。
FIG. 1 is an external perspective view schematically showing a semiconductor device according to the present invention and related technology of the present invention .

【図2】本発明の関連技術の半導体装置の図1における
A−A’部の断面図であり、(a)はA−A’部全体の
断面図、(b)はリード要部を示すための拡大断面図で
ある。
FIGS. 2A and 2B are cross-sectional views taken along the line AA ′ in FIG. 1 of the semiconductor device according to the related art of the present invention; FIG. 2A is a cross-sectional view of the entire line AA ′; FIG.

【図3】図1の半導体装置を底面側(図中B方向から)
見た平面図である。
FIG. 3 shows the semiconductor device of FIG. 1 on the bottom side (from the direction B in the figure)
FIG.

【図4】本発明の半導体装置の製造に用いられるリード
フレームの模式的な平面図である。
FIG. 4 is a schematic plan view of a lead frame used for manufacturing a semiconductor device of the present invention.

【図5】4のリードを中心とした部分を拡大した図で
あり、(a)はリードを中心とした部分の拡大平面図、
(b)は(a)のX−X’部断面図、(c)は(b)を
上方から見た模式的な平面図である。
FIG. 5 is an enlarged view of a portion centered on the lead in FIG . 4, (a) is an enlarged plan view of a portion centered on the lead,
(B) is a sectional view taken along line XX 'of (a), and (c) is a schematic plan view of (b) as viewed from above.

【図6】発明の第,第の実施形態を説明する図
で、(a),(b)はそれぞれ、第,第の実施形態
の半導体装置の図1におけるA−A’部断面を模式的に
示す断面図である。
FIG. 6 is a diagram illustrating first and second embodiments of the present invention.
In, (a), (b), respectively, first, the A-A 'sectional view of FIG. 1 of the semiconductor device of the second embodiment is a cross-sectional view schematically showing.

【図7】本発明の第の実施形態の半導体装置の図1に
おけるA−A’部断面を模式的に示す断面図である。
FIG. 7 is a cross-sectional view schematically showing a cross section taken along line AA ′ of FIG. 1 of a semiconductor device according to a third embodiment of the present invention;

【図8】第1の従来例を模式的に示す図であり、(a)
は相当する第1の従来例の断面図、(b)は第1の従来
例の樹脂封止半導体装置を裏面から見た平面図である。
8A and 8B are diagrams schematically showing a first conventional example, and FIG.
1 is a cross-sectional view of a corresponding first conventional example, and FIG. 2B is a plan view of the resin-sealed semiconductor device of the first conventional example viewed from the back surface.

【図9】第2の従来例の製造方法を示す断面図である。FIG. 9 is a cross-sectional view illustrating a manufacturing method according to a second conventional example.

【符号の説明】[Explanation of symbols]

1,100,200 半導体装置 10,110 リード 11,111 内部端子部 12,112 連結部 13,113 外部端子部 13a 外部端子部の上面 13b 外部端子部の下面 14 凹部 15 第1の端部 16 第2の端部 20,120,220 封止樹脂 30,130 アイランド 31 吊りリード 32 吊りリードの凹部 40,140 半導体チップ 50,150 ボンディング線 60 バンプ 70,270 リードフレーム 80 放熱板 210,230 電極 231 接着剤 240 集積回路素子 250 接続体 271 支持部 290 砥石 1,100,200 Semiconductor device 10,110 Lead 11,111 Internal terminal portion 12,112 Connecting portion 13,113 External terminal portion 13a Upper surface of external terminal portion 13b Lower surface of external terminal portion 14 Recess 15 First end 16 First Ends of 2, 20, 120, 220 Sealing resin 30, 130 Island 31 Suspended lead 32 Suspended lead recess 40, 140 Semiconductor chip 50, 150 Bonding wire 60 Bump 70, 270 Lead frame 80 Heat sink 210, 230 Electrode 231 Adhesion Agent 240 integrated circuit element 250 connector 271 support 290 grindstone

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平11−330343(JP,A) 特開2000−49270(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 23/50 H01L 21/56 H01L 23/28 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-11-330343 (JP, A) JP-A-2000-49270 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/50 H01L 21/56 H01L 23/28

Claims (11)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体チップと、この半導体チップと電
気的に接続されているリードと、前記半導体チップ及び
少なくとも前記リードの一部を封止する封止樹脂とを含
む半導体装置において、前記リードは少なくとも、前記
半導体チップと電気的に接続される内部端子部と、前記
半導体装置を回路基板に実装する際にこの回路基板上の
導体に接続される外部端子部と、前記内部端子部と前記
外部端子部とを連結する連結部とを含んでなり、この連
結部の前記外部端子部と接続している第1の端部の前記
外部端子部の下面に連続する面に前記連結部を幅方向に
横断する凹部を有するとともに少なくとも前記連結部の
第1の端部でデプレス曲げ加工されており、少なくとも
前記半導体チップと前記リードの前記内部端子部と前記
凹部を含む前記連結部と前記外部端子部の一部が前記封
止樹脂に封止され且つ前記外部端子部の下面は前記封止
樹脂の底面に露出しており、更に前記半導体チップと前
記リードの前記内部端子部とがバンプを介して接続され
ていることを特徴とする半導体装置。
2. A semiconductor device comprising: a semiconductor chip; a lead electrically connected to the semiconductor chip; and a sealing resin for sealing the semiconductor chip and at least a part of the lead. At least an internal terminal electrically connected to the semiconductor chip, an external terminal connected to a conductor on the circuit board when the semiconductor device is mounted on the circuit board, and an internal terminal connected to the external terminal. And a connecting portion for connecting the terminal portion to the external terminal portion. The connecting portion is connected to the external terminal portion at a first end connected to a lower surface of the external terminal portion. The connection including at least the semiconductor chip, the internal terminal portion of the lead, and the concave portion, wherein the connection portion includes a concave portion that crosses the semiconductor chip, and is depressed at least at a first end of the connection portion. Department and the lower surface of the portion of the external terminal portion is sealed in the sealing resin and the external terminal portion is exposed at the bottom of the sealing resin and further the semiconductor chip and the front
A semiconductor device , wherein the internal terminals of the leads are connected via bumps .
【請求項2】 半導体チップ裏面に高熱伝導率材料で形
成された放熱板を更に有する請求項1記載の半導体装
置。
2. A high thermal conductivity material is formed on the back surface of the semiconductor chip.
The semiconductor device of claim 1, wherein that having a made the radiating plate further.
【請求項3】 半導体チップと、この半導体チップと電
気的に接続されているリードと、前記半導体チップ及び
少なくとも前記リードの一部を封止する封止樹脂とを含
む半導体装置において、前記リードは少なくとも、前記
半導体チップと電気的に接続される内部端子部と、前記
半導体装置を回路基板に実装する際にこの回路基板上の
導体に接続される外部端子部と、前記内部端子部と前記
外部端子部とを連結する連結部とを含んでなり、この連
結部の前記外部端子部と接続している第1の端部の前記
外部端子部の下面に連続する面に前記連結部を幅方向に
横断する凹部を有するとともに少なくとも前記連結部の
第1の端部でデプレス曲げ加工されており、少なくとも
前記半導体チップと前記リードの前記内部端子部と前記
凹部を含む前記連結部と前記外部端子部の一部が前記封
止樹脂に封止され且つ前記外部端子部の下面は前記封止
樹脂の底面に露出しており、更にデプレス曲げ加工され
た前記リードの前記内部端子部の下面側に、バンプを介
して前記半導体チップが接続されていることを特徴とす
半導体装置。
3. A semiconductor chip, and the semiconductor chip and an
A lead electrically connected, the semiconductor chip and
A sealing resin for sealing at least a part of the lead.
In the semiconductor device, the lead is at least
An internal terminal portion electrically connected to the semiconductor chip;
When mounting a semiconductor device on a circuit board,
An external terminal connected to a conductor, the internal terminal,
And a connecting portion for connecting to an external terminal portion.
A first end connected to the external terminal of the connection portion;
Connect the connecting part in the width direction on the surface
Having a transverse recess and at least the connecting portion
Depressed bending at the first end, at least
The semiconductor chip and the internal terminal portion of the lead;
The connecting portion including the recess and a part of the external terminal portion are sealed.
Sealed with resin and the lower surface of the external terminal portion is sealed
Exposed on the bottom of the resin, and further depressed
Via a bump on the lower surface side of the internal terminal portion of the lead
And the semiconductor chip is connected to the
That the semiconductor device.
【請求項4】 リードの凹部形成面が、このリードのデ
プレス曲げ加工の曲げ方向と反対側の前記リードの面で
ある請求項1乃至3いずれか1項に記載の半導体装置。
4. The concave portion forming surface of the lead is provided
On the side of the lead opposite to the bending direction of the press bending process
The semiconductor device according to one of claims 1 to 3 any one.
【請求項5】 凹部が化学的なエッチングにより形成
された請求項1乃至3いずれか1項に記載の半導体装
置。
Wherein the concave portion is formed by a chemical etching
Semiconductor device according to any one of claims 1 to 3.
【請求項6】 凹部が、コイニング処理により形成され
た請求項1または2に記載の半導体装置。
6. The recess is formed by coining.
The semiconductor device according to claim 1 .
【請求項7】 凹部の深さが、リードの連結部の厚さの
1/4〜2/3である請求項1乃至いずれか1項に記
載の半導体装置。
7. A depth of the recess, the consolidated portion of the lead thickness
The semiconductor device according to any one of claims 1 to 6, which is a 1/4 to 2/3.
【請求項8】 半導体チップと、この半導体チップと電
気的に接続されているリードと、前記半導体チップ及び
少なくとも前記リードの一部を封止する封止樹脂とを含
む半導体装置において、前記リードは少なくとも、前記
半導体チップと電気的に接続される内部端子部と、前記
半導体装置を回路基板に実装する際にこの回路基板上の
導体に接続される外部端子部と、前記内部端子部と前記
外部端子部とを連結する連結部とを含んでなり、この連
結部の厚さが前記外部端子部の厚さの1/3〜3/4で
且つ前記連結部の前記外部端子部と接続している第1の
端部でデプレス曲げ加工されており、少なくとも前記半
導体チップと前記リードの前記内部端子部と前記連結部
と前記外部端子部の一部が前記封止樹脂に封止され且つ
前記外部端子部の下面は前記封止樹脂の底面に露出して
いることを特徴とする半導体装置。
8. A semiconductor chip, and the semiconductor chip and an electric
A lead electrically connected, the semiconductor chip and
A sealing resin for sealing at least a part of the lead.
In the semiconductor device, the lead is at least
An internal terminal portion electrically connected to the semiconductor chip;
When mounting a semiconductor device on a circuit board,
An external terminal connected to a conductor, the internal terminal,
And a connecting portion for connecting to an external terminal portion.
The thickness of the connecting portion is 1/3 to 3/4 of the thickness of the external terminal portion.
And a first terminal connected to the external terminal portion of the connecting portion.
Depressed bending at the end, at least the half
The conductor chip, the internal terminal portion of the lead, and the connection portion
And a part of the external terminal portion is sealed with the sealing resin, and
The lower surface of the external terminal portion is exposed at the bottom of the sealing resin
A semiconductor device.
【請求項9】 リードの外部端子部と連結する連結部の
第1の端部において、デプレス曲げ加工の曲げ方向に対
して反対側の前記リードの表面が段差を有している請求
記載の半導体装置。
9. A connecting portion connected to an external terminal portion of a lead .
At the first end, the bending direction of the depress bending
9. The semiconductor device according to claim 8 , wherein the surface of the lead on the opposite side has a step .
【請求項10】 外部端子部の下面が、封止樹脂の底面
と平坦である請求項1乃至いずれか1項に記載の半導
体装置。
10. A bottom surface of an external terminal portion is a bottom surface of a sealing resin.
The semiconductor device according to any one of claims 1 to 9 is flat.
【請求項11】 部端子部の下面が、封止樹脂の底面
より突出しており、且つその突出量が連結部に形成され
ている凹部の深さを超えない請求項1乃至いずれか1
項に記載の半導体装置。
11. lower surface of the outer portion the terminal portion, the bottom surface of the sealing resin
More protruding, and the protruding amount is formed on the connecting portion.
And does not exceed the depth of the recess are claims 1 to 7 or 1
13. The semiconductor device according to item 9.
JP36787498A 1998-12-24 1998-12-24 Semiconductor device Expired - Fee Related JP3153197B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36787498A JP3153197B2 (en) 1998-12-24 1998-12-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36787498A JP3153197B2 (en) 1998-12-24 1998-12-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2000196005A JP2000196005A (en) 2000-07-14
JP3153197B2 true JP3153197B2 (en) 2001-04-03

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003204027A (en) 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd Lead frame and its manufacturing method, resin sealed semiconductor device and its manufacturing method
JP2005191240A (en) * 2003-12-25 2005-07-14 Renesas Technology Corp Semiconductor device and method for manufacturing the same
WO2008088291A1 (en) 2007-01-16 2008-07-24 Infineon Technologies Ag Method of semiconductor packaging and/or a semiconductor package
JP2010166100A (en) * 2010-05-06 2010-07-29 Panasonic Corp Resin sealed semiconductor device
WO2019092841A1 (en) * 2017-11-10 2019-05-16 新電元工業株式会社 Electronic module
JP7425581B2 (en) * 2019-11-14 2024-01-31 日清紡マイクロデバイス株式会社 Semiconductor device and its manufacturing method

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