JP3521758B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3521758B2
JP3521758B2 JP26212498A JP26212498A JP3521758B2 JP 3521758 B2 JP3521758 B2 JP 3521758B2 JP 26212498 A JP26212498 A JP 26212498A JP 26212498 A JP26212498 A JP 26212498A JP 3521758 B2 JP3521758 B2 JP 3521758B2
Authority
JP
Japan
Prior art keywords
semiconductor
external electrode
conductive plate
semiconductor chip
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26212498A
Other languages
Japanese (ja)
Other versions
JPH11195733A (en
Inventor
敏紀 中山
Original Assignee
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP9-295485 priority Critical
Priority to JP29548597 priority
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP26212498A priority patent/JP3521758B2/en
Publication of JPH11195733A publication Critical patent/JPH11195733A/en
Application granted granted Critical
Publication of JP3521758B2 publication Critical patent/JP3521758B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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Abstract

PROBLEM TO BE SOLVED: To provide a small-sized and thin semiconductor device that can be produced using simple equipment and does not require capital equipment such as a mold and a drive device for conventional transfer mold techniques or a mold and a driving device for bending lead frames. SOLUTION: A conductive plate is etched and part, except at least external electrode terminals, is made thin. After a chip is mounted and resin-sealed, the thin part of the conductive plate is completely removed by grinding it. A semiconductor device 100 has a semiconductor chip 110 inside and is sealed with a resin 150. A die mounting projected part 12 and external electrode terminals 13 are exposed at the lower part. The semiconductor chip 110 is mounted on the die mounting projected part 12 using an adhesive 120. The I/O terminals of the semiconductor chip 110 are connected to external electrode terminals 13 using conductive wires 130. The external electrode terminals 13 are exposed at the lower part of the semiconductor device 100. Consequently, a small-size semiconductor device with I/O terminals that are not projected from the resin can be manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention
【0001】[0001]
【発明の属する技術分野】本発明は、半導体チップを搭
載し、樹脂封止して形成される半導体装置の製造方法、
この方法に用いる半導体装置用導電性板、および半導体
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, in which a semiconductor chip is mounted and resin-sealed.
The present invention relates to a conductive plate for a semiconductor device and a semiconductor device used in this method.
【0002】[0002]
【従来の技術】従来の半導体装置の一例として、図27
に示す構造がある。この技術は、半導体装置用導電性板
(以下、リードフレームとする。)50上に半導体チッ
プ510を接着剤520を用いて設置し、導電性ワイヤ
530を用いて半導体チップ510をリードフレーム5
0を接続する。次いで、チップ周囲をトランスファーモ
ールドと呼ばれる技術を使い樹脂540で封止し、樹脂
540の側端面より突出したリードフレーム50部分を
クランク状に折り曲げることにより半導体装置500を
製造する。
2. Description of the Related Art As an example of a conventional semiconductor device, FIG.
There is a structure shown in. In this technique, a semiconductor chip 510 is placed on a conductive plate (hereinafter referred to as a lead frame) 50 for a semiconductor device with an adhesive 520, and a conductive wire 530 is used to mount the semiconductor chip 510 on the lead frame 5.
Connect 0. Then, a semiconductor device 500 is manufactured by sealing the periphery of the chip with a resin 540 using a technique called transfer molding, and bending the lead frame 50 portion protruding from the side end surface of the resin 540 into a crank shape.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな半導体装置は、以下のような課題を有する。
However, such a semiconductor device has the following problems.
【0004】すなわち、トランスファーモールド技術を
用いるために、モールド用の金型やその駆動装置、ま
た、リードフレームを曲げるための金型とその駆動装置
が必要であり、非常に大きな設備投資を必要としてい
る。また、リードフレーム50を半導体装置毎に折り曲
げるために、工数が多くかかり、半導体装置が高価にな
る。また、リードフレーム50が樹脂540より突出し
ていることにより、半導体装置が大きくなり、実装した
場合に大きな面積を基板上で必要とし、製品としての小
型化が困難である。
That is, in order to use the transfer molding technique, a mold for molding and its driving device, and a mold for bending the lead frame and its driving device are required, which requires a very large capital investment. There is. Further, since the lead frame 50 is bent for each semiconductor device, a lot of man-hours are required and the semiconductor device becomes expensive. Further, since the lead frame 50 projects from the resin 540, the semiconductor device becomes large, and when mounted, a large area is required on the substrate, and miniaturization as a product is difficult.
【0005】本発明は、このような従来技術の課題を解
決するものであり、その目的とするところは、従来に比
して大幅に小型、薄型にすることができるようにした半
導体装置の製造方法と、これにより製造された小型、薄
型の半導体装置、並びにこの半導体装置を製造するのに
利用される導電性板を提供するところにある。
The present invention solves the problems of the prior art as described above, and an object thereof is to manufacture a semiconductor device which can be made much smaller and thinner than the conventional one. A method, a small and thin semiconductor device manufactured by the method, and a conductive plate used for manufacturing the semiconductor device are provided.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明に係る半導体装置の製造方法は、導電性板の
片面にて半導体チップ搭載領域と当該チップ搭載領域の
周囲に配置される外部電極端子形成領域とを残してその
周囲に薄肉部を形成するエッチング工程と、前記半導体
チップ搭載領域上に半導体チップを搭載する工程と、前
記半導体チップと前記外部電極端子形成領域とを電気的
に導通させるボンディング工程と、前記導電性板の半導
体チップ搭載面側にて半導体チップおよび外部電極端子
を内包する樹脂封止工程と、前記樹脂封止工程の後に
記導電性板の非エッチング面側から当該導電性板の薄肉
部相当厚さ分を越えて前記導電性板を研削除去する工程
を備えることを特徴とする。
In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a semiconductor chip mounting region and a periphery of the chip mounting region are arranged on one surface of a conductive plate. An etching step of forming a thin portion around the external electrode terminal forming area while leaving the external electrode terminal forming area, a step of mounting a semiconductor chip on the semiconductor chip mounting area, and an electrical step of electrically connecting the semiconductor chip and the external electrode terminal forming area. And a resin sealing step of encapsulating the semiconductor chip and the external electrode terminals on the side of the conductive plate on which the semiconductor chip is mounted, and the conductive plate after the resin sealing step. A step of grinding and removing the conductive plate from the non-etched surface side of the conductive plate to a thickness corresponding to the thin portion of the conductive plate.
It is characterized by including.
【0007】このような方法をとることで、厚肉部とな
る半導体チップ搭載領域と当該チップ搭載領域の周囲に
配置される外部電極端子形成領域を残し、これらの周辺
領域をハーフエッチングにより薄肉部として形成した導
電性板を用いる。この導電性板のチップ搭載領域として
の厚肉部表面に半導体チップが搭載され、その導電性板
厚肉部突起箇所の周辺に配置された外部電極端子形成領
域の表面と半導体チップのパッド(例えば入出力用)と
を導電性ワイヤなどにより接続する。ワイヤボンディン
グである。導電性板の半導体チップ搭載面側にて半導体
チップおよび外部電極端子、並びに導電性ワイヤなどを
内包する樹脂等により封止し、その後、樹脂封止されて
いない面から前記導電性板薄肉部を例えば研削等により
除去するのである。その結果、研削面側は、導電性板の
外部電極端子の裏面が各々独立して露出するので、その
箇所を入出力端子とした半導体装置を得ることができ、
小型で薄型の半導体装置を簡便な設備により提供するこ
とができる。また、請求項1記載の半導体装置の製造方
法によれば、樹脂側端面より突出した入出力端子がない
半導体装置を製造することが可能である。
By adopting such a method, the semiconductor chip mounting region which becomes the thick portion and the external electrode terminal forming region arranged around the chip mounting region are left, and these peripheral regions are half-etched to form the thin portion. Is used as the conductive plate. A semiconductor chip is mounted on the surface of the thick part of the conductive plate as the chip mounting region, and the surface of the external electrode terminal forming region and the pad of the semiconductor chip arranged around the protruding part of the conductive plate thick part (for example, (For input / output) is connected with a conductive wire or the like. Wire bonding. On the semiconductor chip mounting surface side of the conductive plate, the semiconductor chip and external electrode terminals are sealed with a resin or the like containing a conductive wire and the like, and then the thin portion of the conductive plate is removed from the surface not resin-sealed. For example, it is removed by grinding or the like. As a result, since the back surface of the external electrode terminal of the conductive plate is independently exposed on the ground surface side, it is possible to obtain a semiconductor device having the input / output terminal at that position.
A small and thin semiconductor device can be provided with simple equipment. Further, according to the method of manufacturing a semiconductor device of the first aspect, it is possible to manufacture a semiconductor device having no input / output terminal protruding from the end surface on the resin side.
【0008】また、第2の構成に係る半導体装置の製造
方法は、導電性板の片面にて半導体チップ搭載領域の周
囲に配置される外部電極端子形成領域を残してその周囲
に薄肉部を形成するエッチング工程と、前記薄肉部とし
ての半導体チップ搭載領域上に半導体チップを搭載する
工程と、前記半導体チップと前記外部電極端子形成領域
とを電気的に導通させるボンディング工程と、前記導電
性板の半導体チップ搭載面側にて半導体チップおよび外
部電極端子を内包する樹脂封止工程と、前記樹脂封止工
程の後に前記導電性板の非エッチング面側から当該導電
性板の薄肉部相当厚さ分を越えて前記導電性板を研削除
去する工程を備えることを特徴とする半導体装置の製造
方法。
Further, in the method for manufacturing a semiconductor device according to the second structure, the thin portion is formed around the external electrode terminal forming region which is arranged around the semiconductor chip mounting region on one surface of the conductive plate. Etching step, a step of mounting a semiconductor chip on the semiconductor chip mounting area as the thin portion, a bonding step of electrically connecting the semiconductor chip and the external electrode terminal forming area, and a conductive plate A resin encapsulation step of encapsulating the semiconductor chip and external electrode terminals on the semiconductor chip mounting surface side ;
A method of manufacturing a semiconductor device, further comprising a step of grinding and removing the conductive plate from the non-etched surface side of the conductive plate so as to exceed a thickness corresponding to a thin portion of the conductive plate .
【0009】このような構成では、導電性板をエッチン
グするのは外部電極端子形成領域を除く表面であり、エ
ッチングによって形成された外部電極端子形成領域の間
にチップ搭載領域が薄肉に形成される。チップをこの領
域に接着設置することで、外部電極端子形成領域の頂面
と半導体チップの表面がほぼ同一となり、ワイヤボンデ
ィング後に樹脂封止し、更に導電性板の外部露出面側で
ある非エッチング面側から導電性板の薄肉部相当厚さ以
上、特に半導体チップのシリコン基板厚さ部分を薄くす
る程度まで切削あるいは研削によって取り除く。これに
より、薄形半導体装置を製造することができる。すなわ
ち、半導体チップの搭載領域部分の厚み分を更に除くこ
とができるので、より薄形の半導体装置を得ることがで
きるのである。特に樹脂より突出した入出力端子がない
小型半導体装置を製造することが可能であるとともに、
請求項1記載の半導体装置よりも同一工程ながら更に小
型(薄型)半導体装置を製造することが可能となってい
る。
In such a structure, the conductive plate is etched on the surface excluding the external electrode terminal forming region, and the chip mounting region is formed thin between the external electrode terminal forming regions formed by etching. . By bonding and mounting the chip in this area, the top surface of the external electrode terminal formation area and the surface of the semiconductor chip are almost the same. It is removed from the surface side by cutting or grinding to a thickness equal to or less than the thin portion of the conductive plate, particularly to the extent of thinning the silicon substrate thickness portion of the semiconductor chip. Thereby, a thin semiconductor device can be manufactured. That is, the thickness of the mounting area of the semiconductor chip can be further removed, and a thinner semiconductor device can be obtained. In particular, it is possible to manufacture small semiconductor devices that do not have I / O terminals protruding from the resin.
It is possible to manufacture a smaller (thinner) semiconductor device in the same process as that of the semiconductor device according to the first aspect.
【0010】更に、本発明は、1枚の導電性板状に複数
の半導体装置構成要素の領域を設定し、この複数の領域
の半導体装置構成要素に対して前記各工程を行なった後
に、各半導体装置構成要素単位に分断処理する工程を含
む構成とすることもできる。
Further, according to the present invention, regions of a plurality of semiconductor device constituent elements are set in one conductive plate shape, and after the above-mentioned steps are performed on the semiconductor device constituent elements of the plurality of regions, It is also possible to adopt a configuration including a step of performing a dividing process for each semiconductor device component.
【0011】また、上記製造方法において、導電性板に
薄肉部を形成するエッチングは等方性エッチングとして
行なうことが望ましい。等方性エッチングであるためエ
ッチング領域は奥に進むほどえぐれた状態となる。した
がって、薄肉部から立設した状態にある非エッチング領
域は、表面側に至るにしたがって迫り出し、オーバハン
グ状態となる。このため後工程で樹脂封止が行われる
が、樹脂内への埋め込み側の相当直径が大きくなり、こ
れがアンカとして作用するために薄肉部を研削除去して
島として残されても樹脂から抜け出ることが防止され
る。
In the above manufacturing method, it is desirable that the etching for forming the thin portion on the conductive plate be isotropic etching. Since the etching is isotropic, the depth of the etching region becomes deeper. Therefore, the non-etching region which is erected from the thin portion protrudes toward the surface side and becomes an overhang state. For this reason, resin sealing is performed in a later step, but the equivalent diameter on the embedded side in the resin becomes large, and this acts as an anchor, so even if the thin portion is ground away and left as an island, it can escape from the resin. Is prevented.
【0012】他の半導体装置の製造方法として、上述し
た半導体装置の製造方法であって、外部電極端子形成領
域における前記ボンディング工程にて使われた領域を除
く領域にて厚み方向に切断する封止樹脂工程を含むこと
ができる。
Another method of manufacturing a semiconductor device is the above-described method of manufacturing a semiconductor device, in which a region other than the region used in the bonding step in the external electrode terminal forming region is cut in the thickness direction. A resin process can be included.
【0013】このような構成とすることにより、外観が
直方体形状となっている半導体装置のコーナ縁辺部分の
直交2面に跨ってL字状の直角面外部電極端子が形成さ
れる。これにより基板へのハンダ実装に際してハンダフ
ィレットが大きく形成され、実装固定が強化される。ま
た、半導体装置を基板に平面的に実装せずに立設させた
状態での実装が可能となる。基板に対する実装面積が小
さくなるので、効率的な実装密度が得られる。
With this structure, the L-shaped right-angled external electrode terminals are formed across the two orthogonal surfaces of the corner edge portion of the semiconductor device having a rectangular parallelepiped appearance. As a result, a large solder fillet is formed at the time of solder mounting on the board, and mounting and fixing is strengthened. Further, it is possible to mount the semiconductor device in a state where it is erected on the substrate without being planarly mounted. Since the mounting area for the substrate is reduced, efficient mounting density can be obtained.
【0014】また、前述した半導体装置の製造方法であ
って、前記研削除去する工程では導電性板の薄肉部相当
厚さを超えて半導体チップ裏面側を一部研削することが
できる。
Further, in the above-described method of manufacturing a semiconductor device, in the step of grinding and removing, it is possible to partially grind the back surface side of the semiconductor chip beyond the thickness corresponding to the thin portion of the conductive plate.
【0015】このようにすることで、上記方法に比べ
て、更に薄型の半導体装置が提供できる。しかも除去す
るのは半導体チップの回路が形成されていない裏面側な
ので、回路自体に影響を与えることがない。
By doing so, it is possible to provide a thinner semiconductor device as compared with the above method. Moreover, since the portion of the semiconductor chip to be removed is the back surface side on which the circuit is not formed, the circuit itself is not affected.
【0016】また、前記半導体装置の製造方法であっ
て、前記導電性板の薄肉部を除去する工程の後に前記外
部端子として用いられる部位の露出面に対して導電性メ
ッキを施す工程を更に有してなることを特徴とする。
Further, in the method of manufacturing the semiconductor device, the method further includes a step of conducting conductive plating on an exposed surface of a portion used as the external terminal after the step of removing the thin portion of the conductive plate. It is characterized by being done.
【0017】このようにすることで、露出面の保護(例
えば、露出面の酸化を防止すること)や、半導体装置の
実装基板への実装時のはんだのぬれ性を向上させること
ができる。
By doing so, it is possible to protect the exposed surface (for example, prevent oxidation of the exposed surface) and improve the wettability of the solder when mounting the semiconductor device on the mounting substrate.
【0018】また、複数の半導体装置構成要素を同時に
製造する方法において、前記半導体装置構成要素に対し
て前記各工程を行なった後に前記外部電極端子として用
いられるランド部よりも外側にて半導体装置構成要素単
位に前記導電性板の厚み方向に切断する工程を含む構成
とすることができる。
Further, in the method of simultaneously manufacturing a plurality of semiconductor device constituent elements, the semiconductor device constituent element is arranged outside a land portion used as the external electrode terminal after the above-mentioned steps are performed on the semiconductor device constituent element. The configuration may include a step of cutting the conductive plate in the thickness direction of the element unit.
【0019】このような構成をとることで、複数の半導
体装置が1つの導電性板から製造できることとなり、量
産性に優れる方法である。すなわち、複数の半導体装置
の構成要素に対し樹脂封止、研削等の工程を1回の作業
で行なうことができるので、処理個数が増大し、半導体
装置1個あたりの工数が削減される。
With such a structure, a plurality of semiconductor devices can be manufactured from one conductive plate, which is a method excellent in mass productivity. That is, steps such as resin sealing and grinding can be performed on a plurality of components of the semiconductor device in one operation, so that the number of processes is increased and the number of processes per semiconductor device is reduced.
【0020】一方、本発明に用いられる半導体装置用導
電性板としては、半導体装置構成要素の形成領域内で、
導電性材料からなる平板の片面に対し、少なくとも半導
体チップ搭載領域の周囲に配置される外部電極端子形成
領域を残し、その余の領域の表面層をエッチング除去し
て薄肉部とし、当該薄肉部により前記外部電極端子形成
領域相互が架橋されたことを特徴とする。
On the other hand, the conductive plate for a semiconductor device used in the present invention is as follows:
With respect to one surface of the flat plate made of a conductive material, leaving at least the external electrode terminal forming region arranged around the semiconductor chip mounting region, the surface layer of the remaining region is removed by etching to form a thin portion, and the thin portion The external electrode terminal forming regions are cross-linked with each other.
【0021】更に、半導体装置構成要素の形成領域内
で、導電性材料からなる平板の片面に対し、半導体チッ
プ搭載領域と当該チップ搭載領域の周囲に配置される外
部電極端子形成領域とを残し、その余の領域の表面層を
エッチング除去して薄肉部とし、当該薄肉部により前記
半導体チップ搭載領域と当該チップ搭載領域の周囲に配
置される前記外部電極端子形成領域とが架橋されたもの
を用いる。アンカ作用で埋め込まれた外部電極端子が封
止樹脂から抜け出ることがなくなるのである。また、封
止樹脂に接している面に与えられた曲率面が存在するた
め、これが抜け止め作用をなす。これらは外部電極端子
を形成するために行われる導電性板のエッチング処理を
等方性エッチングによって行なうことで実現できる。
Further, in the formation region of the semiconductor device constituent elements, a semiconductor chip mounting region and an external electrode terminal formation region arranged around the chip mounting region are left on one surface of a flat plate made of a conductive material, The surface layer of the remaining region is removed by etching to form a thin portion, and the thin portion is used to bridge the semiconductor chip mounting region and the external electrode terminal forming region arranged around the chip mounting region. . The external electrode terminal embedded by the anchor action does not come out of the sealing resin. Further, since there is a curvature surface provided on the surface in contact with the sealing resin, this serves as a retaining function. These can be realized by performing the etching process of the conductive plate for forming the external electrode terminals by isotropic etching.
【0022】これらの半導体装置用導電性板であって、
前記外部電極端子形成領域及び薄肉部からなる半導体装
置構成要素が1枚の平板に複数設けられていることを特
徴とするまた、前記半導体装置用導電性板は、銅系材料
からなることを特徴とする。高放熱性を考慮すると銅系
材料を利用することが好ましい。また、半導体チップと
の熱膨張率の差を考慮した場合には、鉄−ニッケル系合
金を使用してもよい。更に、前記薄肉部を形成するエッ
チング工程は等方性のエッチングにより行なうことが望
ましい。
A conductive plate for these semiconductor devices, comprising:
A plurality of semiconductor device constituent elements including the external electrode terminal forming region and the thin portion are provided on one flat plate, and the conductive plate for a semiconductor device is made of a copper-based material. And Considering high heat dissipation, it is preferable to use a copper-based material. In consideration of the difference in coefficient of thermal expansion from the semiconductor chip, an iron-nickel alloy may be used. Further, it is desirable that the etching step for forming the thin portion is performed by isotropic etching.
【0023】本発明に係る半導体装置は、表面に電極を
有する半導体チップと、前記半導体チップの周囲にて各
々が独立して形成されると共に、前記半導体チップの前
記電極と電気的に導通が図られるように接続された外部
電極端子と、前記半導体チップの裏面を除く全面並びに
前記外部電極端子の前記半導体チップ裏面と同じ側の面
を除く全面を覆うように設けられた封止樹脂とを有し、
前記半導体チップの載置部または半導体チップ自体の封
止樹脂からの露出面と前記外部電極端子の封止樹脂から
の露出面が同一平面上に位置するように設定したことを
特徴とする。なお、この構成において、外部電極端子が
半導体チップの周囲に独立して形成されているとある
が、これは半導体チップおよびお互いの外部電極端子同
士とが所定の距離を隔てて島状に配置されていることを
意味している。
In the semiconductor device according to the present invention, a semiconductor chip having an electrode on its surface is formed independently of each other around the semiconductor chip, and electrically connected to the electrode of the semiconductor chip. External electrode terminals connected as described above, and a sealing resin provided so as to cover the entire surface of the semiconductor chip except the back surface and the entire surface of the external electrode terminal except the surface on the same side as the semiconductor chip back surface. Then
The exposed surface of the mounting portion of the semiconductor chip or the semiconductor chip itself from the sealing resin and the exposed surface of the external electrode terminal from the sealing resin are located on the same plane. In this configuration, the external electrode terminals are said to be independently formed around the semiconductor chip. This is because the semiconductor chip and the external electrode terminals are arranged in an island shape with a predetermined distance. It means that
【0024】この構成では、製品形態では外部電極端子
は封止樹脂面から突出しておらず、実装高さを小さくす
ることができる。
In this structure, the external electrode terminals do not project from the sealing resin surface in the product form, and the mounting height can be reduced.
【0025】また、上述の各半導体装置において、前記
外部電極端子部の前記半導体チップ裏面と同じ側の面に
導電性のめっき層が形成されていることを特徴とする。
Further, in each of the above-mentioned semiconductor devices, a conductive plating layer is formed on a surface of the external electrode terminal portion on the same side as the back surface of the semiconductor chip.
【0026】このようにすることで、外部端子部の露出
面の保護がなされることになる。
By doing so, the exposed surface of the external terminal portion is protected.
【0027】また、前記半導体装置において、外部電極
端子部は前記半導体チップの全辺に対応して形成される
ことを特徴とする。このようにすれば、半導体装置の高
集積化が図られる。
Further, in the semiconductor device, the external electrode terminal portion is formed corresponding to the entire side of the semiconductor chip. In this way, high integration of the semiconductor device can be achieved.
【0028】または、前記半導体装置において、外部電
極端子部は前記半導体チップの1辺に対応する位置にお
いて複数列形成されるとともに隣り合う外部端子部は千
鳥状に形成されてなることを特徴とする。このようにす
れば、高集積化が図られた上に、隣り合う外部端子間の
距離を1列に並べた場合に比して得ることができ、実装
基板との接続信頼性を充分に得ることができる。
Alternatively, in the semiconductor device, the external electrode terminal portions are formed in a plurality of rows at positions corresponding to one side of the semiconductor chip, and the adjacent external terminal portions are formed in a zigzag shape. . In this way, high integration can be achieved, and the distance between adjacent external terminals can be obtained as compared with the case where they are arranged in one row, and sufficient connection reliability with the mounting substrate can be obtained. be able to.
【0029】半導体装置の外部電極端子には半田ボール
を予め一体的に取りつけるようにすれば実装が極めて簡
単に行なえる。
If solder balls are integrally attached to the external electrode terminals of the semiconductor device in advance, the mounting can be performed very easily.
【0030】更に、本発明は、半導体チップとボンディ
ングされチップ周辺に独立して配置される外部電極端子
の封止樹脂内への埋め込み部側の相当直径を露出側の相
当直径より大きくした構成とすることができる。半導体
チップとボンディングされチップ周辺に独立して配置さ
れる外部電極端子における封止樹脂に接している面は曲
率を有する面からなるように構成してもよい。このよう
な半導体装置では、当初導電性板と一体的になって薄肉
部を連結材としてチップ搭載領域に接続されていたが、
研削により独立した島としてチップ周辺部にて封止樹脂
内に埋め込まれつつ、先端面のみを外表面に露出して外
部電極面となる。このとき、埋め込み電極の埋め込み側
の相当直径が大きく、露出側の相当直径が小さいため、
Furthermore, according to the present invention, the equivalent diameter of the external electrode terminal, which is bonded to the semiconductor chip and is independently arranged around the chip, on the embedded portion side in the sealing resin is larger than the equivalent diameter on the exposed side. can do. The surface of the external electrode terminal, which is bonded to the semiconductor chip and is independently arranged around the chip, in contact with the sealing resin may be a surface having a curvature. In such a semiconductor device, the thin plate portion was initially connected to the chip mounting area integrally with the conductive plate.
While being embedded in the sealing resin in the peripheral portion of the chip as an independent island by grinding, only the tip surface is exposed to the outer surface to become the external electrode surface. At this time, since the equivalent diameter on the embedded side of the embedded electrode is large and the equivalent diameter on the exposed side is small,
【0031】[0031]
【発明の実施の形態】以下に、本発明に係る半導体装置
の製造方法、半導体装置用導電性板および半導体装置の
具体的実施の形態を図面を参照して詳細に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Specific embodiments of a method for manufacturing a semiconductor device, a conductive plate for a semiconductor device, and a semiconductor device according to the present invention will be described below in detail with reference to the drawings.
【0032】図1および図2は、本発明の第1の実施形
態に係る半導体装置の断面図および底面図である。図示
のように、本発明に係る半導体装置は、半導体チップの
電極と外部電極端子部とを電気的導通を図って樹脂封止
された半導体装置において、前記半導体チップの平面に
沿った封止樹脂外表面部に前記外部電極端子を同一平面
となるように露出形成させてなることを特徴としてい
る。すなわち、第1実施形態に係る半導体装置100内
部に半導体チップ110を持ち、樹脂150により封止
され、全体として外観が直方体形状に形成されている。
直方体の封止樹脂150における下面中央には、銅板か
らなるダイ付け突起部12の底面が臨まれ、またその一
対の縁辺に沿って複数の外部電極端子13が底面の端子
面を露出させて配列している。これらのダイ付け突起部
12と外部電極端子13の端子面と、封止樹脂150の
底面とは一平面をなしている。半導体チップ110は、
接着剤120によりダイ付け突起部12の上面へ固定さ
れている。半導体チップ110の入出力は、導電性ワイ
ヤ130を介して外部電極端子13の上面へ接続され、
ワイヤボンディング側を封止樹脂150により封止して
構成され、前記外部電極端子13が半導体装置100の
下部に露出させていることで入出力をなすようにしてい
る。
1 and 2 are a sectional view and a bottom view of a semiconductor device according to the first embodiment of the present invention. As shown in the figure, the semiconductor device according to the present invention is a semiconductor device in which electrodes of a semiconductor chip and external electrode terminal portions are resin-sealed for electrical conduction, and a sealing resin along a plane of the semiconductor chip. It is characterized in that the external electrode terminals are exposed and formed on the outer surface so as to be flush with each other. That is, the semiconductor chip 110 is provided inside the semiconductor device 100 according to the first embodiment, and the semiconductor chip 110 is sealed with the resin 150, and the overall appearance is formed in a rectangular parallelepiped shape.
At the center of the lower surface of the rectangular parallelepiped sealing resin 150, the bottom surface of the die attaching projection 12 made of a copper plate is exposed, and a plurality of external electrode terminals 13 are arranged along the pair of edges so as to expose the terminal surface of the bottom surface. is doing. The die attaching projections 12, the terminal surfaces of the external electrode terminals 13, and the bottom surface of the sealing resin 150 are coplanar. The semiconductor chip 110 is
It is fixed to the upper surface of the die attachment projection 12 by an adhesive agent 120. The input / output of the semiconductor chip 110 is connected to the upper surface of the external electrode terminal 13 via the conductive wire 130,
The wire bonding side is sealed with a sealing resin 150, and the external electrode terminals 13 are exposed to the lower portion of the semiconductor device 100 to perform input / output.
【0033】このような第1実施形態に係る半導体装置
100の製造方法を図3の工程フローチャートを参照し
て説明する。まず、図3(1)に示しているように、銅
平板からなる半導体装置用導電性板(以下、単に導電性
板とする。)10を用意する。この導電性板10の片面
を等方性エッチング処理して、半導体チップ110の搭
載領域Cと、これに隣接して配置される外部電極端子形
成領域Tとを残して、図3(2)に示すように、それら
の周囲に薄肉部11を形成するようにしている。薄肉部
11は導電性板10の肉厚の半分程度にすればよい。図
4は断面図、図5は導電性板10を上部よりみた平面図
であり、本発明の導電性板の第1実施例を示すものであ
る。エッチング処理は等方性エッチングであるため、図
4に部分的に拡大して示したように、マスク面側からエ
ッチング深さ方向に至るにしたがってエッチング領域が
拡大し、その結果、非エッチング領域は高さ方向におい
て、マスク面側の相当直径Dが基部の相当直径dより大
きくなって、オーバハング状態に形成される。外部電極
端子領域Tは、後述するように薄肉部を研削して除去す
ることで封止樹脂内に残留するので、埋め込み側が大径
となり、露出側が小径となる。したがってアンカ作用を
発揮させることができ、封止樹脂から外部電極端子が抜
け出ることが防止される。
A method of manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to the process flowchart of FIG. First, as shown in FIG. 3A, a conductive plate for a semiconductor device (hereinafter, simply referred to as a conductive plate) 10 made of a copper flat plate is prepared. One side of the conductive plate 10 is isotropically etched to leave the mounting area C of the semiconductor chip 110 and the external electrode terminal forming area T adjacent to the mounting area C, as shown in FIG. As shown, the thin portion 11 is formed around them. The thin portion 11 may be about half the thickness of the conductive plate 10. FIG. 4 is a cross-sectional view, and FIG. 5 is a plan view of the conductive plate 10 as seen from above, showing a first embodiment of the conductive plate of the present invention. Since the etching process is isotropic,
As shown in FIG. 4 partially enlarged, the etching region expands from the mask surface side in the etching depth direction, and as a result, the non-etching region in the height direction has an equivalent diameter D on the mask surface side. Becomes larger than the equivalent diameter d of the base portion and is formed in an overhang state. Since the external electrode terminal region T remains in the sealing resin by grinding and removing the thin portion as described later, the embedded side has a large diameter and the exposed side has a small diameter. Therefore, the anchor action can be exerted, and the external electrode terminals are prevented from coming off from the sealing resin.
【0034】導電性板10は、もとは均一な厚みをもつ
導電性板であり、腐食加工などを施し板状の一部の厚み
を薄くすることにより、チップ搭載領域Cおよび外部電
極端子形成領域Tを厚肉部であるランド部とし、その周
囲に薄肉部11が存在している。この導電性板10の厚
肉部となる中央のランド部はダイ付け突起形成部121
となって、半導体チップを搭載するものであり、別の厚
肉のランド部として隣接配置している外部電極形成部1
31の上面は、半導体チップの入出力部パッドから導電
性ワイヤなどで接続される部分となる。外部電極形成部
131は、単数あるいは複数個、ダイ付け突起形成部1
21の周辺に配置させられる。各突起であるダイ付け突
起形成部121、外部電極形成部131は、独立した突
起になるよう薄肉部11より高くしてある。また、ダイ
付け突起形成部121、外部電極形成部110の一部あ
るいは全部の上面には、導電性めっき等の処理を施す場
合がある。これを図3(3)に示している。
The conductive plate 10 is originally a conductive plate having a uniform thickness, and the chip mounting region C and the external electrode terminal are formed by reducing the thickness of a part of the plate shape by performing corrosion processing or the like. The region T is a land portion that is a thick portion, and the thin portion 11 exists around the land portion. The central land portion, which is the thick portion of the conductive plate 10, is a die attachment projection forming portion 121.
Therefore, the semiconductor chip is mounted on the external electrode forming portion 1 which is adjacently arranged as another thick land portion.
The upper surface of 31 is a portion connected to the input / output pad of the semiconductor chip by a conductive wire or the like. The external electrode forming portion 131 may be a single or a plurality of die attaching projection forming portions 1.
It is arranged around 21. The die-attached protrusion forming portion 121 and the external electrode forming portion 131, which are the respective protrusions, are higher than the thin portion 11 so as to be independent protrusions. In addition, the upper surface of part or all of the die attachment projection forming portion 121 and the external electrode forming portion 110 may be subjected to a treatment such as conductive plating. This is shown in FIG.
【0035】次に図3(4)および図6の断面図に示す
ように、導電性板10のダイ付け突起形成部121の上
に半導体チップ110を接着剤120などを用いて搭載
し、半導体チップ110の入出力パッドと導電性板10
における外部電極形成部131の上部平坦部を導電性ワ
イヤ130を用い接続する(図3(5)参照)。ボンデ
ィング処理した半導体装置の平面図は、図7である。
Next, as shown in the sectional views of FIG. 3 (4) and FIG. 6, the semiconductor chip 110 is mounted on the die attaching projection forming portion 121 of the conductive plate 10 using an adhesive agent 120 or the like, Input / output pad of chip 110 and conductive plate 10
The upper flat portion of the external electrode forming portion 131 in is connected using the conductive wire 130 (see FIG. 3 (5)). FIG. 7 is a plan view of the semiconductor device subjected to the bonding process.
【0036】その後、図3(6)および図8に示すよう
に、導電性板10の上の突起が存在する面において、す
なわち半導体チップ110搭載面のダイ付け突起形成部
121、外部電極形成部131、半導体チップ110、
導電性ワイヤ130が配置される部分で、これらの全て
を覆うように、樹脂150にて封止する。封止したの
ち、導電性板10の樹脂封止されていない面すなわち非
エッチング面側から、薄肉部11の相当厚さの分だけ、
導電性板10が露出している面より研削(あるいはカッ
ティング)する。その際の研削は、薄肉部11が完全に
なくなるまで行う。すなわち、ダイ付け突起部12と外
部電極部13が電気的に完全に独立するような位置であ
る、図3(7)および図8中の研削面160に示す位置
まで研削する。
Then, as shown in FIGS. 3 (6) and 8, on the surface of the conductive plate 10 on which the protrusion is present, that is, the die-attaching protrusion forming portion 121 and the external electrode forming portion of the semiconductor chip 110 mounting surface. 131, the semiconductor chip 110,
The portion where the conductive wire 130 is arranged is sealed with a resin 150 so as to cover all of them. After sealing, from the surface of the conductive plate 10 which is not resin-sealed, that is, the non-etching surface side, the thin film portion 11 having an equivalent thickness,
The surface from which the conductive plate 10 is exposed is ground (or cut). Grinding at that time is performed until the thin portion 11 is completely removed. That is, the die attachment protrusion 12 and the external electrode portion 13 are ground to a position indicated by the grinding surface 160 in FIGS.
【0037】これらの工程を経ることによって得られた
半導体装置が、図1の半導体装置100である。この時
の半導体装置100の裏面、すなわち実装される面の構
造は、図2に示すものになる。導電性板10に形成され
ていたダイ付け突起部12と外部電極端子13がそれぞ
れ独立した状態で半導体装置表面に露出しており、本半
導体装置100の入出力部となる。
The semiconductor device obtained by going through these steps is the semiconductor device 100 of FIG. The structure of the back surface of the semiconductor device 100 at this time, that is, the surface to be mounted is as shown in FIG. The die-attaching protrusions 12 and the external electrode terminals 13 formed on the conductive plate 10 are exposed on the surface of the semiconductor device independently of each other and serve as an input / output portion of the semiconductor device 100.
【0038】この露出面であるダイ付け突起部12の露
出面と外部電極端子13の露出面に、図3(8)に示す
ように、導電性めっきを施し、露出面の酸化防止、実装
時のはんだのぬれ性の向上を考慮する場合もある。
As shown in FIG. 3 (8), conductive plating is applied to the exposed surface of the die attaching protrusion 12 and the exposed surface of the external electrode terminal 13 which are the exposed surfaces to prevent the exposed surface from being oxidized and to be mounted. There is also a case where the improvement of the wettability of the solder is considered.
【0039】次に、本発明に係る第2の実施形態の半導
体装置を図9および図10に示す。この図9および図1
0は、半導体装置の断面図および底面図である。第2の
実施形態に係る半導体装置は、封止樹脂中に埋め込まれ
た半導体チップと埋め込み外部電極形成部とがほぼ同一
厚さ(高さ)を有する構造とされ、特に半導体チップは
活性側とは反対面のシリコン基板側が研削されて薄肉化
されている点に特徴があり、半導体装置としての厚さが
大幅に小さく形成されている。すなわち、半導体装置2
00は、内部に半導体チップ210を持ち、樹脂240
により封止されており、全体として外観が直方体形状に
形成されている。直方体の封止樹脂240における下面
中央には半導体チップ210の裏面、外部電極形成部2
3の底面端子面が露出している。半導体チップ210の
入出力は、導電性ワイヤ230を介して外部電極形成部
23の上面へ接続され、外部電極形成部23が半導体装
置200の下部に露出していることで達成されている。
Next, a semiconductor device according to a second embodiment of the present invention is shown in FIGS. 9 and 10. This FIG. 9 and FIG.
Reference numeral 0 is a sectional view and a bottom view of the semiconductor device. The semiconductor device according to the second embodiment has a structure in which the semiconductor chip embedded in the encapsulating resin and the embedded external electrode forming portion have substantially the same thickness (height). Is characterized in that the silicon substrate side on the opposite side is ground to reduce the thickness, and the thickness of the semiconductor device is significantly reduced. That is, the semiconductor device 2
00 has a semiconductor chip 210 inside and a resin 240
The outer appearance is formed in a rectangular parallelepiped shape as a whole. In the center of the lower surface of the rectangular parallelepiped sealing resin 240, the back surface of the semiconductor chip 210, the external electrode forming portion 2
The bottom terminal surface of 3 is exposed. Input / output of the semiconductor chip 210 is achieved by being connected to the upper surface of the external electrode forming portion 23 via the conductive wire 230 and exposing the external electrode forming portion 23 to the lower portion of the semiconductor device 200.
【0040】この構造を得る為の製造工程を図11に示
す。まず、同図(1)に示すように、銅平板からなる半
導体装置用導電性板(以下、単に導電性板とする。)2
0を用意する。導電性板20は、もとは均一な厚みをも
つ導電性板であり、腐食加工などを施し板状の一部の厚
みを薄くすることにより厚肉部と薄肉部が存在してい
る。第1実施形態がチップ搭載領域Cと外部電極端子形
成領域Tとをランド部として残し、他の領域を薄肉部と
してエッチング処理するようにしているが、この第2実
施形態は、チップ搭載領域Cも薄肉部としてエンチング
する部位とした点が第1実施形態と異なる。すなわち、
導電性板20は半導体チップ搭載領域Cの周囲に配置さ
れる外部電極端子形成領域Tのみをランド部として残
し、図11(2)に示しているように、その周囲にエッ
チング除去された薄肉部21を形成し、この薄肉部は非
エッチング面側の研削により前記外部電極端子形成領域
Tの相互間を分離可能な深さに設定したのである。図1
2はエッチング処理した導電性板20の断面図、図13
は上部よりみた平面図である。
The manufacturing process for obtaining this structure is shown in FIG. First, as shown in FIG. 1A, a conductive plate for a semiconductor device made of a copper flat plate (hereinafter, simply referred to as a conductive plate) 2
Prepare 0. The conductive plate 20 is originally a conductive plate having a uniform thickness, and has a thick portion and a thin portion formed by reducing the thickness of a part of the plate shape by performing corrosion processing or the like. In the first embodiment, the chip mounting region C and the external electrode terminal forming region T are left as lands, and the other regions are etched as thin portions, but in the second embodiment, the chip mounting region C is used. Also, the thinned portion is different from the first embodiment in that it is a portion to be enched. That is,
The conductive plate 20 leaves only the external electrode terminal formation region T arranged around the semiconductor chip mounting region C as a land portion, and as shown in FIG. 11B, a thin portion etched and removed around the region. 21 is formed, and the thin portion is set to a depth at which the external electrode terminal forming regions T can be separated from each other by grinding the non-etched surface side. Figure 1
2 is a cross-sectional view of the conductive plate 20 that has been subjected to the etching treatment, FIG.
Is a plan view seen from above.
【0041】この導電性板20では、半導体チップを搭
載する部分を薄肉部21としている。図12、図13で
示すダイ付け部22の位置に半導体チップを搭載する
(以下、ダイ付け部22とする。)。また、ダイ付け部
22は、薄肉部21の表面の一部である。厚肉部突起箇
所である外部電極形成部231は、半導体チップの入出
力部から導電性ワイヤ230などで接続される部分とな
る。外部電極形成部23は、単数あるいは複数個、ダイ
付け部22の周辺に配置させられる。外部電極形成部2
31は、独立した突起になるように薄肉部21より厚く
してある。また、ダイ付け部22、外部電極形成部23
1の一部あるいは全部の上面には、ボンディングの際の
接合性の向上の為に、図11(3)に示しているよう
に、導電性めっきを施す場合がある。
In the conductive plate 20, the portion on which the semiconductor chip is mounted is the thin portion 21. A semiconductor chip is mounted at the position of the die attaching portion 22 shown in FIGS. 12 and 13 (hereinafter referred to as the die attaching portion 22). The die attaching portion 22 is a part of the surface of the thin portion 21. The external electrode forming portion 231 which is a thick-walled portion projecting portion is a portion connected to the input / output portion of the semiconductor chip by the conductive wire 230 or the like. The external electrode forming portion 23 is arranged in the periphery of the die attaching portion 22 in a single or plural number. External electrode forming part 2
Reference numeral 31 is thicker than the thin portion 21 so as to form an independent protrusion. In addition, the die attaching portion 22 and the external electrode forming portion 23
In order to improve the bondability at the time of bonding, a part or all of the upper surface of 1 may be conductively plated as shown in FIG. 11 (3).
【0042】次に図11(4)および図14の断面図に
示すように、導電性板20のダイ付け部22の上に半導
体チップ210を接着剤220などを用いて搭載し、半
導体チップ210の入出力パッドと導電性板20の外部
電極形成部23の上部平坦部を導電性ワイヤ230を用
い接続する(図11(5)参照)。ボンディング処理し
た半導体装置の平面図は、図15である。
Next, as shown in the sectional views of FIG. 11 (4) and FIG. 14, the semiconductor chip 210 is mounted on the die attaching portion 22 of the conductive plate 20 with an adhesive 220 or the like, and the semiconductor chip 210 is mounted. The input / output pad and the upper flat portion of the external electrode forming portion 23 of the conductive plate 20 are connected using the conductive wire 230 (see FIG. 11 (5)). FIG. 15 is a plan view of the semiconductor device subjected to the bonding process.
【0043】その後、図11(6)および図16に示す
ように導電性板20の上の突起が存在する面、すなわち
半導体チップ210の搭載面のダイ付け部22、外部電
極形成部23、半導体チップ210、導電性ワイヤ23
0の全てを覆うように、樹脂240にて封止する。封止
したのち、導電性板20を薄肉部21側、すなわち樹脂
封止されていない面すなわち非エッチング面側から、導
電性板20が露出している面より研削(あるいはカッテ
ィング)する。その際の研削は、薄肉部21が完全にな
くなるまで行う。すなわち、外部電極形成部23が電気
的に完全に独立する研削面250に示す位置まで研削す
る。この場合、半導体チップ210の底面は、外部電極
形成部23の上面より下方の位置にある為に、研削面2
50まで研削する際には、半導体チップ110の下面の
一部は研削されることになる(図11(7)参照)。
After that, as shown in FIGS. 11 (6) and 16, the surface of the conductive plate 20 on which the projections are present, that is, the mounting surface of the semiconductor chip 210, the die attaching portion 22, the external electrode forming portion 23, and the semiconductor. Chip 210, conductive wire 23
It is sealed with a resin 240 so as to cover all 0s. After the sealing, the conductive plate 20 is ground (or cut) from the thin-walled portion 21 side, that is, the surface not resin-sealed, that is, the non-etched surface side, from the surface where the conductive plate 20 is exposed. Grinding at that time is performed until the thin portion 21 is completely removed. That is, the external electrode forming portion 23 grinds to a position indicated by a grinding surface 250 that is completely electrically independent. In this case, since the bottom surface of the semiconductor chip 210 is located below the top surface of the external electrode forming portion 23, the ground surface 2
When grinding to 50, a part of the lower surface of the semiconductor chip 110 is ground (see FIG. 11 (7)).
【0044】これらの工程を経ることによって得られた
半導体装置が、図9、図10の半導体装置200であ
る。この時の半導体装置200の裏面、すなわち実装さ
れる面の構造は、図10に示すものになる。導電性板2
0に形成されていた外部電極形成部23がそれぞれ独立
した状態で半導体装置表面に露出しており、本半導体装
置200の入出力部となる。それと同時に、搭載されて
いる半導体チップ210の底面が露出した状態となる。
The semiconductor device obtained by going through these steps is the semiconductor device 200 of FIGS. 9 and 10. The structure of the back surface of the semiconductor device 200 at this time, that is, the surface to be mounted is as shown in FIG. Conductive plate 2
The external electrode forming portions 23 formed at 0 are exposed on the surface of the semiconductor device in an independent state, and serve as the input / output portion of the semiconductor device 200. At the same time, the bottom surface of the mounted semiconductor chip 210 is exposed.
【0045】この露出面である外部電極形成部23に導
電性めっきを施し、露出面の酸化防止、実装時のはんだ
のぬれ性の向上を考慮する場合もある。
In some cases, the external electrode forming portion 23, which is the exposed surface, is subjected to conductive plating to prevent oxidation of the exposed surface and improve solder wettability during mounting.
【0046】また、導電性板は、図5あるいは図13に
示すように、1枚に1つの半導体チップを搭載すること
を限定しない。すなわち、図17に示すように、1枚の
導電性板30上に、ダイ付け突起部あるいはダイ付け形
成部31と外部電極形成部32からなる半導体装置構成
要素パターン33を列状あるいは格子状に複数配置する
ことも可能である。
The conductive plate is not limited to mounting one semiconductor chip on each conductive plate, as shown in FIG. 5 or FIG. That is, as shown in FIG. 17, semiconductor device component patterns 33 including die attachment protrusions or die attachment formation portions 31 and external electrode formation portions 32 are arranged in a row or a grid on one conductive plate 30. It is also possible to arrange a plurality.
【0047】この場合、導電性板30上を樹脂封止し、
裏面からの研削を行った後に、切断線35より切り離す
必要がある。しかし、樹脂封止、裏面の研削等を一括し
て行うことが可能であり、大幅な工数の削減が可能であ
る。
In this case, the conductive plate 30 is resin-sealed,
It is necessary to cut off from the cutting line 35 after performing grinding from the back surface. However, resin encapsulation, grinding of the back surface, and the like can be performed at once, and the number of steps can be significantly reduced.
【0048】また全体を通じて、外部電極端子部は半導
体チップの1辺に対応する位置において、複数列に形成
されるとともに隣り合う外部端子部は千鳥状になるよう
に配置形成されてもよい。この構成例を図18〜図20
の模式説明図に示す。図18および図19はダイ付け部
41の側縁部に沿って外部電極端子42を単純に2列並
べた例である。半導体チップの電極パッドと各外部電極
端子42とはJワイヤボンディングの手法を一部に採用
することにより外縁部端子との導通を確保できる。ま
た、図20(1)に示すように、外部電極端子42の配
列を千鳥配列とすれば特別な手法を用いること無く簡単
にボンディングできる。更に同図(2)では、ダイ付け
部41の全周の各辺に沿って外部電極端子42を配列し
たものである。これらの例では、より高集積化したパッ
ケージ製品が得られる。
In addition, the external electrode terminal portions may be formed in a plurality of rows at positions corresponding to one side of the semiconductor chip and the adjacent external terminal portions may be arranged in a zigzag shape. This configuration example is shown in FIGS.
Is shown in the schematic explanatory view of FIG. 18 and 19 are examples in which the external electrode terminals 42 are simply arranged in two rows along the side edge portion of the die attaching portion 41. The electrode pad of the semiconductor chip and each external electrode terminal 42 can secure conduction with the outer edge terminal by partially adopting the J wire bonding technique. Further, as shown in FIG. 20A, if the external electrode terminals 42 are arranged in a staggered arrangement, bonding can be easily performed without using a special method. Further, in FIG. 2B, the external electrode terminals 42 are arranged along each side of the entire circumference of the die attaching portion 41. In these examples, a package product with higher integration can be obtained.
【0049】図21には変形例として外部電極端子42
に対してハンダボール44をマウントした例を示してい
る。実施形態の半導体装置では外部電極端子は封止樹脂
の平面と同一平面上に形成される。このため、基板側へ
の実装に際して面合わせにより端子整合を図らなければ
ならないが、ハンダボール44が突起状態でマウントさ
れるため、基板端子との位置合わせが容易になり、実装
作業を簡便化できる。
FIG. 21 shows a modification of the external electrode terminal 42.
On the other hand, an example in which the solder ball 44 is mounted is shown. In the semiconductor device of the embodiment, the external electrode terminals are formed on the same plane as the plane of the sealing resin. For this reason, when mounting on the board side, it is necessary to achieve terminal matching by face-to-face matching, but since the solder balls 44 are mounted in a protruding state, positioning with the board terminals is easy, and mounting work can be simplified. .
【0050】次に、図22〜図23には第3実施形態に
係る半導体装置の製造方法とこれにより得られる半導体
装置の外観を示している。この実施形態は、半導体チッ
プの電極と外部電極端子部とを電気的導通を図って樹脂
封止された半導体装置において、封止樹脂のコーナ外表
面部に前記外部電極端子をL字状に露出形成させた構成
の半導体装置を得るためのもので、第1および第2実施
形態の製造方法を利用し、特に厚み方向の切断個所を選
択することにより実装上の効果が高い形態の半導体装置
を得ることができる。
Next, FIGS. 22 to 23 show the method of manufacturing a semiconductor device according to the third embodiment and the appearance of the semiconductor device obtained by the method. In this embodiment, in the semiconductor device in which the electrodes of the semiconductor chip and the external electrode terminal portions are electrically sealed with each other by resin sealing, the external electrode terminals are exposed in an L shape on the outer surface portion of the corner of the sealing resin. In order to obtain a semiconductor device having a formed structure, the manufacturing method of the first and second embodiments is used, and in particular, a semiconductor device having a high mounting effect is obtained by selecting a cutting point in the thickness direction. Obtainable.
【0051】この第3実施形態に係る半導体装置の製造
方法を図22を参照して説明する。これは複数の半導体
装置を複数同時に製造するためのもので、複数の装置構
成要素を形成できるような平面積を有する銅板製導電性
板60を準備する。この導電性板60には装置構成要素
単位ごとに半導体チップ搭載領域Cの周囲に配置される
外部電極端子形成領域Tのみをランド部として残し、図
22(2)に示しているように、その周囲にエッチング
除去された薄肉部61を形成し、この薄肉部61は非エ
ッチング面側の研削により前記外部電極端子形成領域T
の相互間を分離可能な深さに設定し、ランド部は隣接す
る装置構成要素の外部電極端子形成部と共用するように
している。
A method of manufacturing the semiconductor device according to the third embodiment will be described with reference to FIG. This is for simultaneously manufacturing a plurality of semiconductor devices, and a copper plate conductive plate 60 having a flat area capable of forming a plurality of device components is prepared. In this conductive plate 60, only the external electrode terminal formation region T arranged around the semiconductor chip mounting region C is left as a land portion for each device component unit, and as shown in FIG. A thin portion 61 that has been removed by etching is formed on the periphery, and the thin portion 61 is ground on the non-etched surface side to form the external electrode terminal forming region T.
Is set to a separable depth, and the land portion is shared with the external electrode terminal forming portion of the adjacent device component.
【0052】この導電性板60では、半導体チップ61
0を搭載する部分を薄肉部61とし、外部電極端子形成
部631で囲まれるダイ付け部62の位置に半導体チッ
プを搭載する。また、ダイ付け部62は、薄肉部61の
表面の一部である。厚肉部突起箇所である外部電極端子
形成部631は、半導体チップの入出力部から導電性ワ
イヤ630などで接続される部分となる。外部電極端子
形成部631は、独立した突起になるように薄肉部61
より厚くしてあるとともに、隣接する装置構成要素と共
用するようにしているため、幅寸法は隣接するチップか
らのくるボンディングワイヤ630をそれぞれ溶着でき
るスペースを確保できるように設定する。また、ダイ付
け部62、外部電極形成部631の一部あるいは全部の
上面には、ボンディングの際の接合性の向上の為に、図
22(3)に示しているように、導電性めっきを施す場
合がある。
In this conductive plate 60, the semiconductor chip 61
The thin-walled portion 61 is the portion on which 0 is mounted, and the semiconductor chip is mounted on the position of the die attachment portion 62 surrounded by the external electrode terminal formation portion 631. The die attaching portion 62 is a part of the surface of the thin portion 61. The external electrode terminal forming portion 631 which is the thick portion protruding portion is a portion connected to the input / output portion of the semiconductor chip by the conductive wire 630 or the like. The external electrode terminal forming portion 631 is formed on the thin portion 61 so as to form an independent protrusion.
Since it is made thicker and is shared with the adjacent device components, the width dimension is set so as to secure a space for welding the bonding wires 630 coming from the adjacent chips, respectively. Further, as shown in FIG. 22 (3), conductive plating is applied to the upper surfaces of part or all of the die attaching portion 62 and the external electrode forming portion 631 in order to improve the bondability during bonding. May be given.
【0053】次に図22(4)の断面図に示すように、
導電性板60のダイ付け部62の上に半導体チップ61
0を接着剤620などを用いて搭載し、半導体チップ6
10の入出力パッドと導電性板60の外部電極形成部6
31の上部平坦部を導電性ワイヤ630を用い接続する
(図22(5)参照)。
Next, as shown in the sectional view of FIG.
The semiconductor chip 61 is placed on the die attaching portion 62 of the conductive plate 60.
0 is mounted using an adhesive 620 or the like, and the semiconductor chip 6
10 input / output pads and the external electrode forming portion 6 of the conductive plate 60
The upper flat portion of 31 is connected using a conductive wire 630 (see FIG. 22 (5)).
【0054】その後、図22(6)に示すように導電性
板60の上の突起が存在する面、すなわち半導体チップ
610の搭載面のダイ付け部62、外部電極形成部63
1、半導体チップ610、導電性ワイヤ630の全てを
覆うように、樹脂640にて封止する。封止したのち、
導電性板60を薄肉部61側、すなわち樹脂封止されて
いない面すなわち非エッチング面側から、導電性板60
が露出している面より研削(あるいはカッティング)す
る。その際の研削は、薄肉部61が完全になくなるまで
行う。すなわち、外部電極端子63が電気的に完全に独
立する研削面650に示す位置まで研削する。この場
合、半導体チップ610の底面は、外部電極形成部63
の上面より下方の位置にある為に、研削面650まで研
削する際には、半導体チップ610の下面の一部は研削
されることになる(図22(7)参照)。
After that, as shown in FIG. 22 (6), the die-attached portion 62 and the external electrode forming portion 63 on the surface of the conductive plate 60 on which the protrusions are present, that is, the mounting surface of the semiconductor chip 610.
1, the semiconductor chip 610, and the conductive wire 630 are all sealed with resin 640. After sealing
From the thin portion 61 side, that is, the surface not resin-sealed, that is, the non-etched surface side, the conductive plate 60 is placed on the conductive plate 60.
Grind (or cut) from the exposed surface. Grinding at that time is performed until the thin portion 61 is completely removed. That is, the external electrode terminal 63 is ground to a position indicated by a ground surface 650 that is completely electrically independent. In this case, the bottom surface of the semiconductor chip 610 has the external electrode forming portion 63.
Since it is located below the upper surface of the semiconductor chip, part of the lower surface of the semiconductor chip 610 is ground when the ground surface 650 is ground (see FIG. 22 (7)).
【0055】ところで、図22(7)から明らかなよう
に、この実施例では複数の装置要素単位が同時に形成さ
れるため、これらを分離するための厚み方向の分断位置
を外部電極端子形成部631を中央から分断するように
分断線660が設定されている。これにより、各半導体
装置600のコーナ部分に図23に示すようなL字形状
の外部電極端子63が形成される。図示のように、実施
形態では、L字形外部電極端子63は、エッチング深さ
にもよるが、直方体のパッケージにおける長辺に沿った
側端面側で長く、パッケージ裏面に露出した面が短くな
るように設定されている。
By the way, as is apparent from FIG. 22 (7), since a plurality of device element units are formed at the same time in this embodiment, the dividing position in the thickness direction for separating these is formed as the external electrode terminal forming portion 631. A dividing line 660 is set so as to divide from the center. As a result, L-shaped external electrode terminals 63 as shown in FIG. 23 are formed at the corners of each semiconductor device 600. As shown in the figure, in the embodiment, the L-shaped external electrode terminal 63 is long on the side end surface side along the long side of the rectangular parallelepiped package, and the surface exposed on the back surface of the package is short, depending on the etching depth. Is set to.
【0056】図24に第4実施形態を示す。これは外部
電極端子形成部731を片側だけに片寄せて配置し、こ
れにワイヤボンディングして樹脂封止させ、厚み方向に
沿って装置単位間を分離する分断線を外部電極端子形成
部731を分割するような位置に設定したものである。
もちろん導電板の薄肉部を除去する工程が含まれる。こ
の実施形態はワイヤボンディングを半導体チップ710
の片側に配置されている電極形成部731のみを対象と
している点が第3実施形態と異なる。したがって、製造
された半導体装置700は図25に示すように、パッケ
ージの片側側縁にのみ外部電極端子73が配置形成され
る。このようにして製造された半導体装置700は、図
26に示すように、パッケージを立設して基板実装する
ことができ、基板への実装面積を小さくすることができ
る利点がある。また、図23に示したパッケージも同様
であるが、図26に示しているようにコーナL型電極は
ハンダ溶着した場合の溶着面積が大きいため、フィレッ
トが確実に形成されて安定した実装を行なえる。
FIG. 24 shows a fourth embodiment. This is achieved by arranging the external electrode terminal forming portion 731 on one side only and wire-bonding the resin to the external electrode terminal forming portion 731 to form a dividing line for separating the device units along the thickness direction from the external electrode terminal forming portion 731. It is set at a position where it is divided.
Of course, the step of removing the thin portion of the conductive plate is included. In this embodiment, wire bonding is performed on the semiconductor chip 710.
The third embodiment is different from the third embodiment in that only the electrode forming portion 731 arranged on one side of the above is targeted. Therefore, in the manufactured semiconductor device 700, as shown in FIG. 25, the external electrode terminals 73 are arranged and formed only on one side edge of the package. As shown in FIG. 26, the semiconductor device 700 manufactured in this manner has an advantage that the package can be erected and mounted on the substrate, and the mounting area on the substrate can be reduced. In addition, the package shown in FIG. 23 is similar, but as shown in FIG. 26, since the corner L-shaped electrode has a large welding area when soldered, the fillet is reliably formed and stable mounting can be performed. It
【0057】[0057]
【発明の効果】以上説明したように、本発明は、予め銅
板などからなる導電板に、少なくとも外部電極端子形成
部に相当する部分(あるいは半導体チップ搭載領域)を
残してその他をエッチングし、薄肉部を形成すると共
に、残されたランドを利用してチップ搭載や電極端子形
成部とチップとのボンディング処理と樹脂封止などを行
ない、その後に前記導電板の薄肉部を完全に除去して外
部電極端子をチップ搭載部と分離配置するようにしたの
で、この種の半導体装置のパッケージサイズを大幅に小
さく、薄型化することができ、小型で薄型の半導体装置
を簡便な方法と設備により製造することができる。
As described above, according to the present invention, a conductive plate made of a copper plate or the like is previously thinned by etching at least a portion corresponding to an external electrode terminal forming portion (or a semiconductor chip mounting region) and etching the rest. Part is formed and the remaining land is used to mount the chip, perform bonding processing between the electrode terminal forming part and the chip, and seal the resin, and then completely remove the thin part of the conductive plate to externally Since the electrode terminals are arranged separately from the chip mounting portion, the package size of this type of semiconductor device can be made significantly smaller and thinner, and a small and thin semiconductor device is manufactured by a simple method and equipment. be able to.
【図面の簡単な説明】[Brief description of drawings]
【図1】 半導体装置の第1実施形態の断面図である。FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor device.
【図2】 図1の底面図である。FIG. 2 is a bottom view of FIG.
【図3】 第1の実施形態に係る半導体装置製造方法を
示すフローチャートである。
FIG. 3 is a flowchart showing a semiconductor device manufacturing method according to the first embodiment.
【図4】 半導体装置用導電性板の第1実施形態の断面
図である。
FIG. 4 is a cross-sectional view of a first embodiment of a conductive plate for a semiconductor device.
【図5】 図4の平面図である。FIG. 5 is a plan view of FIG.
【図6】 第1実施形態に係る半導体装置製造方法にお
けるワイヤボンディング工程後の半導体装置の断面図で
ある。
FIG. 6 is a cross-sectional view of the semiconductor device after the wire bonding step in the semiconductor device manufacturing method according to the first embodiment.
【図7】 図6の同平面図である。7 is a plan view of FIG.
【図8】 第1実施形態に係る半導体装置製造方法にお
ける樹脂封止工程後の半導体装置の断面図である。
FIG. 8 is a sectional view of the semiconductor device after a resin sealing step in the semiconductor device manufacturing method according to the first embodiment.
【図9】 半導体装置の第2実施形態の断面図である。FIG. 9 is a sectional view of a second embodiment of a semiconductor device.
【図10】 図9の底面図である。FIG. 10 is a bottom view of FIG.
【図11】 第2の実施形態に係る半導体装置製造方法
を示すフローチャートである。
FIG. 11 is a flowchart showing a semiconductor device manufacturing method according to the second embodiment.
【図12】 半導体装置用導電性板の第2実施形態の断
面図である。
FIG. 12 is a cross-sectional view of a second embodiment of a conductive plate for a semiconductor device.
【図13】 図12の平面図である。FIG. 13 is a plan view of FIG.
【図14】 第2実施形態に係る半導体装置製造方法に
おけるワイヤボンディング工程後の半導体装置の断面図
である。
FIG. 14 is a cross-sectional view of the semiconductor device after a wire bonding step in the semiconductor device manufacturing method according to the second embodiment.
【図15】 図14の平面図である。FIG. 15 is a plan view of FIG.
【図16】 第2実施形態に係る半導体装置製造方法に
おける樹脂封止工程後の半導体装置の断面図である。
FIG. 16 is a cross-sectional view of the semiconductor device after a resin sealing step in the semiconductor device manufacturing method according to the second embodiment.
【図17】 半導体装置用導電性板の他の実施形態を示
す平面図である。
FIG. 17 is a plan view showing another embodiment of the conductive plate for a semiconductor device.
【図18】 外部電極端子を複数列設けた場合の変形実
施形態の平面説明図である。
FIG. 18 is an explanatory plan view of a modified embodiment in which a plurality of external electrode terminals are provided.
【図19】 図17の断面図である。19 is a cross-sectional view of FIG.
【図20】 外部電極端子を千鳥配置した例と、チップ
全辺に亙って配列した例の平面説明図である。
FIG. 20 is an explanatory plan view of an example in which external electrode terminals are arranged in a staggered manner and an example in which they are arranged over the entire side of the chip.
【図21】 ハンダボールを外部電極端子に形成した例
の半導体装置の断面図である。
FIG. 21 is a cross-sectional view of a semiconductor device in which a solder ball is formed on an external electrode terminal.
【図22】 第3の実施形態に係る半導体装置製造方法
を示すフローチャートである。
FIG. 22 is a flowchart showing a semiconductor device manufacturing method according to the third embodiment.
【図23】 第3の実施形態に係る半導体装置製造方法
により製造された半導体装置の平面斜視図と底面斜視図
である。
FIG. 23 is a plan perspective view and a bottom perspective view of a semiconductor device manufactured by a semiconductor device manufacturing method according to a third embodiment.
【図24】 第4の実施形態に係る半導体製造方法の要
部を示す工程の断面図である。
FIG. 24 is a sectional view of a step showing a main part of the semiconductor manufacturing method according to the fourth embodiment.
【図25】 第4の実施形態に係る半導体製造方法によ
り製造された半導体装置の平面斜視図と底面斜視図であ
る。
FIG. 25 is a plan perspective view and a bottom perspective view of a semiconductor device manufactured by a semiconductor manufacturing method according to a fourth embodiment.
【図26】 同半導体装置の実装形態の説明図である。FIG. 26 is an explanatory diagram of a mounting form of the semiconductor device.
【図27】 従来の半導体装置の断面図である。FIG. 27 is a cross-sectional view of a conventional semiconductor device.
【符号の説明】[Explanation of symbols]
10 導電性板 11 薄肉部 12 ダイ付け突起部 13 外部電極部 100 半導体装置 110 半導体チップ 120 接着剤 121 ダイ付け突起形成部 130 導電性ワイヤ 131 外部電極形成部 150 封止樹脂 160 研削面 20 導電性板 21 薄肉部 22 ダイ付け部 231 外部電極形成部 200 半導体装置 210 半導体チップ 220 接着剤 230 導電性ワイヤ 240 封止樹脂 250 研削面 30 導電性板 311 半導体チップ搭載部 321 外部電極形成部 35 切断線 41 ダイ付け部 42 外部電極端子 44 ハンダボール 50 リードフレーム 500 半導体装置 510 半導体チップ 520 接着剤 530 導電性ワイヤ 540 樹脂 60 導伝版 61 薄肉部 63 外部電極端子部 600 半導体装置 610 半導体チップ 620 接着剤 630 導電性ワイヤ 631 外部電極端子形成部 640 樹脂 650 研削面 660 分断線 10 Conductive plate 11 Thin part 12 Die attaching protrusion 13 External electrode part 100 semiconductor devices 110 semiconductor chips 120 adhesive 121 Die Attaching Protrusion Forming Part 130 conductive wire 131 External Electrode Forming Section 150 sealing resin 160 grinding surface 20 Conductive plate 21 Thin part 22 Die attaching part 231 External electrode forming part 200 Semiconductor device 210 semiconductor chips 220 adhesive 230 conductive wire 240 sealing resin 250 ground surface 30 conductive plate 311 Semiconductor chip mounting part 321 External electrode forming part 35 cutting line 41 Die attaching part 42 External electrode terminal 44 solder balls 50 lead frame 500 semiconductor device 510 semiconductor chips 520 adhesive 530 conductive wire 540 resin 60 version 61 Thin part 63 External electrode terminal 600 semiconductor device 610 semiconductor chip 620 adhesive 630 conductive wire 631 external electrode terminal forming part 640 resin 650 grinding surface 660 breaking line
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平9−252014(JP,A) 特開 平9−82741(JP,A) 特開 平3−94431(JP,A) 特開 平9−8206(JP,A) 特開 平3−99456(JP,A) 特開 平3−94459(JP,A) 特開20001−217372(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 23/28 H01L 21/56 H01L 21/60 301 H01L 21/50 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-9-252014 (JP, A) JP-A-9-82741 (JP, A) JP-A-3-94431 (JP, A) JP-A-9- 8206 (JP, A) JP 3-99456 (JP, A) JP 3-94459 (JP, A) JP 20001-217372 (JP, A) (58) Fields investigated (Int. Cl. 7) , DB name) H01L 23/28 H01L 21/56 H01L 21/60 301 H01L 21/50

Claims (7)

    (57)【特許請求の範囲】(57) [Claims]
  1. 【請求項1】 導電性板の片面にて半導体チップ搭載領
    域と当該チップ搭載領域の周囲に配置される外部電極端
    子形成領域とを残してその周囲に薄肉部を形成するエッ
    チング工程と、 前記半導体チップ搭載領域上に半導体チップを搭載する
    工程と、 前記半導体チップと前記外部電極端子形成領域とを電気
    的に導通させるボンディング工程と、 前記導電性板の半導体チップ搭載面側にて半導体チップ
    および外部電極端子を内包する樹脂封止工程と、 前記樹脂封止工程の後に前記導電性板の非エッチング面
    側から当該導電性板の薄肉部相当厚さ分を越えて前記導
    電性板を研削除去する工程を備えることを特徴とする半
    導体装置の製造方法。
    1. An etching step of forming a thin portion around a semiconductor chip mounting region and an external electrode terminal forming region arranged around the chip mounting region on one surface of a conductive plate, the semiconductor step comprising: A step of mounting a semiconductor chip on a chip mounting area; a bonding step of electrically conducting the semiconductor chip and the external electrode terminal forming area; and a semiconductor chip and an external part on the semiconductor chip mounting surface side of the conductive plate. A resin encapsulation step of encapsulating the electrode terminals, and after the resin encapsulation step, the conductive plate is ground and removed from the non-etched surface side of the conductive plate over a thin portion equivalent thickness of the conductive plate. A method of manufacturing a semiconductor device, comprising the steps of:
  2. 【請求項2】 導電性板の片面にて半導体チップ搭載領
    域の周囲に配置される外部電極端子形成領域を残してそ
    の周囲に薄肉部を形成するエッチング工程と、 前記薄肉部としての半導体チップ搭載領域上に半導体チ
    ップを搭載する工程と、 前記半導体チップと前記外部電極端子形成領域とを電気
    的に導通させるボンディング工程と、 前記導電性板の半導体チップ搭載面側にて半導体チップ
    および外部電極端子を内包する樹脂封止工程と、 前記樹脂封止工程の後に前記導電性板の非エッチング面
    側から当該導電性板の薄肉部相当厚さ分を越えて前記導
    電性板を研削除去する工程を備えることを特徴とする半
    導体装置の製造方法。
    2. An etching step of forming a thin portion around an external electrode terminal forming region which is arranged around the semiconductor chip mounting region on one surface of a conductive plate, and a semiconductor chip mounting as the thin portion. A step of mounting a semiconductor chip on the area, a step of electrically connecting the semiconductor chip and the external electrode terminal forming area, and a semiconductor chip and an external electrode terminal on the semiconductor chip mounting surface side of the conductive plate. A step of encapsulating the resin, and a step of grinding and removing the conductive plate after the resin sealing step from the non-etched surface side of the conductive plate over the thin portion equivalent thickness of the conductive plate. A method of manufacturing a semiconductor device, comprising:
  3. 【請求項3】 請求項1または2に記載の半導体装置の
    製造方法において、1枚の導電性板に複数の半導体装
    置構成要素の領域を設定し、この複数の領域の半導体装
    置構成要素に対して前記各工程を行なった後に、各半導
    体装置構成要素単位に分断処理する工程を含むことを特
    徴とする半導体装置の製造方法。
    3. The method of manufacturing a semiconductor device according to claim 1, wherein regions of a plurality of semiconductor device constituent elements are set on one conductive plate , and the semiconductor device constituent elements of the plurality of regions are set. On the other hand, a method of manufacturing a semiconductor device, including a step of dividing each semiconductor device constituent element unit after performing each of the above steps.
  4. 【請求項4】 請求項1乃至請求項3のいずれかに記載
    の半導体装置の製造方法であって、 前記薄肉部を形成するエッチング工程は等方性のエッチ
    ングにより行なうことを特徴とする半導体装置の製造方
    法。
    4. The method of manufacturing a semiconductor device according to claim 1, wherein the etching step for forming the thin portion is performed by isotropic etching. Manufacturing method.
  5. 【請求項5】 請求項1乃至請求項3のいずれかに記載
    の半導体装置の製造方法であって、 外部電極端子形成領域における前記ボンディング工程に
    て使われた領域を除く領域にて厚み方向に切断する工程
    を含むことを特徴とする半導体装置の製造方法。
    5. The method of manufacturing a semiconductor device according to claim 1, wherein a region other than a region used in the bonding step in the external electrode terminal formation region is formed in a thickness direction. A method of manufacturing a semiconductor device, comprising a step of cutting.
  6. 【請求項6】 請求項1乃至請求項3のいずれかに記載
    の半導体装置の製造方法であって、 前記研削除去する工程の後に前記外部電極端子として用
    いられる部位の露出面に対して導電性メッキを施す工程
    を有してなることを特徴とする半導体装置の製造方法。
    6. The method for manufacturing a semiconductor device according to claim 1, wherein the exposed surface of a portion used as the external electrode terminal is conductive after the step of grinding and removing. A method of manufacturing a semiconductor device, comprising a step of plating.
  7. 【請求項7】 請求項3に記載の半導体装置の製造方法
    において、 前記各半導体装置構成要素単位に分断処理する工程で
    は、前記外部電極端子よりも外側にて半導体装置構成要
    素単位に前記導電性板の厚み方向に分断することを特徴
    とする半導体装置の製造方法。
    7. The method of manufacturing a semiconductor device according to claim 3, wherein, in the step of dividing each semiconductor device constituent element into units, the conductive material is added to the semiconductor device constituent unit outside the external electrode terminal. A method of manufacturing a semiconductor device, characterized by dividing the plate in a thickness direction.
JP26212498A 1997-10-28 1998-09-16 Method for manufacturing semiconductor device Expired - Fee Related JP3521758B2 (en)

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JP29548597 1997-10-28
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