JP3521758B2 - A method of manufacturing a semiconductor device - Google Patents

A method of manufacturing a semiconductor device

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Publication number
JP3521758B2
JP3521758B2 JP26212498A JP26212498A JP3521758B2 JP 3521758 B2 JP3521758 B2 JP 3521758B2 JP 26212498 A JP26212498 A JP 26212498A JP 26212498 A JP26212498 A JP 26212498A JP 3521758 B2 JP3521758 B2 JP 3521758B2
Authority
JP
Japan
Prior art keywords
semiconductor device
external electrode
semiconductor chip
conductive plate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26212498A
Other languages
Japanese (ja)
Other versions
JPH11195733A (en
Inventor
敏紀 中山
Original Assignee
セイコーエプソン株式会社
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Publication date
Priority to JP9-295485 priority Critical
Priority to JP29548597 priority
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP26212498A priority patent/JP3521758B2/en
Publication of JPH11195733A publication Critical patent/JPH11195733A/en
Application granted granted Critical
Publication of JP3521758B2 publication Critical patent/JP3521758B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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Abstract

PROBLEM TO BE SOLVED: To provide a small-sized and thin semiconductor device that can be produced using simple equipment and does not require capital equipment such as a mold and a drive device for conventional transfer mold techniques or a mold and a driving device for bending lead frames. SOLUTION: A conductive plate is etched and part, except at least external electrode terminals, is made thin. After a chip is mounted and resin-sealed, the thin part of the conductive plate is completely removed by grinding it. A semiconductor device 100 has a semiconductor chip 110 inside and is sealed with a resin 150. A die mounting projected part 12 and external electrode terminals 13 are exposed at the lower part. The semiconductor chip 110 is mounted on the die mounting projected part 12 using an adhesive 120. The I/O terminals of the semiconductor chip 110 are connected to external electrode terminals 13 using conductive wires 130. The external electrode terminals 13 are exposed at the lower part of the semiconductor device 100. Consequently, a small-size semiconductor device with I/O terminals that are not projected from the resin can be manufactured.

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、半導体チップを搭載し、樹脂封止して形成される半導体装置の製造方法、 BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention is equipped with the semiconductor chip, a manufacturing method of a semiconductor device formed by resin sealing,
この方法に用いる半導体装置用導電性板、および半導体装置に関する。 Semiconductor device conductive plate used in this method, and a semiconductor device. 【0002】 【従来の技術】従来の半導体装置の一例として、図27 [0002] As an example of a conventional semiconductor device, FIG. 27
に示す構造がある。 There is a structure shown in. この技術は、半導体装置用導電性板(以下、リードフレームとする。)50上に半導体チップ510を接着剤520を用いて設置し、導電性ワイヤ530を用いて半導体チップ510をリードフレーム5 This technique for semiconductor device the conductive plate (hereinafter referred to as the lead frame.) 50 of the semiconductor chip 510 is placed using an adhesive 520 onto the lead frame 5 of the semiconductor chip 510 by using a conductive wire 530
0を接続する。 To connect the 0. 次いで、チップ周囲をトランスファーモールドと呼ばれる技術を使い樹脂540で封止し、樹脂540の側端面より突出したリードフレーム50部分をクランク状に折り曲げることにより半導体装置500を製造する。 Then, sealed with a resin 540 using a technique called chip periphery and transfer molding, to produce the semiconductor device 500 by bending the lead frame 50 portion projecting from the side end surface of the resin 540 in a crank shape. 【0003】 【発明が解決しようとする課題】しかしながら、このような半導体装置は、以下のような課題を有する。 [0003] The present invention is, however, such a semiconductor device has the following problems. 【0004】すなわち、トランスファーモールド技術を用いるために、モールド用の金型やその駆動装置、また、リードフレームを曲げるための金型とその駆動装置が必要であり、非常に大きな設備投資を必要としている。 [0004] That is, in order to use the transfer molding technique, a mold and a driving apparatus thereof for molding, also requires a mold and a driving device for bending the lead frame, it requires a very large capital investments there. また、リードフレーム50を半導体装置毎に折り曲げるために、工数が多くかかり、半導体装置が高価になる。 Further, in order to bend the lead frame 50 for each semiconductor device, it takes a lot steps, the semiconductor device becomes expensive. また、リードフレーム50が樹脂540より突出していることにより、半導体装置が大きくなり、実装した場合に大きな面積を基板上で必要とし、製品としての小型化が困難である。 Further, by the lead frame 50 is protruded from the resin 540, the semiconductor device is increased, a large area when implemented needed on the substrate, it is difficult to reduce the size of the product. 【0005】本発明は、このような従来技術の課題を解決するものであり、その目的とするところは、従来に比して大幅に小型、薄型にすることができるようにした半導体装置の製造方法と、これにより製造された小型、薄型の半導体装置、並びにこの半導体装置を製造するのに利用される導電性板を提供するところにある。 [0005] The present invention is intended to solve the problems of the conventional art, and an object, much smaller than the conventional manufacturing a semiconductor apparatus which can be made thin methods and small to thereby manufactured, thin semiconductor device, and is to provide a conductive plate which is used to manufacture the semiconductor device. 【0006】 【課題を解決するための手段】上記目的を達成するために、本発明に係る半導体装置の製造方法は、導電性板の片面にて半導体チップ搭載領域と当該チップ搭載領域の周囲に配置される外部電極端子形成領域とを残してその周囲に薄肉部を形成するエッチング工程と、前記半導体チップ搭載領域上に半導体チップを搭載する工程と、前記半導体チップと前記外部電極端子形成領域とを電気的に導通させるボンディング工程と、前記導電性板の半導体チップ搭載面側にて半導体チップおよび外部電極端子を内包する樹脂封止工程と、 前記樹脂封止工程の後に前<br>記導電性板の非エッチング面側から当該導電性板の薄肉部相当厚さ分を越えて前記導電性板を研削除去する工程 [0006] To achieve the above object, according to an aspect of manufacturing method of a semiconductor device according to the present invention, at one side of the conductive plate around the semiconductor chip mounting area and the chip mounting area an etching step of forming a thin portion in the periphery, leaving the external electrode terminal formation regions arranged, mounting a semiconductor chip on the semiconductor chip mounting region, and the semiconductor chip and the external electrode terminal formed region a bonding process for electrically conducting and a resin sealing step of encapsulating the semiconductor chip and the external electrode terminals in the semiconductor chip mounting surface side of the conductive plate, before <br> Kishirubeden after the resin sealing step a step of grinding removing said conductive plate from the non-etched surface side of the sexual plate beyond the thin portion corresponding the thickness of the said conductive plates
を備えることを特徴とする。 Characterized in that it comprises a. 【0007】このような方法をとることで、厚肉部となる半導体チップ搭載領域と当該チップ搭載領域の周囲に配置される外部電極端子形成領域を残し、これらの周辺領域をハーフエッチングにより薄肉部として形成した導電性板を用いる。 [0007] By employing such a method, leaving the external electrode terminal formation region disposed around the semiconductor chip mounting area and the chip mounting region to be a thick portion, the thin portion by half-etching these peripheral regions a conductive plate which is formed as employed. この導電性板のチップ搭載領域としての厚肉部表面に半導体チップが搭載され、その導電性板厚肉部突起箇所の周辺に配置された外部電極端子形成領域の表面と半導体チップのパッド(例えば入出力用)とを導電性ワイヤなどにより接続する。 This thick portion surface of the chip mounting area of ​​the conductive plate semiconductor chips are mounted, the conductive plate thick portion surface and the semiconductor chip pad of the external electrode terminal formed region disposed around the projection portion (e.g. etc. by connecting a conductive wire to the input-output) and. ワイヤボンディングである。 A wire bonding. 導電性板の半導体チップ搭載面側にて半導体チップおよび外部電極端子、並びに導電性ワイヤなどを内包する樹脂等により封止し、その後、樹脂封止されていない面から前記導電性板薄肉部を例えば研削等により除去するのである。 The semiconductor chip and the external electrode terminals in the semiconductor chip mounting surface side of the conductive plate, and sealed by resin or the like containing the a conductive wire, after which the surface not sealed with resin the conductive plate thin portion for example it is to remove by grinding or the like. その結果、研削面側は、導電性板の外部電極端子の裏面が各々独立して露出するので、その箇所を入出力端子とした半導体装置を得ることができ、 As a result, the grinding surface side, since the back surface of the external electrode terminal conductive plate is exposed each independently, it is possible to obtain a semiconductor device in which the position input and output terminals,
小型で薄型の半導体装置を簡便な設備により提供することができる。 Compact and can be provided by a simple equipment a thin semiconductor device. また、請求項1記載の半導体装置の製造方法によれば、樹脂側端面より突出した入出力端子がない半導体装置を製造することが可能である。 According to the manufacturing method of a semiconductor device according to claim 1, wherein it is possible to manufacture the semiconductor device without input and output terminals projecting from the resin-side end face. 【0008】また、第2の構成に係る半導体装置の製造方法は、導電性板の片面にて半導体チップ搭載領域の周囲に配置される外部電極端子形成領域を残してその周囲に薄肉部を形成するエッチング工程と、前記薄肉部としての半導体チップ搭載領域上に半導体チップを搭載する工程と、前記半導体チップと前記外部電極端子形成領域とを電気的に導通させるボンディング工程と、前記導電性板の半導体チップ搭載面側にて半導体チップおよび外部電極端子を内包する樹脂封止工程と、 前記樹脂封止工 Further, a method of manufacturing a semiconductor device according to a second configuration, forming a thin portion in the periphery, leaving the external electrode terminal formation region disposed around the semiconductor chip mounting area at one side of the conductive plate an etching step of a step of mounting a semiconductor chip on a semiconductor chip mounting region as the thin portion, and a bonding process for electrically connecting and said and said semiconductor chip external electrode terminal formation region, the conductive plate a resin sealing step of encapsulating the semiconductor chip and the external electrode terminals in the semiconductor chip mounting surface side, the resin Futomeko
程の後に前記導電性板の非エッチング面側から当該導電性板の薄肉部相当厚さ分を越えて前記導電性板を研削除去する工程を備えることを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device characterized by after the extent provided with the conductive plate of the non from the etching side beyond the thin portion corresponding the thickness of the said conductive plate to ground and removed the conductive plate process. 【0009】このような構成では、導電性板をエッチングするのは外部電極端子形成領域を除く表面であり、エッチングによって形成された外部電極端子形成領域の間にチップ搭載領域が薄肉に形成される。 [0009] In such a configuration, to etch conductive plate is a surface except for the external electrode terminal formation region, a chip mounting area is formed thin between the external electrode terminal formation region formed by etching . チップをこの領域に接着設置することで、外部電極端子形成領域の頂面と半導体チップの表面がほぼ同一となり、ワイヤボンディング後に樹脂封止し、更に導電性板の外部露出面側である非エッチング面側から導電性板の薄肉部相当厚さ以上、特に半導体チップのシリコン基板厚さ部分を薄くする程度まで切削あるいは研削によって取り除く。 Chips by bonding installed in this area, becomes the top surface of the semiconductor chip surface of the external electrode terminal formation regions approximately the same, resin-sealed after the wire bonding, non-etching is more external exposed surface side of the conductive plate side conductive plate thin portion corresponding thickness or from, in particular removed by cutting or grinding to the extent of thinning the silicon substrate thickness of the semiconductor chip. これにより、薄形半導体装置を製造することができる。 Thus, it is possible to manufacture a thin semiconductor device. すなわち、半導体チップの搭載領域部分の厚み分を更に除くことができるので、より薄形の半導体装置を得ることができるのである。 That is, it is possible to further excluding the thickness of the mounting region of the semiconductor chip, it is possible to obtain a semiconductor device of more thin. 特に樹脂より突出した入出力端子がない小型半導体装置を製造することが可能であるとともに、 Especially with it is possible to manufacture a small-sized semiconductor device is no input and output terminals projecting from the resin,
請求項1記載の半導体装置よりも同一工程ながら更に小型(薄型)半導体装置を製造することが可能となっている。 Than the semiconductor device according to claim 1, wherein it is possible to further produce a compact (thin) semiconductor device with the same process. 【0010】更に、本発明は、1枚の導電性板状に複数の半導体装置構成要素の領域を設定し、この複数の領域の半導体装置構成要素に対して前記各工程を行なった後に、各半導体装置構成要素単位に分断処理する工程を含む構成とすることもできる。 Furthermore, the present invention sets a region of a plurality of semiconductor devices components on one of the conductive plate, after performing the respective steps to the semiconductor device components of the plurality of regions, each It may be configured to include a step of dividing processed semiconductor device component units. 【0011】また、上記製造方法において、導電性板に薄肉部を形成するエッチングは等方性エッチングとして行なうことが望ましい。 [0011] In the above manufacturing method, the etching for forming the thin portion in the conductive plate is preferably performed as isotropic etching. 等方性エッチングであるためエッチング領域は奥に進むほどえぐれた状態となる。 Etching regions for a isotropic etch is in a state of scooped more proceeds to the end. したがって、薄肉部から立設した状態にある非エッチング領域は、表面側に至るにしたがって迫り出し、オーバハング状態となる。 Therefore, the non-etched region in which a standing from thin portion, protruding accordance reach the surface, the overhang state. このため後工程で樹脂封止が行われるが、樹脂内への埋め込み側の相当直径が大きくなり、これがアンカとして作用するために薄肉部を研削除去して島として残されても樹脂から抜け出ることが防止される。 Although resin sealing is performed in a later step for the equivalent diameter of the embedded side into the resin is increased, it is possible to escape from the resin be left a thin portion as the island was ground and removed in order to act as an anchor There is prevented. 【0012】他の半導体装置の製造方法として、上述した半導体装置の製造方法であって、外部電極端子形成領域における前記ボンディング工程にて使われた領域を除く領域にて厚み方向に切断する封止樹脂工程を含むことができる。 [0012] As another method of manufacturing a semiconductor device, a manufacturing method of the semiconductor device described above, the sealing of cutting in the thickness direction in the region except for the region were used in the bonding step in the external electrode terminal formation region it can include resins step. 【0013】このような構成とすることにより、外観が直方体形状となっている半導体装置のコーナ縁辺部分の直交2面に跨ってL字状の直角面外部電極端子が形成される。 [0013] With such a configuration, the appearance is perpendicular surface external electrode terminals of the L-shaped across the orthogonal dihedral corner edge portion of the semiconductor device has a rectangular parallelepiped shape is formed. これにより基板へのハンダ実装に際してハンダフィレットが大きく形成され、実装固定が強化される。 Thus solder fillet when solder mounting to the substrate is larger, mounted fixed are reinforced. また、半導体装置を基板に平面的に実装せずに立設させた状態での実装が可能となる。 Further, the semiconductor device becomes possible implementation in a state of being erected without planarly mounted on a substrate. 基板に対する実装面積が小さくなるので、効率的な実装密度が得られる。 Since the mounting area for the substrate is small, efficient packing density is obtained. 【0014】また、前述した半導体装置の製造方法であって、前記研削除去する工程では導電性板の薄肉部相当厚さを超えて半導体チップ裏面側を一部研削することができる。 [0014] A method of manufacturing a semiconductor device described above, wherein the step of grinding removal can be partially grinding the semiconductor chip back side beyond the thin portion corresponding the thickness of the conductive plate. 【0015】このようにすることで、上記方法に比べて、更に薄型の半導体装置が提供できる。 [0015] By doing so, compared to the method described above further offer the thin semiconductor device. しかも除去するのは半導体チップの回路が形成されていない裏面側なので、回路自体に影響を与えることがない。 Moreover, since the removal is a rear surface side of the circuit of the semiconductor chip is not formed, it does not affect the circuit itself. 【0016】また、前記半導体装置の製造方法であって、前記導電性板の薄肉部を除去する工程の後に前記外部端子として用いられる部位の露出面に対して導電性メッキを施す工程を更に有してなることを特徴とする。 Further, a manufacturing method of the semiconductor device, further have a step of applying conductive plating to the exposed surface of the site used as the external terminals after the step of removing the thin portion of the conductive plate characterized in that by comprising. 【0017】このようにすることで、露出面の保護(例えば、露出面の酸化を防止すること)や、半導体装置の実装基板への実装時のはんだのぬれ性を向上させることができる。 [0017] In this way, the protection of the exposed surface (e.g., to prevent oxidation of the exposed surface) and can improve the solder wettability implementation When mounted on a substrate of a semiconductor device. 【0018】また、複数の半導体装置構成要素を同時に製造する方法において、前記半導体装置構成要素に対して前記各工程を行なった後に前記外部電極端子として用いられるランド部よりも外側にて半導体装置構成要素単位に前記導電性板の厚み方向に切断する工程を含む構成とすることができる。 Further, in the method for manufacturing a plurality of semiconductor devices components simultaneously, the semiconductor device structure at the outer side than the land portion used as the external electrode terminal after performing said steps to said semiconductor device components it can be configured to the component unit comprising the step of cutting in the thickness direction of the conductive plate. 【0019】このような構成をとることで、複数の半導体装置が1つの導電性板から製造できることとなり、量産性に優れる方法である。 [0019] By adopting such a configuration, the a plurality of semiconductor devices can be manufactured from one conductive plate, a method excellent in mass productivity. すなわち、複数の半導体装置の構成要素に対し樹脂封止、研削等の工程を1回の作業で行なうことができるので、処理個数が増大し、半導体装置1個あたりの工数が削減される。 That is, the components of the resin encapsulation of a plurality of semiconductor devices, since the process of grinding or the like can be performed in one operation, the processing number is increased, man-hour of the semiconductor device per one is reduced. 【0020】一方、本発明に用いられる半導体装置用導電性板としては、半導体装置構成要素の形成領域内で、 Meanwhile, as the semiconductor device conductive plate used in the present invention, in the formation region of the semiconductor device components,
導電性材料からなる平板の片面に対し、少なくとも半導体チップ搭載領域の周囲に配置される外部電極端子形成領域を残し、その余の領域の表面層をエッチング除去して薄肉部とし、当該薄肉部により前記外部電極端子形成領域相互が架橋されたことを特徴とする。 To one side of a flat plate made of a conductive material, at least leaving the external electrode terminal formation region disposed around the semiconductor chip mounting area, and a thin portion of the surface layer of the remaining area is etched away, by the thin wall portion wherein the external electrode terminal formation regions mutually crosslinked. 【0021】更に、半導体装置構成要素の形成領域内で、導電性材料からなる平板の片面に対し、半導体チップ搭載領域と当該チップ搭載領域の周囲に配置される外部電極端子形成領域とを残し、その余の領域の表面層をエッチング除去して薄肉部とし、当該薄肉部により前記半導体チップ搭載領域と当該チップ搭載領域の周囲に配置される前記外部電極端子形成領域とが架橋されたものを用いる。 Furthermore, in the formation region of the semiconductor device components to one side of a flat plate made of a conductive material, leaving an external electrode terminal formed region disposed around the semiconductor chip mounting area and the chip mounting area, and the thin portion of the surface layer of the remaining area is etched away, using those and the semiconductor chip mounting area and the external electrode terminal formed region disposed around the chip mounting area is bridged by the thin wall portion . アンカ作用で埋め込まれた外部電極端子が封止樹脂から抜け出ることがなくなるのである。 External electrode terminals embedded in the anchor effect is than no longer being withdrawn from the sealing resin. また、封止樹脂に接している面に与えられた曲率面が存在するため、これが抜け止め作用をなす。 Moreover, because of the presence of curved surface given to a surface in contact with the sealing resin, which retaining an action. これらは外部電極端子を形成するために行われる導電性板のエッチング処理を等方性エッチングによって行なうことで実現できる。 These can be realized by performing the isotropic etching an etching process of the conductive plate which is performed to form the external electrode terminal. 【0022】これらの半導体装置用導電性板であって、 [0022] A conductive plate for these semiconductor devices,
前記外部電極端子形成領域及び薄肉部からなる半導体装置構成要素が1枚の平板に複数設けられていることを特徴とするまた、前記半導体装置用導電性板は、銅系材料からなることを特徴とする。 The external electrode terminal forming region and a semiconductor device components made of a thin wall is characterized in that is provided with a plurality in a single flat plate also, the semiconductor device for conducting plate, characterized in that it consists of a copper-based material to. 高放熱性を考慮すると銅系材料を利用することが好ましい。 It is preferable to use a consideration of copper-based material with high heat dissipation. また、半導体チップとの熱膨張率の差を考慮した場合には、鉄−ニッケル系合金を使用してもよい。 Also, when considering the difference in thermal expansion coefficient between the semiconductor chips, iron - may be used nickel-based alloy. 更に、前記薄肉部を形成するエッチング工程は等方性のエッチングにより行なうことが望ましい。 Furthermore, an etching step of forming the thin portion is preferably carried out by isotropic etching. 【0023】本発明に係る半導体装置は、表面に電極を有する半導体チップと、前記半導体チップの周囲にて各々が独立して形成されると共に、前記半導体チップの前記電極と電気的に導通が図られるように接続された外部電極端子と、前記半導体チップの裏面を除く全面並びに前記外部電極端子の前記半導体チップ裏面と同じ側の面を除く全面を覆うように設けられた封止樹脂とを有し、 The semiconductor device according to the present invention includes a semiconductor chip having electrodes on a surface, said with each being formed independently at around the semiconductor chip, said electrode and electrically connected to the semiconductor chip of FIG Yes and the external electrode terminal connected to be, and a sealing resin the provided so as to cover the entire surface except for the semiconductor chip rear surface and the same side of the whole surface and the external electrode terminals except the back surface of the semiconductor chip and,
前記半導体チップの載置部または半導体チップ自体の封止樹脂からの露出面と前記外部電極端子の封止樹脂からの露出面が同一平面上に位置するように設定したことを特徴とする。 Wherein the exposed surface of the sealing resin of the exposed surface and the external electrode terminals from the semiconductor chip mounting portion or the semiconductor chip itself of the sealing resin is set to be positioned on the same plane. なお、この構成において、外部電極端子が半導体チップの周囲に独立して形成されているとあるが、これは半導体チップおよびお互いの外部電極端子同士とが所定の距離を隔てて島状に配置されていることを意味している。 Note that in this configuration, although the external electrode terminals are formed independently around the semiconductor chip, which is an external electrode terminals of the semiconductor chip and each other are arranged in an island shape at a predetermined distance which means that is. 【0024】この構成では、製品形態では外部電極端子は封止樹脂面から突出しておらず、実装高さを小さくすることができる。 [0024] In this configuration, the external electrode terminals in product form does not protrude from the sealing resin surface, it is possible to reduce the mounting height. 【0025】また、上述の各半導体装置において、前記外部電極端子部の前記半導体チップ裏面と同じ側の面に導電性のめっき層が形成されていることを特徴とする。 Further, in the semiconductor device described above, wherein said external electrode terminal of the semiconductor chip rear surface conductivity to the same side as the plating layer of is formed. 【0026】このようにすることで、外部端子部の露出面の保護がなされることになる。 [0026] In this way, so that the protection of the exposed surface of the external terminal portion is performed. 【0027】また、前記半導体装置において、外部電極端子部は前記半導体チップの全辺に対応して形成されることを特徴とする。 Further, in the semiconductor device, the external electrode terminal portion, characterized in that it is formed corresponding to all the sides of the semiconductor chip. このようにすれば、半導体装置の高集積化が図られる。 Thus, high integration of the semiconductor device can be achieved. 【0028】または、前記半導体装置において、外部電極端子部は前記半導体チップの1辺に対応する位置において複数列形成されるとともに隣り合う外部端子部は千鳥状に形成されてなることを特徴とする。 [0028] Alternatively, in the semiconductor device, the external electrode terminal portion, characterized by comprising an external terminal portions adjacent with the plurality of rows formed is formed in a zigzag shape at a position corresponding to one side of said semiconductor chip . このようにすれば、高集積化が図られた上に、隣り合う外部端子間の距離を1列に並べた場合に比して得ることができ、実装基板との接続信頼性を充分に得ることができる。 Thus, on the high integration has been achieved, the distance between the adjacent external terminal can be obtained as compared with the case by arranging in a row to obtain sufficient reliability of connection between the mounting substrate be able to. 【0029】半導体装置の外部電極端子には半田ボールを予め一体的に取りつけるようにすれば実装が極めて簡単に行なえる。 The very easily performed implement if so the external electrode terminals attached solder ball in advance integrally in the semiconductor device. 【0030】更に、本発明は、半導体チップとボンディングされチップ周辺に独立して配置される外部電極端子の封止樹脂内への埋め込み部側の相当直径を露出側の相当直径より大きくした構成とすることができる。 Furthermore, the present invention is configured and made larger than the equivalent diameter of the equivalent diameter of the embedding portion side of the semiconductor chip and the bonding is of the external electrode terminals arranged independently around the chip encapsulation in resin exposed side can do. 半導体チップとボンディングされチップ周辺に独立して配置される外部電極端子における封止樹脂に接している面は曲率を有する面からなるように構成してもよい。 Surfaces in contact with the sealing resin of the external electrode terminals arranged independently around the chip is the semiconductor chip and the bonding may be configured such that a surface having a curvature. このような半導体装置では、当初導電性板と一体的になって薄肉部を連結材としてチップ搭載領域に接続されていたが、 In such a semiconductor device has been connected to the chip mounting area thin portion is initially conductive plate integrally as connecting material,
研削により独立した島としてチップ周辺部にて封止樹脂内に埋め込まれつつ、先端面のみを外表面に露出して外部電極面となる。 While it is embedded in the sealing resin at the periphery of the chip as an independent island by grinding, the outer electrode surface by exposing only the distal end surface on the outer surface. このとき、埋め込み電極の埋め込み側の相当直径が大きく、露出側の相当直径が小さいため、 【0031】 【発明の実施の形態】以下に、本発明に係る半導体装置の製造方法、半導体装置用導電性板および半導体装置の具体的実施の形態を図面を参照して詳細に説明する。 In this case, the embedding largely buried side equivalent diameter of the electrodes, for the equivalent diameter of the exposed side is small, [0031] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of producing a semiconductor device according to the present invention, the conductive semiconductor device sex plate and the concrete embodiment of the semiconductor device with reference to the accompanying drawings. 【0032】図1および図2は、本発明の第1の実施形態に係る半導体装置の断面図および底面図である。 FIG. 1 and FIG. 2 is a cross-sectional view and a bottom view of a semiconductor device according to a first embodiment of the present invention. 図示のように、本発明に係る半導体装置は、半導体チップの電極と外部電極端子部とを電気的導通を図って樹脂封止された半導体装置において、前記半導体チップの平面に沿った封止樹脂外表面部に前記外部電極端子を同一平面となるように露出形成させてなることを特徴としている。 As shown, the semiconductor device according to the present invention is a semiconductor device resin-sealed working to electrical conduction between the electrode and the external electrode terminal of the semiconductor chip, a sealing resin along the plane of the semiconductor chip is characterized in the that the external electrode terminals formed by exposing to form so as to be flush on the outer surface. すなわち、第1実施形態に係る半導体装置100内部に半導体チップ110を持ち、樹脂150により封止され、全体として外観が直方体形状に形成されている。 That is, in the semiconductor device 100 according to the first embodiment has a semiconductor chip 110 is sealed with a resin 150, appearance is formed in a rectangular parallelepiped shape as a whole.
直方体の封止樹脂150における下面中央には、銅板からなるダイ付け突起部12の底面が臨まれ、またその一対の縁辺に沿って複数の外部電極端子13が底面の端子面を露出させて配列している。 The center of the lower surface of the rectangular sealing resin 150, the bottom surface of the die with projections 12 made of copper plate is faced, and a plurality of external electrode terminals 13 to expose the terminal surface of the bottom along the pair of edges sequences doing. これらのダイ付け突起部12と外部電極端子13の端子面と、封止樹脂150の底面とは一平面をなしている。 The terminal surfaces of the die with the protrusion 12 and the external electrode terminal 13, and forms a single plane and the bottom surface of the sealing resin 150. 半導体チップ110は、 Semiconductor chip 110,
接着剤120によりダイ付け突起部12の上面へ固定されている。 And it is fixed to the upper surface of the die with the protrusion 12 by an adhesive 120. 半導体チップ110の入出力は、導電性ワイヤ130を介して外部電極端子13の上面へ接続され、 Input and output of the semiconductor chip 110 is connected to the upper surface of the external electrode terminals 13 through conductive wires 130,
ワイヤボンディング側を封止樹脂150により封止して構成され、前記外部電極端子13が半導体装置100の下部に露出させていることで入出力をなすようにしている。 Wire bonding side is constructed by sealing with a sealing resin 150, the external electrode terminal 13 is to form an input and output that is exposed at the bottom of the semiconductor device 100. 【0033】このような第1実施形態に係る半導体装置100の製造方法を図3の工程フローチャートを参照して説明する。 [0033] illustrating the manufacturing method of the semiconductor device 100 according to this first embodiment with reference to the process flowchart of FIG. まず、図3(1)に示しているように、銅平板からなる半導体装置用導電性板(以下、単に導電性板とする。)10を用意する。 First, as shown in FIG. 3 (1), a conductive plate for a semiconductor device made of copper flat plate (hereinafter, simply referred to as conductive plate.) Is prepared 10. この導電性板10の片面を等方性エッチング処理して、半導体チップ110の搭載領域Cと、これに隣接して配置される外部電極端子形成領域Tとを残して、図3(2)に示すように、それらの周囲に薄肉部11を形成するようにしている。 One side of the conductive plate 10 by treatment isotropically etched, leaving a mounting area C of the semiconductor chip 110, and an external electrode terminal formed region T disposed adjacent thereto, in FIG. 3 (2) as shown, so that to form a thin portion 11 around them. 薄肉部11は導電性板10の肉厚の半分程度にすればよい。 The thin portion 11 may be about half the thickness of the conductive plate 10. 図4は断面図、図5は導電性板10を上部よりみた平面図であり、本発明の導電性板の第1実施例を示すものである。 Figure 4 is a cross-sectional view and FIG 5 is a plan view of the conductive plate 10 viewed from above, showing a first embodiment of a conductive plate of the present invention. エッチング処理は等方性エッチングであるため、図 Since the etching process is isotropic etching,
4に部分的に拡大して示したように、マスク面側からエッチング深さ方向に至るにしたがってエッチング領域が拡大し、その結果、非エッチング領域は高さ方向において、マスク面側の相当直径Dが基部の相当直径dより大きくなって、オーバハング状態に形成される。 4 As shown in an enlarged partially in the etching region expanded in accordance extending from the mask surface to the etching depth, as a result, the non-etched region in the height direction, of the mask surface equivalent diameter D There is larger than the equivalent diameter d of the base portion, is formed on the overhang state. 外部電極端子領域Tは、後述するように薄肉部を研削して除去することで封止樹脂内に残留するので、埋め込み側が大径となり、露出側が小径となる。 External electrode terminal region T, so remain in the sealing resin by removing by grinding the thin-walled portion as described later, the embedded side is a large, exposed side becomes small. したがってアンカ作用を発揮させることができ、封止樹脂から外部電極端子が抜け出ることが防止される。 Therefore it is possible to exhibit an anchor effect, thereby preventing the external electrode terminal comes out of the sealing resin. 【0034】導電性板10は、もとは均一な厚みをもつ導電性板であり、腐食加工などを施し板状の一部の厚みを薄くすることにより、チップ搭載領域Cおよび外部電極端子形成領域Tを厚肉部であるランド部とし、その周囲に薄肉部11が存在している。 The conductive plate 10, the original is conductive plate having a uniform thickness, by reducing the portion of the thickness of the corrosion process, such as the applied plate, the chip mounting area C and the external electrode terminals formed the region T and the land portion is thick portion, the thin portion 11 is present around it. この導電性板10の厚肉部となる中央のランド部はダイ付け突起形成部121 Central land portion to be the thick portion of the conductive plate 10 is die with projection forming portion 121
となって、半導体チップを搭載するものであり、別の厚肉のランド部として隣接配置している外部電極形成部1 Becomes, is intended for mounting a semiconductor chip, the external electrode forming portion 1 which is disposed adjacent a land portion of another thick
31の上面は、半導体チップの入出力部パッドから導電性ワイヤなどで接続される部分となる。 Upper surface 31 is a portion to be connected, such as a conductive wire from the output unit pads of the semiconductor chip. 外部電極形成部131は、単数あるいは複数個、ダイ付け突起形成部1 External electrode-forming portions 131, one or a plurality, die with projections forming section 1
21の周辺に配置させられる。 Brought disposed around the 21. 各突起であるダイ付け突起形成部121、外部電極形成部131は、独立した突起になるよう薄肉部11より高くしてある。 Die with projection forming portion 121 is each projection, the external electrode forming portions 131 are higher than the thin portion 11 so as to be separate protrusions. また、ダイ付け突起形成部121、外部電極形成部110の一部あるいは全部の上面には、導電性めっき等の処理を施す場合がある。 Further, the die with the protrusion forming portion 121, on the upper surface of part or all of the external electrode forming portion 110, there is a case of applying the processing such as conductive plating. これを図3(3)に示している。 This is shown in FIG. 3 (3). 【0035】次に図3(4)および図6の断面図に示すように、導電性板10のダイ付け突起形成部121の上に半導体チップ110を接着剤120などを用いて搭載し、半導体チップ110の入出力パッドと導電性板10 [0035] Next, as shown in the sectional view of FIG. 3 (4) and 6, the semiconductor chip 110 is mounted by using an adhesive 120 onto the die with projections forming portions 121 of the conductive plate 10, the semiconductor output pad and the conductive plate 10 of the chip 110
における外部電極形成部131の上部平坦部を導電性ワイヤ130を用い接続する(図3(5)参照)。 Connections with the upper flat portion conductive wire 130 to the external electrode forming portion 131 in (see FIG. 3 (5)). ボンディング処理した半導体装置の平面図は、図7である。 Plan view of the bonding process and the semiconductor device is Fig. 【0036】その後、図3(6)および図8に示すように、導電性板10の上の突起が存在する面において、すなわち半導体チップ110搭載面のダイ付け突起形成部121、外部電極形成部131、半導体チップ110、 [0036] Thereafter, as shown in FIG. 3 (6) and 8, in a plane projection is present on the conductive plate 10, namely die with projection forming portion 121 of the semiconductor chip 110 mounting surface, the external electrode forming portions 131, the semiconductor chip 110,
導電性ワイヤ130が配置される部分で、これらの全てを覆うように、樹脂150にて封止する。 In part the conductive wire 130 is disposed so as to cover all of these, sealed with resin 150. 封止したのち、導電性板10の樹脂封止されていない面すなわち非エッチング面側から、薄肉部11の相当厚さの分だけ、 After sealing, the face or the non-etched surface that is not sealed with resin of the conductive plate 10, by an amount equivalent to the thickness of the thin portion 11,
導電性板10が露出している面より研削(あるいはカッティング)する。 Conductive plate 10 is ground (or cut) from the surface exposed. その際の研削は、薄肉部11が完全になくなるまで行う。 Grinding at that time is performed until the thin portion 11 is completely eliminated. すなわち、ダイ付け突起部12と外部電極部13が電気的に完全に独立するような位置である、図3(7)および図8中の研削面160に示す位置まで研削する。 That is, the die with the protrusion 12 and the external electrode 13 is positioned so as to electrically completely independent, ground to the position shown on the grinding surface 160 in FIG. 3 (7) and FIG. 【0037】これらの工程を経ることによって得られた半導体装置が、図1の半導体装置100である。 The semiconductor device obtained by passing through these steps, a semiconductor device 100 of FIG. この時の半導体装置100の裏面、すなわち実装される面の構造は、図2に示すものになる。 The back surface of the semiconductor device 100 at this time, i.e., the structure of the surface to be mounted is as shown in FIG. 導電性板10に形成されていたダイ付け突起部12と外部電極端子13がそれぞれ独立した状態で半導体装置表面に露出しており、本半導体装置100の入出力部となる。 Die with the protrusion 12 and the external electrode terminal 13 which is formed in the conductive plate 10 is exposed on the semiconductor device surface in a independent state, the output unit of the semiconductor device 100. 【0038】この露出面であるダイ付け突起部12の露出面と外部電極端子13の露出面に、図3(8)に示すように、導電性めっきを施し、露出面の酸化防止、実装時のはんだのぬれ性の向上を考慮する場合もある。 The exposed surface of the exposed surface and the external electrode terminal 13 of the die with the protrusion 12 as the exposed surface, as shown in FIG. 3 (8), subjected to conductive plating, oxidation of the exposed surface, when mounted in the case of considering the improvement of the wettability of the solder is also. 【0039】次に、本発明に係る第2の実施形態の半導体装置を図9および図10に示す。 Next, the semiconductor device of the second embodiment according to the present invention shown in FIGS. 9 and 10. この図9および図1 FIG 9 and FIG. 1
0は、半導体装置の断面図および底面図である。 0 is a cross-sectional view and a bottom view of the semiconductor device. 第2の実施形態に係る半導体装置は、封止樹脂中に埋め込まれた半導体チップと埋め込み外部電極形成部とがほぼ同一厚さ(高さ)を有する構造とされ、特に半導体チップは活性側とは反対面のシリコン基板側が研削されて薄肉化されている点に特徴があり、半導体装置としての厚さが大幅に小さく形成されている。 The semiconductor device according to the second embodiment is an external electrode formation portion and embedded semiconductor chip embedded in the encapsulating resin is a structure having substantially the same thickness (height), particularly semiconductor chips and the active side It is characterized in that the silicon substrate side of the opposite surface is thinned been ground, the thickness of the semiconductor device is formed much smaller. すなわち、半導体装置2 That is, the semiconductor device 2
00は、内部に半導体チップ210を持ち、樹脂240 00 has a semiconductor chip 210 therein, the resin 240
により封止されており、全体として外観が直方体形状に形成されている。 Is sealed, the appearance as a whole is formed in a rectangular parallelepiped shape by. 直方体の封止樹脂240における下面中央には半導体チップ210の裏面、外部電極形成部2 The back surface of the semiconductor chip 210 in the center of the lower surface of the rectangular sealing resin 240, the external electrode forming portion 2
3の底面端子面が露出している。 Bottom terminal surface 3 is exposed. 半導体チップ210の入出力は、導電性ワイヤ230を介して外部電極形成部23の上面へ接続され、外部電極形成部23が半導体装置200の下部に露出していることで達成されている。 Input and output of the semiconductor chip 210 is connected to the upper surface of the external electrode forming portion 23 through a conductive wire 230, it is accomplished by the external electrode forming portion 23 is exposed at the bottom of the semiconductor device 200. 【0040】この構造を得る為の製造工程を図11に示す。 [0040] Figure 11 shows the manufacturing process for obtaining the structure. まず、同図(1)に示すように、銅平板からなる半導体装置用導電性板(以下、単に導電性板とする。)2 First, as shown in FIG. (1), a semiconductor device made of copper flat conductive plates (hereinafter, simply referred to as conductive plate.) 2
0を用意する。 To prepare a 0. 導電性板20は、もとは均一な厚みをもつ導電性板であり、腐食加工などを施し板状の一部の厚みを薄くすることにより厚肉部と薄肉部が存在している。 Conductive plate 20, the original is conductive plate having a uniform thickness, the thick portion and the thin portion is present by reducing the portion of the thickness of the plate subjected to corrosion processing. 第1実施形態がチップ搭載領域Cと外部電極端子形成領域Tとをランド部として残し、他の領域を薄肉部としてエッチング処理するようにしているが、この第2実施形態は、チップ搭載領域Cも薄肉部としてエンチングする部位とした点が第1実施形態と異なる。 Leaving the first embodiment and the chip mounting area C and the external electrode terminal formed region T as a land portion, but so as to etch process other areas as the thin portion, the second embodiment, the chip mounting area C the point that was also a member which Enchingu as thin portion different from the first embodiment. すなわち、 That is,
導電性板20は半導体チップ搭載領域Cの周囲に配置される外部電極端子形成領域Tのみをランド部として残し、図11(2)に示しているように、その周囲にエッチング除去された薄肉部21を形成し、この薄肉部は非エッチング面側の研削により前記外部電極端子形成領域Tの相互間を分離可能な深さに設定したのである。 Conductive plate 20 leaving only the external electrode terminal formation region T which is arranged around the semiconductor chip mounting area C as a land portion, FIG. 11 (2) as to show thin portion which is etched away around 21 is formed, the thin portion is to set the mutual detachable depth of the external electrode terminal formed region T by grinding the non-etched side. 図1 Figure 1
2はエッチング処理した導電性板20の断面図、図13 2 is a cross-sectional view of a conductive plate 20 which is etched, FIG. 13
は上部よりみた平面図である。 Is a plan view as viewed from the top. 【0041】この導電性板20では、半導体チップを搭載する部分を薄肉部21としている。 [0041] In the conductive plate 20 and a thin portion 21 a portion for mounting a semiconductor chip. 図12、図13で示すダイ付け部22の位置に半導体チップを搭載する(以下、ダイ付け部22とする。)。 12, a semiconductor chip mounted on a position of the die mounting portion 22 shown in FIG. 13 (hereinafter referred to as die attachment portion 22.). また、ダイ付け部22は、薄肉部21の表面の一部である。 Further, the die mounting portion 22 is a part of the surface of the thin portion 21. 厚肉部突起箇所である外部電極形成部231は、半導体チップの入出力部から導電性ワイヤ230などで接続される部分となる。 External electrode forming portion 231 is a thick part protruding portion is a portion connected by a conductive wire 230 from the input and output portions of the semiconductor chip. 外部電極形成部23は、単数あるいは複数個、ダイ付け部22の周辺に配置させられる。 External electrode formation portion 23, one or a plurality, is caused disposed around the die mounting portion 22. 外部電極形成部2 External electrode formation portion 2
31は、独立した突起になるように薄肉部21より厚くしてある。 31 are thicker than the thin portion 21 so as to separate projections. また、ダイ付け部22、外部電極形成部23 Further, the die mounting portion 22, the external electrode forming portions 23
1の一部あるいは全部の上面には、ボンディングの際の接合性の向上の為に、図11(3)に示しているように、導電性めっきを施す場合がある。 On the upper surface of the first part or whole, in order to improve the bonding property at the time of bonding, as shown in FIG. 11 (3), there is a case of applying a conductive plating. 【0042】次に図11(4)および図14の断面図に示すように、導電性板20のダイ付け部22の上に半導体チップ210を接着剤220などを用いて搭載し、半導体チップ210の入出力パッドと導電性板20の外部電極形成部23の上部平坦部を導電性ワイヤ230を用い接続する(図11(5)参照)。 [0042] Next, as shown in the sectional view of FIG. 11 (4) and 14, the semiconductor chip 210 on the die mounting portion 22 of the conductive plate 20 is mounted by using an adhesive 220, the semiconductor chip 210 an upper flat portion of the external electrode forming portion 23 of the input and output pads and the conductive plate 20 is connected with a conductive wire 230 (see FIG. 11 (5)). ボンディング処理した半導体装置の平面図は、図15である。 Plan view of the bonding process and the semiconductor device is 15. 【0043】その後、図11(6)および図16に示すように導電性板20の上の突起が存在する面、すなわち半導体チップ210の搭載面のダイ付け部22、外部電極形成部23、半導体チップ210、導電性ワイヤ23 [0043] Then, FIG. 11 (6) and the surface of the projection is present on the conductive plate 20 as shown in FIG. 16, or die mounting portion 22 of the mounting surface of the semiconductor chip 210, the external electrode forming portions 23, the semiconductor chip 210, the conductive wire 23
0の全てを覆うように、樹脂240にて封止する。 To cover all 0, sealed with resin 240. 封止したのち、導電性板20を薄肉部21側、すなわち樹脂封止されていない面すなわち非エッチング面側から、導電性板20が露出している面より研削(あるいはカッティング)する。 After sealing, the conductive plate 20 of the thin portion 21 side, namely a resin-sealed non face or the non-etched surface, the conductive plate 20 is ground (or cut) from the surface exposed. その際の研削は、薄肉部21が完全になくなるまで行う。 Grinding at that time is performed until the thin-walled portion 21 is eliminated completely. すなわち、外部電極形成部23が電気的に完全に独立する研削面250に示す位置まで研削する。 That is ground to the position shown on the grinding surface 250 of the external electrode forming portions 23 are electrically completely independent. この場合、半導体チップ210の底面は、外部電極形成部23の上面より下方の位置にある為に、研削面2 In this case, the bottom surface of the semiconductor chip 210, in order that the upper surface of the external electrode forming portion 23 at a position below the grinding surface 2
50まで研削する際には、半導体チップ110の下面の一部は研削されることになる(図11(7)参照)。 When ground to 50, part of the lower surface of the semiconductor chip 110 will be ground (see FIG. 11 (7)). 【0044】これらの工程を経ることによって得られた半導体装置が、図9、図10の半導体装置200である。 The semiconductor device obtained by passing through these steps, Fig. 9, a semiconductor device 200 in FIG. 10. この時の半導体装置200の裏面、すなわち実装される面の構造は、図10に示すものになる。 The back surface of the semiconductor device 200 at this time, i.e., the structure of the surface to be mounted is as shown in FIG. 10. 導電性板2 Conductive plate 2
0に形成されていた外部電極形成部23がそれぞれ独立した状態で半導体装置表面に露出しており、本半導体装置200の入出力部となる。 0 external electrode formation portion 23, which has been formed is exposed to the semiconductor device surface in a independent state, the output unit of the semiconductor device 200. それと同時に、搭載されている半導体チップ210の底面が露出した状態となる。 At the same time, a state where the bottom surface of the semiconductor chip 210 mounted is exposed. 【0045】この露出面である外部電極形成部23に導電性めっきを施し、露出面の酸化防止、実装時のはんだのぬれ性の向上を考慮する場合もある。 [0045] subjected to conductive plating to the external electrode forming portion 23 is the exposed surface, the prevention of oxidation of the exposed surface, in some cases even considered an improvement of the solder wettability at the time of mounting. 【0046】また、導電性板は、図5あるいは図13に示すように、1枚に1つの半導体チップを搭載することを限定しない。 [0046] The conductive plate, as shown in FIG. 5 or FIG. 13, not limited to mounting a single semiconductor chip on one. すなわち、図17に示すように、1枚の導電性板30上に、ダイ付け突起部あるいはダイ付け形成部31と外部電極形成部32からなる半導体装置構成要素パターン33を列状あるいは格子状に複数配置することも可能である。 That is, as shown in FIG. 17, on a sheet of conductive plate 30, the semiconductor device element pattern 33 consisting of the die with projections or die with forming portion 31 and the external electrode forming portions 32 in rows or grid pattern it is also possible to multiple arrangement. 【0047】この場合、導電性板30上を樹脂封止し、 [0047] In this case, the conductive plate 30 above resin sealing,
裏面からの研削を行った後に、切断線35より切り離す必要がある。 After the grinding the back surface, it is necessary to separate the cutting line 35. しかし、樹脂封止、裏面の研削等を一括して行うことが可能であり、大幅な工数の削減が可能である。 However, it is possible to perform resin sealing, and collectively backside grinding or the like, it is possible to reduce the substantial man-hours. 【0048】また全体を通じて、外部電極端子部は半導体チップの1辺に対応する位置において、複数列に形成されるとともに隣り合う外部端子部は千鳥状になるように配置形成されてもよい。 [0048] Also throughout, at a position corresponding to one side of the external electrode terminal of the semiconductor chip, the external terminal section adjacent is formed in a plurality of rows may be arranged and formed so as to zigzag shape. この構成例を図18〜図20 18 to the configuration example 20
の模式説明図に示す。 It is shown in the schematic illustration. 図18および図19はダイ付け部41の側縁部に沿って外部電極端子42を単純に2列並べた例である。 18 and 19 are examples in which simply arranging two rows external electrode terminals 42 along the side edges of the die mounting portion 41. 半導体チップの電極パッドと各外部電極端子42とはJワイヤボンディングの手法を一部に採用することにより外縁部端子との導通を確保できる。 The electrode pad and the external electrode terminals 42 of the semiconductor chip can be ensured conduction between the outer edge terminals by employing a portion of the method of J wire bonding. また、図20(1)に示すように、外部電極端子42の配列を千鳥配列とすれば特別な手法を用いること無く簡単にボンディングできる。 Further, as shown in FIG. 20 (1), it can not easily bonded using a special technique if the arrangement of the external electrode terminals 42 and the zigzag arrangement. 更に同図(2)では、ダイ付け部41の全周の各辺に沿って外部電極端子42を配列したものである。 In addition FIG. (2), in which an array of external electrode terminals 42 along each side of the entire circumference of the die mounting portion 41. これらの例では、より高集積化したパッケージ製品が得られる。 In these examples, the package product is obtained which is more highly integrated. 【0049】図21には変形例として外部電極端子42 The external electrode terminal 42 as a modification in FIG. 21
に対してハンダボール44をマウントした例を示している。 It shows an example in which to mount the solder balls 44 against. 実施形態の半導体装置では外部電極端子は封止樹脂の平面と同一平面上に形成される。 External electrode terminals in the semiconductor device of the embodiment is formed on the same plane and the plane of the sealing resin. このため、基板側への実装に際して面合わせにより端子整合を図らなければならないが、ハンダボール44が突起状態でマウントされるため、基板端子との位置合わせが容易になり、実装作業を簡便化できる。 Therefore, must be achieved terminals matching the surface alignment when mounting on the substrate side, since the solder balls 44 are mounted in a projecting condition, facilitates the alignment of the substrate terminal, you can simplify the mounting operation . 【0050】次に、図22〜図23には第3実施形態に係る半導体装置の製造方法とこれにより得られる半導体装置の外観を示している。 Next, it shows the appearance of a semiconductor device obtained by this manufacturing method of a semiconductor device according to the third embodiment in FIGS. 22 23. この実施形態は、半導体チップの電極と外部電極端子部とを電気的導通を図って樹脂封止された半導体装置において、封止樹脂のコーナ外表面部に前記外部電極端子をL字状に露出形成させた構成の半導体装置を得るためのもので、第1および第2実施形態の製造方法を利用し、特に厚み方向の切断個所を選択することにより実装上の効果が高い形態の半導体装置を得ることができる。 This embodiment is exposed in the semiconductor device resin-sealed working to electrical conduction between the electrode and the external electrode terminal of the semiconductor chip, the external electrode terminal to the L-shape corner outer surface of the sealing resin intended to obtain a semiconductor device having the structure is formed of a semiconductor device according to the effect on the implementation is high by using the manufacturing method of the first and second embodiments, in particular selecting the cutting point of the thickness direction it is possible to obtain. 【0051】この第3実施形態に係る半導体装置の製造方法を図22を参照して説明する。 [0051] illustrating a method of manufacturing a semiconductor device according to the third embodiment with reference to FIG. 22. これは複数の半導体装置を複数同時に製造するためのもので、複数の装置構成要素を形成できるような平面積を有する銅板製導電性板60を準備する。 This is for manufacturing a plurality of semiconductor devices a plurality simultaneously, to prepare a copper-made conductive plate 60 having a plane area that can form a plurality of apparatus components. この導電性板60には装置構成要素単位ごとに半導体チップ搭載領域Cの周囲に配置される外部電極端子形成領域Tのみをランド部として残し、図22(2)に示しているように、その周囲にエッチング除去された薄肉部61を形成し、この薄肉部61は非エッチング面側の研削により前記外部電極端子形成領域T Left as land portion only external electrode terminal formation region T which is arranged around the semiconductor chip mounting area C per unit component units in the conductive plate 60, as shown in FIG. 22 (2), the forming a thin portion 61 which is etched away around, the external electrode terminal formed region T by grinding of the thin portion 61 unetched surface
の相互間を分離可能な深さに設定し、ランド部は隣接する装置構成要素の外部電極端子形成部と共用するようにしている。 Of the mutual set separable depth, the land portion is to be shared with the external electrode terminal formation portion of the adjacent device components. 【0052】この導電性板60では、半導体チップ61 [0052] In the conductive plate 60, the semiconductor chip 61
0を搭載する部分を薄肉部61とし、外部電極端子形成部631で囲まれるダイ付け部62の位置に半導体チップを搭載する。 The portion for mounting the 0 and the thin portion 61, for mounting a semiconductor chip to the position of the die mounting portion 62 surrounded by the external electrode terminal portion 631. また、ダイ付け部62は、薄肉部61の表面の一部である。 Further, the die mounting portion 62 is a part of the surface of the thin portion 61. 厚肉部突起箇所である外部電極端子形成部631は、半導体チップの入出力部から導電性ワイヤ630などで接続される部分となる。 External electrode terminal portion 631 is a thick part protruding portion is a portion connected by a conductive wire 630 from the input and output portions of the semiconductor chip. 外部電極端子形成部631は、独立した突起になるように薄肉部61 External electrode terminal portion 631, independent become projections as the thin portion 61
より厚くしてあるとともに、隣接する装置構成要素と共用するようにしているため、幅寸法は隣接するチップからのくるボンディングワイヤ630をそれぞれ溶着できるスペースを確保できるように設定する。 With some and thicker, because you have to share an adjacent device components, the width dimension is set so as to secure a space for welding the Kuru bonding wires 630 from the adjacent chips respectively. また、ダイ付け部62、外部電極形成部631の一部あるいは全部の上面には、ボンディングの際の接合性の向上の為に、図22(3)に示しているように、導電性めっきを施す場合がある。 Further, the die mounting portion 62, some or all of the upper surface of the external electrode forming portion 631, in order to improve the bonding property at the time of bonding, as shown in FIG. 22 (3), the conductive plating there is a case of applying. 【0053】次に図22(4)の断面図に示すように、 [0053] Then, as shown in the sectional view of FIG. 22 (4),
導電性板60のダイ付け部62の上に半導体チップ61 The semiconductor chip 61 on the die mounting portion 62 of the conductive plate 60
0を接着剤620などを用いて搭載し、半導体チップ6 0 equipped with an adhesive 620, the semiconductor chip 6
10の入出力パッドと導電性板60の外部電極形成部6 10 the external electrode formation portions 6 of the input and output pads and the conductive plate 60 of
31の上部平坦部を導電性ワイヤ630を用い接続する(図22(5)参照)。 Upper flat portion 31 for connecting a conductive wire 630 (see FIG. 22 (5)). 【0054】その後、図22(6)に示すように導電性板60の上の突起が存在する面、すなわち半導体チップ610の搭載面のダイ付け部62、外部電極形成部63 [0054] Then, a die mounting portion 62 of the mounting surface of FIG. 22 surface protrusions are present on the conductive plate 60 as shown in (6), that is, the semiconductor chip 610, the external electrode forming portions 63
1、半導体チップ610、導電性ワイヤ630の全てを覆うように、樹脂640にて封止する。 1, the semiconductor chip 610, so as to cover all of the conductive wires 630, sealed with resin 640. 封止したのち、 After sealed,
導電性板60を薄肉部61側、すなわち樹脂封止されていない面すなわち非エッチング面側から、導電性板60 The conductive plate 60 thin portion 61 side, namely a resin-sealed non face or the non-etched side conductive plate 60
が露出している面より研削(あるいはカッティング)する。 There is ground from the surface exposed (or cutting). その際の研削は、薄肉部61が完全になくなるまで行う。 Grinding at that time is performed until the thin portion 61 is completely eliminated. すなわち、外部電極端子63が電気的に完全に独立する研削面650に示す位置まで研削する。 That is ground to the position shown on the grinding surface 650 of the external electrode terminals 63 are electrically completely independent. この場合、半導体チップ610の底面は、外部電極形成部63 In this case, the bottom surface of the semiconductor chip 610, the external electrode forming portions 63
の上面より下方の位置にある為に、研削面650まで研削する際には、半導体チップ610の下面の一部は研削されることになる(図22(7)参照)。 For some from the top surface to the lower position, when the ground to the grinding surface 650, a portion of the lower surface of the semiconductor chip 610 will be ground (see FIG. 22 (7)). 【0055】ところで、図22(7)から明らかなように、この実施例では複数の装置要素単位が同時に形成されるため、これらを分離するための厚み方向の分断位置を外部電極端子形成部631を中央から分断するように分断線660が設定されている。 By the way, as is clear from FIG. 22 (7), a plurality of devices elements units in this embodiment are formed at the same time, the external electrode terminal portion 631 a cutting position in the thickness direction to separate them the division line 660 so as to divide the center is set. これにより、各半導体装置600のコーナ部分に図23に示すようなL字形状の外部電極端子63が形成される。 Thus, the external electrode terminal 63 of the L-shape as shown in FIG. 23 at the corner portion of each semiconductor device 600 is formed. 図示のように、実施形態では、L字形外部電極端子63は、エッチング深さにもよるが、直方体のパッケージにおける長辺に沿った側端面側で長く、パッケージ裏面に露出した面が短くなるように設定されている。 As illustrated, in embodiments, L-shaped external electrode terminal 63, depending on the etching depth, so that long in the long side in along the side end face side of the rectangular package is surface exposed to the back of the package is shorter It is set to. 【0056】図24に第4実施形態を示す。 [0056] Figure 24 shows a fourth embodiment. これは外部電極端子形成部731を片側だけに片寄せて配置し、これにワイヤボンディングして樹脂封止させ、厚み方向に沿って装置単位間を分離する分断線を外部電極端子形成部731を分割するような位置に設定したものである。 It arranged offsetting the external electrode terminal portion 731 only on one side, to which was wire bonding was sealed with a resin, an external electrode terminal portion 731 a dividing line which separates the inter-device unit along the thickness direction it is obtained by setting the position so as to divide.
もちろん導電板の薄肉部を除去する工程が含まれる。 Of course it includes the step of removing the thin portion of the conductive plate. この実施形態はワイヤボンディングを半導体チップ710 This embodiment semiconductor chip 710 wire bonding
の片側に配置されている電極形成部731のみを対象としている点が第3実施形態と異なる。 The point that the only electrode formation portion 731 disposed on one side of interest differs from the third embodiment. したがって、製造された半導体装置700は図25に示すように、パッケージの片側側縁にのみ外部電極端子73が配置形成される。 Accordingly, the semiconductor device 700 manufactured as shown in FIG. 25, the external electrode terminals 73 on only one side edge of the package are arranged and formed. このようにして製造された半導体装置700は、図26に示すように、パッケージを立設して基板実装することができ、基板への実装面積を小さくすることができる利点がある。 In this way, the semiconductor device manufactured 700, as shown in FIG. 26, it is possible to board mounting erected package, there is an advantage that it is possible to reduce the mounting area of ​​the substrate. また、図23に示したパッケージも同様であるが、図26に示しているようにコーナL型電極はハンダ溶着した場合の溶着面積が大きいため、フィレットが確実に形成されて安定した実装を行なえる。 Further, although the same applies package shown in FIG. 23, since the corner L-type electrode as shown in FIG. 26 large welding area in the case of solder welding, fillet is surely formed performed stably mounted that. 【0057】 【発明の効果】以上説明したように、本発明は、予め銅板などからなる導電板に、少なくとも外部電極端子形成部に相当する部分(あるいは半導体チップ搭載領域)を残してその他をエッチングし、薄肉部を形成すると共に、残されたランドを利用してチップ搭載や電極端子形成部とチップとのボンディング処理と樹脂封止などを行ない、その後に前記導電板の薄肉部を完全に除去して外部電極端子をチップ搭載部と分離配置するようにしたので、この種の半導体装置のパッケージサイズを大幅に小さく、薄型化することができ、小型で薄型の半導体装置を簡便な方法と設備により製造することができる。 [0057] As described above, according to the present invention, the conductive plate made of pre-copper, other leaving a portion corresponding to at least the external electrode terminal portion (or a semiconductor chip mounting region) etching and, to form a thin portion, by utilizing the remaining land performs like bonding process and resin sealing between the chip mounting and the electrode terminal portion and the chip completely remove the thin portion of the conductive plate thereafter since the external electrode terminal to be arranged separately the chip mounting portion is significantly smaller package size of such semiconductor devices, can be made thinner, and a simple method of thin semiconductor device in small facilities it can be produced by.

【図面の簡単な説明】 【図1】 半導体装置の第1実施形態の断面図である。 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor device. 【図2】 図1の底面図である。 Is a bottom view of FIG. 1; 【図3】 第1の実施形態に係る半導体装置製造方法を示すフローチャートである。 3 is a flowchart showing a semiconductor device manufacturing method according to the first embodiment. 【図4】 半導体装置用導電性板の第1実施形態の断面図である。 4 is a cross-sectional view of a first embodiment of a semiconductor device the conductive plate. 【図5】 図4の平面図である。 Is a plan view of FIG. 5 FIG. 【図6】 第1実施形態に係る半導体装置製造方法におけるワイヤボンディング工程後の半導体装置の断面図である。 6 is a cross-sectional view of a semiconductor device after the wire bonding step in the semiconductor device manufacturing method according to the first embodiment. 【図7】 図6の同平面図である。 FIG. 7 is a plan view of the same shown in FIG. 6. 【図8】 第1実施形態に係る半導体装置製造方法における樹脂封止工程後の半導体装置の断面図である。 8 is a cross-sectional view of a semiconductor device after the resin encapsulation step in semiconductor device manufacturing method according to the first embodiment. 【図9】 半導体装置の第2実施形態の断面図である。 9 is a cross-sectional view of a second embodiment of a semiconductor device. 【図10】 図9の底面図である。 FIG. 10 is a bottom view of FIG. 9. 【図11】 第2の実施形態に係る半導体装置製造方法を示すフローチャートである。 11 is a flowchart showing a semiconductor device manufacturing method according to the second embodiment. 【図12】 半導体装置用導電性板の第2実施形態の断面図である。 12 is a cross-sectional view of a second embodiment of a semiconductor device the conductive plate. 【図13】 図12の平面図である。 13 is a plan view of FIG. 12. 【図14】 第2実施形態に係る半導体装置製造方法におけるワイヤボンディング工程後の半導体装置の断面図である。 14 is a cross-sectional view of a semiconductor device after the wire bonding step in the semiconductor device manufacturing method according to the second embodiment. 【図15】 図14の平面図である。 Is a plan view of FIG. 15 FIG. 14. 【図16】 第2実施形態に係る半導体装置製造方法における樹脂封止工程後の半導体装置の断面図である。 16 is a sectional view of a semiconductor device after the resin encapsulation step in semiconductor device manufacturing method according to the second embodiment. 【図17】 半導体装置用導電性板の他の実施形態を示す平面図である。 17 is a plan view showing another embodiment of a semiconductor device the conductive plate. 【図18】 外部電極端子を複数列設けた場合の変形実施形態の平面説明図である。 18 is an explanatory plan view of a modified embodiment in which the external electrode terminals are provided a plurality of rows. 【図19】 図17の断面図である。 It is a cross-sectional view of the FIG. 19] FIG. 17. 【図20】 外部電極端子を千鳥配置した例と、チップ全辺に亙って配列した例の平面説明図である。 [Figure 20] and examples of the external electrode terminals are staggered an explanatory plan view of the example are arranged over the chip all sides. 【図21】 ハンダボールを外部電極端子に形成した例の半導体装置の断面図である。 21 is a cross-sectional view of a semiconductor device of the example was formed solder balls to the external electrode terminal. 【図22】 第3の実施形態に係る半導体装置製造方法を示すフローチャートである。 22 is a flowchart showing a semiconductor device manufacturing method according to the third embodiment. 【図23】 第3の実施形態に係る半導体装置製造方法により製造された半導体装置の平面斜視図と底面斜視図である。 23 is a top perspective view and bottom perspective view of a semiconductor device a semiconductor device manufactured by the manufacturing method according to the third embodiment. 【図24】 第4の実施形態に係る半導体製造方法の要部を示す工程の断面図である。 24 is a cross-sectional view of a step showing a main part of a semiconductor manufacturing method according to the fourth embodiment. 【図25】 第4の実施形態に係る半導体製造方法により製造された半導体装置の平面斜視図と底面斜視図である。 Figure 25 is a top perspective view and bottom perspective view of the semiconductor semiconductor device manufactured by the manufacturing method according to the fourth embodiment. 【図26】 同半導体装置の実装形態の説明図である。 26 is an explanatory diagram of an implementation of the semiconductor device. 【図27】 従来の半導体装置の断面図である。 27 is a cross-sectional view of a conventional semiconductor device. 【符号の説明】 10 導電性板11 薄肉部12 ダイ付け突起部13 外部電極部100 半導体装置110 半導体チップ120 接着剤121 ダイ付け突起形成部130 導電性ワイヤ131 外部電極形成部150 封止樹脂160 研削面20 導電性板21 薄肉部22 ダイ付け部231 外部電極形成部200 半導体装置210 半導体チップ220 接着剤230 導電性ワイヤ240 封止樹脂250 研削面30 導電性板311 半導体チップ搭載部321 外部電極形成部35 切断線41 ダイ付け部42 外部電極端子44 ハンダボール50 リードフレーム500 半導体装置510 半導体チップ520 接着剤530 導電性ワイヤ540 樹脂60 導伝版61 薄肉部63 外部電極端子部600 半導体装置610 半導体チップ620 接着剤6 [Description of reference numerals] 10 conductive plate 11 thin portion 12 die with projection 13 external electrode portion 100 a semiconductor device 110 semiconductor chip 120 adhesive 121 die with projection forming portion 130 conductive wire 131 external electrode formation portion 150 sealing resin 160 grinding surface 20 conductive plate 21 thin portion 22 die mounting portion 231 the external electrode forming portions 200 a semiconductor device 210 semiconductor chip 220 adhesive 230 electrically conductive wires 240 sealing resin 250 ground surface 30 conductive plate 311 semiconductor chip mounting portion 321 external electrodes forming portion 35 cutting line 41 die mounting portion 42 external electrode terminal 44 solder balls 50 lead frame 500 semiconductor device 510 semiconductor chip 520 adhesive 530 conductive wire 540 resin 60-conduction plate 61 thin portion 63 the external electrode terminal portions 600 a semiconductor device 610 semiconductor chip 620 adhesive 6 0 導電性ワイヤ631 外部電極端子形成部640 樹脂650 研削面660 分断線 0 conductive wire 631 external electrode terminal portion 640 resin 650 ground plane 660 segmentation lines

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平9−252014(JP,A) 特開 平9−82741(JP,A) 特開 平3−94431(JP,A) 特開 平9−8206(JP,A) 特開 平3−99456(JP,A) 特開 平3−94459(JP,A) 特開20001−217372(JP,A) (58)調査した分野(Int.Cl. 7 ,DB名) H01L 23/28 H01L 21/56 H01L 21/60 301 H01L 21/50 ────────────────────────────────────────────────── ─── of the front page continued (56) reference Patent flat 9-252014 (JP, a) JP flat 9-82741 (JP, a) JP flat 3-94431 (JP, a) JP flat 9- 8206 (JP, a) JP flat 3-99456 (JP, a) JP flat 3-94459 (JP, a) JP 20001-217372 (JP, a) (58 ) investigated the field (Int.Cl. 7 , DB name) H01L 23/28 H01L 21/56 H01L 21/60 301 H01L 21/50

Claims (1)

  1. (57)【特許請求の範囲】 【請求項1】 導電性板の片面にて半導体チップ搭載領域と当該チップ搭載領域の周囲に配置される外部電極端子形成領域とを残してその周囲に薄肉部を形成するエッチング工程と、 前記半導体チップ搭載領域上に半導体チップを搭載する工程と、 前記半導体チップと前記外部電極端子形成領域とを電気的に導通させるボンディング工程と、 前記導電性板の半導体チップ搭載面側にて半導体チップおよび外部電極端子を内包する樹脂封止工程と、 前記樹脂封止工程の後に前記導電性板の非エッチング面側から当該導電性板の薄肉部相当厚さ分を越えて前記導電性板を研削除去する工程を備えることを特徴とする半導体装置の製造方法。 (57) [Claims 1 At one side of the conductive plate, leaving an external electrode terminal formed region disposed around the semiconductor chip mounting area and the chip mounting area thin portion on the periphery an etching step of forming a semiconductor chip mounting a semiconductor chip mounting region, wherein the semiconductor chip and the bonding step for electrically connecting the external electrode terminal formation region, the semiconductor chip of the conductive plate beyond a resin sealing step of encapsulating the semiconductor chip and the external electrode terminal at the mounting surface side, a thin portion corresponding the thickness of the said conductive plate from the non-etched surface of the conductive plate after the resin sealing step the method of manufacturing a semiconductor device characterized by comprising the step of grinding removing the conductive plate Te. 【請求項2】 導電性板の片面にて半導体チップ搭載領域の周囲に配置される外部電極端子形成領域を残してその周囲に薄肉部を形成するエッチング工程と、 前記薄肉部としての半導体チップ搭載領域上に半導体チップを搭載する工程と、 前記半導体チップと前記外部電極端子形成領域とを電気的に導通させるボンディング工程と、 前記導電性板の半導体チップ搭載面側にて半導体チップおよび外部電極端子を内包する樹脂封止工程と、 前記樹脂封止工程の後に前記導電性板の非エッチング面側から当該導電性板の薄肉部相当厚さ分を越えて前記導電性板を研削除去する工程を備えることを特徴とする半導体装置の製造方法。 Wherein the etching process for forming the thin portion in the periphery, leaving the external electrode terminal formation regions arranged at one side of the conductive plate around the semiconductor chip mounting region, the semiconductor chip mounting as the thin portion mounting a semiconductor chip on a region, a bonding process for electrically connecting the semiconductor chip and the external electrode terminal formation region, the semiconductor chip and the external electrode terminals in the semiconductor chip mounting surface side of the conductive plate a resin sealing step of encapsulating the step of the grinding conductive plate the conductive plate from the non-etched side beyond the thin portion corresponding the thickness of the said conductive plates removed after the resin sealing step the method of manufacturing a semiconductor device, characterized in that it comprises. 【請求項3】 請求項1または2に記載の半導体装置の製造方法において、1枚の導電性板に複数の半導体装置構成要素の領域を設定し、この複数の領域の半導体装置構成要素に対して前記各工程を行なった後に、各半導体装置構成要素単位に分断処理する工程を含むことを特徴とする半導体装置の製造方法。 3. A method of manufacturing a semiconductor device according to claim 1 or 2, and sets an area of a plurality of semiconductor devices components on one conductive plate, a semiconductor device components of the plurality of regions after performing the steps for manufacturing a semiconductor device characterized by comprising the step of dividing the processing to the semiconductor device components units. 【請求項4】 請求項1乃至請求項3のいずれかに記載の半導体装置の製造方法であって、 前記薄肉部を形成するエッチング工程は等方性のエッチングにより行なうことを特徴とする半導体装置の製造方法。 4. A method of manufacturing a semiconductor device according to any one of claims 1 to 3, the etching process for forming the thin portion and wherein a carried out by isotropic etching the method of production. 【請求項5】 請求項1乃至請求項3のいずれかに記載の半導体装置の製造方法であって、 外部電極端子形成領域における前記ボンディング工程にて使われた領域を除く領域にて厚み方向に切断する工程を含むことを特徴とする半導体装置の製造方法。 5. A method of manufacturing a semiconductor device according to any one of claims 1 to 3, in the thickness direction in the region except for the region were used in the bonding step in the external electrode terminal formation region the method of manufacturing a semiconductor device characterized by comprising the step of cutting. 【請求項6】 請求項1乃至請求項3のいずれかに記載の半導体装置の製造方法であって、 前記研削除去する工程の後に前記外部電極端子として用いられる部位の露出面に対して導電性メッキを施す工程を有してなることを特徴とする半導体装置の製造方法。 6. A method of manufacturing a semiconductor device according to any one of claims 1 to 3, conductive to the exposed surface of the site used as the external electrode terminals after the step of the grinding is removed the method of manufacturing a semiconductor device characterized by comprising a step of plating. 【請求項7】 請求項3に記載の半導体装置の製造方法において、 前記各半導体装置構成要素単位に分断処理する工程では、前記外部電極端子よりも外側にて半導体装置構成要素単位に前記導電性板の厚み方向に分断することを特徴とする半導体装置の製造方法。 7. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of dividing the processing to the semiconductor device component unit, said electrically conductive to the semiconductor device components units at the outer side than the outer electrode terminal the method of manufacturing a semiconductor device characterized by dividing the thickness direction of the plate.
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