JP2003110080A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003110080A
JP2003110080A JP2001300206A JP2001300206A JP2003110080A JP 2003110080 A JP2003110080 A JP 2003110080A JP 2001300206 A JP2001300206 A JP 2001300206A JP 2001300206 A JP2001300206 A JP 2001300206A JP 2003110080 A JP2003110080 A JP 2003110080A
Authority
JP
Japan
Prior art keywords
semiconductor element
lead
semiconductor
semiconductor device
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001300206A
Other languages
Japanese (ja)
Inventor
Yuzo Kashiwagi
勇造 柏木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Electronics Co Ltd
Original Assignee
Citizen Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Electronics Co Ltd filed Critical Citizen Electronics Co Ltd
Priority to JP2001300206A priority Critical patent/JP2003110080A/en
Publication of JP2003110080A publication Critical patent/JP2003110080A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To provide a small semiconductor device in which high density mounting can be realized while enhancing heat dissipation effect by forming a plurality of heat dissipation planes on the surface of a semiconductor chip. SOLUTION: The semiconductor device 21 comprises a semiconductor element 22, a lead frame 31 having a plurality of lead parts 23 extending toward the semiconductor element 22, and a resin material 24 for sealing the semiconductor element 22 and the lead parts 23. Each lead part 23 is formed integrally with a column part 26 and a supporting part 28 projecting from the side face of the column part 26 toward the semiconductor element 22 disposed on the upper surface at the forward end of the supporting part 28. When the semiconductor element 22 and the lead parts 23 are sealed with the resin material 24, the upper surface 23a, side face 23b and bottom face 23c of each column part 26 are exposed as the heat dissipation planes.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、リードフレームを
用いたチップ型の半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type semiconductor device using a lead frame.

【0002】[0002]

【従来の技術】従来、複数の電極部を備えたチップ型の
半導体装置(以下、半導体チップという)は、リード部
及びアイランド部を備えた金属製のリードフレーム上に
半導体素子を搭載し、その上を樹脂材で封止することに
よって形成されている。前記アイランド部は半導体素子
を支持するためのもので、リードフレームの中央部に設
けられる。また、リード部は、前記支持された半導体素
子の素子電極部とボンディングワイヤ等を介して接続さ
れ、その一端が外部基板と接続される外部電極部となっ
ている。図5はこのような従来の半導体チップ1の内部
構造を示したものであり、図6は前記半導体チップ1を
形成するためのリードフレーム2を示したものである。
リードフレーム2は、42アロイ(Ni42%のNi−
Fe合金)やアルミニウム、銅などの薄い金属帯板を用
い、アイランド部4及びリード部7が打ち抜き形成され
たチップ形成領域Aが複数設けられている。アイランド
部4は、リードフレーム本体6から内方に向かって延び
る4本の腕部10を凹設して一段低い位置に設置され
る。また、リード部7は先端に半導体チップ1の外部電
極となる電極部5が形成され、前記アイランド部4の端
部に向けて下方に折り曲げ形成される。したがって、前
記チップ形成領域A内に樹脂材9を充填して半導体チッ
プ1を形成した際に、前記各電極部5はマザーボード等
の外部基板14に接続される下面電極となる。一方、ア
イランド部4から延びる各腕部10の端部は樹脂材9の
側面の露出する放熱部材となる。
2. Description of the Related Art Conventionally, a chip type semiconductor device having a plurality of electrode portions (hereinafter referred to as a semiconductor chip) has a semiconductor element mounted on a metal lead frame having a lead portion and an island portion. It is formed by sealing the top with a resin material. The island portion is for supporting the semiconductor element, and is provided in the central portion of the lead frame. The lead portion is connected to the element electrode portion of the supported semiconductor element via a bonding wire or the like, and one end thereof is an external electrode portion connected to an external substrate. FIG. 5 shows an internal structure of such a conventional semiconductor chip 1, and FIG. 6 shows a lead frame 2 for forming the semiconductor chip 1.
The lead frame 2 is a 42 alloy (Ni 42% Ni-
A thin metal strip such as a Fe alloy), aluminum, or copper is used to provide a plurality of chip forming regions A in which the island portions 4 and the lead portions 7 are punched and formed. The island part 4 is installed at a position lower by one step by recessing four arm parts 10 extending inward from the lead frame body 6. Further, the lead portion 7 is formed with an electrode portion 5 serving as an external electrode of the semiconductor chip 1 at the tip, and is bent downward toward the end portion of the island portion 4. Therefore, when the semiconductor material 1 is formed by filling the resin material 9 in the chip forming region A, the electrode portions 5 become lower surface electrodes connected to the external substrate 14 such as a mother board. On the other hand, the end portion of each arm portion 10 extending from the island portion 4 serves as a heat dissipation member with which the side surface of the resin material 9 is exposed.

【0003】図5に示したような一つの半導体チップ1
を形成するには、先ず、半導体素子3をアイランド部4
に載置し、半導体素子3の素子電極部11と前記リード
部7の先端の電極部5とをボンディングワイヤ8で接続
する。そして、半導体素子3を中心にしてリード部7及
び腕部10にかけて樹脂材9を充填して封入した後、樹
脂材9の外側のリード部7及び腕部10をリードフレー
ム本体6から切り離して単体の半導体チップ1を取り出
す。このようにして形成された半導体チップ1は、樹脂
材9の下面に露出した電極部5をマザーボード等の外部
基板14の電極端子16に半田付けして実装される。
One semiconductor chip 1 as shown in FIG.
First, the semiconductor element 3 is formed on the island portion 4 in order to form the
Then, the element electrode portion 11 of the semiconductor element 3 and the electrode portion 5 at the tip of the lead portion 7 are connected by the bonding wire 8. Then, the lead 7 and the arm 10 are filled with the resin material 9 centering around the semiconductor element 3 and sealed, and then the lead 7 and the arm 10 outside the resin material 9 are separated from the lead frame body 6 to form a single body. The semiconductor chip 1 is taken out. The semiconductor chip 1 thus formed is mounted by soldering the electrode portions 5 exposed on the lower surface of the resin material 9 to the electrode terminals 16 of the external substrate 14 such as a mother board.

【0004】また、図7及び図8に示した従来の半導体
チップ12,15は、放熱部材を設けることによって、
より一層の放熱効果を高めた例である。半導体チップ1
2は、半導体素子3を載置するアイランド部4の裏面側
に放熱用のフィン13が別体で設けられ、半導体素子3
から発した熱はこのフィン13を通じて放出される(特
開平3−214763号公報参照)。一方、半導体チッ
プ15はアイランド部4を支持する腕部10の先端を樹
脂材9から突出させたものである。このように、腕部1
0の一端を樹脂材9から露出させたことで、半導体素子
3から発した熱は腕部10の先端から放出される(特開
平1−128887号公報参照)。
The conventional semiconductor chips 12 and 15 shown in FIGS. 7 and 8 are provided with a heat dissipation member,
This is an example in which the heat dissipation effect is further enhanced. Semiconductor chip 1
2, the fins 13 for heat dissipation are separately provided on the back surface side of the island portion 4 on which the semiconductor element 3 is mounted.
The heat generated from the fins is radiated through the fins 13 (see Japanese Patent Laid-Open No. 3-214763). On the other hand, in the semiconductor chip 15, the tip of the arm portion 10 that supports the island portion 4 is projected from the resin material 9. In this way, the arm 1
By exposing one end of 0 from the resin material 9, the heat generated from the semiconductor element 3 is radiated from the tip of the arm 10 (see Japanese Patent Laid-Open No. 1-128887).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記図
7に示した半導体チップ12にあっては、放熱用のフィ
ン13を別体で設けなければならないため、部品点数の
増加に伴って製造工数及びコストが嵩むといった問題が
あった。
However, in the semiconductor chip 12 shown in FIG. 7, since the fins 13 for heat radiation must be provided separately, the number of manufacturing steps and the number of manufacturing steps increase as the number of parts increases. There was a problem that the cost increased.

【0006】一方、図8に示した半導体チップ15にあ
っては、樹脂材9の側面から突出させた腕部10の先端
が放熱板の役目をしているため、上記のように別途放熱
板を設ける必要はないが、図5に示したようなマザーボ
ード等の外部基板14に実装する際には、腕部10が側
方に突出する分だけ半導体チップ15の実装領域が広く
なってしまうことから、高密度実装及び小型化に制約が
あった。
On the other hand, in the semiconductor chip 15 shown in FIG. 8, since the tip of the arm portion 10 protruding from the side surface of the resin material 9 functions as a heat sink, the heat sink is separately provided as described above. Although it is not necessary to provide the above, when mounting on the external substrate 14 such as a mother board as shown in FIG. 5, the mounting area of the semiconductor chip 15 becomes wider by the amount that the arm portion 10 projects laterally. Therefore, there are restrictions on high-density mounting and miniaturization.

【0007】そこで、本発明の第1の目的は、部品点
数、製造工数及びコストの増加を伴うことなく、半導体
素子から発する熱を効率よく放出することのできる半導
体装置を提供することである。
Therefore, a first object of the present invention is to provide a semiconductor device capable of efficiently radiating heat generated from a semiconductor element without increasing the number of parts, the number of manufacturing steps and the cost.

【0008】また、本発明の第2の目的は、半導体チッ
プの表面に複数の放熱面を形成することで放熱効果が高
められると共に、高密度実装が可能な小型の半導体装置
を提供することである。
A second object of the present invention is to provide a small-sized semiconductor device capable of high-density mounting while enhancing the heat dissipation effect by forming a plurality of heat dissipation surfaces on the surface of a semiconductor chip. is there.

【0009】[0009]

【課題を解決するための手段】上記課題を解決するため
に、本発明の請求項1に係る半導体装置は、半導体素子
と、この半導体素子に向けて延びる複数のリード部を有
するリードフレームと、前記半導体素子及びリード部を
封止する樹脂材とを備えた半導体装置において、前記各
リード部が、柱部と、この柱部の側面から半導体素子に
向けて突出する支持部とで一体に形成され、該支持部の
先端上面に半導体素子を設置すると共に、これら半導体
素子及びリード部を樹脂材で封止したときに各柱部の外
周面を露出させたことを特徴とする。
In order to solve the above-mentioned problems, a semiconductor device according to claim 1 of the present invention includes a semiconductor element and a lead frame having a plurality of lead portions extending toward the semiconductor element. In a semiconductor device including the semiconductor element and a resin material for sealing the lead section, each of the lead sections is integrally formed of a pillar section and a support section protruding from a side surface of the pillar section toward the semiconductor element. The semiconductor element is installed on the upper surface of the tip of the supporting portion, and the outer peripheral surface of each column portion is exposed when the semiconductor element and the lead portion are sealed with a resin material.

【0010】この発明によれば、各リード部が、半導体
素子を載置する支持部と、外周面が露出する柱部とを備
えているため、半導体素子で発生した熱が前記支持部か
ら柱部に伝達され、さらに柱部の外周面から外部に放出
される。また、柱部の上面、側面及び底面を露出させる
ことで、半導体素子からの発生熱をより効果的に放出さ
せることができる。
According to the present invention, since each lead portion has the support portion on which the semiconductor element is mounted and the column portion whose outer peripheral surface is exposed, the heat generated in the semiconductor element is generated from the support portion by the column portion. To the outside of the column, and is further discharged from the outer peripheral surface of the column. In addition, by exposing the top surface, the side surface, and the bottom surface of the pillar portion, it is possible to more effectively release the heat generated from the semiconductor element.

【0011】請求項3に係る発明は、請求項1記載の半
導体装置において、前記支持部が柱部の高さ方向の中心
より下方側の側面から突出され、支持部の先端に半導体
素子を設置したときに柱部の上面が半導体素子より上方
に位置していることを特徴とする。
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the supporting portion is projected from a side surface below the center of the column portion in the height direction, and a semiconductor element is installed at the tip of the supporting portion. The top surface of the pillar portion is located above the semiconductor element when the above is performed.

【0012】この発明によれば、半導体素子を載置する
支持部が柱部の中心より下方側から突出しているので、
前記柱部の上面近辺まで樹脂材を充填させたときに半導
体素子及びボンディングワイヤ等を完全に埋入させた状
態で封止することができる。
According to the present invention, since the supporting portion on which the semiconductor element is mounted projects from the lower side of the center of the pillar portion,
When the resin material is filled up to the vicinity of the upper surface of the pillar portion, the semiconductor element, the bonding wire and the like can be completely embedded and sealed.

【0013】請求項4に係る発明は、請求項1記載の半
導体装置において、前記リード部がリードフレームを構
成する厚肉形状の金属帯板から形成され、金属帯板の厚
みと同一高さを有する柱部と、金属帯板を凹設して形成
される支持部とで構成されていることを特徴とする。
According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the lead portion is formed of a thick metal strip plate constituting a lead frame, and has the same height as the thickness of the metal strip plate. It is characterized in that it is composed of a pillar portion having and a supporting portion formed by recessing a metal strip plate.

【0014】この発明によれば、厚肉形状の金属帯板の
厚みをそのまま柱部の高さにしているので、外部に露出
する面積を有効に増やすことができる。また、支持部は
金属帯板をエッチング加工などで凹設することによって
簡単に形成することができ、柱部と一体構造のリード部
が構成される。
According to the present invention, since the thickness of the thick metal strip plate is directly set to the height of the column portion, the area exposed to the outside can be effectively increased. Further, the supporting portion can be easily formed by recessing the metal strip plate by etching or the like, and the lead portion is formed integrally with the pillar portion.

【0015】[0015]

【発明の実施の形態】以下、添付図面に基づいて本発明
に係る半導体チップの実施形態を詳細に説明する。図1
は本発明の第1実施形態を示す半導体チップの斜視図で
あり、図2は前記半導体チップをマザーボード等の外部
基板に実装したときの断面図である。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor chip according to the present invention will be described in detail below with reference to the accompanying drawings. Figure 1
2 is a perspective view of a semiconductor chip showing a first embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor chip mounted on an external substrate such as a mother board.

【0016】図1及び図2に示されるように、本実施形
態に係る半導体チップ21は、半導体素子22と、該半
導体素子22を載置する4個のリード部23と、該リー
ド部23と半導体素子22とを封止する樹脂材24とで
構成されている。前記半導体素子22は、正方形をした
シリコン結晶体の薄板であり、四隅に素子電極部25を
備えている。各リード部23は高さ及び幅方向に厚みを
持って形成されており、垂直に延びるブロック状の柱部
26と、この柱部26の一側面から水平方向に突出する
平板状の支持部28とで断面が略L字状に形成される。
このようにして形成されたリード部23は、図1に示さ
れるように、支持部28の先端を互いに向かい合わせた
状態で2列に配列される。そして、各支持部28の上面
に半導体素子22の四隅が載置され、素子電極部25が
半田バンプ29を介して支持部28と電気的に接続され
る。その後、半導体素子22及びリード部23全体を樹
脂材24で封止して一個の半導体チップ21となる。こ
のようにして形成された半導体チップ21は、樹脂材2
4の表面に前記柱部26の上面23a,側面23b及び
底面23cが露出した状態となる。この露出させた上面
23a、側面23b及び底面23cは外気と接する放熱
面となるため、半導体素子22で発生した熱を効率よく
半導体チップ21の外部に放出することができる。ま
た、柱部26の底面23cはマザーボード等の外部基板
30aの電極パターン30bに設置される電極面とな
る。なお、この底面23cは外部基板30aの電極パタ
ーン30bと接続面を合わせるために、図1に示したよ
うに、前記支持部28の下面側を僅かに浮かす程度に凹
設される場合もある。
As shown in FIGS. 1 and 2, the semiconductor chip 21 according to this embodiment includes a semiconductor element 22, four lead portions 23 on which the semiconductor element 22 is mounted, and the lead portion 23. It is composed of a resin material 24 that seals the semiconductor element 22. The semiconductor element 22 is a square silicon crystal thin plate, and has element electrode portions 25 at four corners. Each lead portion 23 is formed with a thickness in the height and width directions, and has a block-shaped column portion 26 extending vertically and a flat plate-shaped support portion 28 protruding horizontally from one side surface of the column portion 26. And form a substantially L-shaped cross section.
The lead portions 23 thus formed are arranged in two rows with the tips of the support portions 28 facing each other, as shown in FIG. Then, the four corners of the semiconductor element 22 are placed on the upper surface of each support portion 28, and the element electrode portions 25 are electrically connected to the support portions 28 via the solder bumps 29. After that, the semiconductor element 22 and the entire lead portion 23 are sealed with the resin material 24 to form one semiconductor chip 21. The semiconductor chip 21 thus formed is made of the resin material 2
The upper surface 23a, the side surface 23b, and the bottom surface 23c of the pillar portion 26 are exposed on the surface of No. 4. Since the exposed upper surface 23a, side surface 23b, and bottom surface 23c serve as a heat dissipation surface in contact with the outside air, the heat generated in the semiconductor element 22 can be efficiently released to the outside of the semiconductor chip 21. Further, the bottom surface 23c of the pillar portion 26 serves as an electrode surface installed on the electrode pattern 30b of the external substrate 30a such as a mother board. The bottom surface 23c may be recessed to slightly float the lower surface of the supporting portion 28, as shown in FIG. 1, in order to match the connection surface with the electrode pattern 30b of the external substrate 30a.

【0017】図3は前記半導体チップ21を形成するた
めの土台となるリードフレーム31を示したものであ
る。このリードフレーム31は従来と同様に42アロイ
(Ni42%のNi−Fe合金)やアルミニウム、銅な
どの材質で形成されるが、本実施形態ではリードフレー
ム31が厚肉の金属帯板から作られており、その厚みが
そのまま半導体チップ21の高さになっている。長尺状
のリードフレーム31には半導体チップ21を形成する
ためのチップ形成領域Bが多数配列され、各チップ形成
領域Bには4個のリード部23が互いに向かい合うよう
にして突出形成される。各リード部23は、リードフレ
ーム31の厚みと同一高さを有するブロック状の柱部2
6と、この柱部26の内側を凹設して形成される平板状
の支持部28とで構成される。
FIG. 3 shows a lead frame 31 which is a base for forming the semiconductor chip 21. The lead frame 31 is made of a material such as 42 alloy (Ni 42% Ni—Fe alloy), aluminum, copper, etc. as in the conventional case, but in the present embodiment, the lead frame 31 is made of a thick metal strip. The thickness is the same as the height of the semiconductor chip 21. A large number of chip forming regions B for forming the semiconductor chips 21 are arranged on the long lead frame 31, and four lead portions 23 are formed in each chip forming region B so as to face each other. Each lead portion 23 is a block-shaped column portion 2 having the same height as the thickness of the lead frame 31.
6 and a flat plate-shaped support portion 28 formed by recessing the inside of the column portion 26.

【0018】次に、上記構成のリードフレーム31を打
ち抜き加工とエッチング加工との2工程で製造する場合
を説明するが、エッチング加工のみで上記のリードフレ
ーム31を形成することもできる。以下の〜はリー
ドフレーム31及びこのリードフレーム31を用いた半
導体チップ21の製造工程を順に示したものである。こ
の製造工程を図1及び図3に基づいて説明する。 先ず、厚肉形状の金属帯板をプレス加工やエッチング
加工等によって、リード部23に形成する部分を残して
打ち抜き、チップ形成領域Bを形成する。 次に、前記チップ形成領域B内の中央部に向けた各リ
ード部23の先端部分を上方向からエッチング加工によ
って深く凹設する。これによって、リード部23は、柱
部26と、この柱部26の内側面から水平方向に突出す
る支持部28とで断面L字状に形成される。また、リー
ド部23の下面も必要に応じてエッチング加工による凹
み部を設ける。ただし、下面側を凹設するのは柱部26
の底面23cから支持部28を僅かに浮かせるようにす
るためであるので、深く凹設する必要はない。 前記形成された支持部28の先端部に、半田バンプ2
9が形成された半導体素子22の素子電極部25を載置
し、リフロー処理を施して支持部28の先端部に溶着す
る。 次に、前記半導体素子22が搭載されたチップ形成領
域B内に樹脂材24を充填する。このとき、各リード部
23の上面23a及び底面23cが露出するように充填
する量を調整して樹脂封止する。 前記樹脂材24によって封止されたチップ形成領域B
の外枠に沿ってリードフレーム31を切断し、一つ一つ
の半導体チップ21に分ける。 以上の工程を経ることによって、図1に示されるような
半導体チップ21を製造することができる。
Next, a description will be given of a case where the lead frame 31 having the above-mentioned structure is manufactured by two steps of punching and etching, but the lead frame 31 can be formed only by etching. The following (1) to (2) show the manufacturing steps of the lead frame 31 and the semiconductor chip 21 using the lead frame 31 in order. This manufacturing process will be described with reference to FIGS. First, a thick metal strip is punched by a pressing process, an etching process, or the like, leaving a portion to be formed in the lead portion 23, to form a chip forming region B. Next, the tip portion of each lead portion 23 toward the central portion in the chip forming region B is deeply recessed by etching from above. As a result, the lead portion 23 is formed in an L-shaped cross section by the pillar portion 26 and the support portion 28 that horizontally projects from the inner side surface of the pillar portion 26. Further, the lower surface of the lead portion 23 is also provided with a recessed portion by etching if necessary. However, it is the pillar portion 26 that the lower surface side is recessed.
This is because the support portion 28 is slightly floated from the bottom surface 23c of the base plate 23c, so that it is not necessary to make a deep recess. The solder bump 2 is formed on the tip of the formed support portion 28.
The element electrode portion 25 of the semiconductor element 22 on which 9 is formed is placed and subjected to a reflow process to be welded to the tip portion of the support portion 28. Next, the resin material 24 is filled in the chip forming region B in which the semiconductor element 22 is mounted. At this time, the amount of filling is adjusted so that the upper surface 23a and the bottom surface 23c of each lead portion 23 are exposed, and resin sealing is performed. Chip forming area B sealed by the resin material 24
The lead frame 31 is cut along the outer frame of the semiconductor chip to divide it into individual semiconductor chips 21. Through the above steps, the semiconductor chip 21 as shown in FIG. 1 can be manufactured.

【0019】図4は本発明の半導体チップの第2実施形
態を示したものである。本実施形態の半導体チップ41
は、半導体素子42の実装形態を前記半導体チップ21
のフリップチップ実装方式からワイヤボンド実装方式に
置き換えて形成されたものである。このため、半導体素
子42の素子電極部45を上向きの状態とし、反対側の
面を接着剤で支持部28の端部に固着してからボンディ
ングワイヤ43で半導体素子42の素子電極部45と支
持部28の一端とを導通接続させることになる。
FIG. 4 shows a second embodiment of the semiconductor chip of the present invention. Semiconductor chip 41 of the present embodiment
The semiconductor chip 42 is mounted on the semiconductor chip 21.
The flip chip mounting method is replaced with the wire bond mounting method. Therefore, the element electrode portion 45 of the semiconductor element 42 is placed in an upward state, the opposite surface is fixed to the end portion of the support portion 28 with an adhesive, and then the element electrode portion 45 of the semiconductor element 42 is supported by the bonding wire 43. The one end of the portion 28 is electrically connected.

【0020】上記第1実施形態及び第2実施形態で示し
たように、本発明の半導体チップ21,41は、半導体
素子22,42の土台となるリード部23がリードフレ
ーム31の厚みを生かして立体的に形成され、リード部
23の上面23a,側面23b及び底面23cが外部に
露出しているので、半導体素子22,24が発する熱を
効率よく半導体チップ21,41の外部に放出すること
ができる。また、放熱方向も各リード部23の上面23
a,側面23b,底面23c側に均等であるため、半導
体チップ21,41全体を均等に冷却することができ
る。なお、リード部23の大きさによっては、上面23
a,側面23b,底面23cの全てを露出させなくて
も、所定の放熱効果を得ることができる。
As shown in the first and second embodiments, in the semiconductor chips 21 and 41 of the present invention, the lead portions 23 which are the bases of the semiconductor elements 22 and 42 make use of the thickness of the lead frame 31. Since the upper surface 23a, the side surface 23b, and the bottom surface 23c of the lead portion 23 are three-dimensionally exposed, the heat generated by the semiconductor elements 22 and 24 can be efficiently radiated to the outside of the semiconductor chips 21 and 41. it can. Further, the heat radiation direction is also the upper surface 23 of each lead portion 23.
Since a, the side surface 23b, and the bottom surface 23c are even, it is possible to uniformly cool the entire semiconductor chips 21 and 41. Depending on the size of the lead portion 23, the upper surface 23
A predetermined heat dissipation effect can be obtained without exposing all of a, the side surface 23b, and the bottom surface 23c.

【0021】また、放熱させる面が半導体チップ21,
41から突出することなく、外表面に沿って平面形成さ
れた構造となっているので、半導体チップ21,41全
体の形状及びサイズは従来の放熱板を別途形成した場合
やリード部を延設して放熱板とした半導体チップに比べ
て小さくなる。このため、マザーボード等の外部基板上
に間隔を詰めて高密度実装することができる。
The surface for radiating heat is the semiconductor chip 21,
Since it has a structure in which it is formed flat along the outer surface without protruding from 41, the overall shape and size of the semiconductor chips 21 and 41 are different from those in the case where a conventional heat sink is separately formed or lead portions are extended. It is smaller than the semiconductor chip used as a heat sink. For this reason, it is possible to perform high-density mounting on an external substrate such as a mother board with a narrow space.

【0022】なお、上記実施形態の半導体チップ21,
41では、半導体素子22,42の素子電極部25,4
5が4極の場合の例を示したが、このような半導体チッ
プの構成に限られず、リードフレームのリード部構成を
変更することで、2極等の少極あるいは4極以上の多極
の半導体素子にも応用可能である。
The semiconductor chip 21 of the above embodiment,
41, the element electrode portions 25, 4 of the semiconductor elements 22, 42
Although the example of the case where 5 is 4 poles is shown, it is not limited to such a semiconductor chip structure, but by changing the lead part structure of the lead frame, a small number of poles such as 2 poles or a multi pole of 4 poles or more can be obtained. It can also be applied to semiconductor devices.

【0023】[0023]

【発明の効果】以上説明したように、本発明に係る半導
体装置によれば、各リード部が、半導体素子を載置する
支持部と、外周面が露出する柱部とを備えているので、
半導体素子で発生した熱が前記支持部から柱部に伝達さ
れ、さらに柱部の外周面から外部に放出することができ
る。また、前記柱部の上面、側面及び底面を露出させた
場合には半導体素子から受けた熱を半導体装置の外部に
効率よく放出することができる。
As described above, according to the semiconductor device of the present invention, each lead portion includes the support portion on which the semiconductor element is mounted and the column portion whose outer peripheral surface is exposed.
The heat generated in the semiconductor element can be transferred from the supporting portion to the pillar portion, and can be further radiated to the outside from the outer peripheral surface of the pillar portion. Further, when the top surface, side surface and bottom surface of the pillar portion are exposed, the heat received from the semiconductor element can be efficiently radiated to the outside of the semiconductor device.

【0024】また、本発明によれば、厚肉形状のリード
フレームの厚みがそのまま柱部の高さになっているの
で、外部に露出する面積を有効に増やすことができる。
また、支持部は金属帯板をエッチング加工などで凹設す
ることによって簡単に形成することができるといった効
果がある。
Further, according to the present invention, since the thickness of the thick lead frame is the height of the column portion as it is, the area exposed to the outside can be effectively increased.
Further, there is an effect that the supporting portion can be easily formed by recessing the metal strip plate by etching or the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体装置の第1実施形態の斜視
図である。
FIG. 1 is a perspective view of a first embodiment of a semiconductor device according to the present invention.

【図2】上記図1の半導体装置の断面図である。FIG. 2 is a sectional view of the semiconductor device of FIG.

【図3】上記図1の半導体装置のリードフレームの斜視
図である。
FIG. 3 is a perspective view of a lead frame of the semiconductor device of FIG.

【図4】本発明に係る半導体装置の第2実施形態の斜視
図である。
FIG. 4 is a perspective view of a second embodiment of a semiconductor device according to the present invention.

【図5】従来のリードフレームで製造された半導体装置
の断面図である。
FIG. 5 is a cross-sectional view of a semiconductor device manufactured using a conventional lead frame.

【図6】上記図5で使用されたリードフレームの斜視図
である。
FIG. 6 is a perspective view of the lead frame used in FIG. 5;

【図7】従来の放熱対策が施された半導体装置の一例を
示す斜視図である。
FIG. 7 is a perspective view showing an example of a conventional semiconductor device provided with heat dissipation measures.

【図8】従来の放熱対策が施された半導体装置の他の例
を示す斜視図である。
FIG. 8 is a perspective view showing another example of a conventional semiconductor device provided with heat dissipation measures.

【符号の説明】[Explanation of symbols]

21,41 半導体装置(半導体チップ) 22,42 半導体素子 23 リード部 23a 上面 23b 側面 23c 底面 24 樹脂材 25,45 素子電極部 26 柱部 28 支持部 31 リードフレーム 21,41 Semiconductor device (semiconductor chip) 22,42 Semiconductor element 23 Lead 23a upper surface 23b side 23c bottom 24 Resin material 25,45 Element electrode part 26 Pillars 28 Support 31 lead frame

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子と、この半導体素子に向けて
延びる複数のリード部を有するリードフレームと、前記
半導体素子及びリード部を封止する樹脂材とを備えた半
導体装置において、 前記各リード部が、柱部と、この柱部の側面から半導体
素子に向けて突出する支持部とで一体に形成され、該支
持部の先端上面に半導体素子を設置すると共に、これら
半導体素子及びリード部を樹脂材で封止したときに各柱
部の外周面を露出させたことを特徴とする半導体装置。
1. A semiconductor device comprising a semiconductor element, a lead frame having a plurality of lead portions extending toward the semiconductor element, and a resin material for sealing the semiconductor element and the lead portion, wherein each of the lead portions is provided. Is formed integrally with a pillar portion and a supporting portion protruding from the side surface of the pillar portion toward the semiconductor element, and the semiconductor element is installed on the top surface of the tip of the supporting portion, and the semiconductor element and the lead portion are made of resin. A semiconductor device, wherein an outer peripheral surface of each pillar portion is exposed when sealed with a material.
【請求項2】 前記柱部の外周面が、該柱部の上面、側
面及び底面である請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the outer peripheral surface of the pillar portion is an upper surface, a side surface and a bottom surface of the pillar portion.
【請求項3】 前記支持部が、柱部の高さ方向の中心よ
り下方側の側面から突出され、支持部の先端に半導体素
子を設置したときに柱部の上面が半導体素子より上方に
位置してなる請求項1記載の半導体装置。
3. The support portion is projected from a side surface below the center of the column portion in the height direction, and the upper surface of the column portion is located above the semiconductor element when the semiconductor element is installed at the tip of the support portion. The semiconductor device according to claim 1, wherein
【請求項4】 前記リード部が、リードフレームを構成
する厚肉形状の金属帯板から形成され、金属帯板の厚み
と同一高さを有する柱部と、金属帯板を凹設して形成さ
れる支持部とで構成されてなる請求項1記載の半導体装
置。
4. The lead portion is formed of a thick-walled metal strip plate which constitutes a lead frame, and a column portion having the same height as the thickness of the metal strip plate is formed by recessing the metal strip plate. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of:
JP2001300206A 2001-09-28 2001-09-28 Semiconductor device Pending JP2003110080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001300206A JP2003110080A (en) 2001-09-28 2001-09-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001300206A JP2003110080A (en) 2001-09-28 2001-09-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2003110080A true JP2003110080A (en) 2003-04-11

Family

ID=19120815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001300206A Pending JP2003110080A (en) 2001-09-28 2001-09-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2003110080A (en)

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US8319320B2 (en) 2010-02-08 2012-11-27 Kabushiki Kaisha Toshiba LED module
US8338845B2 (en) 2010-01-29 2012-12-25 Kabushiki Kaisha Toshiba LED package and method for manufacturing the same
US8487418B2 (en) 2010-01-29 2013-07-16 Kabushiki Kaisha Toshiba LED package
US8497521B2 (en) 2010-01-29 2013-07-30 Kabushiki Kaisha Toshiba LED package
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US8637892B2 (en) 2010-01-29 2014-01-28 Kabushiki Kaisha Toshiba LED package and method for manufacturing same
US8525202B2 (en) 2010-01-29 2013-09-03 Kabushiki Kaisha Toshiba LED package, method for manufacturing LED package, and packing member for LED package
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