KR100369393B1 - Lead frame and semiconductor package using it and its manufacturing method - Google Patents

Lead frame and semiconductor package using it and its manufacturing method Download PDF

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Publication number
KR100369393B1
KR100369393B1 KR10-2001-0015966A KR20010015966A KR100369393B1 KR 100369393 B1 KR100369393 B1 KR 100369393B1 KR 20010015966 A KR20010015966 A KR 20010015966A KR 100369393 B1 KR100369393 B1 KR 100369393B1
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KR
South Korea
Prior art keywords
surface
ground ring
chip
lead
formed
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KR10-2001-0015966A
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Korean (ko)
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KR20020076017A (en
Inventor
이형주
Original Assignee
앰코 테크놀로지 코리아 주식회사
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Priority to KR10-2001-0015966A priority Critical patent/KR100369393B1/en
Publication of KR20020076017A publication Critical patent/KR20020076017A/en
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Publication of KR100369393B1 publication Critical patent/KR100369393B1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
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Abstract

A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

Description

리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법{Lead frame and semiconductor package using it and its manufacturing method} A lead frame and a semiconductor package using the same, and a method of manufacturing {Lead frame and semiconductor package using it and its manufacturing method}

본 발명은 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 MLF(Micro LeadFrame)형 반도체패키지에 이용되는 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법에 관한 것이다. The invention When, described in further detail to a method of manufacturing the semiconductor package and a lead frame using this, and relates to a lead frame and a semiconductor package and a manufacturing method using the same that is used in semiconductor packages (Micro LeadFrame) MLF.

일반적으로 반도체패키지용 리드프레임이란 구리(Cu), 구리 합금(Cu Alloy), 합금 37(니켈(Ni)37%, 철(Fe)55%) 등의 연속된 금속 스트립(Strip)을 기계적 스탬핑(Stamping)이나 화학적 에칭(Etching) 방법에 의해 제조한 것으로, 그 역할은 반도체칩과 외부 회로(예를 들면, 마더보드)를 연결시켜 주는 전선(Lead) 역할과 반도체패키지를 마더보드(Mother Board)에 고정시켜 주는 버팀대(Frame)의 역할을 동시에 수행하는 것을 말한다. In general, a lead frame for a semiconductor package is copper (Cu), copper alloy (Cu Alloy), alloy 37 (nickel (Ni) 37%, iron (Fe) 55%) the continuous metal strip (Strip) the mechanical stamping, such as ( Stamping) and chemical etching (etching), as manufactured by the method, its role is the semiconductor chip and the external circuit (e. g., a wire (Lead) serves as a semiconductor package that connects to the mother board) motherboard (mother board) It acts as a brace (Frame) that secure the means for simultaneously.

이러한 종래의 리드프레임중 MLF형 반도체패키지(200')에 이용되는 리드프레임(100')이 도6a 및 도6b에 도시되어 있으며, 이를 참조하여 종래의 리드프레임(100') 구조를 설명하면 다음과 같다. And (lead frame 100) used for the conventional lead-MLF type semiconductor package 200 'of the frame 6a and is illustrated in Figure 6b, Referring to the conventional lead frame (100') structure this then and the like.

먼저 도6a에 도시된 바와 같이 대략 판상의 사각 프레임(2')이 구비되어 있고, 상기 프레임(2')의 내측으로는 다수의 타이바(4')가 연장되어 있으며, 상기 타이바(4')에는 대략 사각판상의 칩탑재판(8')이 연결 및 지지되어 있다. First and even "and is a provided, the frame (2 substantially plate-shaped rectangular frame (2), as shown in 6a to the inside of) extends a plurality of tie bars (4 '), the tie bars (4 ') it has a substantially rectangular plate-like chip-mounting plate (8' is a) and the connection support. 또한, 상기 칩탑재판(8')의 외주연에는 다수의 리드(10')가 대략 방사상으로 배열되어 있으며, 상기 모든 리드(10')는 상기 리드(10')와 대략 수직 방향으로 형성된 댐바(12')에 연결되어 있다. Further, "outer periphery of, the plurality of leads (10, the chip mounting plate 8 ', and A) are arranged in a substantially radial, all of the leads 10' of the lead (10 'daemba formed in a substantially vertical direction with) It is connected to a 12 '. 상기 댐바(12')는 양끝단이 상기 프레임(2')에 연결되어 있고, 또한 상기 댐바(12')는 다수의 지지용 리드(14')에 연결되어 있다. The daemba (12 ') has at both ends the frame (2' and is connected to), may also be connected to the daemba (12 ') includes a plurality of support leads (for 14'). 더불어, 상기 지지용 리드(14')는 상기 프레임(2')에 연결되어 있다. In addition, the support leads (14 ') for the said frame (2' is connected to).

계속해서, 도8b에 도시된 바와 같이 상기 리드(10')중 상기 칩탑재판(8')을 향하는 영역은 일정 깊이로 부분에칭되어 있고, 상기 칩탑재판(8')의 둘레 영역도 일정 깊이로 부분에칭되어 있다. Subsequently, the said lid (10 ') as shown in Figure 8b of the chip mounting board (8' region facing) are partial etching to a predetermined depth, and the peripheral zone is also constant in the plate (8 ') of the chip It is etched to a depth section.

여기서, 편의상 상기 칩탑재판(8')의 상면을 제1면(8a'), 하면을 제2면(8b') 및 부분에칭된 영역을 제3면(8c')으로 정의한다. Here, for convenience define "the upper surface of the first surface (8a the chip mounting plate 8, a), a second surface (8b ') and a third surface portion etched region (8c') when the. 또한, 상기 리드(10')의 상면을제1면(10a'), 하면을 제2면(10b') 및 부분에칭된 부분을 제3면(10c')으로 정의한다. In addition, the definition, the upper surface of the first surface (10a of the lead 10 'to) the second surface (10b') and the third surface portion etched portion (10c ') when the.

또한, 도시되지는 않았지만, 상기 칩탑재판(8') 근처의 타이바(4')에도 일정깊이로 부분에칭된 제3면이 형성되어 있다. In addition, there is a third surface portion etched by a predetermined depth is formed to have, though not shown, tie bars (4, near) the chip mounting plate 8 '.

한편, 상기 프레임(2'), 댐바(12') 및 지지용 리드(14')는 반도체패키지 제조 공정중 싱귤레이션(Singulation) 공정에서 모두 제거되는 부분이다. On the other hand, the frame (2 '), daemba (12') and the support leads 14 'for being the portion removed from the singulation (Singulation) process of a semiconductor package manufacturing process. 따라서, 실제의 반도체패키지(200')에서는 상기 칩탑재판(8') 및 타이바(4')와 리드(10')가 주요 구성요소가 된다. Therefore, 'in the above chip-mounting plate (8, the semiconductor package 200' in real) and tie bars (4 ') and the lid (10') is a major component.

이러한 리드프레임(100')을 이용한 반도체패키지(200')가 도7a 및 도7b에 도시되어 있다. Such a lead frame, a semiconductor package (200 using a) 100 'is shown in Figures 7a and 7b. 여기서, 상기 도7a는 반도체패키지(200')의 단면도이고, 도7b는 그 저면도이다. Here, the FIG. 7a is a sectional view of the semiconductor package 200 ', Figure 7b is the bottom view.

도시된 바와 같이 대략 평면인 제1면(8a')과 제2면(8b')을 갖고, 상기 제1면(8a')과 제2면(8b') 사이에는 제3면(8c')이 형성된 칩탑재판(8')이 구비되어 있다. Substantially planar first surface (8a ') and a second surface (8b') of said first surface (8a ') and a second surface (8b') between, the third surface (8c ') has, as illustrated is formed, the chip mounting board (8 ') are provided. 여기서, 상기 제3면(8c')을 상술한 바와 같이 제2면(8b') 둘레에 형성되어 있다. Here, there is formed a (second circumferential surface 8b) as described above, the third surface (8c) ".

또한, 상기 칩탑재판(8')의 제1면(8a')에는 접착수단(28')에 의해 다수의 입출력패드(22')를 갖는 반도체칩(20')이 접착되어 있다. Further, the semiconductor chip 20 'is bonded with a (plurality of input and output pads 22) by a "first surface (8a a), the adhesive means 28, the plate 8' of the chip. 또한, 상기 칩탑재판(8')의 외주연에는 대략 평면인 제1면(10a')과 제2면(10b')을 갖고, 상기 제1면(10a')과 제2면(10b') 사이에는 제3면(10c')이 형성된 리드(10')가 구비되어 있다. Further, the chip-mounting plate (8 ') outer periphery of a substantially planar first surface (10a' 'has the first surface (10a) and the second surface (10b) ") and a second surface (10b' ) between is provided with a third surface (10c '), the lid (10, formed "). 여기서, 상기 제3면(10c')은 상기 칩탑재판(8')을 향하는 부분에 형성되어 있다. Here, the third face (10c ') is the chip-mounting plate (8' is formed in a portion facing).

또한, 상기 반도체칩(20')의 입출력패드(22')와 상기 리드(10')의 제1면(10a')은 도전성와이어(24')에 의해 기계적 및 전기적으로 상호 연결되어 있고, 상기 칩탑재판(8'), 반도체칩(20'), 도전성와이어(24') 및 리드(10')는 봉지재로 봉지되어 있다. In addition, the "first surface (10a in), input-output pad (22) and the lead (10), the semiconductor chip 20 'may be interconnected mechanically and electrically by the conductive wires (24'), wherein chip-mounting plate (8 '), the semiconductor die (20'), the conductive wires (24 ') and the lead (10') is sealed with a sealing material. 여기서, 상기 봉지재로 봉지된 영역을 봉지부(26')로 정의한다. Here, it defines the area sealed with the sealing material to the sealing portion 26 '.

상기와 같이 칩탑재판(8') 및 리드(10')에 제3면(8c',10c')이 형성된 이유는, 상기 칩탑재판(8') 및 리드(10')가 봉지부(26')에서 수평 또는 수직 방향으로 쉽게 이탈되지 않도록 하기 위함이다. The chip mounting board (8 ') and the lead (10') the third surface (8c ', 10c') The reason is that the chip mounting board (8 ') and the lead (10') formed in such as the seal portion ( 26 ') at is to prevent easy release in the horizontal or vertical direction.

한편, 상기 칩탑재판(8') 및 리드(10')중 제2면(8b')은 상기 봉지부(26') 외측으로 노출되어 있다. On the other hand, the chip mounting board (8 '), a second surface (8b') of the lid and (10 ') has the sealing part (26' are exposed to the outside). 즉, 상기 칩탑재판(8') 및 리드(10')중 제1면(8a',10a') 및 제3면(8c',10c')은 봉지부(26') 내측에 위치되고, 상기 제2면(8b',10b')은 봉지부(26') 외측으로 노출되어 있다. That is, the chip-mounting plate (8 ') and the lead (10') of the first surface (8a ', 10a') and third surface (8c ', 10c') is located at the inner seal portion (26 '), the second side (8b ', 10b') are exposed to the outside seal portion 26 '. 따라서, 상기 리드(10')의 제2면(10b')이 차후 마더보드에 실장되는 영역이 되고, 또한 상기 반도체칩(20')의 열은 상기 칩탑재판(8')을 통하여 외부로 용이하게 방출됨을 알 수 있다. Therefore, the above is a "second surface (10b of) the area to be mounted on a future mother board lead 10 ', and out through a" column of the chip mounting board (8 of) the semiconductor chip 20' it can be seen that easily released.

도9b에서 미설명 부호 4'는 봉지부(26') 외측으로 노출된 타이바이다. In Figure 9b, reference numeral 4 'is a seal portion (26' bayida tie exposed to the outside).

그러나, 이러한 종래의 리드프레임 및 이를 이용한 반도체패키지는 반도체칩의 그라운드(Ground) 신호를 처리하는 수단이 리드가 됨으로써, 신호용 리드를 낭비하는 문제가 있다. However, the conventional lead frame and a semiconductor package using the same by being the means for processing the ground (Ground) signal of the semiconductor chip, the lead, there is a problem that a waste of the signal lead. 즉, 반도체칩의 입출력패드 중에는 전력 공급용 및 신호용 입출력 패드뿐만 아니라 다수의 그라운드용 입출력패드도 존재하는데, 상기 그라운드용 입출력패드가 상기 리드에 도전성와이어로 본딩되기 때문에, 신호용 리드가 과다하게 낭비되는 문제가 있다. That is, in during the input and output pads of the semiconductor chip as well as the power supply for and signal input and output pads exist IO pad for a number of the ground, the input-output pad for the ground that since the bonding of the conductive wire to the lead, waste of the signal lead to excessive there is a problem.

상기 낭비된 신호용 리드의 갯수를 보충하기 위해서는 통상 상기 리드프레임의 리드를 파인피치(Fine Pitch)화 하여야 하는데, 이런 경우에는 그 제조 비용이 더욱 증가하여 바람직하지 않다. Screen to be fine pitch (Fine Pitch) the normal lead of the lead frame in order to compensate for the total number of the signal lead of waste, such a case is not preferable in that the manufacturing cost further increases. 또한, 상기 낭비된 신호용 리드를 보충하기 위해서 상기 리드프레임의 전체적인 크기를 크게 제조하는 방법도 있으나, 이런 경우에는 상기 리드프레임을 이용한 반도체패키지의 부피가 더욱 커져 현재의 경박단소화 추세에 대응하지 못하는 문제가 있다. In addition, although a method for increasing production the overall size of the leadframe, in this case the volume of the semiconductor package using the lead frame further increases do not correspond to the current frivolous stage digestion trends in order to make up for the said waste signal lead there is a problem.

더불어, 상기한 문제를 해결하기 위해 그라운드용의 도전성와이어를 상기 리드대신 상기 칩탑재판의 둘레면에 직접 본딩하는 방법도 있으나, 이 경우에는 상기 칩탑재판의 제3면이 히트블럭에 접촉하지 않은 상태이기 때문에 본딩시 바운싱(Bouncing)이 심하게 발생하여 와이어본딩 수율이 현저히 저하되는 문제가 있다. In addition, a conductive wire for the ground in order to solve the above problem, instead of the lead, but also a method of directly bonding the peripheral surface of the chip mounting board, and in this case to the third side of the chip mounting board in contact with the heat block since the state that the bonding upon bouncing (bouncing) severely occurs a problem that the wire-bonding yield considerably lowered. 즉, 와이어 본딩 공정중에는 상기 리드프레임이 고열을 발생시키는 대략 평판 모양의 히트블럭 상면에 위치되고, 이어서 클램프로 고정된 후 실제의 와이어 본딩이 수행되는데, 상기와 같이 반도체칩의 입출력패드와 칩탑재판의 둘레면 사이의 와이어 본딩중에는 상기 칩탑재판의 제3면이 히트블럭과 직접 접촉(직접 접촉되는 영역은 하면(제2면)임)되지 않은 상태가 됨으로써, 본딩시 캐필러리와의 접촉에 의해 바운싱이 심하게 발생하게 된다. That is, during the wire bonding process is located on the top surface substantially flat-plate-like heat block diagram of which is the leadframe in high temperature, was then fixed to the clamp there is the actual wire bonding performance of, with input and output pads of the semiconductor chip and the chip as described above, during the wire bonding between the peripheral surface of the plate (if the domain is in direct contact (second surface) Lim) the third side of the chip mounting board in direct contact with the heat block between being a non-state cache bonding capillary this bouncing by the contact will occur severely. 결국, 상기 바운싱에 의해 와이어 본딩이 양호하게 수행되지 않음은 당연하다. After all, the wire bonding does not be satisfactorily performed by the bouncing is natural.

한편, 상기 리드 및 칩탑재판이 봉지부에서 이탈되는 현상을 억제하기 위해 상기 리드 및 칩탑재판에 비록 제3면이 형성되어 있기는 하지만, 실제로 상기 반도체패키지가 마더보드에 실장된 후 여러 가혹한 환경에서 작동하게 되면, 상기 봉지부에서 상기 리드 및 칩탑재판이 비교적 쉽게 이탈되는 문제가 있다. On the other hand, it is though the third surface to the leads and the chip mounting board is formed to suppress the phenomenon plate with the leads and the chip is separated from the seal portion, but after the fact on which the semiconductor package mounted on the mother board with several severe environment When working on, in the sealing portion with the lead plate and the chip, there is a problem that is relatively easy exit.

본 발명은 상기와 같은 종래의 문제를 해결하기 위해 안출한 것으로, 본 발명의 목적은 칩탑재판에 그라운드용의 와이어 본딩시, 그 칩탑재판의 바운싱(Bouncing) 현상을 억제할 수 있는 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법을 제공하는데 있다. The present invention is one devised to solve the conventional problems as described above, the lead frame with the object of the invention is to suppress bouncing (Bouncing) phenomenon, the chip-mounting plate during wire bonding for the ground on the mounting board chip and to provide a semiconductor package and a manufacturing method using the same.

본 발명의 다른 목적은 리드 및 칩탑재판 등이 봉지부에 더욱 강하게 결합되어 수직 또는 수평방향으로 쉽게 이탈되지 않는 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법을 제공하는데 있다. Another object of the present invention to provide a lead and a chip-mounting board, such as the seal portion is more strongly coupled to the vertical or horizontal direction easily lead frame does not exit, and the semiconductor package and a manufacturing method using the same on.

본 발명의 또다른 목적은 반도체칩의 그라운드 신호를 리드가 아닌 칩탑재판쪽으로 인출하여, 신호용 리드의 갯수를 최대한 확보할 수 있는 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법을 제공하는데 있다. A further object of the present invention to provide a take-off to the ground signal of the semiconductor chip toward the chip mounting board instead of the lead, the lead can be secured as much as possible the number of the signal lead frame and a semiconductor package and a manufacturing method using the same.

도1a 및 도1b는 본 발명에 의한 리드프레임을 도시한 평면도 및 저면도이다. Figures 1a and 1b are a plan view and a bottom view showing a lead frame according to the present invention.

도2a 내지 도2c는 도1a 및 도1b의 II선, Ⅱ-Ⅱ선 및 Ⅲ-Ⅲ선에 대한 단면도이다. Figures 2a to 2c is a II line cross-sectional view on the line Ⅱ-Ⅱ and Ⅲ-Ⅲ line of Figure 1a and 1b.

도3a 내지 도3c는 본 발명에 의한 반도체패키지를 도시한 단면도이고, 도3d는 그 저면도이다. Figures 3a to 3c are sectional views showing a semiconductor package according to the invention, Figure 3d is its bottom view.

도4는 본 발명에 의한 반도패키지의 제조 방법을 도시한 순차 설명도이다. Figure 4 is a sequential explanatory view illustrating a method of manufacturing a semiconductive package according to the present invention.

도5a 내지 도5f는 도4에 따른 반도체패키지의 제조 상태를 도시한 상태도이다. Figure 5a-5f is a state diagram showing a state of manufacturing the semiconductor package according to Fig.

도6a는 종래의 리드프레임을 도시한 평면도이고, 도6b는 도6a의 I'-I'선에 대한 단면도이다. Figure 6a is a plan view showing a conventional lead frame, and Figure 6b is a cross-sectional view of the I'-I 'line of 6a.

도7a 및 도7b는 종래의 리드프레임을 이용한 반도체패키지의 단면도 및 저면도이다. Figure 7a and Figure 7b is a cross-sectional view and a bottom view of the semiconductor package using the conventional lead frame.

- 도면중 주요 부호에 대한 - for the major reference characters

100; 100; 본 발명에 의한 리드프레임 A lead frame according to the invention

2; 2; 프레임 4; Frame 4; 타이바 Tie Bar

4a,4b,4c; 4a, 4b, 4c; 타이바의 제1면, 제2면 및 제3면 The first surface of the tie bar, the second surface and the third surface

6; 6; 그라운드링 Ground ring

6a,6b,6c; 6a, 6b, 6c; 그라운드링의 제1면, 제2면 및 제3면 The first surface of the ground ring, the second surface and the third surface

8; 8; 칩탑재판 Chip mounting plate

8a,8b,8c; 8a, 8b, 8c; 칩탑재판의 제1면, 제2면 및 제3면 The first surface of the chip mounting board, the second surface and the third surface

10; 10; 리드 lead

10a,10b,10c; 10a, 10b, 10c; 리드의 제1면, 제2면 및 제3면 The first surface of the lid, a second surface and a third surface

12; 12; 댐바 14; Daemba 14; 지지용리드 Support leads for

16; 16; 장공 Slot

200; 200; 본 발명에 의한 반도체패키지 20; The semiconductor package 20 according to the present invention; 반도체칩 Semiconductor chips

22; 22; 입출력패드 24; Input-output pad 24; 도전성와이어 Conductive wires

26; 26; 봉지부 Bag unit

상기한 목적을 달성하기 위해 본 발명에 의한 리드프레임은 대략 평판 모양의 프레임과; A lead frame according to the present invention to achieve the above object is a frame of substantially plate-like and; 상기 프레임 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과; And is positioned on the frame inner side, the ground ring substantially planar first surface and having a second surface, said first and second surfaces between is formed with a plurality of third side of the first surface and the opposite surface and; 상기 그라운드링 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과; And is located in the ground ring inner side, on the periphery of the second side is at the same time substantially planar first and second surfaces of said first and second surfaces between, the first surface and the opposite surface have a third the chip mounting board and a surface formed; 상기 프레임으로부터 내측으로 연장되어, 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와; Extending inwardly from said frame, said ground ring and chip and connecting and supporting the mounting plate, having a substantially planar first and second surfaces, in opposition to the first surface between the first and second surfaces a plurality of tie bars at the same time - surface having a third surface on the outside of the parts associated with the ground ring; 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드를 포함하여 이루어진 것을 특징으로 한다. Which it is substantially radially arranged on the outer periphery of the ground ring, the substantially planar first surface and a having a second surface, the first surface and the said ground ring between the second surface is at the same time of the first surface and the opposite surface characterized in that made in the head portion includes a plurality of lead is the third surface is formed.

여기서, 상기 그라운드링과 상기 칩탑재판 사이에는 다수의 장공(長空)이 형성되어 있다. Here, a number of elongated holes (長空) is formed between the ground ring and the chip mounting board.

또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과; The semiconductor package according to the invention to achieve the above object has a substantially planar first and second surfaces, said first and second surfaces between, the first surface and the opposite surface is at the same time the first 2, the chip mounting board having a third surface on the periphery of the; 상기 칩탑재판의 외주연에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과; And is located at the outer periphery of the chip mounting board, substantially planar first surface and a having a second surface, said first and second surfaces between, the first surface and the opposite surface of the plurality of the third surface is formed, the ground ring and; 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와; The ground ring and the connecting and supporting the chip mounting board and substantially planar first surface and a having a second surface, the first surface and the second among has the first surface opposite to the at the same time coupled to the ground ring face side a plurality of tie bar portions formed on the outer side of the third surface; 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에제3면이 형성된 다수의 리드와; Which it is substantially radially arranged on the outer periphery of the ground ring, the substantially planar first surface and a having a second surface, the first surface and the said ground ring between the second surface is at the same time of the first surface and the opposite surface a plurality of leads are formed on the third surface facing portion; 상기 칩탑재판의 제1면에 다수의 입출력패드를 가지며 접착수단으로 접착된 반도체칩과; It said chip having a plurality of input-output pads on the first surface of the plate adhered to the semiconductor chip and the adhesive means; 상기 반도체칩의 입출력패드와 상기 그라운드링 및 리드의 제1면을 상호 기계적 및 전기적으로 연결하는 도전성와이어와; And conductive wires connecting a first side of the input-output pad and the ground ring and the lead of the semiconductor chip to each other mechanically and electrically; 상기 칩탑재판, 타이바, 그라운드링, 리드, 반도체칩 및 도전성와이어가 봉지재로 봉지되어 있되, 상기 칩탑재판, 타이바, 그라운드링 및 리드의 제2면은 봉지부 외측으로 노출되도록 형성된 봉지부를 포함하여 이루어진 것을 특징으로 한다. Itdoe the chip-mounting plate, a tie-bar, the ground ring, the lead, the semiconductor chip and the conductive wires are sealed with a sealing material, the second surface of the chip mounting board, tie bars, the ground ring and the lead is formed so as to be exposed to the seal portion outwardly It made in that includes a bag characterized.

여기서, 상기 그라운드링은 제2면과 대응되는 제1면에만 도전성와이어가 본딩된 것을 특징으로 한다. Here, the ground ring is characterized in that only the conductive wire is bonded the first surface is the second surface and the corresponding.

또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 대략 평판 모양의 프레임과, 상기 프레임 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과, 상기 그라운드링 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과, 상기 프레임으로부터 내측으로 연장되어, 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와, 상기 그라운드링의 외주 In addition, a method for manufacturing a semiconductor package according to the invention to achieve the above object and is positioned in the frame, and the frame inner side of the substantially flat plate shape having a substantially planar first and second surfaces, the first between the surface and the second surface has been located on the first surface opposite to a plurality of the ground ring and, wherein the ground ring inner side having a third surface side, has a substantially planar first and second surfaces, said first between the first surface and the second surface is the first surface and the opposite surface is at the same time with the chip is a third surface formed on the periphery of the second side plate, extending inwardly from said frame, said ground ring and the chip mounting board connection and the support, and a third surface on the outside of the substantially planar first surface and part of claim has the second face, between the first surface and the second surface is connected to both a first surface and the opposite surface and the ground ring a plurality of tie bars, the outer periphery of the ground ring formed 에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드를 포함하여 이루어진 리드프레임을 제공하는 단계와; Substantially and are radially arranged, the third surface substantially planar first surface and part of claim has the second face, between the first surface and the second surface is facing the ground ring at the same time of the first surface and the opposite surface in providing a lead frame comprising an a plurality of leads formed and; 상기 칩탑재판의 제1면에 접착수단을 이용하여 다수의 입출력패드가 형성된 반도체칩을 접착하는 단계와; Comprising the steps of: bonding a plurality of semiconductor chip input and output pads are formed using the adhesive means on the first surface of the chip mounting board; 상기 반도체칩의 입출력패드와 상기 그라운드링 및 리드의 제1면을 도전성와이어를 이용하여 기계적 및 전기적으로 본딩하는 단계와; The step of bonding a first surface of the input pad and the ground ring and the lead of the semiconductor chip mechanically and electrically with the conductive wires and; 상기 칩탑재판, 타이바, 그라운드링, 리드, 반도체칩 및 도전성와이어를 봉지재로 봉지하되, 상기 칩탑재판, 타이바, 그라운드링 및 리드의 제2면은 외측으로 노출되도록 봉지부를 형성하는 단계와; The chip-mounting plate, a tie-bar, the ground ring, the lead, but sealing the semiconductor chip and the conductive wires with a sealing material, the chip mounting board, tie bars, ground second surface of the ring and the lead is forming the bag so as to be exposed to the outside step; 상기 프레임에서 상기 리드 및 타이바의 외측을 소잉하여 낱개의 반도체패키지로 싱귤레이션하는 단계를 포함하여 이루어진 것을 특징으로 한다. In the frame it is characterized in that made in comprising the step of singulating the semiconductor package by a singulated by sawing the outer side of the lead and the tie bars.

여기서, 상기 와이어 본딩 단계는 도전성와이어가 상기 그라운드링의 제2면과 대응되는 제1면에 본딩되도록 한다. Here, the wire bonding step is such that the conductive wire is bonded to the first surface on which the second surface and the corresponding of said ground ring.

상기와 같이 하여 본 발명은 그라운드용의 도전성와이어를 제1면, 제2면 및 제3면이 형성된 그라운드링중 제2면(와이어 본딩중 히터블럭에 접촉되는 면)과 대응하는 제1면에 본딩함으로써, 와이어 본딩중 그라운드링의 바운싱(Bouncing) 현상을 억제할 수 있다. The present invention as described above has a first surface corresponding to the conductive wire for the ground and the (surface in contact with the heater block of the wire bonding), the first surface, second surface and third surface are formed a ground ring second face of by bonding, it is possible to suppress the bouncing (bouncing) phenomenon of the ground ring of wire bonding. 따라서, 와이어 본딩이 양호하게 수행되어 전체적인 와이어 본딩 수율이 향상된다. Accordingly, the wire bonding is carried out satisfactorily thereby improving the overall yield of the wire bonding.

즉, 종래에는 칩탑재판의 둘레면(제3면과 대응되는 제1면)에 본딩함으로써 바운싱 현상에 의해 와이어 본딩 수율이 현저히 저하되었지만, 본 발명은 이와 반대로 와이어 본딩 수율이 현저히 향상된다. That is, conventionally, by bonding the (first surface corresponding to the third surface), the circumferential surface of the chip mounting board, but by the bouncing phenomenon wire-bonding yield is significantly reduced, the present invention is on the other hand a wire-bonding yield is remarkably improved.

또한, 본 발명은 칩탑재판 및 리드뿐만 아니라 그라운드링중 제1면 및 제3면이 봉지부 내측에 위치됨으로써, 특히 상기 칩탑재판과 봉지부 사이의 결합력이 더욱 향상된다. In addition, the present invention is the bonding force between the seal portion being located inside the first surface and the third surface of not only the chip mounting board and the lead ground ring, in particular the chip mounting board and the sealing portion is further improved. 즉, 종래에는 상기 칩탑재판의 제1면 및 제3면이 봉지부 내측에 위치되었지만, 본 발명은 상기 칩탑재판과 연결된 그라운드링의 제1면 및 제3면이 봉지부 내측에 더 위치됨으로써, 전체적으로 상기 칩탑재판과 봉지부와의 결합력이 더욱 향상된다. That it is, in the prior art, but the first surface and the third surface of the chip mounting board positioned on the sealing portion inner side, the present invention is the first surface and the third surface of the ground ring is connected to the chip mounting board further position the sealing portion inner whereby, as a whole and the bonding strength between the chip mounting board and the sealing portion it is further improved.

더불어, 반도체칩의 그라운드 신호를 처리하는 수단이 리드가 아닌 별도의 그라운드링이 됨으로써, 다수의 신호용 리드를 더 확보하게 된다. In addition, being a means for processing the signal ground of the semiconductor chip, a separate ground ring non-lead, the more secure the plurality of signal lead.

즉, 반도체칩의 입출력패드 중 다수의 그라운드용 입출력패드를 도전성와이어를 이용하여 리드가 아닌 그라운드링에 모두 본딩함으로써, 그만큼 나머지 전력공급용 또는 신호용 입출력패드에 대한 리드를 확보하게 된다. That is, since both the input and output bonding pads of the plurality of input and output ground pads of the semiconductor chip to the ground ring and not the lid using a conductive wire, is so secure the lid on for the rest of the power supply or signal input and output pads.

따라서, 종래와 같이 파인피치화한 리드프레임을 제조하거나, 크기가 더 큰 리드프레임을 제조할 필요가 없다. Thus, producing a fine pitch by a lead frame as in the prior art, or it is not necessary to size the manufacture larger lead frame.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다. Referring now to the accompanying drawings, preferred embodiments of the present invention self skilled enough to easily carry out the present invention in the art and described in detail as follows.

도1a 및 도1b는 본 발명에 의한 리드프레임(100)을 도시한 평면도 및 저면도이다. Figures 1a and 1b are a plan view and a bottom view showing a lead frame 100 according to the present invention.

대퍅 평판 모양의 프레임(2)이 구비되어 있다. Daepya flat plate shape has a frame (2) is provided for. 상기 프레임(2) 내측에는 대략 사각링 모양의 그라운드링(6)이 위치되어 있으며, 상기 그라운드링(6) 내측에는대략 사각판 모양의 칩탑재판(8)이 위치되어 있다. The frame (2) inner side is substantially rectangular ring shape, and a ground ring (6) is the position, plate 8, the ground ring 6 with an inner side of the substantially rectangular plate-like chip position.

상기 프레임(2)으로부터는 내측으로 다수의 타이바(4)가 형성되어 있으며, 상기 타이바(4)에는 상기 그라운드링(6) 및 칩탑재판(8)이 연결 및 지지되어 있다. From the frame (2) has a plurality of tie bars (4) are formed in the inner side, and the tie bars 4 is provided with plate 8, the ground ring 6 and the chip is connected to and supported.

여기서, 상기 칩탑재판(8)과 그라운드링(6) 사이에는 다수의 장공(16)이 더 형성되어, 상기 칩탑재판(8)과 상기 그라운드링(6)은 일정거리 이격되어 있다. Here, the chip mounting plate 8 and the ground ring (6) is between the plurality of elongated holes 16 are further formed, wherein the chip mounting plate 8 and the ground ring (6) are spaced a certain distance. 물론, 상기 칩탑재판(8)과 그라운드링(6)의 일정영역은 타이바(4)에 의해 상호 연결되어 있다. Of course, a certain area of ​​the chip mounting plate 8 and the ground ring (6) are interconnected by a tie bar (4).

계속해서, 상기 그라운드링(6)의 외주연에는 대략 방사상으로 다수의 리드(10)가 배열되어 있다. There continues to be, a plurality of leads (10) in a substantially radial outer periphery of the ground ring 6 is arranged. 상기 모든 리드(10)는 그 리드(10)의 길이 방향과 수직 방향을 이루는 댐바(12)에 연결되어 있으며, 상기 댐바(12)는 프레임(2)에 연결되어 있다. All the lead 10 is connected to a daemba (12) forming the longitudinal and vertical direction of the lead 10, the daemba 12 is connected to the frame (2). 또한, 상기 댐바(12)는 다수의 지지용 리드(14)의 일단에 연결되어 있으며, 상기 지지용 리드(14)의 타단은 프레임(2)에 연결되어 있다. In addition, the daemba 12 is connected to one end of the plurality of support leads (14), the other end of the support leads (14) is connected to the frame (2). 도1b에서 해칭(Hatching)으로 표시된 영역은 부분 에칭된 영역으로서, 아래의 설명에서는 제3면으로 설명된다. As shown in FIG region 1b by hatching (Hatching) is part of the etched regions, the description below will be described as the third surface.

도2a 내지 도2c는 도1a 및 도1b의 II선, Ⅱ-Ⅱ선 및 Ⅲ-Ⅲ선을 도시한 단면도이다. Figures 2a to 2c is a cross-sectional view of the line II, line Ⅱ-Ⅱ and Ⅲ-Ⅲ line of Figure 1a and 1b.

도시된 바와 같이 칩탑재판(8)은 대략 평면인 제1면(8a)과 제2면(8b)을 갖고, 상기 제1면(8a)과 제2면(8b) 사이에는 상기 제1면(8a)과 반대면인 동시에 상기 제2면(8b)의 둘레에 제3면(8c)이 형성되어 있다. In the first surface between the mounted chip, as illustrated plate 8 is substantially planar first surface (8a) and the second having a surface (8b), said first surface (8a) and a second side (8b) has a third surface (8c) are formed on the periphery of (8a) with the same time the second side (8b) opposite surface. 즉, 상기 제2면(8b)의 둘레에는상기 제1면(8a) 및 제2면(8b)과 수직 방향으로 일정 깊이 함몰 또는 부분에칭된 제3면(8c)이 형성되어 있다. That is, the first has two circumferential surfaces, the first (8a) and a second surface a third surface (8c) with a certain depth of the recessed portion or the etching (8b) and the vertical direction of the face (8b) is formed.

또한, 상기 칩탑재판(8)의 외주연에는 일정거리 이격되어 그라운드링(6)이 형성되어 있으며, 상기 그라운드링(6)은 대략 평면인 제1면(6a)과 제2면(6b)을 갖고, 상기 제1면(6a)과 제2면(6b) 사이에는 상기 제1면(6a)과 반대면인 다수의 제3면(6c)이 더 형성되어 있다. Further, the outer periphery of the chip mounting board (8) are spaced apart a predetermined distance, and a ground ring (6) is formed, the ground ring 6 and a second side (6b) substantially planar first surface (6a) to have said first surface (6a) and a second side (6b) between the first surface has (6a) and the other side of the plurality of the third surface (6c) are further formed. 즉, 상기 그라운드링(6)은 제2면(6b)에 상기 제1면(6a) 및 제2면(6b)과 수직 방향으로 일정깊이 함몰 또는 부분에칭된 다수의 제3면(6c)이 형성되어 있으며, 이는 대략 상기 제2면(6b)과 함께 요철(凹凸) 모양으로 형성되어 있다. That is, the ground ring 6 has a second surface (6b) of the first surface (6a) and a second side (6b) and the plurality of third side (6c) in the vertical direction with a predetermined depth depression or partial etching on the is formed, and which is formed in a shape substantially the second surface roughness (凹凸) with (6b). 또한, 상기 그라운드링(6)의 제1면(6a)에는 일정 두께의 도금층(도시되지 않음)이 더 형성될 수도 있다. In addition, the plating layer having a predetermined thickness has a first surface (6a) of said ground ring 6 (not shown) may be further formed. 즉, 상기 제1면(6a)에는 은(Ag) 또는 금(Au)과 같은 금속으로 도금층이 더 형성되어 차후 도전성와이어와의 양호한 본딩을 유도할 수도 있다. That is, the first surface (6a) there is further formed a coating layer of a metal such as silver (Ag) or gold (Au) can also lead to good bonding with the subsequent conductive wire.

한편, 상기 그라운드링(6)의 외주연에는 다수의 리드(10)가 위치되어 있으며, 상기 리드(10)는 대략 평면인 제1면(10a)과 제2면(10b)을 갖고, 상기 제1면(10a)과 제2면(10b) 사이에는 상기 제1면(10a)과 반대면인 동시에 상기 그라운드링(6)을 향하는 부분에 제3면(10c)이 형성되어 있다. On the other hand, the outer periphery of the ground ring (6) has a plurality of leads 10 are located, have the lead 10 is substantially planar first surface (10a) and the second surface (10b), wherein between the first face (10a) and the second surface (10b) has the first surface (10a) and has the other side at the same time the third surface (10c) on the part facing the ground ring 6 is formed. 즉, 상기 제1면(10a) 및 제2면(10b)과 수직 방향으로 일정깊이 함몰 또는 부분에칭된 제3면(10c)이 형성되어 있다. That is, the first surface (10a) and the second surface a third surface (10c) recessed a predetermined depth by etching or part (10b) and the vertical direction is formed. 더불어, 상기 리드(10)의 제1면(10a)에도 차후 도전성와이어(24)와의 양호한 본딩을 위해 은(Ag) 또는 금(Au)과 같은 금속으로 일정 두께의 도금층이 더 형성될 수도 있다. The first surface of the addition, the lead (10) (10a) also can be a plated layer having a predetermined thickness further formed from a metal such as silver (Ag) or gold (Au) for good bonding with the subsequent conductive wire (24).

상기 리드(10)는 일체의 댐바(12)에 연결되어 있으며, 상기 댐바(12)는 지지용 리드(14)를 통하여 그 외측의 프레임(2)에 연결되어 있다. The lead 10 is connected to a daemba 12 of the integral, the daemba 12 is through the support leads 14 for connection to the outside of the frame (2).

더불어, 상기 타이바(4)는 대략 평면인 제1면(4a)과 제2면(4b)을 갖고, 상기 제1면(4a)과 제2면(4b) 사이에는 상기 제1면(4a)과 반대면인 동시에 상기 그라운드링(6)과 연결된 부분의 외측에 제3면(4c)이 형성되어 있다. In addition, the tie bar (4) is substantially planar first surface (4a) and the second having a surface (4b), between the first surface (4a) and the second surface (4b) has the first surface (4a ) and the other side is at the same time, the third surface (4c on the outer side of the portion coupled to the ground ring 6) is formed. 즉, 상기 제1면(4a) 및 제2면(4b)과 수직 방향으로 일정 깊이 함몰 또는 부분에칭된 제3면(4c)이 형성되어 있다. That is, the first surface (4a) and the second surface a third surface (4c) of a predetermined depth by etching the recessed portion or (4b) and a vertical direction is formed. 여기서도, 상기 타이바(4)의 제1면(4a)에는 차후 도전성와이어와의 양호한 본딩을 위해 은(Ag) 또는 금(Au)과 같은 금속에 의해 일정 두께의 도금층이 더 형성될 수 있다. Once again, the first surface (4a), the plated layer having a predetermined thickness by a metal such as silver (Ag) or gold (Au) for good bonding with the subsequent conductive wire of the tie bar (4) can be further formed.

이러한 리드프레임(100)은 모두 구리(Cu), 구리 합금(Cu Alloy), 합금 37(니켈(Ni)37%, 철(Fe)55%) 등의 연속된 금속 스트립(Strip)을 기계적 스탬핑(Stamping)이나 화학적 에칭(Etching) 방법에 의해 제조된 것으로서, 이것의 형성 방법은 반도체패키지의 제조 방법 설명에서 하기로 한다. The lead frame 100 includes both copper (Cu), copper alloy (Cu Alloy), alloy 37 (nickel (Ni) 37%, iron (Fe), 55%) the continuous metal strip (Strip) the mechanical stamping, such as ( Stamping) and chemical etching (as manufactured by etching) method, forming method of this will be given in the method for manufacturing a semiconductor package described.

이어서, 도3a 내지 도3c는 본 발명에 의한 반도체패키지(200)를 도시한 단면도이고, 도3d는 그 저면도이다. Next, Figs. 3a to 3c are sectional views showing a semiconductor package 200 according to the present invention, Figure 3d is its bottom view.

도시된 바와 같이 대략 평면인 제1면(8a)과 제2면(8b)을 갖고, 상기 제1면(8a)과 제2면(8b) 사이에는 상기 제1면(8a)과 반대면인 동시에 상기 제2면(8b)의 둘레에 제3면(8c)이 형성된 칩탑재판(8)이 구비되어 있다. A substantially planar first surface (8a) and the second having a surface (8b), said first surface (8a) and a second side (8b) has the first surface (8a) and the other side between as illustrated at the same time it is provided with a chip-mounting plate (8) having a third surface (8c) on the periphery of the second side (8b).

상기 칩탑재판(8)의 외주연에는 일정 거리 이격된 채, 대략 평면인제1면(6a)과 제2면(6b)을 갖고, 상기 제1면(6a)과 제2면(6b) 사이에는 상기 제1면(6a)과 반대면인 다수의 제3면(6c)이 형성된 그라운드링(6)이 위치되어 있다. The chip mounting plate 8, the outer periphery is less than a predetermined distance apart of between approximately flat in Spain first surface (6a) and a second surface (6b) to, having the first surface (6a) and a second surface (6b) in the second is the first surface (6a) and the other side of a plurality of the ground ring (6) on three sides (6c) are formed in this location.

여기서, 상기 그라운드링(6)의 제1면(6a)에는 은(Ag) 또는 금(Au)과 같은 금속으로 일정두께의 도금층이 더 형성될 수 있다. Here, the first surface (6a) of said ground ring 6 may be a plated layer having a predetermined thickness to form more of a metal, such as silver (Ag) or gold (Au).

또한, 상기 그라운드링(6) 및 칩탑재판(8)을 연결 및 지지하며, 대략 평면인 제1면(4a)과 제2면(4b)을 갖고, 상기 제1면(4a)과 제2면(4b) 사이에는 상기 제1면(4a)과 반대면인 동시에 상기 그라운드링(6)과 연결된 부분의 외측에는 제3면(4c)이 형성된 다수의 타이바(4)가 위치되어 있다. Further, the ground ring 6 and a connecting and supporting the chip mounting plate 8, has a substantially planar first surface (4a) and the second surface (4b), the first surface (4a) and the second if the outer side of the part (4b) between is coupled to the first surface (4a) and in the same time the ground ring 6 opposite surface has a plurality of tie bars 4, the third surface (4c) is formed, it is located. 여기서도, 상기 타이바(4)의 제1면(4a)에는 은(Ag) 또는 금(Au)과 같은 금속으로 일정두께의 도금층이 더 형성될 수도 있다. Here again, the first surface (4a) of the tie bars 4 may be a plated layer having a predetermined thickness to form more of a metal, such as silver (Ag) or gold (Au).

계속해서, 상기 그라운드링(6)의 외주연에는 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면(10a)과 제2면(10b)을 갖고, 상기 제1면(10a)과 제2면(10b) 사이에는 상기 제1면(10a)과 반대면인 동시에 상기 그라운드링(6)을 향하는 부분에 제3면(10c)이 형성된 다수의 리드(10)가 위치되어 있다. Then, the outer periphery of the ground ring (6) are arranged in a substantially radial, having a substantially planar first surface (10a) and the second surface (10b), said first surface (10a) and a second side (10b) is between the first and is the first surface (10a) and the other side which have the same number of lead 10. the third surface (10c) on the part facing the ground ring 6 formed position. 여기서도, 상기 리드(10)의 제1면(10a)에는 은(Ag) 또는 금(Au)과 같은 금속으로 일정두께의 도금층이 더 형성될 수도 있다. Here again, the first surface (10a) of the lead 10 may be a plating layer having a predetermined thickness to form more of a metal, such as silver (Ag) or gold (Au).

한편, 상기 칩탑재판(8)의 제1면(8a)에는 다수의 입출력패드(22)를 갖는 반도체칩(20)이 접착수단(28)으로 접착되어 있다. On the other hand, the first side (8a) of the chip mounting plate 8 has a semiconductor chip 20 having a plurality of input and output pads 22 are adhered to the adhesive means 28.

또한, 상기 반도체칩(20)의 입출력패드(22)와 상기 그라운드링(6) 및 리드(10)의 제1면(6a,10a)은 골드와이어 또는 알루미늄와이어와 같은도전성와이어(24)에 의해 기계적 및 전기적으로 상호 연결되어 있다. Further, the first surface (6a, 10a) of the input-output pad (22) and the ground ring 6 and the lead 10 of the semiconductor chip 20 by conductive wires 24 such as gold wires or aluminum wires mechanical and are electrically connected to each other.

여기서, 상기 리드(10)에 연결된 도전성와이어(24)는 전력 공급용 또는 신호용이고, 상기 그라운드링(6)에 연결된 도전성와이어(24)는 반도체칩(20)의 그라운드용이다. Here, the conductive wire 24 is a power supply for the signals or a conductive wire 24 connected to the ground ring (6) connected to the lead 10 is for the ground of the semiconductor chip 20.

또한, 상기 그라운드링(6)은 상기 제2면(6b)과 대응되는 제1면(6a)에만 도전성와이어(24)가 본딩될 수 있다. Further, the ground ring 6 may be the bonding the second surface (6b), the first surface (6a) only the conductive wires 24 corresponding to the. 이는 차후 설명하겠지만, 와이어 본딩시 그라운드링(6)의 바운싱(Bouncing) 현상을 최소화하기 위한 선택이다. This is selected to minimize the bouncing (Bouncing) phenomenon will be discussed later, when wire-bonding the ground ring (6).

또한, 상기 칩탑재판(8), 타이바(4), 그라운드링(6), 리드(10), 반도체칩(20) 및 도전성와이어(24)는 봉지재로 봉지되어 일정 형태의 봉지부(26)를 구성하고 있되, 상기 칩탑재판(8), 타이바(4), 그라운드링(6) 및 리드(10)의 제2면(8b, 4b,6b,10b)은 봉지부(26) 외측으로 노출되어 있다. Further, the chip-mounting plate (8), tie bars (4), the ground ring 6, leads 10, semiconductor chip 20 and the conductive wires 24 are sealed with a sealing material a certain shape of the seal portion ( 26) the itdoe and configuration, the second side (8b, 4b, 6b, 10b of the chip mounting board (8), tie bars 4, and a ground ring (6) and the lead 10) is a bag portion 26 It is exposed to the outside. 즉, 상기 칩탑재판(8), 타이바(4), 그라운드링(6) 및 리드(10)의 제1면(8a,4a,6a,10a), 제3면(8c,4c,6c,10c) 및 각각의 측면은 상기 봉지부(26) 내측에 위치되어 인터락킹(Inter-locking)되고, 상기 제2면(8b,4b,6b,10b)은 봉지부(26) 외측으로 노출됨으로써, 차후 마더보드에 실장 가능한 형태로 되어 있다. That is, the chip-mounting plate (8), tie bars 4, the first surface (8a, 4a, 6a, 10a) of the ground ring 6 and the lead 10, the third surface (8c, 4c, 6c, by 10c) and each side is inter-locking (inter-locking) is located inside the bag portion 26, the second side (8b, 4b, 6b, 10b) is exposed to the outside seal portion 26, It is mounted in a form for subsequent motherboard.

또한, 상기 봉지부(26) 외측으로 노출된 칩탑재판(8), 타이바(4), 그라운드링(6) 및 리드(10)의 제2면(8b,4b,6b,10b)에는 통상 구리(Cu), 금(Au), 솔더(Pb/Sn), 주석(Sn), 니켈(Ni), 팔라디엄(Pd) 또는 납땜 가능한 금속 등으로 일정 두께의 도금층(도시되지 않음)이 형성될 수 있다. Further, the seal portion 26, the second side (8b, 4b, 6b, 10b) for mounting the exposed chip to the outside plate (8), tie bars 4, and a ground ring (6) and the lead (10) for normal copper (Cu), gold (Au), solder (Pb / Sn), tin (Sn), nickel (Ni), Palladium plating layer having a predetermined thickness with (Pd) or a solderable metal or the like (not shown) is to be formed can.

통상 상기와 같은 반도체패키지(200)는 리드(10), 그라운드링(6) 및타이바(4)의 제2면(10b,6b,4b)이 마더보드의 소정 패턴에 실장되지만, 상기 반도체패키지(200)의 방열성능을 향상시키기 위해 상기 칩탑재판(8)의 제2면(8)도 상기 마더보드의 소정 패턴에 솔더 페이스트(Solder Paste)등으로 실장될 수 있다. The semiconductor package 200, such as a normally the lead 10, a ground ring (6) and tie bars (4) a but the second surface (10b, 6b, 4b) is mounted on the predetermined pattern of the mother board of the semiconductor package to improve the heat radiation performance of the 200 second side of the plate 8, the chip 8 can also be mounted in a solder paste (solder paste) in a predetermined pattern of the motherboard.

도4는 본 발명에 의한 반도패키지의 제조 방법을 도시한 순차 설명도이고, 도5a 내지 도5f는 도4에 따른 반도체패키지의 제조 상태를 도시한 상태도로서, 이를 각 단계별로 설명하면 다음과 같다. As Figure 4 shows manufacturing conditions of the semiconductor package according to Fig sequential explanatory view illustrating a method of manufacturing a semiconductive package according to the invention, Fig. 5a-5f is a four state diagram will be described it to each step as follows: .

1. 리드프레임 제공 단계(S1)로서, 도1a,1b,2a,2b 및 도5a에 도시된 것과 같은 리드프레임(100)을 제공한다. 1. As a lead frame providing step (S1), and provides a lead frame 100 as shown in Fig. 1a, 1b, 2a, 2b and 5a. 이러한 리드프레임(100)은 통상 금속 스트립(Metal Strip)의 화학적 ?? These chemical ?? of the lead frame 100 is typically a metal strip (Metal Strip) 에칭(Wet Etching)에 의해 형성된다. It is formed by etching (Wet Etching).

주지된 바와 같이, 화학적 에칭은 포토리토그래피(Photolithography), 포토레지스트(Photoresist) 그리고 금속 스트립에 패턴을 에칭하기 위한 화학 용액 등을 사용한다. As is known, chemical etching uses photolithography (Photolithography), photoresist (Photoresist) and the chemical solution or the like for etching a pattern on a metal strip. 일반적으로, 포트레지스트층은 스트립의 한면 또는 양면에 형성된다. Generally, the photoresist layer is formed on one side or both sides of the strip. 다음으로, 상기 포트레지스트층은 원하는 패턴이 그려진 마스크를 통하여 빛에 노출된다. Next, the photoresist layer is exposed to light through a mask, the desired pattern is drawn. 계속해서, 화학용액이 마스킹된 스트립의 한면 또는 양면에 적용된다. Next, apply to one or both sides of the chemical solution masking strip. 스트립의 노출된 영역은 에칭되어 제거되고, 금속 스트립에 원하는 패턴이 남게 된다. The exposed part of the strip is etched away, leaving a desired pattern on a metal strip.

통상, 2회에 걸친 에칭이 도1a,1b,2a,2b 및 도5a의 리드프레임을 형성하기 위해 수행된다. In general, it is carried out to form the etching over the second time the lead frame of FIG. 1a, 1b, 2a, 2b and 5a. 제1에칭은 스트립의 한면 또는 양면상에 포토레지스트 패턴을 따라서 스트립의 한면 또는 양면에 실시된다. The first etching is thus a photoresist pattern on one or both sides of the strip is carried on one or both sides of the strip. 이러한 제1에칭은 도1a에 도시된 바와 같이, 리드프레임(100)의 전체적 패턴을 형성하기 위해 금속 스트립의 소정 영역을 완전히 관통하여 실시된다. This first etch is conducted completely through the predetermined region of the metal strip to form the whole pattern of the lead frame 100, as shown in Figure 1a. 다음으로, 2번째 포토레지스트 패턴은 리드프레임(100) 한면의 일정 영역에 형성된다. Next, a second photoresist pattern is formed on a predetermined area of ​​the one-side lead frame 100. 칩탑재판(8)의 둘레 영역과, 그라운드링(6), 타이바(4) 및 리드(10)의 선택된 영역은 2번째 포토레지스트 패턴에 의해 감싸여지지 않고, 따라서 차후의 에칭에서 보다 많이 에칭된다. And the peripheral area of ​​the chip mounting plate 8, the ground ring (6), selected areas of the tie bars 4 and the lead 10 is without being enclosed by the second photoresist pattern, and thus a lot more from a subsequent etching It is etched. 제2에칭은 상기 2번째 포토레지스트 패턴을 따라서 리드프레임(100)의 한면에 부분적으로 실시된다. The second etching is carried out to the second photo-resist pattern according to the part on one side of the lead frame 100. 이러한 제2에칭은 도1b,2a,2b,5a에 도시된 리드프레임(100)의 함몰된 표면을 형성한다.(예를 들면, 칩탑재판(8)의 제3면(8c), 그라운드링(6)의 제3면(6c), 타이바(4)의 제3면(4c) 및 리드(10)의 제3면(10c)이 상기 제2에칭에 의해 형성된다) 상기 화학용액이 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)의 선택된 영역의 두께 및 선택된 거리를 에칭하였을 때, 상기 제2에칭은 중지된다. The second etching is also 1b, 2a, 2b, to form a recessed surface of the lead frame 100 shown in 5a. (E.g., the third side of the chip mounting board (8), (8c), the ground ring the third surface (10c) of the third side (6c), tie bars 4, the third surface (4c) and the lead 10 of is formed by the second etching) that the chemical solution chips 6 when etching the mounting plate 8, the ground ring 6, the thickness and the selected distance of the selected area of ​​the tie bars 4 and the lead 10, the second etching is stopped. 즉, 상기 제2에칭은 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)중 선택된 영역의 두께만큼 실시된다. That is, the second etching is carried out by a depth of the selected area of ​​the chip mounting plate 8, the ground ring 6, tie bars 4, and the lead 10. 이러한 제2에칭 단계에 의한 에칭량은 봉지부(26)에서 상기 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)가 안전하도록, 즉, 칩탑재판(8)의 제3면(8c), 그라운드링(6)의 제3면(6c), 타이바(4)의 제3면(4c) 및 리드(10)의 제3면(10c) 하부로 충분한 량의 봉지재 또는 봉지부가 형성될 정도로 실시된다. This second etching amount due to the etching steps, with the chips in the bag portion 26, plate 8, the ground ring 6, tie bars 4, and the lead 10 is to secure, that is, a chip mounting board ( 8) the third surface (8c), the ground ring 6, the third side (6c), tie bars 4, the third surface (4c) and the lead (10) the third surface (10c) sufficient to lower portions of the of the It is carried out to such an extent that part of the sealing material or the sealing capacity is formed. 일반적으로, 상기 제2에칭은 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10) 두께의 대략 50%를 제거하지만, 제거된 량은 상기 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10) 두께의 대략 25%에서 75% 범위일 수 있다. In general, the second etching is a chip mounting plate 8, the ground ring 6, tie bars 4, and the lead 10 to remove about 50% of the thickness, however, the removal amount with the chip plate (8 ), it may be a ground ring 6, tie bars 4, and the lead 10 is approximately 75% in the range 25% of the thickness. 에칭 과정의 불완전성으로 인해, 상기 각각의 제3면(4c,6c,8c,10c)은 평면이 아니고 근사적으로 평면에 가까울수 있으며, 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)의 측벽 각도도 90°가 아니고 원형의 코너를 이룰 수 있다. Because of imperfections in the etching process, each said third face (4c, 6c, 8c, 10c) is not a plane be close to the approximate plane, and the chip mounting plate 8, the ground ring 6, tie bar rather than 4, and the side wall angle of 90 ° of the lead 10 can form a corner of the round.

여기서, 상기 제1,2에칭은 순서가 바뀔 수도 있으며, 또한 상기 제1에칭에 의해서만 소정의 목적을 달성할 수도 있다. Here, the first and the second etching may be reversed, the order, may also achieve the desired purposes only by the first etching. 즉, 상기 제1에칭에 의해 총체적 리드(10) 패턴을 형성함은 물론, 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)를 소정 두께 이상으로 에칭하여 상기한 바와 같이 단면상 계단형의 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)를 구비할 수 있을 것이다. That is, forming a total lead 10 patterns by the first etching, as well as to a predetermined etching over the thickness of the chip mounting plate 8, the ground ring 6, tie bars 4, and the lead 10 It will be provided with a chip-mounting plate 8, the ground ring 6, tie bars 4, and the lead 10 of the step-like cross section, as described above.

선택적으로, 리드프레임은 리드프레임의 전체적 패턴을 스탬핑하는 제1단계와, 상기했듯이 리드프레임의 함몰된 표면까지 스탬핑된 리드프레임의 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)를 부분적으로 화학적 에칭하는 제2단계에 의해 형성될 수도 있다. Alternatively, the lead frame is a first step of stamping the overall pattern of the lead frame, the As of the lead frame stamped from the recessed surface of the lead frame, the chip mounting plate 8, the ground ring 6, tie bars (4 ) and it is in part the lead 10 may be formed by a second step of chemical etching.

2. 반도체칩 탑재 및 접착 단계(S2)로서, 도5b에 도시된 바와 같이 상면에 다수의 입출력패드(22)가 형성된 반도체칩(20)을 칩탑재판(8)의 제1면(8a) 중앙에 접착수단을 이용하여 접착한다. 2. The first surface of the semiconductor chip and a bonding step (S2), a plurality of input and output pad 22 is formed the semiconductor chip 20 to the chip mounting plate 8 on the upper surface as shown in Figure 5b (8a) It is bonded by using the adhesive means at the center. 칩탑재판(8) 상에 반도체칩(20)의 탑재와 접착은 통상적인 반도체칩 접착 장비와 통상적인 반도체칩 접착 에폭시를 이용하여 구현할 수 있다. Mounting and bonding the semiconductor chip 20 on the chip mounting plate 8 can be implemented using a conventional semiconductor chip, bonding equipment and a conventional semiconductor chip bonded epoxy.

상기 반도체칩 접착 단계와 차후의 조립 단계에서, 상기 리드프레임은 정전방전(ESD, ElectroStatic Discharge)으로부터 보호되도록 접지된다. In the assembling step of the semiconductor chip and the subsequent bonding step, the lead frame is grounded to protect against electrostatic discharge (ESD, ElectroStatic Discharge).

3. 와이어 본딩 단계(S3)로서, 도5c에 도시된 바와 같이 상기 반도체칩(20) 상면의 각 입출력패드(22)와 그라운드링(6)(또는 타이바(4)) 및 각 리드(10)의 제1면(6a,4a,10a)을 골드와이어(Au Wire) 또는 알루미늄와이어(Al Wire)와 같은 도전성와이어(24)로 또는 이것의 등가물을 이용하여 기계적 및 전기적으로 접속한다. 3. The wire bonding step as (S3), the semiconductor chip 20 and the ground ring, each input and output pads 22 of the top surface 6 (or the tie bars (4)), and each lead as shown in Figure 5c (10 ) and the first surface (6a, 4a, 10a) a gold wire (Au wire) or aluminum wire (Al wire) and connected mechanically and electrically using a conductive wire (or its equivalent to 24) of the same. 상기 제1면(6a,4a,10a)은 도전성와이어(24)와의 본딩력을 향상시키기 위해, 금(Au), 은(Ag), 니켈(Ni), 팔라디엄(Pd), 구리(Cu) 및 다른 금속들로 도금될 수 있다. It said first surface (6a, 4a, 10a) is to enhance the bonding force between the conductive wires 24, gold (Au), silver (Ag), nickel (Ni), Palladium (Pd), copper (Cu) and it may be plated with other metals. 이때, 상기 리드프레임은 정전방전에 의해 반도체칩(20)에 이상이 생기지 않도록 상기 본딩 공정 동안 접지된다. At this time, the lead frame is grounded during said bonding step so that due to electrostatic discharge that there is no more than the semiconductor chip 20.

또한, 이때 상기 리드프레임(100)은 통상 히트블럭(도시되지 않음) 상부에 위치하게 되는데, 상기 그라운드링(6)은 제2면(6b) 및 제3면(6c)이 대략 요철 형태로 되어 있음으로써, 상기 그라운드링(6)은 와이어 본딩중 바운싱(Bouncing) 현상 없이 상기 히트블럭 상에 고정된다. Also, where the leadframe 100 is typically a heat block (not shown) there is located at the top, the ground ring 6 has a second surface (6b) and the third surface (6c) is a substantially convex shape by that, the ground ring 6 is fixed on the heat block without bouncing phenomenon (bouncing) of wire bonding. 따라서, 상기 도전성와이어(24)는 상기 그라운드링(6)의 제1면(6a)에 안정적으로 본딩이 수행될 수 있다. Thus, the conductive wire 24 can be reliably bonded to the first surface (6a) of said ground ring 6 do. 바람직하기로, 상기 도전성와이어(24)는 상기 그라운드링(6)중 제2면(6b)(히트블럭에 접촉되는 면)과 대응되는 제1면(6a)에 본딩됨이 가장 효율적일 것이다. Preferably, the conductive wire 24 is the ground ring (6) of being the second side (6b) bonded to the first surface (6a) corresponding to the (surface in contact with the heat block) is the most efficient.

한편, 상기 그라운드링(6)에 본딩되는 도전성와이어(24)는 그라운드용이다. On the other hand, the conductive wires 24 bonded to the ground ring 6 is for ground. 즉, 반도체칩(20)의 입출력패드(22)중 그라운드용은 상기 도전성와이어(24)에 의해 상기 그라운드링(6) 또는 타이바(4)에 본딩된다. That is, for input and output of the pad 22 of the semiconductor chip 20 is bonded to the ground on the ground ring (6) or the tie bars 4 by means of the conductive wire 24. 물론, 상기 반도체칩(20)의 입출력패드(22)중 전력 공급용 또는 신호용은 상기 도전성와이어(24)에 의해 상기 리드(10)에 본딩된다. Of course, the input and output pads 22 of the power supply or for signals of the semiconductor chip 20 is bonded to the lead 10 by the conductive wires (24).

4. 봉지 단계(S4)로서, 도5d 및 도5e에 도시된 바와 같이 점착성 접착 봉지재가 상기 리드프레임상에 적용되어 일정 형태의 봉지부(26)를 형성한다. 4. The bag as step (S4), is applied onto the tacky adhesive sealing material of the lead frame as shown in Fig. 5d and Fig. 5e to form a predetermined shape of the seal portion 26. 상기 봉지부(26)는 다른 무엇보다도, 반도체칩(20), 도전성와이어(24), 칩탑재판(8) 제1면(8a), 제3면(8c) 및 측면, 그라운드링(6)의 제1면(6a), 제3면(6c) 및 측면, 타이바(4)의 제1면(4a), 제3면(4c) 및 측면, 리드(10)의 제1면(10a), 제3면(10c) 및 측면을 덮는다. The sealing section 26 First of all, the semiconductor chip 20 and the other, a conductive wire 24, the chip mounting plate 8, a first surface (8a), the third surface (8c) and a side surface, the ground ring 6 of the first surface (6a), the first surface (10a) of the third surface (6c) and side tie bars 4, the first surface (4a), the third surface (4c) and the side lead 10 of the , covering the third face (10c) and to the side. 칩탑재판(8)의 제2면(8b), 그라운드링(6)의 제2면(6b), 타이바(4)의 제2면(4b) 및 리드(10)의 제2면(10b)은 봉지부(26)에 의해 덮혀지지 않고 외부로 노출된다. The second surface of the chip mounting plate 8, a second side (8b), a ground ring (6) the second surface (6b), tie bars 4, the second surface (4b) and the lead 10 of the of (10b ) it is exposed to the outside without being covered with the seal portion (26).

상기와 같은 봉지 공정은 적용분야에 따라서 여러가지로 수행될 수 있다. Sealing process as described above may be performed in various ways according to the application. 예를 들면, 통상적인 플락스틱 봉지 기술을 이용하여 성취될 수 있다. For example, it may be accomplished using conventional sealing techniques Flac stick. 이와 같은 방법에서, 리드프레임은 금형내에 위치되고, 리드프레임의 상면에 봉지재에 의해 일정 형태의 봉지부가 형성된다. In such a method, the lead frame is placed in a mold, is added to a bag of predetermined shape formed by the sealing material on the top surface of the lead frame. 상기 봉지재는 통상적인 기술에 이용되는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)일 수 있다. It may be an epoxy molding compound (Epoxy Molding Compound) used in the encapsulant conventional techniques. 상기 에폭시 몰딩 컴파운드의 예는 일본의 니토사(Nitto Company)로부터 구할 수 있는 NITTO MP-8000AN 몰딩 컴파운드, 일본의 수미토모사(Sumitomo Company)로부터 구할 수 있는 EME 7351 UT 등이 있다. Examples of the epoxy molding compound can include EME UT 7351 that is available from NITTO MP-8000AN molding compound, which is available from Japanese Needle soil (Nitto Company), it can be simulated Mito (Sumitomo Company) in Japan. 통상적인 게이트가 봉지 공정을 원할히 할 수 있도록 리드프레임에 형성될 수 있다. Conventional gate may be formed on the lead frame to the sealing process smoothly. 금형의 측면은 봉지부(26)가 금형으로부터 용이하게 빠지도록 테이퍼(Taper)되어 있다. Side of the mold is tapered (Taper) to fall to facilitate the sealing portion 26 of the mold.

선택적으로, 상기 봉지 공정을 이용하는 대신, 액상 봉지재를 이용할 수 있다. Alternatively, instead of using the sealing process, it is possible to use a liquid sealing material. 예를 들면, 첫번째 단계로서 도5c의 리드프레임을 수평면에 위치시킨다. For example, as a first step thereby position the lead frame of Figure 5c to the horizontal plane. 두번째 단계로서, 캘리포니아, Dexter-Hysol Company of City of Industry로부터 구입할 수 있는 HYSOL 4451 에폭시와 같은 통상적인 경화 가능한 점착성 접착 재료의접촉성 비드(Bead)가 반도체칩(20) 주위 및 적어도 댐바(12) 내측의 소정 리드(10) 영역에 폐직사각 댐을 형성하도록 리드프레임상에 적용될 수 있다. As a second step, California, Dexter-Hysol Company of City of, such as HYSOL 4451 epoxy, available from Industry conventional curing contact between the bead (Bead) of the available viscous adhesive material is around and at least daemba 12, semiconductor chip 20 It can be applied on the lead frame so as to form a closed rectangular dam for a predetermined lead 10 of the inner area. 세번째 단계로서, 1시간동안 대략 140℃로 가열하는 것과 같은 공정에 의해 상기 댐을 경화시킨다. As a third step, to cure the dam by a process such as heating to approximately 140 ℃ for 1 hour. 네번째 단계로서, HYSOL 4450 액체 봉지재와 같은, 봉지부(26)를 형성하기에 적당한 통상적인 경화가능한 점착성 접착제가 상기 댐내에서 봉지된다. As a fourth step, a liquid sealing material 4450 HYSOL suitable conventional curable pressure-sensitive adhesive on to the same, to form a bag portion 26 and is sealed from the daemnae. 마지막 단계로서, 1시간동안 대략 140℃로 가열하는 것과 같은 공정에 의해 리드프레임상에 경화된 봉지부(26)가 경화 및 형성되도록 한다. As a final step, the seal portion 26 is cured on the lead frame by a process such as heating to approximately 140 ℃ for one hour so that the curing and forming.

상기와 같은 봉지 공정후에는 통상 상기 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)의 제2면(8b,6b,4b,10b)을 포함하는, 봉지부(26)로 덮혀지지 않은 리드프레임의 일정영역이 마더보드에 실장될 수 있는 통상적인 도금용 금속으로 도금될 수 있다. After the sealing process as described above, a bag containing typically the chip mounting plate 8, the ground ring 6, tie bars 4 and the second side (8b, 6b, 4b, 10b) of the lead 10 the constant regions of the lead frame that is not covered by portion 26 may be plated with conventional plating metal products which can be mounted on the motherboard. 도금용 금속의 예는 그 적용분야에 따라서 금, 니켈, 팔라디엄, 인코넬(Inconel), 납과 주석의 솔더 또는 탄탈륨(Tantalum) 등을 포함한다. Examples of the metal for plating is thus include gold, nickel, Palladium, Inconel (Inconel), lead and tin solder or tantalum (Tantalum) such that the field of application. 상기 단계는 리드프레임(100)을 형성하기 위해 사용된 금속이 도금 또는 예비 도금 등을 필요로 하지 않을 경우 생략될 수 있다. The step may be omitted if the metal used to form the lead frame 100 does not require plating or pre-plating. 예를 들어, 상기 단계는 리드프레임을 제조하기 위해 사용된 금속 스트립이 니켈 팔라디엄으로 도금된 구리일 경우 생략될 수 있다. For example, the step may be a metal strip used for producing the lead frame skipping if the copper plated with nickel Palladium.

5. 싱귤레이션 단계(S5)로서, 도5f에 도시된 바와 같이 봉지부(26)가 형성된 리드프레임을 절단한다. 5. As a singulation step (S5), and cutting the lead frame, the sealing part 26 formed as shown in Figure 5f. 즉, 댐바(12) 내측인 리드(10)의 일정 영역을 절단한다. That is, cutting the predetermined region of the daemba 12 inside the lead 10. 상기 절단은 리드(10)의 제2면(10b)을 완전히 관통하여 실시된다. The cutting is carried out by completely through the second side (10b) of the lead 10. 또한, 이어서 상기 봉지부(26) 외측의 타이바(4)도 절단한다. Further, the cutting is then also tie bars 4 of the outer seal portion (26). 상기와 같이 하여, 마침내 상기 리드프레임과 상기 봉지부(26) 사이에 위치된 모든 영역이 제거되고 완전한 반도체패키지가 얻어진다. As described above, until all the areas located between the lead frame and the sealing portion 26 is removed, and is obtained a complete semiconductor package.

상기 단계는 펀치, 톱, 또는 이와 동등한 절단 장치를 이용하여 실시될 수 있다. The step may be carried out using a punch, saw, or other equivalent cutting devices. 예를 들어, 상기 펀치나 톱은 봉지부(26) 외측에서 사용될 수 있다. For example, the punch or top may be used in the outer seal portion (26). 펀치가 사용된 경우, 완성된 반도패키지는 한번의 펀치 작동으로 리드프레임으로부터 완전하게 절단될 수 있다. If a punch is used, the finished Peninsula package can be completely cut from the lead frame with a single punching operation. 이는 통상 상기 리드프레임을 뒤집은 상태에서 펀치로 댐바(12)의 내측의 리드(10) 및 타이바(4)를 각각 절단함으로써 구현된다. This is achieved by cutting each of the inner leads 10 and the tie bars (4) of the daemba 12 to the punch in a state upside down of the normal of the lead frame. 절단 위치는 봉지부(26) 측면으로 연장되는 절단된 리드(10) 또는 타이바(4)의 영역이 0에서, 예를 들면 0.5mm에 이르기까지 변경될 수 있다. Cut position may be changed, from the area 0 of the lead 10 or the tie bars (4) extending in the cutting side of sealing section 26, for example to 0.5mm.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다. The present invention, as in the above will be possible, though has been described only the embodiments of the not limited to this, the embodiment in variously modified without departing from the scope and spirit of the invention.

따라서 본 발명에 의한 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법에 의하면, 그라운드용의 도전성와이어를 제1면, 제2면 및 제3면이 형성된 그라운드링중 제2면(와이어 본딩중 히터블럭에 접촉되는 면)과 대응하는 제1면에 본딩함으로써, 와이어 본딩중 그라운드링의 바운싱(Bouncing) 현상을 억제하는 효과가 있다. Therefore, in accordance with the present invention a lead frame and a semiconductor package and a manufacturing method using the same according to, among the electrically conductive wires for the ground first surface, a second surface and a formed on three sides the ground ring of the second surface (wire bonding heater block by surface bonding the first surface corresponding to a) in contact with, the effect of suppressing the bouncing (bouncing) phenomenon of the ground ring of wire bonding. 따라서, 와이어 본딩이 양호하게 수행되어 전체적인 와이어 본딩 수율이 향상되는 효과가 있다. Therefore, there is an effect that the wire bonding is performed satisfactorily improve the overall yield of the wire bonding.

즉, 종래에는 칩탑재판의 둘레면(제3면과 대응되는 제1면)에 본딩함으로써바운싱 현상에 의해 와이어 본딩 수율이 현저히 저하되었지만, 본 발명은 이와 반대로 와이어 본딩 수율이 현저히 향상된다. That is, conventionally, by bonding the (first surface corresponding to the third surface), the circumferential surface of the chip mounting board, but by the bouncing phenomenon wire-bonding yield is significantly reduced, the present invention is on the other hand a wire-bonding yield is remarkably improved.

또한, 본 발명은 칩탑재판 및 리드뿐만 아니라 그라운드링중 제1면 및 제3면이 봉지부 내측에 위치됨으로써, 특히 상기 칩탑재판과 봉지부 사이의 결합력이 더욱 향상된다. In addition, the present invention is the bonding force between the seal portion being located inside the first surface and the third surface of not only the chip mounting board and the lead ground ring, in particular the chip mounting board and the sealing portion is further improved. 즉, 종래에는 상기 칩탑재판의 제1면 및 제3면이 봉지부 내측에 위치되었지만, 본 발명은 상기 칩탑재판과 연결된 그라운드링의 제1면 및 제3면이 봉지부 내측에 더 위치됨으로써, 전체적으로 상기 칩탑재판과 봉지부와의 결합력이 더욱 향상되는 효과가 있다. That it is, in the prior art, but the first surface and the third surface of the chip mounting board positioned on the sealing portion inner side, the present invention is the first surface and the third surface of the ground ring is connected to the chip mounting board further position the sealing portion inner thereby, the overall effect of the bonding force with the chip mounting board and the sealing portion is further improved.

더불어, 반도체칩의 그라운드 신호를 처리하는 수단이 리드가 아닌 별도의 그라운드링이 됨으로써, 다수의 신호용 리드를 더 확보하는 효과가 있다. In addition, being a means for processing the signal ground of the semiconductor chip, a separate ground ring non-lead, this has the effect of further securing the plurality of signal lead.

즉, 반도체칩의 입출력패드 중 다수의 그라운드용 입출력패드를 도전성와이어를 이용하여 리드가 아닌 그라운드링에 모두 본딩함으로써, 그만큼 나머지 전력공급용 또는 신호용 입출력패드에 대한 리드를 확보하게 된다. That is, since both the input and output bonding pads of the plurality of input and output ground pads of the semiconductor chip to the ground ring and not the lid using a conductive wire, is so secure the lid on for the rest of the power supply or signal input and output pads.

따라서, 종래와 같이 파인피치화한 리드프레임을 제조하거나, 크기가 더 큰 리드프레임을 제조할 필요가 없다. Thus, producing a fine pitch by a lead frame as in the prior art, or it is not necessary to size the manufacture larger lead frame.

Claims (6)

  1. 대략 평판 모양의 프레임과; Frame of approximately plate-like and;
    상기 프레임 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과; And is positioned on the frame inner side, the ground ring substantially planar first surface and having a second surface, said first and second surfaces between is formed with a plurality of third side of the first surface and the opposite surface and;
    상기 그라운드링 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과; And is located in the ground ring inner side, on the periphery of the second side is at the same time substantially planar first and second surfaces of said first and second surfaces between, the first surface and the opposite surface have a third the chip mounting board and a surface formed;
    상기 프레임으로부터 내측으로 연장되어, 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와; Extending inwardly from said frame, said ground ring and chip and connecting and supporting the mounting plate, having a substantially planar first and second surfaces, in opposition to the first surface between the first and second surfaces a plurality of tie bars at the same time - surface having a third surface on the outside of the parts associated with the ground ring;
    상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드를 포함하여 이루어진 리드프레임. Which it is substantially radially arranged on the outer periphery of the ground ring, the substantially planar first surface and a having a second surface, the first surface and the said ground ring between the second surface is at the same time of the first surface and the opposite surface a lead frame comprising an plurality of leads are formed on the third surface facing portion.
  2. 제1항에 있어서, 상기 그라운드링과 상기 칩탑재판 사이에는 다수의 장공(長空)이 형성된 것을 특징으로 하는 리드프레임. The lead frame according to claim according to claim 1, wherein between said ground ring and said chip mounting board is formed with a plurality of elongated holes (長空).
  3. 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과; Having a substantially planar first and second surfaces, the first surface and the second surface is between the first surface and the opposite surface of the chip at the same time with claim 3 having a surface on the circumference of the second side plate and;
    상기 칩탑재판의 외주연에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과; And is located at the outer periphery of the chip mounting board, substantially planar first surface and a having a second surface, said first and second surfaces between, the first surface and the opposite surface of the plurality of the third surface is formed, the ground ring and;
    상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와; The ground ring and the connecting and supporting the chip mounting board and substantially planar first surface and a having a second surface, the first surface and the second among has the first surface opposite to the at the same time coupled to the ground ring face side a plurality of tie bar portions formed on the outer side of the third surface;
    상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드와; Which it is substantially radially arranged on the outer periphery of the ground ring, the substantially planar first surface and a having a second surface, the first surface and the said ground ring between the second surface is at the same time of the first surface and the opposite surface a plurality of leads are formed on the third surface facing portion;
    상기 칩탑재판의 제1면에 다수의 입출력패드를 가지며 접착수단으로 접착된 반도체칩과; It said chip having a plurality of input-output pads on the first surface of the plate adhered to the semiconductor chip and the adhesive means;
    상기 반도체칩의 입출력패드와 상기 그라운드링 및 리드의 제1면을 상호 기계적 및 전기적으로 연결하는 도전성와이어와; And conductive wires connecting a first side of the input-output pad and the ground ring and the lead of the semiconductor chip to each other mechanically and electrically;
    상기 칩탑재판, 타이바, 그라운드링, 리드, 반도체칩 및 도전성와이어가 봉지재로 봉지되어 있되, 상기 칩탑재판, 타이바, 그라운드링 및 리드의 제2면은 봉지부 외측으로 노출되도록 형성된 봉지부를 포함하여 이루어진 반도체패키지. Itdoe the chip-mounting plate, a tie-bar, the ground ring, the lead, the semiconductor chip and the conductive wires are sealed with a sealing material, the second surface of the chip mounting board, tie bars, the ground ring and the lead is formed so as to be exposed to the seal portion outwardly A semiconductor package comprising: a bag made in.
  4. 제3항에 있어서, 상기 그라운드링은 제2면과 대응되는 제1면에만 도전성와이어가 본딩된 것을 특징으로 하는 반도체패키지. 4. The method of claim 3, wherein the ground ring is a semiconductor package, characterized in that the conductive wires only to a first surface on which the second surface and the corresponding bonding.
  5. 대략 평판 모양의 프레임과, 상기 프레임 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과, 상기 그라운드링 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과, 상기 프레임으로부터 내측으로 연장되어, 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와, 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 And it is located in the substantially flat-shaped frame and the frame inner side of said first and second surfaces between, the first surface and the opposite surface of the plurality of the third has substantially planar first and second surfaces, ground ring surface formed with, and is located on the ground ring inside, having a substantially planar first and second surfaces, said first and second surfaces between, the said first both a first surface and the opposite surface second side periphery to the chip mounting board is formed on three sides of and extending inwardly from said frame, and connected to and supporting said ground ring and the chip mounting board, having a substantially planar first surface and a second surface, wherein first and between the first and second surfaces has been substantially radially arranged on the outer periphery of the first surface and the opposite surface which have the same number of tie bars, the ground having a third surface on the outside of the parts associated with the ground ring , having a substantially planar first surface and a second surface, wherein 1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드를 포함하여 이루어진 리드프레임을 제공하는 단계와; Comprising the steps of: providing a lead frame made by the section at the same time of the first surface and the other side facing the ground ring including a plurality of leads are formed between the third surface and second surfaces;
    상기 칩탑재판의 제1면에 접착수단을 이용하여 다수의 입출력패드가 형성된 반도체칩을 접착하는 단계와; Comprising the steps of: bonding a plurality of semiconductor chip input and output pads are formed using the adhesive means on the first surface of the chip mounting board;
    상기 반도체칩의 입출력패드와 상기 그라운드링 및 리드의 제1면을 도전성와이어를 이용하여 기계적 및 전기적으로 본딩하는 단계와; The step of bonding a first surface of the input pad and the ground ring and the lead of the semiconductor chip mechanically and electrically with the conductive wires and;
    상기 칩탑재판, 타이바, 그라운드링, 리드, 반도체칩 및 도전성와이어를 봉지재로 봉지하되, 상기 칩탑재판, 타이바, 그라운드링 및 리드의 제2면은 외측으로 노출되도록 봉지부를 형성하는 단계와; The chip-mounting plate, a tie-bar, the ground ring, the lead, but sealing the semiconductor chip and the conductive wires with a sealing material, the chip mounting board, tie bars, ground second surface of the ring and the lead is forming the bag so as to be exposed to the outside step;
    상기 프레임에서 상기 리드 및 타이바의 외측을 소잉하여 낱개의 반도체패키지로 싱귤레이션하는 단계를 포함하여 이루어진 반도체패키지의 제조 방법. The process for manufacturing a semiconductor package made, including the step of singulating the semiconductor package by a singulated by sawing the outer side of the lead and the tie bars in the frame.
  6. 제5항에 있어서, 상기 와이어 본딩 단계는 도전성와이어가 상기 그라운드링의 제2면과 대응되는 제1면에 본딩되도록 함을 특징으로 하는 반도체패키지의 제조 방법. The method of claim 5 wherein said wire bonding step for manufacturing a semiconductor package, characterized in that the electrically conductive wire that is bonded to a first surface corresponding to the second side of the ground ring.
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Families Citing this family (148)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6639308B1 (en) 1999-12-16 2003-10-28 Amkor Technology, Inc. Near chip size semiconductor package
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
JP4417541B2 (en) * 2000-10-23 2010-02-17 ローム株式会社 Semiconductor device and manufacturing method thereof
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100369393B1 (en) 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 Lead frame and semiconductor package using it and its manufacturing method
US20070108609A1 (en) * 2001-07-19 2007-05-17 Samsung Electronics Co., Ltd. Bumped chip carrier package using lead frame and method for manufacturing the same
KR100445072B1 (en) * 2001-07-19 2004-08-21 삼성전자주식회사 Bumped chip carrier package using lead frame and method for manufacturing the same
JP4054188B2 (en) * 2001-11-30 2008-02-27 富士通株式会社 Semiconductor device
JP3939554B2 (en) * 2002-01-15 2007-07-04 シャープ株式会社 Semiconductor lead frame
US6798046B1 (en) * 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
EP1470587A1 (en) * 2002-02-01 2004-10-27 Infineon Technologies AG A lead frame
US6838751B2 (en) * 2002-03-06 2005-01-04 Freescale Semiconductor Inc. Multi-row leadframe
SG105544A1 (en) * 2002-04-19 2004-08-27 Micron Technology Inc Ultrathin leadframe bga circuit package
US6818973B1 (en) * 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US7135760B2 (en) * 2002-09-30 2006-11-14 St Assembly Test Services Ltd. Moisture resistant integrated circuit leadframe package
US7042071B2 (en) 2002-10-24 2006-05-09 Matsushita Electric Industrial Co., Ltd. Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US8188584B1 (en) 2002-11-08 2012-05-29 Amkor Technology, Inc. Direct-write wafer level chip scale package
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US20040124508A1 (en) * 2002-11-27 2004-07-01 United Test And Assembly Test Center Ltd. High performance chip scale leadframe package and method of manufacturing the package
US8129222B2 (en) * 2002-11-27 2012-03-06 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
SG157957A1 (en) * 2003-01-29 2010-01-29 Interplex Qlp Inc Package for integrated circuit die
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6927483B1 (en) * 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US20040227216A1 (en) * 2003-05-16 2004-11-18 Mortan Robert F. Flex resistant semiconductor die pad, leadframe, and package
TWI250632B (en) * 2003-05-28 2006-03-01 Siliconware Prec Ind Co Ltd Ground-enhancing semiconductor package and lead frame
US7049683B1 (en) * 2003-07-19 2006-05-23 Ns Electronics Bangkok (1993) Ltd. Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound
KR100983304B1 (en) 2003-08-22 2010-09-20 삼성테크윈 주식회사 Lead frame, semiconductor package manufactured by applying same, and manufacturing method of semiconductor package
US7102209B1 (en) * 2003-08-27 2006-09-05 National Semiconductor Corporation Substrate for use in semiconductor manufacturing and method of making same
KR100568225B1 (en) * 2003-11-06 2006-04-07 삼성전자주식회사 Lead Frame and method for fabricating semiconductor package using the same
US7144517B1 (en) * 2003-11-07 2006-12-05 Amkor Technology, Inc. Manufacturing method for leadframe and for semiconductor package using the leadframe
US7315077B2 (en) * 2003-11-13 2008-01-01 Fairchild Korea Semiconductor, Ltd. Molded leadless package having a partially exposed lead frame pad
US7215009B1 (en) * 2004-02-23 2007-05-08 Altera Corporation Expansion plane for PQFP/TQFP IR—package design
US7060536B2 (en) * 2004-05-13 2006-06-13 St Assembly Test Services Ltd. Dual row leadframe and fabrication method
US8536688B2 (en) * 2004-05-25 2013-09-17 Stats Chippac Ltd. Integrated circuit leadframe and fabrication method therefor
JP4525277B2 (en) * 2004-09-30 2010-08-18 ルネサスエレクトロニクス株式会社 Semiconductor device
US7217991B1 (en) * 2004-10-22 2007-05-15 Amkor Technology, Inc. Fan-in leadframe semiconductor package
US7387916B2 (en) * 2004-12-02 2008-06-17 Texas Instruments Incorporated Sharp corner lead frame
US7671474B2 (en) * 2005-02-23 2010-03-02 Nxp B.V. Integrated circuit package device with improved bond pad connections, a lead-frame and an electronic device
TWM279015U (en) * 2005-04-26 2005-10-21 Lingsen Precision Ind Ltd Metal leadframes for integrated circuits with different thickness of pins
US7504733B2 (en) * 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
US7968377B2 (en) * 2005-09-22 2011-06-28 Stats Chippac Ltd. Integrated circuit protruding pad package system
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US20070132075A1 (en) * 2005-12-12 2007-06-14 Mutsumi Masumoto Structure and method for thin single or multichip semiconductor QFN packages
US7816186B2 (en) * 2006-03-14 2010-10-19 Unisem (Mauritius) Holdings Limited Method for making QFN package with power and ground rings
US7446375B2 (en) * 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
US7671463B2 (en) * 2006-03-30 2010-03-02 Stats Chippac Ltd. Integrated circuit package system with ground ring
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7556987B2 (en) * 2006-06-30 2009-07-07 Stats Chippac Ltd. Method of fabricating an integrated circuit with etched ring and die paddle
US20080036078A1 (en) * 2006-08-14 2008-02-14 Ciclon Semiconductor Device Corp. Wirebond-less semiconductor package
US8422243B2 (en) * 2006-12-13 2013-04-16 Stats Chippac Ltd. Integrated circuit package system employing a support structure with a recess
US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7834435B2 (en) 2006-12-27 2010-11-16 Mediatek Inc. Leadframe with extended pad segments between leads and die pad, and leadframe package using the same
TWI385774B (en) * 2007-12-26 2013-02-11 Mediatek Inc Leadframe package and leadframe
US8124461B2 (en) * 2006-12-27 2012-02-28 Mediatek Inc. Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
US8089166B2 (en) * 2006-12-30 2012-01-03 Stats Chippac Ltd. Integrated circuit package with top pad
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
WO2008100247A1 (en) * 2007-02-12 2008-08-21 Agere Systems Inc. A quad flat no lead (qfn) integrated circuit (ic) package having a modified paddle and method for designing the package
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
TWI337387B (en) * 2007-04-20 2011-02-11 Chipmos Technologies Inc Leadframe for leadless package, package structure and manufacturing method using the same
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US8283757B2 (en) * 2007-07-18 2012-10-09 Mediatek Inc. Quad flat package with exposed common electrode bars
SG149724A1 (en) * 2007-07-24 2009-02-27 Micron Technology Inc Semicoductor dies with recesses, associated leadframes, and associated systems and methods
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7948066B2 (en) * 2007-12-26 2011-05-24 Stats Chippac Ltd. Integrated circuit package system with lead locking structure
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8569872B2 (en) * 2008-07-01 2013-10-29 Stats Chippac Ltd. Integrated circuit package system with lead-frame paddle scheme for single axis partial saw isolation
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) * 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
JP5493323B2 (en) * 2008-09-30 2014-05-14 凸版印刷株式会社 Manufacturing method of lead frame type substrate
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8049312B2 (en) * 2009-01-12 2011-11-01 Texas Instruments Incorporated Semiconductor device package and method of assembly thereof
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8383962B2 (en) * 2009-04-08 2013-02-26 Marvell World Trade Ltd. Exposed die pad package with power ring
US8810015B2 (en) * 2009-06-14 2014-08-19 STAT ChipPAC Ltd. Integrated circuit packaging system with high lead count and method of manufacture thereof
US8551820B1 (en) * 2009-09-28 2013-10-08 Amkor Technology, Inc. Routable single layer substrate and semiconductor package including same
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
JP5255009B2 (en) * 2010-02-26 2013-08-07 ルネサスエレクトロニクス株式会社 Semiconductor device
US8492887B2 (en) * 2010-03-25 2013-07-23 Stats Chippac Ltd. Integrated circuit packaging system with leadframe and method of manufacture thereof
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8409922B2 (en) * 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US8404524B2 (en) * 2010-09-16 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with paddle molding and method of manufacture thereof
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
KR101796116B1 (en) 2010-10-20 2017-11-10 삼성전자 주식회사 Semiconductor device, memory module and memory system having the same and operating method thereof
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8377750B2 (en) * 2010-12-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with multiple row leads and method of manufacture thereof
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
JP5562874B2 (en) 2011-01-12 2014-07-30 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
KR101250529B1 (en) * 2011-06-08 2013-04-03 에스티에스반도체통신 주식회사 QFN(Quad Flat No-leads) package and the method of fabricating the same
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US8633575B1 (en) * 2012-05-24 2014-01-21 Amkor Technology, Inc. IC package with integrated electrostatic discharge protection
KR101398016B1 (en) * 2012-08-08 2014-05-30 앰코 테크놀로지 코리아 주식회사 Lead frame package and manufacturing method thereof
DE102012215449A1 (en) * 2012-08-31 2014-03-27 Osram Opto Semiconductors Gmbh Housing for an electronic component, electronic module, method for manufacturing a housing for an electronic component and method for producing an electronic module
KR101486790B1 (en) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 Micro Lead Frame for semiconductor package
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9000570B2 (en) * 2013-07-11 2015-04-07 Freescale Semiconductor, Inc. Semiconductor device with corner tie bars
CN104425392A (en) * 2013-08-27 2015-03-18 优博创新科技有限公司 Cavity package with pre-molded substrate
KR101563911B1 (en) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 Semiconductor package
TW201539674A (en) * 2014-04-10 2015-10-16 Chipmos Technologies Inc Quad flat no-lead package and manufacturing method thereof
JP6483498B2 (en) * 2014-07-07 2019-03-13 ローム株式会社 Electronic device and its mounting structure
US9704785B2 (en) * 2015-01-14 2017-07-11 Mediatek Inc. Semiconductor package with die paddle
US9728510B2 (en) 2015-04-10 2017-08-08 Analog Devices, Inc. Cavity package with composite substrate
CN106129035A (en) * 2015-05-05 2016-11-16 飞思卡尔半导体公司 There is the exposed pad formula ic package of moulded locking
KR20170015632A (en) * 2015-07-29 2017-02-09 엘지디스플레이 주식회사 Organic light emitting display device
US9337140B1 (en) * 2015-09-01 2016-05-10 Freescale Semiconductor, Inc. Signal bond wire shield
JP6352876B2 (en) * 2015-09-15 2018-07-04 東芝メモリ株式会社 Manufacturing method of semiconductor device
JP6603538B2 (en) * 2015-10-23 2019-11-06 新光電気工業株式会社 Lead frame and manufacturing method thereof
US10043739B2 (en) * 2015-10-30 2018-08-07 Shinko Electric Industries Co., Ltd. Semiconductor device and leadframe
US9966652B2 (en) * 2015-11-03 2018-05-08 Amkor Technology, Inc. Packaged electronic device having integrated antenna and locking structure
TWI557183B (en) 2015-12-16 2016-11-11 Ind Tech Res Inst Silicon siloxane composition, and the optoelectronic device which comprises
CN105470234B (en) * 2016-01-12 2017-12-22 气派科技股份有限公司 A kind of SOT23 lead frames and its packaging technology flow
JP1603175S (en) * 2017-10-19 2018-05-07

Family Cites Families (379)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2596993A (en) 1949-01-13 1952-05-20 United Shoe Machinery Corp Method and mold for covering of eyelets by plastic injection
US3435815A (en) 1966-07-15 1969-04-01 Micro Tech Mfg Inc Wafer dicer
US3734660A (en) 1970-01-09 1973-05-22 Tuthill Pump Co Apparatus for fabricating a bearing device
US4189342A (en) 1971-10-07 1980-02-19 U.S. Philips Corporation Semiconductor device comprising projecting contact layers
US3838984A (en) 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
US4054238A (en) 1976-03-23 1977-10-18 Western Electric Company, Inc. Method, apparatus and lead frame for assembling leads with terminals on a substrate
JPS6131627B2 (en) 1977-12-07 1986-07-21 Kyushu Nippon Electric
US4332537A (en) 1978-07-17 1982-06-01 Dusan Slepcevic Encapsulation mold with removable cavity plates
JPS639378B2 (en) 1978-08-02 1988-02-29 Hitachi Ltd
US4221925A (en) 1978-09-18 1980-09-09 Western Electric Company, Incorporated Printed circuit board
JPS5588356A (en) 1978-12-27 1980-07-04 Hitachi Ltd Semiconductor device
US4289922A (en) 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame
JPS5745959A (en) 1980-09-02 1982-03-16 Nec Corp Resin-sealed semiconductor device
US4417266A (en) 1981-08-14 1983-11-22 Amp Incorporated Power and ground plane structure for chip carrier
US4451224A (en) 1982-03-25 1984-05-29 General Electric Company Mold device for making plastic articles from resin
FR2524707B1 (en) 1982-04-01 1985-05-31 Cit Alcatel Method for encapsulating semiconductor components, and encapsulated components obtained
US4646710A (en) 1982-09-22 1987-03-03 Crystal Systems, Inc. Multi-wafer slicing with a fixed abrasive
JPS59227143A (en) 1983-06-07 1984-12-20 Dainippon Printing Co Ltd Package of integrated circuit
JPS60195957A (en) 1984-03-19 1985-10-04 Hitachi Ltd Lead frame
US4737839A (en) 1984-03-19 1988-04-12 Trilogy Computer Development Partners, Ltd. Semiconductor chip mounting system
JPH0612796B2 (en) 1984-06-04 1994-02-16 株式会社日立製作所 Semiconductor device
JPS6139555A (en) 1984-07-31 1986-02-25 Toshiba Corp Resin sealed type semiconductor device with heat sink
US4862246A (en) 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
US4862245A (en) 1985-04-18 1989-08-29 International Business Machines Corporation Package semiconductor chip
JPS629639A (en) 1985-07-05 1987-01-17 Nec Yamagata Ltd Manufacture of semiconductor device
US4727633A (en) 1985-08-08 1988-03-01 Tektronix, Inc. Method of securing metallic members together
US4756080A (en) 1986-01-27 1988-07-12 American Microsystems, Inc. Metal foil semiconductor interconnection method
US4812896A (en) 1986-11-13 1989-03-14 Olin Corporation Metal electronic package sealed with thermoplastic having a grafted metal deactivator and antioxidant
US5087961A (en) 1987-01-28 1992-02-11 Lsi Logic Corporation Semiconductor device package
JPS63205935A (en) 1987-02-23 1988-08-25 Toshiba Corp Resin-sealed type semiconductor device equipped with heat sink
KR960006710B1 (en) 1987-02-25 1996-05-22 미다 가쓰시게 Surface mount plastic package semiconductor integrated circuit and the manufacturing method thereof and well asmount struct
JP2509607B2 (en) 1987-03-23 1996-06-26 株式会社東芝 Resin-sealed semiconductor device
US5059379A (en) 1987-07-20 1991-10-22 Mitsubishi Denki Kabushiki Kaisha Method of resin sealing semiconductor devices
US4942454A (en) 1987-08-05 1990-07-17 Mitsubishi Denki Kabushiki Kaisha Resin sealed semiconductor device
KR890702161A (en) 1987-08-26 1989-12-23 다니이 아끼오 Integrated circuit device and a method of manufacturing the same
JPH01106456A (en) 1987-10-19 1989-04-24 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
US4987475A (en) 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
US4907067A (en) 1988-05-11 1990-03-06 Texas Instruments Incorporated Thermally efficient power device package
US5096852A (en) 1988-06-02 1992-03-17 Burr-Brown Corporation Method of making plastic encapsulated multichip hybrid integrated circuits
EP0424530B1 (en) 1988-07-08 1996-10-02 Oki Electric Industry Company, Limited Resin-sealed semiconductor device
US4935803A (en) 1988-09-09 1990-06-19 Motorola, Inc. Self-centering electrode for power devices
US5277972B1 (en) 1988-09-29 1996-11-05 Tomoegawa Paper Co Ltd Adhesive tapes
EP0361975B1 (en) 1988-09-29 1995-05-24 Tomoegawa Paper Co. Ltd. Adhesive tapes
US5057900A (en) 1988-10-17 1991-10-15 Semiconductor Energy Laboratory Co., Ltd. Electronic device and a manufacturing method for the same
US5018003A (en) 1988-10-20 1991-05-21 Mitsubishi Denki Kabushiki Kaisha Lead frame and semiconductor device
US5266834A (en) 1989-03-13 1993-11-30 Hitachi Ltd. Semiconductor device and an electronic device with the semiconductor devices mounted thereon
US5070039A (en) 1989-04-13 1991-12-03 Texas Instruments Incorporated Method of making an integrated circuit using a pre-served dam bar to reduce mold flash and to facilitate flash removal
US4999700A (en) 1989-04-20 1991-03-12 Honeywell Inc. Package to board variable pitch tab
JPH0558655B2 (en) 1989-05-22 1993-08-27 Tokyo Shibaura Electric Co
FR2659157B2 (en) 1989-05-26 1994-09-30 Lemaire Gerard Process for manufacturing a so-called card smart card, and board obtained by such process.
US5417905A (en) 1989-05-26 1995-05-23 Esec (Far East) Limited Method of making a card having decorations on both faces
EP0405755B1 (en) 1989-05-31 1995-11-29 Fujitsu Limited Pin grid array packaging structure
WO1993017457A1 (en) 1989-07-01 1993-09-02 Ryo Enomoto Substrate for mounting semiconductor and method of producing the same
JPH0671062B2 (en) 1989-08-30 1994-09-07 株式会社東芝 Resin-sealed semiconductor device
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5041902A (en) 1989-12-14 1991-08-20 Motorola, Inc. Molded electronic package with compression structures
US5151039A (en) 1990-04-06 1992-09-29 Advanced Interconnections Corporation Integrated circuit adapter having gullwing-shaped leads
JP2540652B2 (en) 1990-06-01 1996-10-09 株式会社東芝 Semiconductor device
AT186795T (en) 1990-07-21 1999-12-15 Mitsui Chemicals Inc A semiconductor device having a package
EP0509065A4 (en) 1990-08-01 1994-02-09 Staktek Corporation
US5029386A (en) 1990-09-17 1991-07-09 Hewlett-Packard Company Hierarchical tape automated bonding method
US5335771A (en) 1990-09-25 1994-08-09 R. H. Murphy Company, Inc. Spacer trays for stacking storage trays with integrated circuits
US5391439A (en) 1990-09-27 1995-02-21 Dai Nippon Printing Co., Ltd. Leadframe adapted to support semiconductor elements
US5298685A (en) 1990-10-30 1994-03-29 International Business Machines Corporation Interconnection method and structure for organic circuit boards
US5216278A (en) 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5157480A (en) 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5172214A (en) 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5118298A (en) 1991-04-04 1992-06-02 Advanced Interconnections Corporation Through hole mounting of integrated circuit adapter leads
US5281849A (en) 1991-05-07 1994-01-25 Singh Deo Narendra N Semiconductor package with segmented lead frame
US5168368A (en) 1991-05-09 1992-12-01 International Business Machines Corporation Lead frame-chip package with improved configuration
US5172213A (en) 1991-05-23 1992-12-15 At&T Bell Laboratories Molded circuit package having heat dissipating post
US5221642A (en) 1991-08-15 1993-06-22 Staktek Corporation Lead-on-chip integrated circuit fabrication method
JP2658661B2 (en) 1991-09-18 1997-09-30 日本電気株式会社 A method for manufacturing a multilayer printed wiring board
JP2518569B2 (en) 1991-09-19 1996-07-24 三菱電機株式会社 Semiconductor device
US5200809A (en) 1991-09-27 1993-04-06 Vlsi Technology, Inc. Exposed die-attach heatsink package
US5332864A (en) 1991-12-27 1994-07-26 Vlsi Technology, Inc. Integrated circuit package having an interposer
JPH06120374A (en) 1992-03-31 1994-04-28 Amkor Electron Inc Semiconductor package structure, semiconductor packaging method, and heat radiation plate for the semiconductor package
US5250841A (en) 1992-04-06 1993-10-05 Motorola, Inc. Semiconductor device with test-only leads
JP3177060B2 (en) 1992-04-13 2001-06-18 株式会社リコー Reversible thermosensitive recording label and card
US5539251A (en) 1992-05-11 1996-07-23 Micron Technology, Inc. Tie bar over chip lead frame design
US5214845A (en) 1992-05-11 1993-06-01 Micron Technology, Inc. Method for producing high speed integrated circuits
US5639990A (en) 1992-06-05 1997-06-17 Mitsui Toatsu Chemicals, Inc. Solid printed substrate and electronic circuit package using the same
US5278446A (en) 1992-07-06 1994-01-11 Motorola, Inc. Reduced stress plastic package
US5285352A (en) 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
JPH0637202A (en) 1992-07-20 1994-02-10 Mitsubishi Electric Corp Package for microwave ic
JPH0653394A (en) 1992-07-28 1994-02-25 Shinko Electric Ind Co Ltd Plane support for multilayer lead frame
GB9216079D0 (en) 1992-07-28 1992-09-09 Foseco Int Lining of molten metal handling vessel
US5592025A (en) 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
KR0128251Y1 (en) 1992-08-21 1998-10-15 문정환 Lead exposed type semiconductor device
JPH0692076A (en) 1992-09-16 1994-04-05 Oki Electric Ind Co Ltd Lead frame form for ic card module
US5608267A (en) 1992-09-17 1997-03-04 Olin Corporation Molded plastic semiconductor package including heat spreader
JP2670408B2 (en) 1992-10-27 1997-10-29 株式会社東芝 Resin-sealed semiconductor device and a manufacturing method thereof
US5859471A (en) 1992-11-17 1999-01-12 Shinko Electric Industries Co., Ltd. Semiconductor device having tab tape lead frame with reinforced outer leads
US5409362A (en) 1992-11-24 1995-04-25 Neu Dynamics Corp. Encapsulation molding equipment
US5406124A (en) 1992-12-04 1995-04-11 Mitsui Toatsu Chemicals, Inc. Insulating adhesive tape, and lead frame and semiconductor device employing the tape
US5457340A (en) * 1992-12-07 1995-10-10 Integrated Device Technology, Inc. Leadframe with power and ground planes
JPH06196603A (en) 1992-12-23 1994-07-15 Shinko Electric Ind Co Ltd Manufacture of lead frame
KR960009089B1 (en) 1993-03-04 1996-07-10 문정환 Mold for package molding and plastic charge-coupled device and the manufacturing method using the mold
JPH06268101A (en) 1993-03-17 1994-09-22 Hitachi Ltd Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US5327008A (en) 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
US5358905A (en) 1993-04-02 1994-10-25 Texas Instruments Incorporated Semiconductor device having die pad locking to substantially reduce package cracking
US5474958A (en) 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
KR0152901B1 (en) 1993-06-23 1998-10-01 문정환 Plastic package and method for manufacture thereof
JP2526787B2 (en) 1993-07-01 1996-08-21 日本電気株式会社 The semiconductor device for Li - Dofure - No
JPH0730051A (en) 1993-07-09 1995-01-31 Fujitsu Ltd Semiconductor device
JP2875139B2 (en) 1993-07-15 1999-03-24 株式会社東芝 A method of manufacturing a semiconductor device
US5336931A (en) 1993-09-03 1994-08-09 Motorola, Inc. Anchoring method for flow formed integrated circuit covers
US6326678B1 (en) * 1993-09-03 2001-12-04 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US5641997A (en) 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5414299A (en) 1993-09-24 1995-05-09 Vlsi Technology, Inc. Semi-conductor device interconnect package assembly for improved package performance
US5517056A (en) 1993-09-30 1996-05-14 Motorola, Inc. Molded carrier ring leadframe having a particular resin injecting area design for gate removal and semiconductor device employing the same
US5467252A (en) 1993-10-18 1995-11-14 Motorola, Inc. Method for plating using nested plating buses and semiconductor device having the same
US5545923A (en) 1993-10-22 1996-08-13 Lsi Logic Corporation Semiconductor device assembly with minimized bond finger connections
US5452511A (en) 1993-11-04 1995-09-26 Chang; Alexander H. C. Composite lead frame manufacturing method
KR960011206B1 (en) 1993-11-09 1996-08-21 김광호 Word-line driving circuit of semiconductor memory device
JP3289162B2 (en) 1993-11-12 2002-06-04 本田技研工業株式会社 Method punching cast of casting parts
JPH07142627A (en) 1993-11-18 1995-06-02 Fujitsu Ltd Semiconductor device and manufacture thereof
US5521429A (en) 1993-11-25 1996-05-28 Sanyo Electric Co., Ltd. Surface-mount flat package semiconductor device
US5673479A (en) 1993-12-20 1997-10-07 Lsi Logic Corporation Method for mounting a microelectronic circuit peripherally-leaded package including integral support member with spacer
US5434057A (en) * 1994-02-02 1995-07-18 Quidel Corporation Sperm motility assay and devices
US5637922A (en) 1994-02-07 1997-06-10 General Electric Company Wireless radio frequency power semiconductor devices using high density interconnect
US5821457A (en) 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
KR970010676B1 (en) 1994-03-29 1997-06-30 문정환 Package and the lead frame thereof
JPH07288309A (en) 1994-04-19 1995-10-31 Mitsubishi Electric Corp Semiconductor device, manufacture thereof and semiconductor module
US5701034A (en) 1994-05-03 1997-12-23 Amkor Electronics, Inc. Packaged semiconductor die including heat sink with locking feature
JP3243116B2 (en) 1994-05-17 2002-01-07 株式会社日立製作所 Semiconductor device
US5544412A (en) 1994-05-24 1996-08-13 Motorola, Inc. Method for coupling a power lead to a bond pad in an electronic module
US5429992A (en) 1994-05-25 1995-07-04 Texas Instruments Incorporated Lead frame structure for IC devices with strengthened encapsulation adhesion
US5766972A (en) 1994-06-02 1998-06-16 Mitsubishi Denki Kabushiki Kaisha Method of making resin encapsulated semiconductor device with bump electrodes
JPH07335783A (en) 1994-06-13 1995-12-22 Fujitsu Ltd Semiconductor device and semiconductor device unit
JPH07335804A (en) 1994-06-14 1995-12-22 Dainippon Printing Co Ltd Lead frame and its manufacture
US5604376A (en) 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
JPH0837252A (en) 1994-07-22 1996-02-06 Nec Corp Semiconductor device
US5454905A (en) 1994-08-09 1995-10-03 National Semiconductor Corporation Method for manufacturing fine pitch lead frame
KR0145768B1 (en) 1994-08-16 1998-08-01 김광호 Method for manufacturing a semiconductor package using lead frame
US5723899A (en) 1994-08-30 1998-03-03 Amkor Electronics, Inc. Semiconductor lead frame having connection bar and guide rings
US5508556A (en) 1994-09-02 1996-04-16 Motorola, Inc. Leaded semiconductor device having accessible power supply pad terminals
US5543657A (en) 1994-10-07 1996-08-06 International Business Machines Corporation Single layer leadframe design with groundplane capability
US5581122A (en) 1994-10-25 1996-12-03 Industrial Technology Research Institute Packaging assembly with consolidated common voltage connections for integrated circuits
JP3475306B2 (en) 1994-10-26 2003-12-08 大日本印刷株式会社 Method for manufacturing a resin-sealed semiconductor device
US5665996A (en) 1994-12-30 1997-09-09 Siliconix Incorporated Vertical power mosfet having thick metal layer to reduce distributed resistance
US5767546A (en) 1994-12-30 1998-06-16 Siliconix Incorporated Laternal power mosfet having metal strap layer to reduce distributed resistance
US5528076A (en) 1995-02-01 1996-06-18 Motorola, Inc. Leadframe having metal impregnated silicon carbide mounting area
JPH08222681A (en) 1995-02-14 1996-08-30 Toshiba Corp Resin sealed semiconductor device
JP2679681B2 (en) 1995-04-28 1997-11-19 日本電気株式会社 The semiconductor device package and a manufacturing method thereof for a semiconductor device
JPH08306853A (en) 1995-05-09 1996-11-22 Fujitsu Ltd Semiconductor device, manufacture thereof and manufacture of lead frame
KR0163526B1 (en) 1995-05-17 1999-02-01 김광호 Semiconductor device fabrication method involving formation step of protection layer on a contact pad by irradiate ultraviolet rays/ozone
US6323550B1 (en) 1995-06-06 2001-11-27 Analog Devices, Inc. Package for sealing an integrated circuit die
JPH098205A (en) 1995-06-14 1997-01-10 Dainippon Printing Co Ltd Resin sealed semiconductor device
JPH098206A (en) 1995-06-19 1997-01-10 Dainippon Printing Co Ltd Lead frame and bga resin sealed semiconductor device
JPH098207A (en) 1995-06-21 1997-01-10 Dainippon Printing Co Ltd Resin sealed semiconductor device
US5650663A (en) 1995-07-03 1997-07-22 Olin Corporation Electronic package with improved thermal properties
US5745984A (en) 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
JP3170182B2 (en) 1995-08-15 2001-05-28 株式会社東芝 Resin-sealed semiconductor device and a manufacturing method thereof
TW359880B (en) 1995-08-30 1999-06-01 Samsung Electronics Co Ltd Method of manufacturing semiconductor chip package
US6239384B1 (en) 1995-09-18 2001-05-29 Tessera, Inc. Microelectric lead structures with plural conductors
JP3163961B2 (en) 1995-09-22 2001-05-08 日立電線株式会社 Semiconductor device
JP3123638B2 (en) 1995-09-25 2001-01-15 株式会社三井ハイテック Semiconductor device
JPH0992776A (en) 1995-09-28 1997-04-04 Mitsubishi Electric Corp Lead frame and semiconductor device
JP3292798B2 (en) 1995-10-04 2002-06-17 三菱電機株式会社 Semiconductor device
US5801440A (en) 1995-10-10 1998-09-01 Acc Microelectronics Corporation Chip package board having utility rings
US5696666A (en) 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
JP3426811B2 (en) 1995-10-18 2003-07-14 株式会社東芝 Semiconductor device and manufacturing method thereof
JP3176542B2 (en) 1995-10-25 2001-06-18 シャープ株式会社 Semiconductor device and manufacturing method thereof
US5854511A (en) 1995-11-17 1998-12-29 Anam Semiconductor, Inc. Semiconductor package including heat sink with layered conductive plate and non-conductive tape bonding to leads
KR100214463B1 (en) 1995-12-06 1999-08-02 구본준 Lead frame of clip type and method manufacture of the package
KR0167297B1 (en) 1995-12-18 1998-12-15 문정환 L.o.c package and the manufacturing method thereof
US5689135A (en) 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5646831A (en) 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
KR0179803B1 (en) 1995-12-29 1999-03-20 문정환 Lead-exposured semiconductor package
KR0157929B1 (en) 1995-12-30 1999-01-15 문정환 Semiconductor package molding apparatus of multi-layer mold type
US5661088A (en) 1996-01-11 1997-08-26 Motorola, Inc. Electronic component and method of packaging
US5866939A (en) 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
US5760465A (en) 1996-02-01 1998-06-02 International Business Machines Corporation Electronic package with strain relief means
US5977613A (en) 1996-03-07 1999-11-02 Matsushita Electronics Corporation Electronic component, method for making the same, and lead frame and mold assembly for use therein
JPH09260575A (en) 1996-03-22 1997-10-03 Mitsubishi Electric Corp Semiconductor device and lead frame
JPH09260538A (en) 1996-03-27 1997-10-03 Miyazaki Oki Electric Co Ltd Resin sealed semiconductor device manufacturing method and its mounting structure
JPH09260568A (en) 1996-03-27 1997-10-03 Mitsubishi Electric Corp Semiconductor device and its manufacture
KR100220154B1 (en) 1996-04-01 1999-09-01 김규현 Method manufacture of semiconductor package
US6169329B1 (en) 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5776798A (en) 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
US5902959A (en) 1996-09-05 1999-05-11 International Rectifier Corporation Lead frame with waffled front and rear surfaces
US5886397A (en) 1996-09-05 1999-03-23 International Rectifier Corporation Crushable bead on lead finger side surface to improve moldability
US5854512A (en) 1996-09-20 1998-12-29 Vlsi Technology, Inc. High density leaded ball-grid array package
US5736432A (en) 1996-09-20 1998-04-07 National Semiconductor Corporation Lead frame with lead finger locking feature and method for making same
US5817540A (en) 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
DE69635518D1 (en) 1996-09-30 2006-01-05 St Microelectronics Srl Plastic package for electronic arrangements
JP3012816B2 (en) 1996-10-22 2000-02-28 松下電子工業株式会社 Resin-sealed semiconductor device and a manufacturing method thereof
US5814884C1 (en) 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die
US6072228A (en) 1996-10-25 2000-06-06 Micron Technology, Inc. Multi-part lead frame with dissimilar materials and method of manufacturing
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
JP2936062B2 (en) 1996-11-11 1999-08-23 富士通株式会社 A method of manufacturing a semiconductor device
US5856911A (en) 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
EP0844665A3 (en) 1996-11-21 1999-10-27 Texas Instruments Incorporated Wafer level packaging
US5814881A (en) 1996-12-20 1998-09-29 Lsi Logic Corporation Stacked integrated chip package and method of making same
US5977615A (en) 1996-12-24 1999-11-02 Matsushita Electronics Corporation Lead frame, method of manufacturing lead frame, semiconductor device and method of manufacturing semiconductor device
KR20040045045A (en) 1996-12-26 2004-05-31 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device
JP3538290B2 (en) 1997-01-09 2004-06-14 株式会社ルネサステクノロジ Wiring members and the lead frame having the same
US5894108A (en) 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US5994166A (en) 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US6201292B1 (en) 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
KR100230515B1 (en) 1997-04-04 1999-11-15 윤종용 Method for producting lead frame with uneven surface
US6271582B1 (en) 1997-04-07 2001-08-07 Micron Technology, Inc. Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
US5986885A (en) 1997-04-08 1999-11-16 Integrated Device Technology, Inc. Semiconductor package with internal heatsink and assembly method
KR100235308B1 (en) 1997-06-30 1999-12-15 윤종용 A semiconductor chip package having twice bent tie bar and small die pad
US6025640A (en) 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
EP0895287A3 (en) 1997-07-31 2006-04-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and lead frame for the same
US6359221B1 (en) 1997-08-04 2002-03-19 Dai Nippon Insatsu Kabushiki Kaisha Resin sealed semiconductor device, circuit member for use therein
US5889318A (en) 1997-08-12 1999-03-30 Micron Technology, Inc. Lead frame including angle iron tie bar and method of making the same
US5977630A (en) 1997-08-15 1999-11-02 International Rectifier Corp. Plural semiconductor die housed in common package with split heat sink
JP3638771B2 (en) 1997-12-22 2005-04-13 沖電気工業株式会社 Semiconductor device
JP4098864B2 (en) 1997-12-26 2008-06-11 東北リコー株式会社 Paper discharge device
JPH11233712A (en) 1998-02-12 1999-08-27 Hitachi Ltd Semiconductor device, its manufacture and electric apparatus using the semiconductor device
US6130473A (en) 1998-04-02 2000-10-10 National Semiconductor Corporation Lead frame chip scale package
KR100260997B1 (en) 1998-04-08 2000-07-01 마이클 디. 오브라이언 Semiconductor package
JPH11307719A (en) 1998-04-20 1999-11-05 Mitsubishi Electric Corp Semiconductor device
JP3420057B2 (en) 1998-04-28 2003-06-23 株式会社東芝 Resin-sealed semiconductor device
US6335564B1 (en) 1998-05-06 2002-01-01 Conexant Systems, Inc. Single Paddle having a semiconductor device and a passive electronic component
JP3562311B2 (en) 1998-05-27 2004-09-08 松下電器産業株式会社 Method for fabricating a lead frame and resin-sealed semiconductor device
JP2000049184A (en) 1998-05-27 2000-02-18 Hitachi Ltd Semiconductor device and production thereof
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6933594B2 (en) 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6635957B2 (en) 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6294100B1 (en) 1998-06-10 2001-09-25 Asat Ltd Exposed die leadless plastic chip carrier
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6585905B1 (en) 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6194777B1 (en) 1998-06-27 2001-02-27 Texas Instruments Incorporated Leadframes with selective palladium plating
US6201186B1 (en) 1998-06-29 2001-03-13 Motorola, Inc. Electronic component assembly and method of making the same
US6297548B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
JP2000022044A (en) 1998-07-02 2000-01-21 Mitsubishi Electric Corp Semiconductor device and its manufacture
SE512710C2 (en) 1998-07-08 2000-05-02 Ericsson Telefon Ab L M Capsule for högeffekttransistorchip for high frequencies including an electrically and thermally conductive flange
US6084297A (en) 1998-09-03 2000-07-04 Micron Technology, Inc. Cavity ball grid array apparatus
US6222259B1 (en) 1998-09-15 2001-04-24 Hyundai Electronics Industries Co., Ltd. Stack package and method of fabricating the same
SG88741A1 (en) 1998-09-16 2002-05-21 Texas Instr Singapore Pte Ltd Multichip assembly semiconductor
US6373127B1 (en) 1998-09-29 2002-04-16 Texas Instruments Incorporated Integrated capacitor on the back of a chip
US6421013B1 (en) 1999-10-04 2002-07-16 Amerasia International Technology, Inc. Tamper-resistant wireless article including an antenna
US6281568B1 (en) 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
US6339255B1 (en) 1998-10-24 2002-01-15 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chips in a single semiconductor package
US6285075B1 (en) 1998-11-02 2001-09-04 Asat, Limited Integrated circuit package with bonding planes on a ceramic ring using an adhesive assembly
US6211462B1 (en) 1998-11-05 2001-04-03 Texas Instruments Incorporated Low inductance power package for integrated circuits
DE19851070A1 (en) 1998-11-05 2000-05-18 Wacker Siltronic Halbleitermat Method for simultaneous separation of several discs of brittle, hard workpiece; involves rotating workpiece and using wire saw
US6184465B1 (en) 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
JP2000164788A (en) 1998-11-20 2000-06-16 Anam Semiconductor Inc Lead frame for semiconductor package and semiconductor package using the lead frame and its manufacture
US6310386B1 (en) 1998-12-17 2001-10-30 Philips Electronics North America Corp. High performance chip/package inductor integration
JP3169919B2 (en) 1998-12-21 2001-05-28 九州日本電気株式会社 Ball grid array type semiconductor device and a manufacturing method thereof
JP3512657B2 (en) 1998-12-22 2004-03-31 シャープ株式会社 Semiconductor device
KR100379835B1 (en) 1998-12-31 2003-06-19 앰코 테크놀로지 코리아 주식회사 The semiconductor package and a method of manufacturing the same
JP3560488B2 (en) 1999-01-29 2004-09-02 ユナイテッド マイクロエレクトロニクス コープUnited Microelectronics Corp. Chip scale package for multi-chip
US6377464B1 (en) 1999-01-29 2002-04-23 Conexant Systems, Inc. Multiple chip module with integrated RF capabilities
US6075700A (en) 1999-02-02 2000-06-13 Compaq Computer Corporation Method and system for controlling radio frequency radiation in microelectronic packages using heat dissipation structures
US6208020B1 (en) 1999-02-24 2001-03-27 Matsushita Electronics Corporation Leadframe for use in manufacturing a resin-molded semiconductor device
TW413874B (en) 1999-04-12 2000-12-01 Siliconware Prec Ind Co Ltd BGA semiconductor package having exposed heat dissipation layer and its manufacturing method
US6184573B1 (en) 1999-05-13 2001-02-06 Siliconware Precision Industries Co., Ltd. Chip packaging
JP3398721B2 (en) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド Semiconductor package and a method of manufacturing the same
TW409377B (en) 1999-05-21 2000-10-21 Siliconware Prec Ind Co Ltd Small scale ball grid array package
US6256200B1 (en) 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
US6258629B1 (en) * 1999-08-09 2001-07-10 Amkor Technology, Inc. Electronic device package and leadframe and method for making the package
TW423133B (en) 1999-09-14 2001-02-21 Advanced Semiconductor Eng Manufacturing method of semiconductor chip package
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
US6388336B1 (en) 1999-09-15 2002-05-14 Texas Instruments Incorporated Multichip semiconductor assembly
JP3691993B2 (en) 1999-10-01 2005-09-07 新光電気工業株式会社 Semiconductor device and manufacturing method thereof, carrier substrate and manufacturing method thereof
KR100526844B1 (en) * 1999-10-15 2005-11-08 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method
KR20010037254A (en) * 1999-10-15 2001-05-07 마이클 디. 오브라이언 Semiconductor package
JP2001127246A (en) 1999-10-29 2001-05-11 Fujitsu Ltd Semiconductor device
US7253503B1 (en) 1999-11-05 2007-08-07 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
TW429494B (en) 1999-11-08 2001-04-11 Siliconware Prec Ind Co Ltd Quad flat non-leaded package
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
KR100421774B1 (en) 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method
JP2001177051A (en) 1999-12-20 2001-06-29 Toshiba Corp Semiconductor device and system apparatus
US6198171B1 (en) 1999-12-30 2001-03-06 Siliconware Precision Industries Co., Ltd. Thermally enhanced quad flat non-lead package of semiconductor
KR20010058583A (en) 1999-12-30 2001-07-06 마이클 디. 오브라이언 Lead End Grid Array Semiconductor package
US6333252B1 (en) 2000-01-05 2001-12-25 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6559525B2 (en) 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
JP3420153B2 (en) * 2000-01-24 2003-06-23 Necエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6342730B1 (en) 2000-01-28 2002-01-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6261864B1 (en) 2000-01-28 2001-07-17 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6306685B1 (en) 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
US6238952B1 (en) 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6399415B1 (en) 2000-03-20 2002-06-04 National Semiconductor Corporation Electrical isolation in panels of leadless IC packages
US6384472B1 (en) 2000-03-24 2002-05-07 Siliconware Precision Industries Co., Ltd Leadless image sensor package structure and method for making the same
KR100583494B1 (en) 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 Semiconductor package
US6444499B1 (en) 2000-03-30 2002-09-03 Amkor Technology, Inc. Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components
US6355502B1 (en) 2000-04-25 2002-03-12 National Science Council Semiconductor package and method for making the same
TW466720B (en) 2000-05-22 2001-12-01 Siliconware Prec Ind Co Ltd Semiconductor package with flash-prevention structure and manufacture method
JP2001351929A (en) 2000-06-09 2001-12-21 Hitachi Ltd Semiconductor device and its manufacturing method
US6404043B1 (en) 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US6483178B1 (en) 2000-07-14 2002-11-19 Siliconware Precision Industries Co., Ltd. Semiconductor device package structure
JP2002033441A (en) 2000-07-14 2002-01-31 Mitsubishi Electric Corp Semiconductor device
JP2002043503A (en) 2000-07-25 2002-02-08 Nec Kyushu Ltd Semiconductor device
KR100414479B1 (en) 2000-08-09 2004-01-07 주식회사 코스타트반도체 Implantable circuit tapes for implanted semiconductor package and method for manufacturing thereof
US6429508B1 (en) 2000-08-09 2002-08-06 Kostat Semiconductor Co., Ltd. Semiconductor package having implantable conductive lands and method for manufacturing the same
US6400004B1 (en) 2000-08-17 2002-06-04 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package
SG87194A1 (en) 2000-08-17 2002-03-19 Samsung Techwin Co Ltd Lead frame and method of manufacturing the lead frame
US20020024122A1 (en) 2000-08-25 2002-02-28 Samsung Electronics Co., Ltd. Lead frame having a side ring pad and semiconductor chip package including the same
US6611048B1 (en) * 2000-08-25 2003-08-26 Skyworks Solutions, Inc. Exposed paddle leadframe for semiconductor die packaging
JP2002076228A (en) 2000-09-04 2002-03-15 Dainippon Printing Co Ltd Resin-sealed semiconductor device
US6624005B1 (en) 2000-09-06 2003-09-23 Amkor Technology, Inc. Semiconductor memory cards and method of making same
TW508774B (en) 2000-09-15 2002-11-01 Samsung Techwin Co Ltd Lead frame, semiconductor package having the same, method of manufacturing semiconductor package, molding plates and molding machine for manufacturing semiconductor package
TW462121B (en) 2000-09-19 2001-11-01 Siliconware Prec Ind Co Ltd Heat sink type ball grid array package
KR100402822B1 (en) 2000-09-21 2003-10-22 이희영 Mandibular angle retractor
JP3923716B2 (en) 2000-09-29 2007-06-06 株式会社東芝 Semiconductor device
JP2002118222A (en) 2000-10-10 2002-04-19 Rohm Co Ltd Semiconductor device
US6476474B1 (en) 2000-10-10 2002-11-05 Siliconware Precision Industries Co., Ltd. Dual-die package structure and method for fabricating the same
JP3649111B2 (en) 2000-10-24 2005-05-18 株式会社村田製作所 RF module and an electronic device using the same using a high-frequency circuit board and it
US6459148B1 (en) 2000-11-13 2002-10-01 Walsin Advanced Electronics Ltd QFN semiconductor package
US6337510B1 (en) 2000-11-17 2002-01-08 Walsin Advanced Electronics Ltd Stackable QFN semiconductor package
TW458377U (en) 2000-11-23 2001-10-01 Siliconware Prec Ind Co Ltd Sensor structure of quad flat package without external leads
US20020140081A1 (en) 2000-12-07 2002-10-03 Young-Huang Chou Highly integrated multi-layer circuit module having ceramic substrates with embedded passive devices
KR20020049944A (en) 2000-12-20 2002-06-26 박종섭 semiconductor package and method for fabricating the same
US6464121B2 (en) 2000-12-21 2002-10-15 Xerox Corporation Specialized tool adapted for a process for manufacture and interconnection between adjoining printed wiring boards
US6507120B2 (en) 2000-12-22 2003-01-14 Siliconware Precision Industries Co., Ltd. Flip chip type quad flat non-leaded package
KR100731007B1 (en) 2001-01-15 2007-06-22 앰코 테크놀로지 코리아 주식회사 stack-type semiconductor package
TW473951B (en) 2001-01-17 2002-01-21 Siliconware Prec Ind Co Ltd Non-leaded quad flat image sensor package
US6348726B1 (en) * 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
JP4731021B2 (en) 2001-01-25 2011-07-20 ローム株式会社 Semiconductor device manufacturing method and semiconductor device
US6518089B2 (en) 2001-02-02 2003-02-11 Texas Instruments Incorporated Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US6815324B2 (en) 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
JP2002252297A (en) 2001-02-23 2002-09-06 Hitachi Ltd Electronic circuit device using multilayer circuit board
US6661083B2 (en) 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
JP2004519916A (en) 2001-03-02 2004-07-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィKoninklijke Philips Electronics N.V. Module and electronic device
US6545347B2 (en) * 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100369393B1 (en) * 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 Lead frame and semiconductor package using it and its manufacturing method
US6603196B2 (en) 2001-03-28 2003-08-05 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
US20020158318A1 (en) 2001-04-25 2002-10-31 Chen Hung Nan Multi-chip module
JP3666411B2 (en) 2001-05-07 2005-06-29 ソニー株式会社 High-frequency module device
US6437429B1 (en) 2001-05-11 2002-08-20 Walsin Advanced Electronics Ltd Semiconductor package with metal pads
US6686649B1 (en) 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
US20030006055A1 (en) 2001-07-05 2003-01-09 Walsin Advanced Electronics Ltd Semiconductor package for fixed surface mounting
US6482680B1 (en) 2001-07-20 2002-11-19 Carsem Semiconductor Sdn, Bhd. Flip-chip on lead frame
US6380048B1 (en) 2001-08-02 2002-04-30 St Assembly Test Services Pte Ltd Die paddle enhancement for exposed pad in semiconductor packaging
SG120858A1 (en) 2001-08-06 2006-04-26 Micron Technology Inc Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same
US6740427B2 (en) 2001-09-21 2004-05-25 Intel Corporation Thermo-mechanically robust C4 ball-limiting metallurgy to prevent failure due to die-package interaction and method of making same
US6713311B2 (en) * 2001-09-25 2004-03-30 Texas Instruments Incorporated Method for screening semiconductor devices for contact coplanarity
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
TW510034B (en) 2001-11-15 2002-11-11 Siliconware Prec Ind Co Ltd Ball grid array semiconductor package
JP2003179099A (en) 2001-12-12 2003-06-27 Toshiba Corp Semiconductor device and method of manufacturing the same
DE10201781B4 (en) 2002-01-17 2007-06-06 Infineon Technologies Ag High frequency power device and high frequency power module and method of making the same
EP1470587A1 (en) 2002-02-01 2004-10-27 Infineon Technologies AG A lead frame
JP2003243595A (en) 2002-02-19 2003-08-29 Hamada Technos:Kk Semiconductor device with incorporated passive component
US6838751B2 (en) 2002-03-06 2005-01-04 Freescale Semiconductor Inc. Multi-row leadframe
US20030198032A1 (en) 2002-04-23 2003-10-23 Paul Collander Integrated circuit assembly and method for making same
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6696644B1 (en) 2002-08-08 2004-02-24 Texas Instruments Incorporated Polymer-embedded solder bumps for reliable plastic package attachment
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
TW563233B (en) 2002-09-11 2003-11-21 Advanced Semiconductor Eng Process and structure for semiconductor package
US6972481B2 (en) 2002-09-17 2005-12-06 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US7053476B2 (en) 2002-09-17 2006-05-30 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US7064426B2 (en) 2002-09-17 2006-06-20 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US20040061213A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US7205647B2 (en) 2002-09-17 2007-04-17 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US6838761B2 (en) 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US20040080025A1 (en) 2002-09-17 2004-04-29 Shinko Electric Industries Co., Ltd. Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same
JP2004158753A (en) 2002-11-08 2004-06-03 Sony Corp Lead frame material, manufacturing method, and semiconductor device and manufacturing method
US20040089926A1 (en) 2002-11-12 2004-05-13 Taiwan Ic Packaging Corporation Ultra thin semiconductor device
TWI290757B (en) 2002-12-30 2007-12-01 Advanced Semiconductor Eng Thermal enhance MCM package and the manufacturing method thereof
JP4245370B2 (en) 2003-02-21 2009-03-25 大日本印刷株式会社 Manufacturing method of semiconductor device
JP2005011838A (en) 2003-06-16 2005-01-13 Toshiba Corp Semiconductor device and its assembling method
US7102209B1 (en) 2003-08-27 2006-09-05 National Semiconductor Corporation Substrate for use in semiconductor manufacturing and method of making same
US7245007B1 (en) 2003-09-18 2007-07-17 Amkor Technology, Inc. Exposed lead interposer leadframe package
US7015571B2 (en) 2003-11-12 2006-03-21 Advanced Semiconductor Engineering, Inc. Multi-chips module assembly package
US7053469B2 (en) 2004-03-30 2006-05-30 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package and manufacturing method thereof
JP2006120935A (en) 2004-10-22 2006-05-11 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
KR100652397B1 (en) 2005-01-17 2006-12-01 삼성전자주식회사 Stack type semiconductor package using an interposer print circuit board
US20060216868A1 (en) 2005-03-25 2006-09-28 Advanced Semiconductor Engineering Inc. Package structure and fabrication thereof
JP4520355B2 (en) 2005-04-19 2010-08-04 パナソニック株式会社 Semiconductor module
US7683266B2 (en) 2005-07-29 2010-03-23 Sanyo Electric Co., Ltd. Circuit board and circuit apparatus using the same
JP4426518B2 (en) 2005-10-11 2010-03-03 東京エレクトロン株式会社 Processing equipment
JP5129473B2 (en) 2005-11-15 2013-01-30 富士フイルム株式会社 Radiation detector
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
TWI335070B (en) 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
JP5166992B2 (en) 2008-06-25 2013-03-21 積水化学工業株式会社 Fireproof coating structure
JP5283460B2 (en) 2008-09-11 2013-09-04 喜義 工藤 Pillow
JP5745959B2 (en) 2011-07-08 2015-07-08 日本放送協会 OFDM transmitter and receiver for wireless microphone

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US7928542B2 (en) 2011-04-19
US7521294B2 (en) 2009-04-21
US7170150B2 (en) 2007-01-30
US20020140061A1 (en) 2002-10-03
US20040159918A1 (en) 2004-08-19
KR20020076017A (en) 2002-10-09
US20090166842A1 (en) 2009-07-02
US6713322B2 (en) 2004-03-30
US20060289973A1 (en) 2006-12-28
US20110140250A1 (en) 2011-06-16

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