KR100369393B1 - Lead frame and semiconductor package using it and its manufacturing method - Google Patents

Lead frame and semiconductor package using it and its manufacturing method Download PDF

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Publication number
KR100369393B1
KR100369393B1 KR10-2001-0015966A KR20010015966A KR100369393B1 KR 100369393 B1 KR100369393 B1 KR 100369393B1 KR 20010015966 A KR20010015966 A KR 20010015966A KR 100369393 B1 KR100369393 B1 KR 100369393B1
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KR
South Korea
Prior art keywords
ground ring
mounting plate
chip mounting
plane
lead
Prior art date
Application number
KR10-2001-0015966A
Other languages
Korean (ko)
Other versions
KR20020076017A (en
Inventor
이형주
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR10-2001-0015966A priority Critical patent/KR100369393B1/en
Priority to US10/013,160 priority patent/US6713322B2/en
Publication of KR20020076017A publication Critical patent/KR20020076017A/en
Application granted granted Critical
Publication of KR100369393B1 publication Critical patent/KR100369393B1/en
Priority to US10/774,893 priority patent/US7170150B2/en
Priority to US11/510,544 priority patent/US7521294B2/en
Priority to US12/399,600 priority patent/US7928542B2/en
Priority to US13/036,359 priority patent/US8102037B2/en

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

이 발명은 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법에 관한 것으로, 칩탑재판에 그라운드용의 와이어를 본딩시 그 칩탑재판의 바운싱(Bouncing) 현상을 억제하고, 또한 칩탑재판 등이 봉지부에서 이탈되지 않도록, 리드프레임의 칩탑재판 외주연에 그라운드링을 더 형성시키되, 상기 그라운드링은 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성되도록 한 리드프레임과, 상기 리드프레임이 이용된 반도체패키지 및 그 제조 방법을 특징으로 함.The present invention relates to a lead frame, a semiconductor package using the same, and a method of manufacturing the same. When the ground wire is bonded to the chip mounting board, the chipping board is prevented from bouncing and the chip mounting board is encapsulated. A ground ring is further formed on the outer periphery of the chip mounting plate of the lead frame, so that the ground ring has a first plane and a second plane that are substantially planar, and between the first and second surfaces. And a lead frame configured to form a plurality of third surfaces opposite to the first surface, a semiconductor package using the lead frame, and a method of manufacturing the same.

Description

리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법{Lead frame and semiconductor package using it and its manufacturing method}Lead frame and semiconductor package using same and manufacturing method thereof {Lead frame and semiconductor package using it and its manufacturing method}

본 발명은 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 MLF(Micro LeadFrame)형 반도체패키지에 이용되는 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법에 관한 것이다.The present invention relates to a lead frame, a semiconductor package using the same, and a method of manufacturing the same, and more particularly, to a lead frame used in a MLF (Micro LeadFrame) type semiconductor package, a semiconductor package using the same, and a method of manufacturing the same.

일반적으로 반도체패키지용 리드프레임이란 구리(Cu), 구리 합금(Cu Alloy), 합금 37(니켈(Ni)37%, 철(Fe)55%) 등의 연속된 금속 스트립(Strip)을 기계적 스탬핑(Stamping)이나 화학적 에칭(Etching) 방법에 의해 제조한 것으로, 그 역할은 반도체칩과 외부 회로(예를 들면, 마더보드)를 연결시켜 주는 전선(Lead) 역할과 반도체패키지를 마더보드(Mother Board)에 고정시켜 주는 버팀대(Frame)의 역할을 동시에 수행하는 것을 말한다.In general, a lead frame for a semiconductor package is a mechanical stamping of continuous metal strips such as copper (Cu), copper alloy (Cu Alloy), and alloy 37 (37% nickel (55% nickel) and 55% iron (Fe)). Manufactured by stamping or chemical etching method, its role is to connect the semiconductor chip and external circuit (for example, the motherboard) and the semiconductor package to the mother board It is to simultaneously perform the role of the frame that is fixed to the frame.

이러한 종래의 리드프레임중 MLF형 반도체패키지(200')에 이용되는 리드프레임(100')이 도6a 및 도6b에 도시되어 있으며, 이를 참조하여 종래의 리드프레임(100') 구조를 설명하면 다음과 같다.Among the conventional lead frames, the lead frame 100 ′ used for the MLF type semiconductor package 200 ′ is shown in FIGS. 6A and 6B. Referring to this, the structure of the conventional lead frame 100 ′ will be described below. Same as

먼저 도6a에 도시된 바와 같이 대략 판상의 사각 프레임(2')이 구비되어 있고, 상기 프레임(2')의 내측으로는 다수의 타이바(4')가 연장되어 있으며, 상기 타이바(4')에는 대략 사각판상의 칩탑재판(8')이 연결 및 지지되어 있다. 또한, 상기 칩탑재판(8')의 외주연에는 다수의 리드(10')가 대략 방사상으로 배열되어 있으며, 상기 모든 리드(10')는 상기 리드(10')와 대략 수직 방향으로 형성된 댐바(12')에 연결되어 있다. 상기 댐바(12')는 양끝단이 상기 프레임(2')에 연결되어 있고, 또한 상기 댐바(12')는 다수의 지지용 리드(14')에 연결되어 있다. 더불어, 상기 지지용 리드(14')는 상기 프레임(2')에 연결되어 있다.First, as shown in FIG. 6A, a substantially plate-shaped rectangular frame 2 ′ is provided, and a plurality of tie bars 4 ′ extend inside the frame 2 ′, and the tie bars 4 are extended. ') Is substantially connected to and supported by the chip mounting plate 8' in the form of a square plate. In addition, a plurality of leads 10 'are arranged substantially radially on the outer periphery of the chip mounting plate 8', and all the leads 10 'are formed in a direction substantially perpendicular to the leads 10'. Connected to (12 '). Both ends of the dam bar 12 'are connected to the frame 2', and the dam bar 12 'is connected to a plurality of support leads 14'. In addition, the support lead 14 'is connected to the frame 2'.

계속해서, 도8b에 도시된 바와 같이 상기 리드(10')중 상기 칩탑재판(8')을 향하는 영역은 일정 깊이로 부분에칭되어 있고, 상기 칩탑재판(8')의 둘레 영역도 일정 깊이로 부분에칭되어 있다.Subsequently, as shown in Fig. 8B, a region of the lead 10 'facing the chip mounting plate 8' is partially etched to a predetermined depth, and the peripheral region of the chip mounting plate 8 'is also constant. Partially etched to depth.

여기서, 편의상 상기 칩탑재판(8')의 상면을 제1면(8a'), 하면을 제2면(8b') 및 부분에칭된 영역을 제3면(8c')으로 정의한다. 또한, 상기 리드(10')의 상면을제1면(10a'), 하면을 제2면(10b') 및 부분에칭된 부분을 제3면(10c')으로 정의한다.Here, for convenience, the upper surface of the chip mounting plate 8 'is defined as the first surface 8a', the lower surface as the second surface 8b ', and the partially etched region as the third surface 8c'. In addition, an upper surface of the lead 10 'is defined as a first surface 10a', a lower surface of a second surface 10b 'and a portion etched as a third surface 10c'.

또한, 도시되지는 않았지만, 상기 칩탑재판(8') 근처의 타이바(4')에도 일정깊이로 부분에칭된 제3면이 형성되어 있다.Although not shown, a third surface partially etched to a predetermined depth is also formed in the tie bar 4 'near the chip mounting plate 8'.

한편, 상기 프레임(2'), 댐바(12') 및 지지용 리드(14')는 반도체패키지 제조 공정중 싱귤레이션(Singulation) 공정에서 모두 제거되는 부분이다. 따라서, 실제의 반도체패키지(200')에서는 상기 칩탑재판(8') 및 타이바(4')와 리드(10')가 주요 구성요소가 된다.Meanwhile, the frame 2 ', the dam bar 12', and the support lead 14 'are all removed in the singulation process of the semiconductor package manufacturing process. Therefore, in the actual semiconductor package 200 ', the chip mounting plate 8', the tie bar 4 ', and the lead 10' are the main components.

이러한 리드프레임(100')을 이용한 반도체패키지(200')가 도7a 및 도7b에 도시되어 있다. 여기서, 상기 도7a는 반도체패키지(200')의 단면도이고, 도7b는 그 저면도이다.The semiconductor package 200 'using the lead frame 100' is shown in FIGS. 7A and 7B. 7A is a cross-sectional view of the semiconductor package 200 ', and FIG. 7B is a bottom view thereof.

도시된 바와 같이 대략 평면인 제1면(8a')과 제2면(8b')을 갖고, 상기 제1면(8a')과 제2면(8b') 사이에는 제3면(8c')이 형성된 칩탑재판(8')이 구비되어 있다. 여기서, 상기 제3면(8c')을 상술한 바와 같이 제2면(8b') 둘레에 형성되어 있다.As shown there is an approximately planar first surface 8a 'and a second surface 8b' and a third surface 8c 'between the first surface 8a' and the second surface 8b '. The formed chip mounting plate 8 'is provided. Here, the third surface 8c 'is formed around the second surface 8b' as described above.

또한, 상기 칩탑재판(8')의 제1면(8a')에는 접착수단(28')에 의해 다수의 입출력패드(22')를 갖는 반도체칩(20')이 접착되어 있다. 또한, 상기 칩탑재판(8')의 외주연에는 대략 평면인 제1면(10a')과 제2면(10b')을 갖고, 상기 제1면(10a')과 제2면(10b') 사이에는 제3면(10c')이 형성된 리드(10')가 구비되어 있다. 여기서, 상기 제3면(10c')은 상기 칩탑재판(8')을 향하는 부분에 형성되어 있다.Further, the semiconductor chip 20 'having a plurality of input / output pads 22' is bonded to the first surface 8a 'of the chip mounting plate 8' by the bonding means 28 '. In addition, the outer periphery of the chip mounting plate 8 'has a first plane 10a' and a second plane 10b 'which are substantially planar, and the first plane 10a' and the second plane 10b '. ) Is provided with a lead 10 'having a third surface 10c'. Here, the third surface 10c 'is formed at a portion facing the chip mounting plate 8'.

또한, 상기 반도체칩(20')의 입출력패드(22')와 상기 리드(10')의 제1면(10a')은 도전성와이어(24')에 의해 기계적 및 전기적으로 상호 연결되어 있고, 상기 칩탑재판(8'), 반도체칩(20'), 도전성와이어(24') 및 리드(10')는 봉지재로 봉지되어 있다. 여기서, 상기 봉지재로 봉지된 영역을 봉지부(26')로 정의한다.In addition, the input / output pad 22 'of the semiconductor chip 20' and the first surface 10a 'of the lead 10' are mechanically and electrically interconnected by conductive wires 24 '. The chip mounting plate 8 ', the semiconductor chip 20', the conductive wire 24 'and the lead 10' are sealed with an encapsulant. Here, the region encapsulated with the encapsulant is defined as an encapsulation portion 26 '.

상기와 같이 칩탑재판(8') 및 리드(10')에 제3면(8c',10c')이 형성된 이유는, 상기 칩탑재판(8') 및 리드(10')가 봉지부(26')에서 수평 또는 수직 방향으로 쉽게 이탈되지 않도록 하기 위함이다.The reason why the third surface 8c 'and 10c' is formed on the chip mounting plate 8 'and the lead 10' as described above is that the chip mounting plate 8 'and the lead 10' are encapsulated. 26 ') is to prevent easy separation in the horizontal or vertical direction.

한편, 상기 칩탑재판(8') 및 리드(10')중 제2면(8b')은 상기 봉지부(26') 외측으로 노출되어 있다. 즉, 상기 칩탑재판(8') 및 리드(10')중 제1면(8a',10a') 및 제3면(8c',10c')은 봉지부(26') 내측에 위치되고, 상기 제2면(8b',10b')은 봉지부(26') 외측으로 노출되어 있다. 따라서, 상기 리드(10')의 제2면(10b')이 차후 마더보드에 실장되는 영역이 되고, 또한 상기 반도체칩(20')의 열은 상기 칩탑재판(8')을 통하여 외부로 용이하게 방출됨을 알 수 있다.On the other hand, the second surface 8b 'of the chip mounting plate 8' and the lead 10 'is exposed outside the encapsulation portion 26'. That is, the first surface 8a 'and 10a' and the third surface 8c 'and 10c' of the chip mounting plate 8 'and the lead 10' are positioned inside the encapsulation portion 26 '. The second surfaces 8b 'and 10b' are exposed to the outside of the encapsulation 26 '. Therefore, the second surface 10b 'of the lead 10' becomes a region to be mounted on the motherboard later, and the heat of the semiconductor chip 20 'is transferred to the outside through the chip mounting plate 8'. It can be seen that it is easily released.

도9b에서 미설명 부호 4'는 봉지부(26') 외측으로 노출된 타이바이다.In FIG. 9B, reference numeral 4 ′ denotes a tie bar exposed to the outside of the encapsulation portion 26 ′.

그러나, 이러한 종래의 리드프레임 및 이를 이용한 반도체패키지는 반도체칩의 그라운드(Ground) 신호를 처리하는 수단이 리드가 됨으로써, 신호용 리드를 낭비하는 문제가 있다. 즉, 반도체칩의 입출력패드 중에는 전력 공급용 및 신호용 입출력 패드뿐만 아니라 다수의 그라운드용 입출력패드도 존재하는데, 상기 그라운드용 입출력패드가 상기 리드에 도전성와이어로 본딩되기 때문에, 신호용 리드가 과다하게 낭비되는 문제가 있다.However, such a conventional lead frame and a semiconductor package using the same have a problem in that a signal for processing a ground signal of a semiconductor chip becomes a lead, thereby wasting a signal lead. That is, in the input / output pads of the semiconductor chip, there are a plurality of ground input / output pads as well as power supply and signal input / output pads. Since the ground input / output pads are bonded to the leads with conductive wires, excessive signal leads are wasted. there is a problem.

상기 낭비된 신호용 리드의 갯수를 보충하기 위해서는 통상 상기 리드프레임의 리드를 파인피치(Fine Pitch)화 하여야 하는데, 이런 경우에는 그 제조 비용이 더욱 증가하여 바람직하지 않다. 또한, 상기 낭비된 신호용 리드를 보충하기 위해서 상기 리드프레임의 전체적인 크기를 크게 제조하는 방법도 있으나, 이런 경우에는 상기 리드프레임을 이용한 반도체패키지의 부피가 더욱 커져 현재의 경박단소화 추세에 대응하지 못하는 문제가 있다.In order to make up for the number of wasted signal leads, the lead of the lead frame should be fine pitched. In this case, the manufacturing cost is further increased, which is not preferable. In addition, there is a method of manufacturing the overall size of the lead frame to compensate for the wasted signal leads, but in this case, the volume of the semiconductor package using the lead frame is further increased, which does not correspond to the current trend of light and short there is a problem.

더불어, 상기한 문제를 해결하기 위해 그라운드용의 도전성와이어를 상기 리드대신 상기 칩탑재판의 둘레면에 직접 본딩하는 방법도 있으나, 이 경우에는 상기 칩탑재판의 제3면이 히트블럭에 접촉하지 않은 상태이기 때문에 본딩시 바운싱(Bouncing)이 심하게 발생하여 와이어본딩 수율이 현저히 저하되는 문제가 있다. 즉, 와이어 본딩 공정중에는 상기 리드프레임이 고열을 발생시키는 대략 평판 모양의 히트블럭 상면에 위치되고, 이어서 클램프로 고정된 후 실제의 와이어 본딩이 수행되는데, 상기와 같이 반도체칩의 입출력패드와 칩탑재판의 둘레면 사이의 와이어 본딩중에는 상기 칩탑재판의 제3면이 히트블럭과 직접 접촉(직접 접촉되는 영역은 하면(제2면)임)되지 않은 상태가 됨으로써, 본딩시 캐필러리와의 접촉에 의해 바운싱이 심하게 발생하게 된다. 결국, 상기 바운싱에 의해 와이어 본딩이 양호하게 수행되지 않음은 당연하다.In addition, in order to solve the above problem, there is a method of directly bonding the conductive wire for ground to the peripheral surface of the chip mounting plate instead of the lead, but in this case, the third surface of the chip mounting plate does not contact the heat block. Since it is not in the state of the bonding (Bouncing) occurs badly at the time of bonding (wire bonding yield) is a problem that is significantly reduced. That is, during the wire bonding process, the lead frame is positioned on an upper surface of a substantially flat heat block that generates high heat, and then fixed with a clamp, and then actual wire bonding is performed. During wire bonding between the circumferential surfaces of the plate, the third surface of the chip mounting plate is not in direct contact with the heat block (the area in direct contact is the lower surface (second surface)). Bounce occurs badly by contact. As a result, it is obvious that wire bonding is not performed well by the bounce.

한편, 상기 리드 및 칩탑재판이 봉지부에서 이탈되는 현상을 억제하기 위해 상기 리드 및 칩탑재판에 비록 제3면이 형성되어 있기는 하지만, 실제로 상기 반도체패키지가 마더보드에 실장된 후 여러 가혹한 환경에서 작동하게 되면, 상기 봉지부에서 상기 리드 및 칩탑재판이 비교적 쉽게 이탈되는 문제가 있다.On the other hand, although the third surface is formed on the lead and the chip mounting plate in order to suppress the separation of the lead and the chip mounting plate from the encapsulation portion, in many harsh environments after the semiconductor package is actually mounted on the motherboard When operating in, there is a problem that the lead and the chip mounting plate is relatively easily separated from the encapsulation.

본 발명은 상기와 같은 종래의 문제를 해결하기 위해 안출한 것으로, 본 발명의 목적은 칩탑재판에 그라운드용의 와이어 본딩시, 그 칩탑재판의 바운싱(Bouncing) 현상을 억제할 수 있는 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법을 제공하는데 있다.The present invention has been made to solve the above-described conventional problems, an object of the present invention, when the wire bonding for the ground to the chip mounting plate, the lead frame that can suppress the bouncing phenomenon of the chip mounting plate And to provide a semiconductor package and a manufacturing method using the same.

본 발명의 다른 목적은 리드 및 칩탑재판 등이 봉지부에 더욱 강하게 결합되어 수직 또는 수평방향으로 쉽게 이탈되지 않는 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법을 제공하는데 있다.It is another object of the present invention to provide a lead frame, a semiconductor package using the same, and a method of manufacturing the same, wherein the lead and the chip mounting plate are more strongly coupled to the encapsulation part so that they are not easily separated in the vertical or horizontal direction.

본 발명의 또다른 목적은 반도체칩의 그라운드 신호를 리드가 아닌 칩탑재판쪽으로 인출하여, 신호용 리드의 갯수를 최대한 확보할 수 있는 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법을 제공하는데 있다.It is another object of the present invention to provide a lead frame, a semiconductor package using the same, and a method of manufacturing the same, which lead the ground signal of the semiconductor chip to the chip mounting plate instead of the lead, thereby ensuring the maximum number of signal leads.

도1a 및 도1b는 본 발명에 의한 리드프레임을 도시한 평면도 및 저면도이다.1A and 1B are a plan view and a bottom view of a lead frame according to the present invention.

도2a 내지 도2c는 도1a 및 도1b의 I-I선, Ⅱ-Ⅱ선 및 Ⅲ-Ⅲ선에 대한 단면도이다.2A to 2C are cross-sectional views taken along lines I-I, II-II, and III-III of FIGS. 1A and 1B.

도3a 내지 도3c는 본 발명에 의한 반도체패키지를 도시한 단면도이고, 도3d는 그 저면도이다.3A to 3C are cross-sectional views showing a semiconductor package according to the present invention, and FIG. 3D is a bottom view thereof.

도4는 본 발명에 의한 반도패키지의 제조 방법을 도시한 순차 설명도이다.4 is a sequential explanatory diagram showing a method of manufacturing a peninsula package according to the present invention.

도5a 내지 도5f는 도4에 따른 반도체패키지의 제조 상태를 도시한 상태도이다.5A through 5F are state diagrams illustrating a manufacturing state of the semiconductor package of FIG. 4.

도6a는 종래의 리드프레임을 도시한 평면도이고, 도6b는 도6a의 I'-I'선에 대한 단면도이다.FIG. 6A is a plan view illustrating a conventional lead frame, and FIG. 6B is a cross-sectional view taken along line I'-I 'of FIG. 6A.

도7a 및 도7b는 종래의 리드프레임을 이용한 반도체패키지의 단면도 및 저면도이다.7A and 7B are cross-sectional and bottom views of a semiconductor package using a conventional lead frame.

- 도면중 주요 부호에 대한-For major symbols in the drawings

100; 본 발명에 의한 리드프레임100; Lead frame according to the present invention

2; 프레임 4; 타이바2; Frame 4; Tie bar

4a,4b,4c; 타이바의 제1면, 제2면 및 제3면4a, 4b, 4c; First, second and third sides of the tie bar

6; 그라운드링6; Ground ring

6a,6b,6c; 그라운드링의 제1면, 제2면 및 제3면6a, 6b, 6c; First, second and third sides of the ground ring

8; 칩탑재판8; Chip board

8a,8b,8c; 칩탑재판의 제1면, 제2면 및 제3면8a, 8b, 8c; First, second and third sides of the chipboard

10; 리드10; lead

10a,10b,10c; 리드의 제1면, 제2면 및 제3면10a, 10b, 10c; First side, second side and third side of the lid

12; 댐바 14; 지지용리드12; Dambar 14; Support Lead

16; 장공16; Longevity

200; 본 발명에 의한 반도체패키지 20; 반도체칩200; A semiconductor package 20 according to the present invention; Semiconductor chip

22; 입출력패드 24; 도전성와이어22; Input and output pads 24; Conductive Wire

26; 봉지부26; Encapsulation

상기한 목적을 달성하기 위해 본 발명에 의한 리드프레임은 대략 평판 모양의 프레임과; 상기 프레임 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과; 상기 그라운드링 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과; 상기 프레임으로부터 내측으로 연장되어, 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와; 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, a lead frame according to the present invention includes a frame having a substantially flat shape; A ground ring positioned inside the frame, the ground ring having a first surface and a second surface that are substantially planar, and a plurality of third surfaces opposite to the first surface are formed between the first and second surfaces; It is located inside the ground ring, and has a first plane and a second plane which are substantially planar, and between the first and second planes is opposite to the first plane and a third around the second plane. A chip mounting plate formed with a surface; Extending inwardly from the frame to connect and support the ground ring and the chip mounting plate, the first and second surfaces being substantially planar, opposite the first and second surfaces; A plurality of tie bars having a third surface formed on the outer side of the portion which is connected to the ground ring at the same time; It is substantially radially arranged on the outer circumference of the ground ring, and has a first plane and a second plane that are substantially planar, and between the first and second surfaces is opposite to the first surface and at the same time the ground ring is connected. It characterized in that it comprises a plurality of leads formed with a third surface facing portion.

여기서, 상기 그라운드링과 상기 칩탑재판 사이에는 다수의 장공(長空)이 형성되어 있다.Here, a plurality of long holes are formed between the ground ring and the chip mounting plate.

또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과; 상기 칩탑재판의 외주연에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과; 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와; 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에제3면이 형성된 다수의 리드와; 상기 칩탑재판의 제1면에 다수의 입출력패드를 가지며 접착수단으로 접착된 반도체칩과; 상기 반도체칩의 입출력패드와 상기 그라운드링 및 리드의 제1면을 상호 기계적 및 전기적으로 연결하는 도전성와이어와; 상기 칩탑재판, 타이바, 그라운드링, 리드, 반도체칩 및 도전성와이어가 봉지재로 봉지되어 있되, 상기 칩탑재판, 타이바, 그라운드링 및 리드의 제2면은 봉지부 외측으로 노출되도록 형성된 봉지부를 포함하여 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, the semiconductor package according to the present invention has a first plane and a second plane which are substantially planar, and between the first and second planes is opposite to the first plane and at the same time. A chip mounting plate having a third surface formed around two surfaces thereof; Located on an outer circumference of the chip mounting plate, the chip has a first plane and a second plane that are substantially planar, and a plurality of third surfaces that are opposite to the first surface are formed between the first and second surfaces. Ground ring; Connecting and supporting the ground ring and the chip mounting plate, the first and second surfaces being substantially planar, and between the first and second surfaces, the first and second surfaces being opposite to the first surface and connected to the ground ring. A plurality of tie bars having a third surface formed outside of the portion; It is substantially radially arranged on the outer circumference of the ground ring, and has a first plane and a second plane that are substantially planar, and between the first and second surfaces is opposite to the first surface and at the same time the ground ring is connected. A plurality of leads having a third surface on the facing portion; A semiconductor chip having a plurality of input / output pads on the first surface of the chip mounting plate and bonded by an adhesive means; Conductive wires that mechanically and electrically connect the input / output pads of the semiconductor chip to the first surfaces of the ground ring and the leads; The chip mounting plate, the tie bar, the ground ring, the lead, the semiconductor chip and the conductive wire are encapsulated with the encapsulant, and the second surface of the chip mounting plate, the tie bar, the ground ring and the lead is exposed to the outside of the encapsulation part. Characterized in that it comprises a sealing portion.

여기서, 상기 그라운드링은 제2면과 대응되는 제1면에만 도전성와이어가 본딩된 것을 특징으로 한다.Here, the ground ring is characterized in that the conductive wire is bonded only to the first surface corresponding to the second surface.

또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 대략 평판 모양의 프레임과, 상기 프레임 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과, 상기 그라운드링 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과, 상기 프레임으로부터 내측으로 연장되어, 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와, 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드를 포함하여 이루어진 리드프레임을 제공하는 단계와; 상기 칩탑재판의 제1면에 접착수단을 이용하여 다수의 입출력패드가 형성된 반도체칩을 접착하는 단계와; 상기 반도체칩의 입출력패드와 상기 그라운드링 및 리드의 제1면을 도전성와이어를 이용하여 기계적 및 전기적으로 본딩하는 단계와; 상기 칩탑재판, 타이바, 그라운드링, 리드, 반도체칩 및 도전성와이어를 봉지재로 봉지하되, 상기 칩탑재판, 타이바, 그라운드링 및 리드의 제2면은 외측으로 노출되도록 봉지부를 형성하는 단계와; 상기 프레임에서 상기 리드 및 타이바의 외측을 소잉하여 낱개의 반도체패키지로 싱귤레이션하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the method for manufacturing a semiconductor package according to the present invention in order to achieve the above object has a substantially flat plate-shaped frame, located inside the frame, having a first plane and a second plane which are substantially planar, wherein the first A ground ring having a plurality of third surfaces that are opposite to the first surface, and a first surface and a second surface which are positioned inside the ground ring and are substantially planar between the surface and the second surface. A chip mounting plate formed between the first surface and the second surface opposite to the first surface and having a third surface formed around the second surface, and extending inwardly from the frame, so that the ground ring and the chip mounting plate A first surface and a second surface that are substantially planar, and having a first surface and a second surface, wherein a third surface is provided between the first surface and the second surface, the surface opposite to the first surface and at the outside of the portion connected to the ground ring. A plurality of tie bars formed and the outside of the ground ring Substantially radially arranged at the periphery, having a first plane and a second plane that are substantially planar, and between the first and second planes, a third portion in the portion opposite to the first plane and facing the ground ring; Providing a lead frame comprising a plurality of leads formed with a surface; Bonding a semiconductor chip having a plurality of input / output pads formed thereon using an adhesive means to the first surface of the chip mounting plate; Bonding the input and output pads of the semiconductor chip and the first surfaces of the ground ring and the leads to each other mechanically and electrically by using conductive wires; The chip mounting plate, the tie bar, the ground ring, the lead, the semiconductor chip and the conductive wire is encapsulated with an encapsulant, wherein the second surface of the chip mounting plate, tie bar, ground ring and the lead is formed to expose the outside Steps; Singing the outside of the lead and tie bar in the frame and singulating into a single semiconductor package, characterized in that made.

여기서, 상기 와이어 본딩 단계는 도전성와이어가 상기 그라운드링의 제2면과 대응되는 제1면에 본딩되도록 한다.Here, the wire bonding step allows the conductive wire to be bonded to the first surface corresponding to the second surface of the ground ring.

상기와 같이 하여 본 발명은 그라운드용의 도전성와이어를 제1면, 제2면 및 제3면이 형성된 그라운드링중 제2면(와이어 본딩중 히터블럭에 접촉되는 면)과 대응하는 제1면에 본딩함으로써, 와이어 본딩중 그라운드링의 바운싱(Bouncing) 현상을 억제할 수 있다. 따라서, 와이어 본딩이 양호하게 수행되어 전체적인 와이어 본딩 수율이 향상된다.As described above, the present invention provides a conductive wire for ground on a first surface corresponding to a second surface (surface contacting the heater block during wire bonding) of the ground ring on which the first, second and third surfaces are formed. By bonding, a bouncing phenomenon of the ground ring during wire bonding can be suppressed. Therefore, wire bonding is performed well, and the overall wire bonding yield is improved.

즉, 종래에는 칩탑재판의 둘레면(제3면과 대응되는 제1면)에 본딩함으로써 바운싱 현상에 의해 와이어 본딩 수율이 현저히 저하되었지만, 본 발명은 이와 반대로 와이어 본딩 수율이 현저히 향상된다.That is, in the related art, the wire bonding yield is remarkably decreased by the bounce phenomenon by bonding to the circumferential surface (the first surface corresponding to the third surface) of the chip mounting plate, but the wire bonding yield is remarkably improved in the present invention.

또한, 본 발명은 칩탑재판 및 리드뿐만 아니라 그라운드링중 제1면 및 제3면이 봉지부 내측에 위치됨으로써, 특히 상기 칩탑재판과 봉지부 사이의 결합력이 더욱 향상된다. 즉, 종래에는 상기 칩탑재판의 제1면 및 제3면이 봉지부 내측에 위치되었지만, 본 발명은 상기 칩탑재판과 연결된 그라운드링의 제1면 및 제3면이 봉지부 내측에 더 위치됨으로써, 전체적으로 상기 칩탑재판과 봉지부와의 결합력이 더욱 향상된다.In addition, in the present invention, the first and third surfaces of the ground ring as well as the chip mounting plate and the lead are positioned inside the encapsulation portion, thereby further improving the bonding force between the chip mounting plate and the encapsulation portion. That is, although the first and third surfaces of the chip mounting plate are conventionally located inside the encapsulation part, in the present invention, the first and third surfaces of the ground ring connected to the chip mounting plate are further located inside the encapsulation part. As a result, the bonding force between the chip mounting plate and the encapsulation portion is further improved as a whole.

더불어, 반도체칩의 그라운드 신호를 처리하는 수단이 리드가 아닌 별도의 그라운드링이 됨으로써, 다수의 신호용 리드를 더 확보하게 된다.In addition, since the means for processing the ground signal of the semiconductor chip is a separate ground ring instead of a lead, a plurality of signal leads are further secured.

즉, 반도체칩의 입출력패드 중 다수의 그라운드용 입출력패드를 도전성와이어를 이용하여 리드가 아닌 그라운드링에 모두 본딩함으로써, 그만큼 나머지 전력공급용 또는 신호용 입출력패드에 대한 리드를 확보하게 된다.That is, by bonding a plurality of ground input / output pads among the input / output pads of the semiconductor chip to the ground ring instead of the leads using conductive wires, the lead for the remaining power supply or signal input / output pads is secured accordingly.

따라서, 종래와 같이 파인피치화한 리드프레임을 제조하거나, 크기가 더 큰 리드프레임을 제조할 필요가 없다.Therefore, there is no need to manufacture a fine-pitched lead frame or a lead frame of larger size as in the prior art.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도1a 및 도1b는 본 발명에 의한 리드프레임(100)을 도시한 평면도 및 저면도이다.1A and 1B are a plan view and a bottom view of a lead frame 100 according to the present invention.

대퍅 평판 모양의 프레임(2)이 구비되어 있다. 상기 프레임(2) 내측에는 대략 사각링 모양의 그라운드링(6)이 위치되어 있으며, 상기 그라운드링(6) 내측에는대략 사각판 모양의 칩탑재판(8)이 위치되어 있다.A flat plate-shaped frame 2 is provided. An approximately square ring-shaped ground ring 6 is located inside the frame 2, and a chip-shaped mounting plate 8 having an approximately square plate shape is located inside the ground ring 6.

상기 프레임(2)으로부터는 내측으로 다수의 타이바(4)가 형성되어 있으며, 상기 타이바(4)에는 상기 그라운드링(6) 및 칩탑재판(8)이 연결 및 지지되어 있다.A plurality of tie bars 4 are formed inward from the frame 2, and the ground rings 6 and the chip mounting plate 8 are connected to and supported by the tie bars 4.

여기서, 상기 칩탑재판(8)과 그라운드링(6) 사이에는 다수의 장공(16)이 더 형성되어, 상기 칩탑재판(8)과 상기 그라운드링(6)은 일정거리 이격되어 있다. 물론, 상기 칩탑재판(8)과 그라운드링(6)의 일정영역은 타이바(4)에 의해 상호 연결되어 있다.Here, a plurality of long holes 16 are further formed between the chip mounting plate 8 and the ground ring 6, and the chip mounting plate 8 and the ground ring 6 are spaced apart from each other by a predetermined distance. Of course, certain areas of the chip mounting plate 8 and the ground ring 6 are connected to each other by tie bars 4.

계속해서, 상기 그라운드링(6)의 외주연에는 대략 방사상으로 다수의 리드(10)가 배열되어 있다. 상기 모든 리드(10)는 그 리드(10)의 길이 방향과 수직 방향을 이루는 댐바(12)에 연결되어 있으며, 상기 댐바(12)는 프레임(2)에 연결되어 있다. 또한, 상기 댐바(12)는 다수의 지지용 리드(14)의 일단에 연결되어 있으며, 상기 지지용 리드(14)의 타단은 프레임(2)에 연결되어 있다. 도1b에서 해칭(Hatching)으로 표시된 영역은 부분 에칭된 영역으로서, 아래의 설명에서는 제3면으로 설명된다.Subsequently, a plurality of leads 10 are arranged substantially radially on the outer circumference of the ground ring 6. All the leads 10 are connected to a dam bar 12 which is perpendicular to the longitudinal direction of the leads 10, and the dam bars 12 are connected to the frame 2. In addition, the dam bar 12 is connected to one end of the plurality of support leads 14, and the other end of the support lead 14 is connected to the frame 2. The area indicated by hatching in FIG. 1B is a partially etched area, which is described as a third surface in the following description.

도2a 내지 도2c는 도1a 및 도1b의 I-I선, Ⅱ-Ⅱ선 및 Ⅲ-Ⅲ선을 도시한 단면도이다.2A to 2C are cross-sectional views showing lines I-I, II-II, and III-III of FIGS. 1A and 1B.

도시된 바와 같이 칩탑재판(8)은 대략 평면인 제1면(8a)과 제2면(8b)을 갖고, 상기 제1면(8a)과 제2면(8b) 사이에는 상기 제1면(8a)과 반대면인 동시에 상기 제2면(8b)의 둘레에 제3면(8c)이 형성되어 있다. 즉, 상기 제2면(8b)의 둘레에는상기 제1면(8a) 및 제2면(8b)과 수직 방향으로 일정 깊이 함몰 또는 부분에칭된 제3면(8c)이 형성되어 있다.As shown, the chip mounting plate 8 has a first plane 8a and a second plane 8b which are substantially planar, and the first plane between the first plane 8a and the second plane 8b. A third surface 8c is formed around the second surface 8b while being opposite to the surface of 8a. That is, a third surface 8c recessed or partially etched to a predetermined depth in the direction perpendicular to the first surface 8a and the second surface 8b is formed around the second surface 8b.

또한, 상기 칩탑재판(8)의 외주연에는 일정거리 이격되어 그라운드링(6)이 형성되어 있으며, 상기 그라운드링(6)은 대략 평면인 제1면(6a)과 제2면(6b)을 갖고, 상기 제1면(6a)과 제2면(6b) 사이에는 상기 제1면(6a)과 반대면인 다수의 제3면(6c)이 더 형성되어 있다. 즉, 상기 그라운드링(6)은 제2면(6b)에 상기 제1면(6a) 및 제2면(6b)과 수직 방향으로 일정깊이 함몰 또는 부분에칭된 다수의 제3면(6c)이 형성되어 있으며, 이는 대략 상기 제2면(6b)과 함께 요철(凹凸) 모양으로 형성되어 있다. 또한, 상기 그라운드링(6)의 제1면(6a)에는 일정 두께의 도금층(도시되지 않음)이 더 형성될 수도 있다. 즉, 상기 제1면(6a)에는 은(Ag) 또는 금(Au)과 같은 금속으로 도금층이 더 형성되어 차후 도전성와이어와의 양호한 본딩을 유도할 수도 있다.In addition, a ground ring 6 is formed on the outer circumference of the chip mounting plate 8 at a predetermined distance, and the ground ring 6 has a first plane 6a and a second plane 6b which are substantially planar. And a plurality of third surfaces 6c which are opposite to the first surface 6a are further formed between the first surface 6a and the second surface 6b. That is, the ground ring 6 has a plurality of third surfaces 6c recessed or partially etched in a vertical direction with the first surface 6a and the second surface 6b on the second surface 6b. It is formed, and it is formed in an uneven shape with the said 2nd surface 6b substantially. In addition, a plating layer (not shown) having a predetermined thickness may be further formed on the first surface 6a of the ground ring 6. That is, a plating layer may be further formed on the first surface 6a of metal such as silver (Ag) or gold (Au) to induce good bonding with the conductive wire.

한편, 상기 그라운드링(6)의 외주연에는 다수의 리드(10)가 위치되어 있으며, 상기 리드(10)는 대략 평면인 제1면(10a)과 제2면(10b)을 갖고, 상기 제1면(10a)과 제2면(10b) 사이에는 상기 제1면(10a)과 반대면인 동시에 상기 그라운드링(6)을 향하는 부분에 제3면(10c)이 형성되어 있다. 즉, 상기 제1면(10a) 및 제2면(10b)과 수직 방향으로 일정깊이 함몰 또는 부분에칭된 제3면(10c)이 형성되어 있다. 더불어, 상기 리드(10)의 제1면(10a)에도 차후 도전성와이어(24)와의 양호한 본딩을 위해 은(Ag) 또는 금(Au)과 같은 금속으로 일정 두께의 도금층이 더 형성될 수도 있다.On the other hand, a plurality of leads 10 are located on the outer circumference of the ground ring 6, and the leads 10 have a first plane 10a and a second plane 10b which are substantially planar. A third surface 10c is formed between the first surface 10a and the second surface 10b at a portion opposite to the first surface 10a and facing the ground ring 6. That is, the third surface 10c recessed or partially etched to a predetermined depth in the vertical direction with the first surface 10a and the second surface 10b is formed. In addition, a plating layer having a predetermined thickness may be further formed on the first surface 10a of the lead 10 with a metal such as silver (Ag) or gold (Au) for good bonding with the conductive wires 24.

상기 리드(10)는 일체의 댐바(12)에 연결되어 있으며, 상기 댐바(12)는 지지용 리드(14)를 통하여 그 외측의 프레임(2)에 연결되어 있다.The lid 10 is connected to the integral dam bar 12, and the dam bar 12 is connected to the frame 2 on the outside thereof through the supporting lead 14.

더불어, 상기 타이바(4)는 대략 평면인 제1면(4a)과 제2면(4b)을 갖고, 상기 제1면(4a)과 제2면(4b) 사이에는 상기 제1면(4a)과 반대면인 동시에 상기 그라운드링(6)과 연결된 부분의 외측에 제3면(4c)이 형성되어 있다. 즉, 상기 제1면(4a) 및 제2면(4b)과 수직 방향으로 일정 깊이 함몰 또는 부분에칭된 제3면(4c)이 형성되어 있다. 여기서도, 상기 타이바(4)의 제1면(4a)에는 차후 도전성와이어와의 양호한 본딩을 위해 은(Ag) 또는 금(Au)과 같은 금속에 의해 일정 두께의 도금층이 더 형성될 수 있다.In addition, the tie bar 4 has a first surface 4a and a second surface 4b which are substantially planar, and the first surface 4a between the first surface 4a and the second surface 4b. The third surface 4c is formed on the outside of the portion connected to the ground ring 6 at the same time as the surface opposite to). That is, the third surface 4c which is recessed or partially etched to a predetermined depth in the direction perpendicular to the first surface 4a and the second surface 4b is formed. Here, a plating layer having a predetermined thickness may be further formed on the first surface 4a of the tie bar 4 by a metal such as silver (Ag) or gold (Au) for good bonding with the conductive wire.

이러한 리드프레임(100)은 모두 구리(Cu), 구리 합금(Cu Alloy), 합금 37(니켈(Ni)37%, 철(Fe)55%) 등의 연속된 금속 스트립(Strip)을 기계적 스탬핑(Stamping)이나 화학적 에칭(Etching) 방법에 의해 제조된 것으로서, 이것의 형성 방법은 반도체패키지의 제조 방법 설명에서 하기로 한다.These lead frames 100 are all mechanically stamped on a continuous metal strip such as copper (Cu), copper alloy (Cu Alloy), alloy 37 (37% nickel (55% nickel), iron (Fe) 55%) Manufactured by stamping) or chemical etching, and the method of forming the same will be described later in the description of the manufacturing method of the semiconductor package.

이어서, 도3a 내지 도3c는 본 발명에 의한 반도체패키지(200)를 도시한 단면도이고, 도3d는 그 저면도이다.3A to 3C are cross-sectional views showing the semiconductor package 200 according to the present invention, and FIG. 3D is a bottom view thereof.

도시된 바와 같이 대략 평면인 제1면(8a)과 제2면(8b)을 갖고, 상기 제1면(8a)과 제2면(8b) 사이에는 상기 제1면(8a)과 반대면인 동시에 상기 제2면(8b)의 둘레에 제3면(8c)이 형성된 칩탑재판(8)이 구비되어 있다.As shown there is a first plane 8a and a second plane 8b which are substantially planar, and between the first plane 8a and the second plane 8b is opposite to the first plane 8a. At the same time, the chip mounting plate 8 is provided with a third surface 8c formed around the second surface 8b.

상기 칩탑재판(8)의 외주연에는 일정 거리 이격된 채, 대략 평면인제1면(6a)과 제2면(6b)을 갖고, 상기 제1면(6a)과 제2면(6b) 사이에는 상기 제1면(6a)과 반대면인 다수의 제3면(6c)이 형성된 그라운드링(6)이 위치되어 있다.An outer circumference of the chip mounting plate 8 has a first plane 6a and a second plane 6b which are substantially planar, and are spaced apart from each other, between the first plane 6a and the second plane 6b. The ground ring 6 is formed with a plurality of third surfaces 6c opposite to the first surface 6a.

여기서, 상기 그라운드링(6)의 제1면(6a)에는 은(Ag) 또는 금(Au)과 같은 금속으로 일정두께의 도금층이 더 형성될 수 있다.Here, a plating layer having a predetermined thickness may be further formed on the first surface 6a of the ground ring 6 with a metal such as silver (Ag) or gold (Au).

또한, 상기 그라운드링(6) 및 칩탑재판(8)을 연결 및 지지하며, 대략 평면인 제1면(4a)과 제2면(4b)을 갖고, 상기 제1면(4a)과 제2면(4b) 사이에는 상기 제1면(4a)과 반대면인 동시에 상기 그라운드링(6)과 연결된 부분의 외측에는 제3면(4c)이 형성된 다수의 타이바(4)가 위치되어 있다. 여기서도, 상기 타이바(4)의 제1면(4a)에는 은(Ag) 또는 금(Au)과 같은 금속으로 일정두께의 도금층이 더 형성될 수도 있다.Further, the ground ring 6 and the chip mounting plate 8 are connected and supported, and have a first plane 4a and a second plane 4b which are substantially planar, and the first plane 4a and the second plane. Between the surfaces 4b, a plurality of tie bars 4 on which the third surface 4c is formed are located on the outer side of the portion opposite to the first surface 4a and connected to the ground ring 6. Here, the plating layer having a predetermined thickness may be further formed on the first surface 4a of the tie bar 4 with a metal such as silver (Ag) or gold (Au).

계속해서, 상기 그라운드링(6)의 외주연에는 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면(10a)과 제2면(10b)을 갖고, 상기 제1면(10a)과 제2면(10b) 사이에는 상기 제1면(10a)과 반대면인 동시에 상기 그라운드링(6)을 향하는 부분에 제3면(10c)이 형성된 다수의 리드(10)가 위치되어 있다. 여기서도, 상기 리드(10)의 제1면(10a)에는 은(Ag) 또는 금(Au)과 같은 금속으로 일정두께의 도금층이 더 형성될 수도 있다.Subsequently, the outer circumference of the ground ring 6 has a substantially radially arranged first surface 10a and a second surface 10b, and the first surface 10a and the second surface. A plurality of leads 10 having a third surface 10c formed on a portion opposite to the first surface 10a and facing toward the ground ring 6 are positioned between the portions 10b. Here, the plating layer having a predetermined thickness may be further formed on the first surface 10a of the lead 10 by using a metal such as silver (Ag) or gold (Au).

한편, 상기 칩탑재판(8)의 제1면(8a)에는 다수의 입출력패드(22)를 갖는 반도체칩(20)이 접착수단(28)으로 접착되어 있다.On the other hand, the semiconductor chip 20 having a plurality of input / output pads 22 is bonded to the first surface 8a of the chip mounting plate 8 by the bonding means 28.

또한, 상기 반도체칩(20)의 입출력패드(22)와 상기 그라운드링(6) 및 리드(10)의 제1면(6a,10a)은 골드와이어 또는 알루미늄와이어와 같은도전성와이어(24)에 의해 기계적 및 전기적으로 상호 연결되어 있다.In addition, the input / output pads 22 of the semiconductor chip 20 and the first surfaces 6a and 10a of the ground ring 6 and the lead 10 may be formed by conductive wires 24 such as gold wires or aluminum wires. It is mechanically and electrically interconnected.

여기서, 상기 리드(10)에 연결된 도전성와이어(24)는 전력 공급용 또는 신호용이고, 상기 그라운드링(6)에 연결된 도전성와이어(24)는 반도체칩(20)의 그라운드용이다.Here, the conductive wire 24 connected to the lead 10 is for power supply or signal, and the conductive wire 24 connected to the ground ring 6 is for grounding the semiconductor chip 20.

또한, 상기 그라운드링(6)은 상기 제2면(6b)과 대응되는 제1면(6a)에만 도전성와이어(24)가 본딩될 수 있다. 이는 차후 설명하겠지만, 와이어 본딩시 그라운드링(6)의 바운싱(Bouncing) 현상을 최소화하기 위한 선택이다.In addition, the conductive ring 24 may be bonded to the ground ring 6 only on the first surface 6a corresponding to the second surface 6b. As will be described later, this is a choice for minimizing bouncing of the ground ring 6 during wire bonding.

또한, 상기 칩탑재판(8), 타이바(4), 그라운드링(6), 리드(10), 반도체칩(20) 및 도전성와이어(24)는 봉지재로 봉지되어 일정 형태의 봉지부(26)를 구성하고 있되, 상기 칩탑재판(8), 타이바(4), 그라운드링(6) 및 리드(10)의 제2면(8b, 4b,6b,10b)은 봉지부(26) 외측으로 노출되어 있다. 즉, 상기 칩탑재판(8), 타이바(4), 그라운드링(6) 및 리드(10)의 제1면(8a,4a,6a,10a), 제3면(8c,4c,6c,10c) 및 각각의 측면은 상기 봉지부(26) 내측에 위치되어 인터락킹(Inter-locking)되고, 상기 제2면(8b,4b,6b,10b)은 봉지부(26) 외측으로 노출됨으로써, 차후 마더보드에 실장 가능한 형태로 되어 있다.In addition, the chip mounting plate 8, the tie bar 4, the ground ring 6, the lead 10, the semiconductor chip 20, and the conductive wire 24 are encapsulated with an encapsulant to form a certain encapsulation portion ( 26, the chip mounting plate 8, the tie bar 4, the ground ring 6, and the second surfaces 8b, 4b, 6b, and 10b of the lid 10 are encapsulated 26. It is exposed to the outside. That is, the first surface 8a, 4a, 6a, 10a, the third surface 8c, 4c, 6c of the chip mounting plate 8, tie bar 4, ground ring 6 and lead 10, 10c) and each side surface are positioned inside the encapsulation 26 to inter-lock, and the second surfaces 8b, 4b, 6b, and 10b are exposed out of the encapsulation 26. It can be mounted on the motherboard later.

또한, 상기 봉지부(26) 외측으로 노출된 칩탑재판(8), 타이바(4), 그라운드링(6) 및 리드(10)의 제2면(8b,4b,6b,10b)에는 통상 구리(Cu), 금(Au), 솔더(Pb/Sn), 주석(Sn), 니켈(Ni), 팔라디엄(Pd) 또는 납땜 가능한 금속 등으로 일정 두께의 도금층(도시되지 않음)이 형성될 수 있다.In addition, the chip mounting plate 8, the tie bar 4, the ground ring 6, and the second surfaces 8b, 4b, 6b, and 10b exposed to the outside of the encapsulation part 26 are usually disposed. A plating layer (not shown) having a predetermined thickness may be formed of copper (Cu), gold (Au), solder (Pb / Sn), tin (Sn), nickel (Ni), palladium (Pd), or a solderable metal, or the like. Can be.

통상 상기와 같은 반도체패키지(200)는 리드(10), 그라운드링(6) 및타이바(4)의 제2면(10b,6b,4b)이 마더보드의 소정 패턴에 실장되지만, 상기 반도체패키지(200)의 방열성능을 향상시키기 위해 상기 칩탑재판(8)의 제2면(8)도 상기 마더보드의 소정 패턴에 솔더 페이스트(Solder Paste)등으로 실장될 수 있다.Usually, the semiconductor package 200 as described above has the lead 10, the ground ring 6, and the second surfaces 10b, 6b, and 4b of the tie 4 mounted on a predetermined pattern of the motherboard. In order to improve the heat dissipation performance of the 200, the second surface 8 of the chip mounting plate 8 may also be mounted with solder paste or the like on a predetermined pattern of the motherboard.

도4는 본 발명에 의한 반도패키지의 제조 방법을 도시한 순차 설명도이고, 도5a 내지 도5f는 도4에 따른 반도체패키지의 제조 상태를 도시한 상태도로서, 이를 각 단계별로 설명하면 다음과 같다.4 is a sequential explanatory diagram illustrating a method of manufacturing a semiconductor package according to the present invention, and FIGS. 5A to 5F are state diagrams illustrating a manufacturing state of the semiconductor package according to FIG. 4. .

1. 리드프레임 제공 단계(S1)로서, 도1a,1b,2a,2b 및 도5a에 도시된 것과 같은 리드프레임(100)을 제공한다. 이러한 리드프레임(100)은 통상 금속 스트립(Metal Strip)의 화학적 ?? 에칭(Wet Etching)에 의해 형성된다.1. As a lead frame providing step S1, a lead frame 100 as shown in Figs. 1A, 1B, 2A, 2B and 5A is provided. Such a lead frame 100 is usually formed of a chemical strip of a metal strip. It is formed by Wet Etching.

주지된 바와 같이, 화학적 에칭은 포토리토그래피(Photolithography), 포토레지스트(Photoresist) 그리고 금속 스트립에 패턴을 에칭하기 위한 화학 용액 등을 사용한다. 일반적으로, 포트레지스트층은 스트립의 한면 또는 양면에 형성된다. 다음으로, 상기 포트레지스트층은 원하는 패턴이 그려진 마스크를 통하여 빛에 노출된다. 계속해서, 화학용액이 마스킹된 스트립의 한면 또는 양면에 적용된다. 스트립의 노출된 영역은 에칭되어 제거되고, 금속 스트립에 원하는 패턴이 남게 된다.As is well known, chemical etching uses photolithography, photoresist and chemical solutions for etching patterns on metal strips, and the like. Generally, the photoresist layer is formed on one or both sides of the strip. Next, the photoresist layer is exposed to light through a mask on which a desired pattern is drawn. Subsequently, a chemical solution is applied to one or both sides of the masked strip. Exposed areas of the strip are etched away, leaving a desired pattern on the metal strip.

통상, 2회에 걸친 에칭이 도1a,1b,2a,2b 및 도5a의 리드프레임을 형성하기 위해 수행된다. 제1에칭은 스트립의 한면 또는 양면상에 포토레지스트 패턴을 따라서 스트립의 한면 또는 양면에 실시된다. 이러한 제1에칭은 도1a에 도시된 바와 같이, 리드프레임(100)의 전체적 패턴을 형성하기 위해 금속 스트립의 소정 영역을 완전히 관통하여 실시된다. 다음으로, 2번째 포토레지스트 패턴은 리드프레임(100) 한면의 일정 영역에 형성된다. 칩탑재판(8)의 둘레 영역과, 그라운드링(6), 타이바(4) 및 리드(10)의 선택된 영역은 2번째 포토레지스트 패턴에 의해 감싸여지지 않고, 따라서 차후의 에칭에서 보다 많이 에칭된다. 제2에칭은 상기 2번째 포토레지스트 패턴을 따라서 리드프레임(100)의 한면에 부분적으로 실시된다. 이러한 제2에칭은 도1b,2a,2b,5a에 도시된 리드프레임(100)의 함몰된 표면을 형성한다.(예를 들면, 칩탑재판(8)의 제3면(8c), 그라운드링(6)의 제3면(6c), 타이바(4)의 제3면(4c) 및 리드(10)의 제3면(10c)이 상기 제2에칭에 의해 형성된다) 상기 화학용액이 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)의 선택된 영역의 두께 및 선택된 거리를 에칭하였을 때, 상기 제2에칭은 중지된다. 즉, 상기 제2에칭은 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)중 선택된 영역의 두께만큼 실시된다. 이러한 제2에칭 단계에 의한 에칭량은 봉지부(26)에서 상기 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)가 안전하도록, 즉, 칩탑재판(8)의 제3면(8c), 그라운드링(6)의 제3면(6c), 타이바(4)의 제3면(4c) 및 리드(10)의 제3면(10c) 하부로 충분한 량의 봉지재 또는 봉지부가 형성될 정도로 실시된다. 일반적으로, 상기 제2에칭은 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10) 두께의 대략 50%를 제거하지만, 제거된 량은 상기 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10) 두께의 대략 25%에서 75% 범위일 수 있다. 에칭 과정의 불완전성으로 인해, 상기 각각의 제3면(4c,6c,8c,10c)은 평면이 아니고 근사적으로 평면에 가까울수 있으며, 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)의 측벽 각도도 90°가 아니고 원형의 코너를 이룰 수 있다.Typically, two etchings are performed to form the leadframe of FIGS. 1A, 1B, 2A, 2B and 5A. The first etching is carried out on one or both sides of the strip along the photoresist pattern on one or both sides of the strip. This first etching is carried out through a predetermined area of the metal strip to form the overall pattern of the lead frame 100, as shown in Figure 1a. Next, the second photoresist pattern is formed in a predetermined region of one surface of the lead frame 100. The circumferential region of the chipboard 8 and the selected regions of the ground ring 6, tie bar 4 and lead 10 are not covered by the second photoresist pattern and thus are more numerous in subsequent etching. Is etched. The second etching is partially performed on one surface of the lead frame 100 along the second photoresist pattern. This second etching forms the recessed surface of the leadframe 100 shown in Figs. 1B, 2A, 2B and 5A. (E.g., the third surface 8c of the chip mounting plate 8, the ground ring). The third surface 6c of (6), the third surface 4c of the tie bar 4 and the third surface 10c of the lid 10 are formed by the second etching. When the thickness and the selected distance of the selected region of the mounting plate 8, the ground ring 6, the tie bar 4 and the lid 10 are etched, the second etching is stopped. That is, the second etching is performed by the thickness of the selected region of the chip mounting plate 8, the ground ring 6, the tie bar 4, and the lead 10. The etching amount by the second etching step is such that the chip mounting plate 8, the ground ring 6, the tie bar 4, and the lid 10 are secured in the encapsulation part 26, that is, the chip mounting plate ( 8, the third surface 8c of the ground ring 6, the third surface 4c of the tie bar 4 and the lower portion of the third surface 10c of the lid 10 are sufficient. It is carried out to such an extent that an amount of encapsulant or encapsulation is formed. Generally, the second etching removes approximately 50% of the thickness of the chip mounting plate 8, the ground ring 6, the tie bar 4, and the lid 10, but the amount removed is the chip mounting plate 8. ), Ground ring 6, tie bar 4, and lead 10 may range from approximately 25% to 75% of the thickness. Due to the imperfection of the etching process, each of the third surfaces 4c, 6c, 8c, and 10c may be approximately planar rather than planar, with chip mounting plate 8, ground ring 6, tie The angles of the side walls of the bar 4 and the lid 10 may also form a circular corner rather than 90 degrees.

여기서, 상기 제1,2에칭은 순서가 바뀔 수도 있으며, 또한 상기 제1에칭에 의해서만 소정의 목적을 달성할 수도 있다. 즉, 상기 제1에칭에 의해 총체적 리드(10) 패턴을 형성함은 물론, 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)를 소정 두께 이상으로 에칭하여 상기한 바와 같이 단면상 계단형의 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)를 구비할 수 있을 것이다.Here, the order of the first and second etchings may be reversed, and a predetermined purpose may be achieved only by the first etching. That is, by forming the overall lead 10 pattern by the first etching, the chip mounting plate 8, the ground ring 6, the tie bar 4 and the lead 10 are etched to a predetermined thickness or more. As described above, the stepped chip mounting plate 8, the ground ring 6, the tie bar 4, and the lid 10 may be provided.

선택적으로, 리드프레임은 리드프레임의 전체적 패턴을 스탬핑하는 제1단계와, 상기했듯이 리드프레임의 함몰된 표면까지 스탬핑된 리드프레임의 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)를 부분적으로 화학적 에칭하는 제2단계에 의해 형성될 수도 있다.Optionally, the leadframe comprises a first step of stamping the overall pattern of the leadframe, and the chip mounting plate 8, ground ring 6, tie bar 4 of the leadframe stamped to the recessed surface of the leadframe as described above. ) And a second step of partially chemically etching the lid 10.

2. 반도체칩 탑재 및 접착 단계(S2)로서, 도5b에 도시된 바와 같이 상면에 다수의 입출력패드(22)가 형성된 반도체칩(20)을 칩탑재판(8)의 제1면(8a) 중앙에 접착수단을 이용하여 접착한다. 칩탑재판(8) 상에 반도체칩(20)의 탑재와 접착은 통상적인 반도체칩 접착 장비와 통상적인 반도체칩 접착 에폭시를 이용하여 구현할 수 있다.2. In the step of mounting and bonding the semiconductor chip (S2), the semiconductor chip 20 having a plurality of input / output pads 22 formed thereon as shown in FIG. 5B is formed on the first surface 8a of the chip mounting plate 8. Adhesion in the center using adhesive means. Mounting and bonding of the semiconductor chip 20 on the chip mounting plate 8 may be implemented using conventional semiconductor chip bonding equipment and conventional semiconductor chip bonding epoxy.

상기 반도체칩 접착 단계와 차후의 조립 단계에서, 상기 리드프레임은 정전방전(ESD, ElectroStatic Discharge)으로부터 보호되도록 접지된다.In the semiconductor chip bonding step and the subsequent assembly step, the lead frame is grounded to be protected from electrostatic discharge (ESD).

3. 와이어 본딩 단계(S3)로서, 도5c에 도시된 바와 같이 상기 반도체칩(20) 상면의 각 입출력패드(22)와 그라운드링(6)(또는 타이바(4)) 및 각 리드(10)의 제1면(6a,4a,10a)을 골드와이어(Au Wire) 또는 알루미늄와이어(Al Wire)와 같은 도전성와이어(24)로 또는 이것의 등가물을 이용하여 기계적 및 전기적으로 접속한다. 상기 제1면(6a,4a,10a)은 도전성와이어(24)와의 본딩력을 향상시키기 위해, 금(Au), 은(Ag), 니켈(Ni), 팔라디엄(Pd), 구리(Cu) 및 다른 금속들로 도금될 수 있다. 이때, 상기 리드프레임은 정전방전에 의해 반도체칩(20)에 이상이 생기지 않도록 상기 본딩 공정 동안 접지된다.3. As the wire bonding step S3, as shown in FIG. 5C, each input / output pad 22 and ground ring 6 (or tie bar 4) and each lead 10 on the upper surface of the semiconductor chip 20 are shown. The first surfaces 6a, 4a, and 10a of the c) are electrically and electrically connected to conductive wires 24, such as gold wires or aluminum wires, or by using an equivalent thereof. The first surfaces 6a, 4a, and 10a may be formed of gold (Au), silver (Ag), nickel (Ni), palladium (Pd), and copper (Cu) to improve bonding strength with the conductive wires 24. And other metals. In this case, the lead frame is grounded during the bonding process so that no abnormality occurs in the semiconductor chip 20 due to the electrostatic discharge.

또한, 이때 상기 리드프레임(100)은 통상 히트블럭(도시되지 않음) 상부에 위치하게 되는데, 상기 그라운드링(6)은 제2면(6b) 및 제3면(6c)이 대략 요철 형태로 되어 있음으로써, 상기 그라운드링(6)은 와이어 본딩중 바운싱(Bouncing) 현상 없이 상기 히트블럭 상에 고정된다. 따라서, 상기 도전성와이어(24)는 상기 그라운드링(6)의 제1면(6a)에 안정적으로 본딩이 수행될 수 있다. 바람직하기로, 상기 도전성와이어(24)는 상기 그라운드링(6)중 제2면(6b)(히트블럭에 접촉되는 면)과 대응되는 제1면(6a)에 본딩됨이 가장 효율적일 것이다.In addition, at this time, the lead frame 100 is normally positioned above the heat block (not shown), and the ground ring 6 has a second surface 6b and a third surface 6c having roughly uneven shapes. As such, the ground ring 6 is fixed on the heat block without bouncing during wire bonding. Therefore, the conductive wire 24 may be stably bonded to the first surface 6a of the ground ring 6. Preferably, the conductive wire 24 is most efficiently bonded to the first surface 6a corresponding to the second surface 6b (the surface in contact with the heat block) of the ground ring 6.

한편, 상기 그라운드링(6)에 본딩되는 도전성와이어(24)는 그라운드용이다. 즉, 반도체칩(20)의 입출력패드(22)중 그라운드용은 상기 도전성와이어(24)에 의해 상기 그라운드링(6) 또는 타이바(4)에 본딩된다. 물론, 상기 반도체칩(20)의 입출력패드(22)중 전력 공급용 또는 신호용은 상기 도전성와이어(24)에 의해 상기 리드(10)에 본딩된다.On the other hand, the conductive wire 24 bonded to the ground ring 6 is for ground. That is, the ground for the input / output pads 22 of the semiconductor chip 20 is bonded to the ground ring 6 or the tie bar 4 by the conductive wires 24. Of course, the power supply or the signal for the input / output pads 22 of the semiconductor chip 20 is bonded to the lead 10 by the conductive wires 24.

4. 봉지 단계(S4)로서, 도5d 및 도5e에 도시된 바와 같이 점착성 접착 봉지재가 상기 리드프레임상에 적용되어 일정 형태의 봉지부(26)를 형성한다. 상기 봉지부(26)는 다른 무엇보다도, 반도체칩(20), 도전성와이어(24), 칩탑재판(8) 제1면(8a), 제3면(8c) 및 측면, 그라운드링(6)의 제1면(6a), 제3면(6c) 및 측면, 타이바(4)의 제1면(4a), 제3면(4c) 및 측면, 리드(10)의 제1면(10a), 제3면(10c) 및 측면을 덮는다. 칩탑재판(8)의 제2면(8b), 그라운드링(6)의 제2면(6b), 타이바(4)의 제2면(4b) 및 리드(10)의 제2면(10b)은 봉지부(26)에 의해 덮혀지지 않고 외부로 노출된다.4. In the encapsulation step S4, as shown in Figs. 5D and 5E, an adhesive adhesive encapsulant is applied on the lead frame to form an encapsulation portion 26 of some form. The encapsulation part 26 includes, among other things, the semiconductor chip 20, the conductive wires 24, the chip mounting plate 8, the first surface 8a, the third surface 8c and the side surfaces, and the ground ring 6. First surface 6a, third surface 6c and side surfaces thereof, first surface 4a, third surface 4c and side surfaces of tie bar 4, first surface 10a of lid 10 It covers the 3rd surface 10c and the side surface. The second surface 8b of the chip mounting plate 8, the second surface 6b of the ground ring 6, the second surface 4b of the tie bar 4, and the second surface 10b of the lid 10. ) Is not covered by the encapsulation 26 and is exposed to the outside.

상기와 같은 봉지 공정은 적용분야에 따라서 여러가지로 수행될 수 있다. 예를 들면, 통상적인 플락스틱 봉지 기술을 이용하여 성취될 수 있다. 이와 같은 방법에서, 리드프레임은 금형내에 위치되고, 리드프레임의 상면에 봉지재에 의해 일정 형태의 봉지부가 형성된다. 상기 봉지재는 통상적인 기술에 이용되는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)일 수 있다. 상기 에폭시 몰딩 컴파운드의 예는 일본의 니토사(Nitto Company)로부터 구할 수 있는 NITTO MP-8000AN 몰딩 컴파운드, 일본의 수미토모사(Sumitomo Company)로부터 구할 수 있는 EME 7351 UT 등이 있다. 통상적인 게이트가 봉지 공정을 원할히 할 수 있도록 리드프레임에 형성될 수 있다. 금형의 측면은 봉지부(26)가 금형으로부터 용이하게 빠지도록 테이퍼(Taper)되어 있다.The encapsulation process as described above may be performed in various ways depending on the application. For example, it can be accomplished using conventional plastic encapsulation techniques. In this method, the lead frame is placed in a mold, and an encapsulation portion of a form is formed on the upper surface of the lead frame by an encapsulant. The encapsulant may be an epoxy molding compound used in a conventional technique. Examples of the epoxy molding compound include NITTO MP-8000AN molding compound available from Nitto Company of Japan, EME 7351 UT available from Sumitomo Company of Japan, and the like. Conventional gates may be formed in the leadframe to facilitate the encapsulation process. The side surface of the mold is tapered so that the sealing portion 26 can be easily taken out of the mold.

선택적으로, 상기 봉지 공정을 이용하는 대신, 액상 봉지재를 이용할 수 있다. 예를 들면, 첫번째 단계로서 도5c의 리드프레임을 수평면에 위치시킨다. 두번째 단계로서, 캘리포니아, Dexter-Hysol Company of City of Industry로부터 구입할 수 있는 HYSOL 4451 에폭시와 같은 통상적인 경화 가능한 점착성 접착 재료의접촉성 비드(Bead)가 반도체칩(20) 주위 및 적어도 댐바(12) 내측의 소정 리드(10) 영역에 폐직사각 댐을 형성하도록 리드프레임상에 적용될 수 있다. 세번째 단계로서, 1시간동안 대략 140℃로 가열하는 것과 같은 공정에 의해 상기 댐을 경화시킨다. 네번째 단계로서, HYSOL 4450 액체 봉지재와 같은, 봉지부(26)를 형성하기에 적당한 통상적인 경화가능한 점착성 접착제가 상기 댐내에서 봉지된다. 마지막 단계로서, 1시간동안 대략 140℃로 가열하는 것과 같은 공정에 의해 리드프레임상에 경화된 봉지부(26)가 경화 및 형성되도록 한다.Alternatively, instead of using the encapsulation process, a liquid encapsulant may be used. For example, as a first step, the lead frame of Fig. 5C is placed on a horizontal plane. As a second step, a contact bead of a conventional curable tacky adhesive material, such as HYSOL 4451 epoxy, available from the Dexter-Hysol Company of City of Industry, California, is formed around the semiconductor chip 20 and at least the dambar 12. It can be applied on the lead frame to form a closed rectangular dam in the region of the predetermined lead 10 inside. As a third step, the dam is cured by a process such as heating to approximately 140 ° C. for one hour. As a fourth step, a conventional curable adhesive adhesive suitable for forming the encapsulation 26, such as a HYSOL 4450 liquid encapsulant, is encapsulated in the dam. As a final step, the cured encapsulation 26 is cured and formed on the leadframe by a process such as heating to approximately 140 ° C. for one hour.

상기와 같은 봉지 공정후에는 통상 상기 칩탑재판(8), 그라운드링(6), 타이바(4) 및 리드(10)의 제2면(8b,6b,4b,10b)을 포함하는, 봉지부(26)로 덮혀지지 않은 리드프레임의 일정영역이 마더보드에 실장될 수 있는 통상적인 도금용 금속으로 도금될 수 있다. 도금용 금속의 예는 그 적용분야에 따라서 금, 니켈, 팔라디엄, 인코넬(Inconel), 납과 주석의 솔더 또는 탄탈륨(Tantalum) 등을 포함한다. 상기 단계는 리드프레임(100)을 형성하기 위해 사용된 금속이 도금 또는 예비 도금 등을 필요로 하지 않을 경우 생략될 수 있다. 예를 들어, 상기 단계는 리드프레임을 제조하기 위해 사용된 금속 스트립이 니켈 팔라디엄으로 도금된 구리일 경우 생략될 수 있다.After the encapsulation process as described above, the encapsulation usually includes the chip mounting plate 8, the ground ring 6, the tie bar 4, and the second surfaces 8b, 6b, 4b and 10b of the lid 10. Certain areas of the leadframe that are not covered by the portion 26 may be plated with conventional plating metal that may be mounted on the motherboard. Examples of metals for plating include gold, nickel, palladium, Inconel, lead and tin solder or tantalum depending on the application. The step may be omitted when the metal used to form the lead frame 100 does not require plating or preplating. For example, the step may be omitted if the metal strip used to manufacture the leadframe is copper plated with nickel palladium.

5. 싱귤레이션 단계(S5)로서, 도5f에 도시된 바와 같이 봉지부(26)가 형성된 리드프레임을 절단한다. 즉, 댐바(12) 내측인 리드(10)의 일정 영역을 절단한다. 상기 절단은 리드(10)의 제2면(10b)을 완전히 관통하여 실시된다. 또한, 이어서 상기 봉지부(26) 외측의 타이바(4)도 절단한다. 상기와 같이 하여, 마침내 상기 리드프레임과 상기 봉지부(26) 사이에 위치된 모든 영역이 제거되고 완전한 반도체패키지가 얻어진다.5. In the singulation step S5, the lead frame in which the encapsulation part 26 is formed is cut as shown in FIG. 5F. That is, the predetermined region of the lid 10 inside the dam bar 12 is cut. The cutting is carried out through the second surface 10b of the lid 10 completely. Furthermore, the tie bar 4 outside the said sealing part 26 is also cut | disconnected next. In this manner, all regions located between the lead frame and the encapsulation 26 are finally removed and a complete semiconductor package is obtained.

상기 단계는 펀치, 톱, 또는 이와 동등한 절단 장치를 이용하여 실시될 수 있다. 예를 들어, 상기 펀치나 톱은 봉지부(26) 외측에서 사용될 수 있다. 펀치가 사용된 경우, 완성된 반도패키지는 한번의 펀치 작동으로 리드프레임으로부터 완전하게 절단될 수 있다. 이는 통상 상기 리드프레임을 뒤집은 상태에서 펀치로 댐바(12)의 내측의 리드(10) 및 타이바(4)를 각각 절단함으로써 구현된다. 절단 위치는 봉지부(26) 측면으로 연장되는 절단된 리드(10) 또는 타이바(4)의 영역이 0에서, 예를 들면 0.5mm에 이르기까지 변경될 수 있다.The step can be carried out using a punch, saw, or equivalent cutting device. For example, the punch or saw may be used outside the encapsulation 26. If a punch is used, the finished peninsula package can be cut completely from the leadframe in one punch operation. This is usually achieved by cutting the lid 10 and tie bar 4 inside of the dam bar 12 with a punch in the inverted state of the lead frame. The cutting position may vary from zero to, for example, 0.5 mm, of the region of the cut lead 10 or tie bar 4 extending to the side of the encapsulation 26.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

따라서 본 발명에 의한 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법에 의하면, 그라운드용의 도전성와이어를 제1면, 제2면 및 제3면이 형성된 그라운드링중 제2면(와이어 본딩중 히터블럭에 접촉되는 면)과 대응하는 제1면에 본딩함으로써, 와이어 본딩중 그라운드링의 바운싱(Bouncing) 현상을 억제하는 효과가 있다. 따라서, 와이어 본딩이 양호하게 수행되어 전체적인 와이어 본딩 수율이 향상되는 효과가 있다.Therefore, according to the lead frame according to the present invention and the semiconductor package using the same and a method of manufacturing the same, the conductive wire for ground includes a second surface of the ground ring in which the first surface, the second surface, and the third surface are formed (heater block during wire bonding). By bonding to the first surface corresponding to the surface in contact with the surface), there is an effect of suppressing the bouncing phenomenon of the ground ring during wire bonding. Therefore, the wire bonding is performed well, there is an effect that the overall wire bonding yield is improved.

즉, 종래에는 칩탑재판의 둘레면(제3면과 대응되는 제1면)에 본딩함으로써바운싱 현상에 의해 와이어 본딩 수율이 현저히 저하되었지만, 본 발명은 이와 반대로 와이어 본딩 수율이 현저히 향상된다.That is, in the related art, the wire bonding yield is remarkably lowered by the bounce phenomenon by bonding to the peripheral surface (the first surface corresponding to the third surface) of the chip mounting plate, but the wire bonding yield is remarkably improved in the present invention.

또한, 본 발명은 칩탑재판 및 리드뿐만 아니라 그라운드링중 제1면 및 제3면이 봉지부 내측에 위치됨으로써, 특히 상기 칩탑재판과 봉지부 사이의 결합력이 더욱 향상된다. 즉, 종래에는 상기 칩탑재판의 제1면 및 제3면이 봉지부 내측에 위치되었지만, 본 발명은 상기 칩탑재판과 연결된 그라운드링의 제1면 및 제3면이 봉지부 내측에 더 위치됨으로써, 전체적으로 상기 칩탑재판과 봉지부와의 결합력이 더욱 향상되는 효과가 있다.In addition, in the present invention, the first and third surfaces of the ground ring as well as the chip mounting plate and the lead are positioned inside the encapsulation portion, thereby further improving the bonding force between the chip mounting plate and the encapsulation portion. That is, although the first and third surfaces of the chip mounting plate are conventionally located inside the encapsulation part, in the present invention, the first and third surfaces of the ground ring connected to the chip mounting plate are further located inside the encapsulation part. By doing so, there is an effect that the bonding force between the chip mounting plate and the sealing portion as a whole further improves.

더불어, 반도체칩의 그라운드 신호를 처리하는 수단이 리드가 아닌 별도의 그라운드링이 됨으로써, 다수의 신호용 리드를 더 확보하는 효과가 있다.In addition, since the means for processing the ground signal of the semiconductor chip is a separate ground ring instead of a lead, there is an effect of further securing a plurality of signal leads.

즉, 반도체칩의 입출력패드 중 다수의 그라운드용 입출력패드를 도전성와이어를 이용하여 리드가 아닌 그라운드링에 모두 본딩함으로써, 그만큼 나머지 전력공급용 또는 신호용 입출력패드에 대한 리드를 확보하게 된다.That is, by bonding a plurality of ground input / output pads among the input / output pads of the semiconductor chip to the ground ring instead of the leads using conductive wires, the lead for the remaining power supply or signal input / output pads is secured accordingly.

따라서, 종래와 같이 파인피치화한 리드프레임을 제조하거나, 크기가 더 큰 리드프레임을 제조할 필요가 없다.Therefore, there is no need to manufacture a fine-pitched lead frame or a lead frame of larger size as in the prior art.

Claims (6)

대략 평판 모양의 프레임과;An approximately flat frame; 상기 프레임 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과;A ground ring positioned inside the frame, the ground ring having a first surface and a second surface that are substantially planar, and a plurality of third surfaces opposite to the first surface are formed between the first and second surfaces; 상기 그라운드링 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과;It is located inside the ground ring, and has a first plane and a second plane which are substantially planar, and between the first and second planes is opposite to the first plane and a third around the second plane. A chip mounting plate formed with a surface; 상기 프레임으로부터 내측으로 연장되어, 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와;Extending inwardly from the frame to connect and support the ground ring and the chip mounting plate, the first and second surfaces being substantially planar, opposite the first and second surfaces; A plurality of tie bars having a third surface formed on the outer side of the portion which is connected to the ground ring at the same time; 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드를 포함하여 이루어진 리드프레임.It is substantially radially arranged on the outer circumference of the ground ring, and has a first plane and a second plane that are substantially planar, and between the first and second surfaces is opposite to the first surface and at the same time the ground ring is connected. A lead frame comprising a plurality of leads having a third surface on the facing portion. 제1항에 있어서, 상기 그라운드링과 상기 칩탑재판 사이에는 다수의 장공(長空)이 형성된 것을 특징으로 하는 리드프레임.The lead frame according to claim 1, wherein a plurality of long holes are formed between the ground ring and the chip mounting plate. 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과;A chip mounting plate having a first surface and a second surface which are substantially planar, and having a third surface formed around the second surface while being opposite to the first surface between the first and second surfaces; 상기 칩탑재판의 외주연에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과;Located on an outer circumference of the chip mounting plate, the chip has a first plane and a second plane that are substantially planar, and a plurality of third surfaces that are opposite to the first surface are formed between the first and second surfaces. Ground ring; 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와;Connecting and supporting the ground ring and the chip mounting plate, the first and second surfaces being substantially planar, and between the first and second surfaces, the first and second surfaces being opposite to the first surface and connected to the ground ring. A plurality of tie bars having a third surface formed outside of the portion; 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드와;It is substantially radially arranged on the outer circumference of the ground ring, and has a first plane and a second plane that are substantially planar, and between the first and second surfaces is opposite to the first surface and at the same time the ground ring is connected. A plurality of leads formed with a third surface on the facing portion; 상기 칩탑재판의 제1면에 다수의 입출력패드를 가지며 접착수단으로 접착된 반도체칩과;A semiconductor chip having a plurality of input / output pads on the first surface of the chip mounting plate and bonded by an adhesive means; 상기 반도체칩의 입출력패드와 상기 그라운드링 및 리드의 제1면을 상호 기계적 및 전기적으로 연결하는 도전성와이어와;Conductive wires that mechanically and electrically connect the input / output pads of the semiconductor chip to the first surfaces of the ground ring and the leads; 상기 칩탑재판, 타이바, 그라운드링, 리드, 반도체칩 및 도전성와이어가 봉지재로 봉지되어 있되, 상기 칩탑재판, 타이바, 그라운드링 및 리드의 제2면은 봉지부 외측으로 노출되도록 형성된 봉지부를 포함하여 이루어진 반도체패키지.The chip mounting plate, the tie bar, the ground ring, the lead, the semiconductor chip and the conductive wire are encapsulated with the encapsulant, and the second surface of the chip mounting plate, the tie bar, the ground ring and the lead is exposed to the outside of the encapsulation part. Semiconductor package including an encapsulation. 제3항에 있어서, 상기 그라운드링은 제2면과 대응되는 제1면에만 도전성와이어가 본딩된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 3, wherein the ground ring has conductive wires bonded only to a first surface corresponding to a second surface. 대략 평판 모양의 프레임과, 상기 프레임 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 다수의 제3면이 형성된 그라운드링과, 상기 그라운드링 내측에 위치되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 제2면의 둘레에 제3면이 형성된 칩탑재판과, 상기 프레임으로부터 내측으로 연장되어, 상기 그라운드링 및 칩탑재판을 연결 및 지지하며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링과 연결된 부분의 외측에 제3면이 형성된 다수의 타이바와, 상기 그라운드링의 외주연에 대략 방사상으로 배열되어 있으며, 대략 평면인 제1면과 제2면을 갖고, 상기 제1면과 제2면 사이에는 상기 제1면과 반대면인 동시에 상기 그라운드링을 향하는 부분에 제3면이 형성된 다수의 리드를 포함하여 이루어진 리드프레임을 제공하는 단계와;A plurality of third frames having a generally flat plate-shaped frame, located inside the frame, having first and second surfaces that are substantially planar, and being opposite to the first surface between the first and second surfaces; A ground ring having a face, and a first surface and a second surface which are located inside the ground ring, and which are substantially planar, and between the first and second surfaces, are opposite to the first surface and at the same time. A chip mounting plate having a third surface formed around two surfaces thereof, extending inwardly from the frame to connect and support the ground ring and the chip mounting plate, and having first and second surfaces that are substantially planar; A plurality of tie bars having a third surface formed on the outer side of the portion connected to the ground ring and opposite to the first surface between the first and second surfaces, and substantially radially arranged on the outer circumference of the ground ring. Has a first plane and a second plane that are approximately planar, A first surface and a second surface, the method comprising: between providing a lead frame made in the part facing the ground ring at the same time of the first surface and the opposite surface comprises a plurality of leads are formed with the third side; 상기 칩탑재판의 제1면에 접착수단을 이용하여 다수의 입출력패드가 형성된 반도체칩을 접착하는 단계와;Bonding a semiconductor chip having a plurality of input / output pads formed thereon using an adhesive means to the first surface of the chip mounting plate; 상기 반도체칩의 입출력패드와 상기 그라운드링 및 리드의 제1면을 도전성와이어를 이용하여 기계적 및 전기적으로 본딩하는 단계와;Bonding the input and output pads of the semiconductor chip and the first surfaces of the ground ring and the leads to each other mechanically and electrically by using conductive wires; 상기 칩탑재판, 타이바, 그라운드링, 리드, 반도체칩 및 도전성와이어를 봉지재로 봉지하되, 상기 칩탑재판, 타이바, 그라운드링 및 리드의 제2면은 외측으로 노출되도록 봉지부를 형성하는 단계와;The chip mounting plate, the tie bar, the ground ring, the lead, the semiconductor chip and the conductive wire is encapsulated with an encapsulant, wherein the second surface of the chip mounting plate, tie bar, ground ring and the lead is formed to expose the outside Steps; 상기 프레임에서 상기 리드 및 타이바의 외측을 소잉하여 낱개의 반도체패키지로 싱귤레이션하는 단계를 포함하여 이루어진 반도체패키지의 제조 방법.The method of manufacturing a semiconductor package comprising the step of sawing the outer side of the lead and tie bar in the frame into a single semiconductor package. 제5항에 있어서, 상기 와이어 본딩 단계는 도전성와이어가 상기 그라운드링의 제2면과 대응되는 제1면에 본딩되도록 함을 특징으로 하는 반도체패키지의 제조 방법.The method of claim 5, wherein the wire bonding step allows the conductive wire to be bonded to a first surface corresponding to the second surface of the ground ring.
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US20060289973A1 (en) 2006-12-28
US20090166842A1 (en) 2009-07-02
US8102037B2 (en) 2012-01-24
KR20020076017A (en) 2002-10-09
US7928542B2 (en) 2011-04-19
US20020140061A1 (en) 2002-10-03
US20040159918A1 (en) 2004-08-19
US20110140250A1 (en) 2011-06-16
US7170150B2 (en) 2007-01-30
US7521294B2 (en) 2009-04-21

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