JPH098207A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

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Publication number
JPH098207A
JPH098207A JP7176898A JP17689895A JPH098207A JP H098207 A JPH098207 A JP H098207A JP 7176898 A JP7176898 A JP 7176898A JP 17689895 A JP17689895 A JP 17689895A JP H098207 A JPH098207 A JP H098207A
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JP
Japan
Prior art keywords
portion
inner lead
surface
semiconductor element
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7176898A
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Japanese (ja)
Inventor
Masaru Sasaki
Junichi Yamada
賢 佐々木
淳一 山田
Original Assignee
Dainippon Printing Co Ltd
大日本印刷株式会社
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Application filed by Dainippon Printing Co Ltd, 大日本印刷株式会社 filed Critical Dainippon Printing Co Ltd
Priority to JP7176898A priority Critical patent/JPH098207A/en
Publication of JPH098207A publication Critical patent/JPH098207A/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PURPOSE: To provide a resin sealed semiconductor device which can cope with the increased number of terminals and can be reduced more in size by providing the electrode sections of semiconductor elements between inner leads and electrically connecting the electrode sections to the front ends of inner leads on the side opposite to the semiconductor element mounting side through wires. CONSTITUTION: A semiconductor element 110 is mounted on and fixed to inner leads 131 with an insulating adhesive material 150 so that an electrode section (pad) 111 on the electrode section 111 side surface of the element 110 can be put between the leads 131. The electrode section 111 is electrically connected to the second surfaces 31Ab of the leads 131 at the front ends of inner lead sections 131 through wires 120. The thickness of the inner lead sections 131 is adjusted to 40μm and the thickness of portion other than the sections 131 is maintained at the thickness of a lead frame material which is 0.15mm. The arranging pitch of the inner leads is adjusted to as narrow as 0.12mm so that the number of terminals can be increased.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は,半導体装置の多端子化に対応でき、且つ、実装性の良い小型化が可能な樹脂封止型半導体装置に関するもので、特に、エッチング加工により、インナーリード部をリードフレーム素材の厚さよりも薄肉に外形加工したリードフレームを用いた樹脂封止型半導体装置に関する。 BACKGROUND OF THE INVENTION The present invention can correspond to a multi-terminal of semiconductor devices, and, as it relates to a resin sealed semiconductor device capable of mounting with good size reduction, in particular, by etching, the inner leads part a resin sealed semiconductor device using a lead frame trimmed to be thinner than the thickness of the leadframe material to.

【0002】 [0002]

【従来の技術】従来より用いられている樹脂封止型の半導体装置(プラスチックリードフレームパッケージ) BACKGROUND OF THE INVENTION Semiconductor devices of a resin sealed type which has been conventionally used (plastic lead frame package)
は、一般に図11(a)に示されるような構造であり、 Is generally a structure as shown in FIG. 11 (a),
半導体素子1120を搭載するダイパッド部1111や周囲の回路との電気的接続を行うためのアウターリード部1113、アウターリード部1113に一体となったインナーリード部1112、該インナーリード部111 Outer lead portions 1113 for electrical connection between the die pad portion 1111 and peripheral circuits for mounting a semiconductor element 1120, the inner lead portion 1112 is integral to the outer lead portion 1113, the inner lead portions 111
2の先端部と半導体素子1120の電極パッド1121 Electrode pads 1121 of the second tip and the semiconductor device 1120
とを電気的に接続するためのワイヤ1130、半導体素子1120を封止して外界からの応力、汚染から守る樹脂1140等からなっており、半導体素子1120をリードフレームのダイパッド1111部等に搭載した後に、樹脂1140により封止してパッケージとしたもので、半導体素子1120の電極パッド1121に対応できる数のインナーリード1112を必要とするものである。 Preparative electrically connected to wire 1130 for the stress from the outside to seal the semiconductor element 1120, and consists like resin 1140 to protect from contamination, mounting the semiconductor device 1120 to the die pad 1111 parts, etc. of the lead frame later, obtained by a package sealed with a resin 1140, those requiring the number of inner leads 1112 to accommodate the electrode pads 1121 of the semiconductor device 1120. そして、このような樹脂封止型の半導体装置の組立部材として用いられる(単層)リードフレームは、一般には図11(b)に示すような構造のもので、半導体素子を搭載するためのダイパッド1111と、ダイパッド1111の周囲に設けられた半導体素子と結線するためのインナーリード1112、該インナーリード1112 Then, (single layer) lead frame used as an assembly member of such a resin-sealed type semiconductor device, generally those of the structure shown in FIG. 11 (b), the die pad for mounting a semiconductor element 1111, an inner lead 1112 for semiconductor elements and wiring arranged around the die pad 1111, the inner lead 1112
に連続して外部回路との結線を行うためのアウターリード1113、樹脂封止する際のダムとなるダムバー11 Outer leads 1113 for performing connection with an external circuit in succession, dam bars 11 as a dam during the resin sealing
14、リードフレーム1110全体を支持するフレーム(枠)部1115等を備えており、通常、コバール、4 14, comprises a frame (frame) 1115 or the like for supporting the entire lead frame 1110, usually Kovar, 4
2合金(42%ニッケル−鉄合金)、銅系合金のような導電性に優れた金属を用い、プレス法もしくはエッチング法により形成されていた。 2 alloy (42% nickel - iron alloy), using the excellent conductivity metals such as copper-based alloys were formed by a press method or an etching method.

【0003】このようなリードフレームを利用した樹脂封止型の半導体装置(プラスチックリードフレームパッケージ)においても、電子機器の軽薄短小化の時流と半導体素子の高集積化に伴い、小型薄型化かつ電極端子の増大化が顕著で、その結果、樹脂封止型半導体装置、特にQFP(Quad Flat Package)及びTQFP(Thin Quad Flat Packa [0003] In such a semiconductor device of a resin sealing type using a lead frame (Plastic Leaded frame package), with higher integration of bandwagon and semiconductor element miniaturization of electronic devices, smaller and thinner and electrode increase in the terminal is significant, as a result, the resin sealed semiconductor device, especially QFP (Quad Flat Package) and TQFP (Thin Quad Flat Packa
ge)等では、リードの多ピン化が著しくなってきた。 In ge) and the like, the number of pins of the lead has become remarkably.
上記の半導体装置に用いられるリードフレームは、微細なものはフオトリソグラフイー技術を用いたエッチング加工方法により作製され、微細でないものはプレスによる加工方法による作製されるのが一般的であったが、このような半導体装置の多ピン化に伴い、リードフレームにおいても、インナーリード部先端の微細化が進み、当初は、微細なものに対しては、プレスによる打ち抜き加工によらず、リードフレーム部材の板厚が0.25mm Lead frame used in the semiconductor device are those fine is fabricated by etching method using a photolithographic e art, those that are not fine is being produced by the processing method according to the press were common, as the number of pins of the semiconductor device, also in the lead frame, the process proceeds miniaturization of the inner lead tip, initially, for those fine, regardless of the punching with a press, of the lead frame member plate thickness is 0.25mm
程度のものを用い、エッチング加工で対応してきた。 With such a degree, it has responded by etching. このエッチング加工方法の工程について以下、図10に基づいて簡単に述べておく。 Processes for the etching process will leave described briefly with reference to FIG. 先ず、銅合金もしくは42% First, a copper alloy or 42%
ニッケル−鉄合金からなる厚さ0.25mm程度の薄板(リードフレーム素材1010)を十分洗浄(図10 Nickel - thickness 0.25mm approximately thin plate made of an iron alloy (lead frame material 1010) was thoroughly washed (10
(a))した後、重クロム酸カリウムを感光剤とした水溶性カゼインレジスト等のフオトレジスト1020を該薄板の両表面に均一に塗布する。 (A)) was uniformly coated a photoresist 1020 of the water-soluble casein resist or the like as a photosensitive agent potassium dichromate on both surfaces of the thin plate. ((図10(b)) 次いで、所定のパターンが形成されたマスクを介して高圧水銀灯でレジスト部を露光した後、所定の現像液で該感光性レジストを現像して(図10(c))、レジストパターン1030を形成し、硬膜処理、洗浄処理等を必要に応じて行い、塩化第二鉄水溶液を主たる成分とするエッチング液にて、スプレイにて該薄板(リードフレーム素材1010)に吹き付け所定の寸法形状にエッチングし、貫通させる。(図10(d)) 次いで、レジスト膜を剥膜処理し(図10(e))、洗浄後、所望のリードフレームを得て、エッチング加工工程を終了する。このように、エッチング加工等によって作製されたリードフレームは、更に、所定のエリアに銀メッキ等が施される。次いで、洗浄、乾燥等の処理を経て、インナー ((FIG. 10 (b)) Then, after exposing the resist portion in a high-pressure mercury lamp through a mask having a predetermined pattern is formed, by developing the photosensitive resist in predetermined developer (FIG. 10 (c) ), a resist pattern 1030 is formed, hardening processing is performed as necessary cleaning process or the like, in an etching solution to the aqueous solution of ferric chloride as a main component, the thin plate by spraying the (lead frame material 1010) blowing etched into a predetermined size and shape, to penetrate. (FIG. 10 (d)) then, the resist film was 剥膜 process (FIG. 10 (e)), after washing, obtain a desired lead frame, etching process It terminates. Thus, the lead frame made by etching or the like, silver plating or the like is applied to a predetermined area. then, after washing, a process such as drying, inner ード部を固定用の接着剤付きポリイミドテープにてテーピング処理したり、必要に応じて所定の量タブ吊りバーを曲げ加工し、ダイパッド部をダウンセットする処理を行う。しかし、エッチング加工方法においては、エッチング液による腐蝕は被加工板の板厚方向の他に板幅(面)方向にも進むため、その微細化加工にも限度があるのが一般的で、図10に示すように、リードフレーム素材の両面からエッチングするため、ラインアンドスペース形状の場合、ライン間隔の加工限度幅は、板厚の50〜100%程度と言われている。又、リードフレームの後工程等のアウターリードの強度を考えた場合、一般的には、その板厚は約0.125mm以上必要とされている。この為、図10に示すようなエッチング加工方法の場合、リードフレー Or taping treatment with an adhesive with a polyimide tape for fixing the over de section, if necessary by bending a predetermined quantity tab suspension bar, it performs a process of down-set the die pad portion. However, in the etching method since the corrosion by the etchant proceeds to other the plate width (plane) direction of the plate thickness direction of the work plate, its miniaturization general that there is a limit to the processing, as shown in FIG. 10, for etching from both sides of the lead frame material, the case of the line-and-space shape, machining limits the width of the line spacing is said 50 to 100% of the plate thickness. also, outer leads of the process or the like after the lead frame considering the strength of, in general, the thickness is required not less than about 0.125 mm. Therefore, when the etching method as shown in FIG. 10, the lead frame ムの板厚を0.15 The thickness of the beam 0.15
mm〜0.125mm程度まで薄くすることにより、ワイヤボンデイングのための必要な平坦幅70〜80確保し、0.165mmピッチ程度の微細なインナーリード部先端のエッチングによる加工を達成してきたが、これが限度とされていた。 By thinning to about Mm~0.125Mm, wire Bonde flat width 70-80 securing necessary for queuing, have been achieved working by etching fine inner lead tip of about 0.165mm pitch, which is It had been the limit.

【0004】しかしながら、近年、樹脂封止型半導体装置は、小パッケージでは、電極端子であるインナーリードのピッチが0.165mmピッチを経て、既に0.1 However, in recent years, resin-encapsulated semiconductor device, in small packages, the pitch of the inner lead is an electrode terminal through the 0.165mm pitch, already 0.1
5〜0.13mmピッチまでの狭ピッチ化要求がでてきた事と、エッチング加工において、リード部材の板厚を薄した場合には、アセンブリ工程や実装工程といった後工程におけるアウターリードの強度確保が難しいという点から、単にリード部材の板厚を薄くしてエッチング加工を行う方法にも限界が出てきた。 And that the narrow pitch request until 5~0.13mm pitch came out, in the etching process, when thin the thickness of the lead member, the strength of the outer lead securing in step after such assembly process and the mounting process in view of difficulty, simply it comes out is a limit to how to reduce the thickness of the lead member performing etching.

【0005】これに対応する方法として、アウターリードの強度を確保したまま微細化を行う方法で、インナーリード部分をハーフエッチングもしくはプレスにより薄くしてエッチング加工を行う方法が提案されている。 As a method corresponding thereto, in a manner of performing while miniaturization and ensuring the strength of the outer leads, the method of performing etching by reducing the inner lead portions by half etching or press have been proposed. しかし、プレスにより薄くしてエッチング加工をおこなう場合には、後工程においての精度が不足する(例えば、 However, when performing etching with thinned by press, accuracy in a subsequent step is insufficient (for example,
めっきエリアの平滑性)、ボンデイング、モールデイング時のクランプに必要なインナーリードの平坦性、寸法精度が確保されない、製版を2度行なわなければならない等製造工程が複雑になる、等問題点が多くある。 Smoothness of the plating areas), bonding, flatness mall Day ing time of the inner lead necessary to clamp, not be ensured dimensional accuracy, such as manufacturing processes must be performed prepress twice it is complicated, many like problems is there. そして、インナーリード部分をハーフエッチングにより薄くしてエッチング加工を行う方法の場合にも、製版を2度行なわなければならず、製造工程が複雑になるという問題があり、いずれも実用化には、未だ至っていないのが現状である。 Even in the process of performing etching by reducing the inner lead portions by half etching it must be performed prepress twice, there is a problem that the manufacturing process becomes complicated, the both practical, is the current situation is not yet reached.

【0006】 [0006]

【発明が解決しようとする課題】一方、電子機器の軽薄短小化の時流に伴い、半導体パッケージにおいても、小型で実装性が良いものが求められるようになってきて、 [SUMMARY OF THE INVENTION Meanwhile, with the times of the miniaturization of electronic devices, also in the semiconductor package, come to those small implementation is good is determined,
外形寸法をほぼ半導体素子に合わせて、封止用樹脂により樹脂封止したCSP(Chip Size Pack The combined external dimensions substantially the semiconductor element, CSP the resin-sealed by a sealing resin (Chip Size Pack
age)と言われるパッケージが提案されるようになってきた。 Package which is said to age) has come to be proposed. CSPを使う恩恵を以下に簡単に述べる。 The benefit to use the CSP briefly described below. 第一にピン数が同じなら、QFP(Quad Fla If first the number of pins is the same, QFP (Quad Fla
t Package)やBGA(Ball Grid t Package) and BGA (Ball Grid
Array)に比べ実装面積を格段に小さくできる。 Can be significantly reduced footprint compared to Array). 第二に、パッケージ寸法が同じならQFPやBGAよりもピン数を多くとれる。 Secondly, the package size can take many number of pins than the same if QFP or BGA. QFPについては、パッケージや基板の反りを考えると、実用的にを使える寸法は最大40mm角であり、アウターリードピッチが0.5m For QFP, given the warp of the package and the substrate, the dimensions that can be used practically is the largest 40mm angle, the outer lead pitch is 0.5m
mピッチのQFPでは304ピンが限界となる。 304 pins the QFP of m pitch is the limit. さらにピン数を増やすためには、0.4mmピッチや0.3m To further increase the number of pins, 0.4 mm pitch and 0.3m
mピッチが必要となるが、この場合には、ユーザが量産性の高い実装(一括リフロー・ハンダ付け)を行うのが難しくなってくる。 Although m pitches is required, in this case, the user it becomes difficult to perform high mounting mass productivity (batch reflow soldering). 一般にはQFPの製造に関してはアウターリードピッチが0.3mmピッチ以下ではコストを上げずに量産するのは困難と言われている。 In general, it is said that is difficult to mass production without increasing the cost in the outer lead pitch is 0.3mm pitch following is for the production of QFP. BGA BGA
は、上記QFPの限界を打破するものとし注目を集め始めたもので、外部端子を二次元アレイ状にし、外部端子ピッチを広げることで実装の負担を軽減しようとするものである。 Is intended began attention shall break the limit of the QFP, and an external terminal in a two-dimensional array, it is intended to reduce the burden of the implementation by widening the external terminal pitch. BGAの場合、外部端子が300ピンを超える領域でも、従来通りの一括リフロー・ハンダ付けはできるが、30mm〜40mm角になると、温度サイクルによって外部端子のハンダ・バンプにクラックが入るため、600ピン〜700ピン、最大でも1000ピンが実用の限界と一般には言われている。 For BGA, even in a region where the external terminals is greater than 300 pin, although it is batch reflow-soldering of conventional, at the 30mm~40mm angle, because the cracks in the solder bump of the external terminals by a temperature cycle, 600 pin 700 pin, 1000 pins at most is said in general and practical limitations. 外部端子をパッケージ裏面に二次元アレイに設けたCSPの場合には、B When the external terminals on the package back surface of the CSP provided in a two-dimensional array, B
GAのコンセプトを引継ぎ、且つ、アレイ状の端子ピッチを増やすことが可能となる。 It takes over the GA concept, and, it is possible to increase the array of terminal pitch. また、BGA同様、一括リフロー・ハンダ付けが可能である。 In addition, BGA Similarly, it is possible to batch reflow soldering. 第三に、QFPやBGAに比べるとパッケージ内部の配線長が短かくなるため、寄生容量が小さくなり伝搬遅延時間が短くなる。 Third, since the wiring length inside the package it is shorter than the QFP and BGA, the propagation delay time parasitic capacitance is reduced is shortened. LSIクロック周波数が100MH 100MH is LSI clock frequency
zを超えるようになると、QFPではパッケージ内の伝搬が問題になってしまう。 And so more than z, propagation in the package in the QFP becomes a problem. 内部配線長を短かくしたCS CS the internal wiring length is short hidden
Pの方が有利である。 If the P is advantageous. しかしながら、CSPは実装面では優れるものの、多端子化に対しては、端子のピッチをさらに狭めることが必要で、この面での限界がある。 However, although CSP is excellent in mounting surface, for number of terminals, is necessary to further narrow the pitch of the terminals, there is a limit in this respect. 本発明は、このような状況のもと、リードフレームを用いた樹脂封止型半導体装置において、多端子化に対応でき、且つ、一層の小型化に対応できる半導体装置を提供しようとするものである。 The present invention is based on these circumstances, in the resin sealing type semiconductor device using a lead frame, it can support multi-terminal of, and, intended to provide a semiconductor device which can cope with further miniaturization is there.

【0007】 [0007]

【課題を解決するための手段】本発明の樹脂封止型半導体装置は、2段エッチング加工によりインナーリードの厚さがリードフレーム素材の厚さよりも薄肉に外形加工されたリードフレームを用い、外形寸法をほぼ半導体素子に合わせて封止用樹脂により樹脂封止したCSP(C Resin-sealed semiconductor device of the present invention According to an aspect of the use of a lead frame thickness of the inner lead is trimmed to be thinner than the thickness of the leadframe material by two-step etching process, outer CSP was resin-sealed with a sealing resin to suit almost semiconductor device dimensions (C
hip Size Package)型の半導体装置であって、前記リードフレームは、リードフレーム素材よりも薄肉のインナーリードと、該インナーリードに一体的に連結したリードフレーム素材と同じ厚さの外部回路と接続するための柱状の端子柱とを有し、且つ、端子柱はインナーリードの外部側においてインナーリードに対して厚み方向に直交し、かつ半導体素子搭載側と反対側に設けられており、端子柱の先端面に半田等からなる端子部を設け、端子部を封止用樹脂部から露出させ、端子柱の外部側の側面を封止用樹脂部から露出させており、 A hip Size Package) type semiconductor device, the lead frame is connected to the thin inner lead than the lead frame material, to the inner lead to an external circuit having the same thickness as that of the leadframe material linked integrally and a columnar terminal post for, and, terminal post is perpendicular to the thickness direction with respect to the inner lead at the outer side of the inner lead, and is provided on the opposite side of the semiconductor element mounting side, the terminal post the terminal portion comprising the front end surface of a solder or the like is provided, to expose the terminal portions from the sealing resin portion and is exposed from the sealing resin portion external side surface of the terminal post,
半導体素子は、半導体素子の電極部(パッド)を有する面にて、インナーリード部に絶縁接着材を介して搭載されており、半導体素子の電極部(パッド)はインナーリード間に設けられ、半導体素子搭載側とは反対側のインナーリード先端面とワイヤにて電気的に結線されていることを特徴とするものである。 Semiconductor elements at the surface having the electrodes of the semiconductor element (the pad), is mounted through an insulating adhesive material on the inner lead portion, the electrode of the semiconductor element (pad) is provided between the inner leads, the semiconductor the element mounting side is characterized in that it is electrically connected at the opposite side of the inner lead front end surface and the wire. また、本発明の樹脂封止型半導体装置は、2段エッチング加工によりインナーリードの厚さがリードフレーム素材の厚さよりも薄肉に外形加工されたリードフレームを用い、外形寸法をほぼ半導体素子に合わせて封止用樹脂により樹脂封止したCS The resin encapsulated semiconductor device of the present invention, using a lead frame that is trimmed to be thinner than the thickness of the inner lead of the lead frame material thickness by two-step etching process, combined nearly semiconductor element Dimensions CS was resin-sealed by the sealing resin Te
P(Chip Size Package)型の半導体装置であって、前記リードフレームは、リードフレーム素材よりも薄肉のインナーリードと、該インナーリードに一体的に連結したリードフレーム素材と同じ厚さの外部回路と接続するための柱状の端子柱とを有し、且つ、 A P (Chip Size Package) type semiconductor device, the lead frame includes a thin inner lead than the lead frame material, and an external circuit of the same thickness as that of the leadframe material linked integrally to said inner leads and a terminal post of the columnar for connecting, and,
端子柱はインナーリードの外部側においてインナーリードに対して厚み方向に直交し、かつ半導体素子搭載側と反対側に設けられており、端子柱の先端の一部を封止用樹脂部から露出させて端子部とし、端子柱の外部側の側面を封止用樹脂部から露出させており、半導体素子は、 Terminal post is perpendicular to the thickness direction with respect to the inner lead at the outer side of the inner lead and the semiconductor element mounting side is provided on the opposite side, so as to expose a part of the tip of the terminal post from the sealing resin portion a terminal portion Te, and is exposed from the sealing resin portion external side surface of the terminal post, a semiconductor element,
半導体素子の電極部(パッド)を有する面にて、インナーリード部に絶縁接着材を介して搭載されており、半導体素子の電極部(パッド)はインナーリード間に設けられ、半導体素子搭載側とは反対側のインナーリード先端面とワイヤにて電気的に結線されていることを特徴とするものである。 At the surface having the electrodes of the semiconductor element (the pad), is mounted through an insulating adhesive material on the inner lead portion, the electrode of the semiconductor element (pad) is provided between the inner leads, the semiconductor element mounting side it is characterized in that it is electrically connected at the opposite side of the inner lead front end surface and the wire. そして上記において、請求項1ないし2 And in the above, claims 1 2
において、リードフレームはダイパッドを有しており、 In the lead frame has a die pad,
半導体素子はその電極部(パッド)をインナーリード部とダイパッド部との間に設けていることを特徴とするものである。 The semiconductor device is characterized in that it provided the electrode portion (pad) between the inner lead and the die pad portion. また、本発明の樹脂封止型半導体装置は、2 The resin encapsulated semiconductor device of the present invention, 2
段エッチング加工によりインナーリードの厚さがリードフレーム素材の厚さよりも薄肉に外形加工されたリードフレームを用い、外形寸法をほぼ半導体素子に合わせて封止用樹脂により樹脂封止したCSP(Chip Si CSP of the thickness of the inner lead by the step etching processing using a lead frame that is trimmed to be thinner than the thickness of the leadframe material, resin-sealed by a sealing resin combined external dimensions substantially the semiconductor element (Chip Si
ze Package)型の半導体装置であって、前記リードフレームは、リードフレーム素材よりも薄肉のインナーリードと、該インナーリードに一体的に連結したリードフレーム素材と同じ厚さの外部回路と接続するための柱状の端子柱とを有し、且つ、端子柱はインナーリードの外部側においてインナーリードに対して厚み方向に直交し、かつ半導体素子搭載側と反対側に設けられており、端子柱の先端面に半田等からなる端子部を設け、 A ze Package) type semiconductor device, the lead frame includes a thin inner lead than the lead frame material, for connection to an external circuit of the same thickness as that of the leadframe material linked integrally to said inner leads of and a columnar terminal post, and, terminal post is perpendicular to the thickness direction with respect to the inner lead at the outer side of the inner lead, and is provided on the opposite side of the semiconductor element mounting side, the tip of the terminal post the terminal portion made of solder or the like to the surface provided,
端子部を封止用樹脂部から露出させ、端子柱の外部側の側面を封止用樹脂部から露出させており、半導体素子は、半導体素子の一面に設けられたバンプを介してインナーリード部に搭載され、半導体素子とインナーリード部とが電気的に接続していることを特徴とするものである。 The terminal portion is exposed from the sealing resin portion, the external side surface of the terminal post and is exposed from the sealing resin portion, the semiconductor element, the inner lead portion via a bump formed on one surface of the semiconductor element mounted on the semiconductor element and the inner lead portion is characterized in that it is electrically connected. また、本発明の樹脂封止型半導体装置は、2段エッチング加工によりインナーリードの厚さがリードフレーム素材の厚さよりも薄肉に外形加工されたリードフレームを用い、外形寸法をほぼ半導体素子に合わせて封止用樹脂により樹脂封止したCSP(Chip Size The resin encapsulated semiconductor device of the present invention, using a lead frame that is trimmed to be thinner than the thickness of the inner lead of the lead frame material thickness by two-step etching process, combined nearly semiconductor element Dimensions CSP was resin-sealed by the sealing resin Te (Chip Size
Package)型の半導体装置であって、前記リードフレームは、リードフレーム素材よりも薄肉のインナーリードと、該インナーリードに一体的に連結したリードフレーム素材と同じ厚さの外部回路と接続するための柱状の端子柱とを有し、且つ、端子柱はインナーリードの外部側においてインナーリードに対して厚み方向に直交し、かつ半導体素子搭載側と反対側に設けられており、 A Package) type semiconductor device, the lead frame includes a thin inner lead than the lead frame material, to the inner leads to be connected to an external circuit having the same thickness as that of the leadframe material linked integrally and a columnar terminal post, and, terminal post is perpendicular to the thickness direction with respect to the inner lead at the outer side of the inner lead, and is provided on the opposite side of the semiconductor element mounting side,
端子柱の先端の一部を封止用樹脂部から露出させて端子部とし、端子柱の外部側の側面を封止用樹脂部から露出させており、半導体素子は、半導体素子の一面に設けられたバンプを介してインナーリード部に搭載され、半導体素子とインナーリード部とが電気的に接続していることを特徴とするものである。 A part of the tip of the terminal post is exposed from the sealing resin portion and the terminal portion, an external side surface of the terminal post and is exposed from the sealing resin portion, the semiconductor element is provided on one surface of the semiconductor element mounted on the inner lead portion via a bump that is, the semiconductor element and the inner lead portion is characterized in that it is electrically connected. そして上記において、インナーリードは、断面形状が略方形で第1面、第2面、第3面、第4面の4面を有しており、かつ第1面はリードフレーム素材と同じ厚さの他の部分の一方の面と同一平面上にあって第2面に向き合っており、第3面、第4面はインナーリードの内側に向かって凹んだ形状に形成されていることを特徴とするものである。 And in the above, the inner leads, a first surface cross-sectional shape with a substantially rectangular, the second surface, the third surface has the four sides of the fourth surface, and the first surface is the same thickness as the lead frame material is and opposite there of on one surface flush with the other part to the second surface, the third surface, the fourth surface is a feature that is formed on the recessed toward the inside of the inner leads it is intended to. 尚、ここでは、 It should be noted that, here,
CSP(Chip Size Package)型の半導体装置とは、半導体素子の厚み方向を除いた、X、Y The CSP (Chip Size Package) type semiconductor device, except for the thickness direction of the semiconductor element, X, Y
方向の外形寸法にほぼ近い形で封止用樹脂により樹脂封止した半導体装置の総称を言っており、本発明の半導体装置は、その中でもリードフレームを用いたものである。 And said generic semiconductor device resin-sealed by a sealing resin in substantially the form close to the direction of the outer dimensions, the semiconductor device of the present invention are those using a lead frame among them. また、上記において、端子柱の先端面に半田等からなる端子部を設け、端子部を封止用樹脂部から露出させる場合、半田等からなる端子部は封止用樹脂部から突出したものが一般的であるが、必ずしも突出する必要はない。 In the above, the terminal portion comprising a distal end surface of the terminal post of a solder or the like is provided, when exposing the terminal portions from the sealing resin portion, the terminal portions made of solder or the like things protruding from the resin portion for sealing it is generally but not necessarily protrudes. また、必要に応じて、封止用樹脂部から露出された端子柱の外部側の側面部分を接着材等を介して保護枠で覆っても良い。 If necessary, the side portions of the outer side of the exposed terminal post from the sealing resin portion may be covered with a protective frame via an adhesive or the like.

【0008】 [0008]

【作用】本発明の樹脂封止型半導体装置は、上記のように構成することにより、リードフレームを用いた樹脂封止型半導体装置において、多端子化に対応でき、且つ、 [Action] resin-sealed semiconductor device of the present invention, by the structure described above, in the resin sealing type semiconductor device using a lead frame, can support multi-terminal of, and,
実装性の良い小型の半導体装置の提供を可能とするものであり、同時に、従来の図11(b)に示す単層リードフレームを用いた場合のように、ダムバーのプレスによる除去工程や、アウターリードのフオーミング工程を必要としないため、これらの工程に起因して発生していたアウターリードのスキューの問題やアウターリードの平坦性(コープラナリティー)の問題を全く無くすことができる半導体装置の提供を可能とするものである。 Is intended to enable the provision of mounting with good small semiconductor device, at the same time, as in the case of using a single layer lead frame shown in the prior art of FIG. 11 (b), and removing step by the press of the dam bar, outer It does not require a lead Fuomingu steps, providing a semiconductor device which can eliminate these flatness due to occurred have been of the outer lead skew problems and outer leads in step (Coop Rana Rithy) problem at all and it makes it possible to. 詳しくは、2段エッチング加工によりインナーリード部の厚さが素材の厚さよりも薄肉に外形加工された、即ち、インナーリードを微細に加工された多ピンのリードフレームを用いているたとにより、半導体装置の多端子化に対応できるものとしており、且つ、外形寸法をほぼ半導体素子に合わせて、封止用樹脂により樹脂封止したCSP Specifically, the two-step etching process the thickness of the inner lead portion is trimmed to be thinner than the thickness of the material, i.e., by that uses the multi-pin lead frame which has been processed the inner lead fine semiconductor is assumed to be corresponding to the number of terminals of the device, and, combined external dimensions substantially the semiconductor element, resin-sealed by the sealing resin CSP
(Chip Size Package)型の半導体装置としていることにより、小型化して作製することを可能としている。 By being a (Chip Size Package) type semiconductor device, it is made possible to produce with miniaturization. 更に、後述する、図8に示す2段エッンチングにより作製された、インナーリードは、断面形状が略方形で第1面、第2面、第3面、第4面の4面を有しており、かつ第1面はリードフレーム素材と同じ厚さの他の部分の一方の面と同一平面上にあって第2面に向き合っており、第3面、第4面はインナーリードの内側に向かって凹んだ形状に形成されていることにより、インナーリード部の第2面は平坦性を確保でき、ワイヤボンデイング性の良いものとしている。 Furthermore, described below, were prepared by two-stage Ennchingu shown in FIG. 8, the inner lead, the first surface is the cross-sectional shape with a substantially rectangular, the second surface, the third surface has the four sides of the fourth surface and the first surface is opposite the second surface be on one face flush with the other parts of the same thickness as that of the lead frame material, the third surface, the fourth surface is towards the inside of the inner leads by being formed in the recessed Te, the second surface of the inner lead portions can be secured flatness, it is assumed good wire bonding property. また第1面も平坦面で、第3面、第4面はインナーリード側に凹状であるためインナーリード部は、安定しており、且つ、ワイヤボンデイングの平坦幅を広くとれる。 Also the flat surface and the first surface, the third surface, the inner lead portions because of the concave fourth surface on the inner lead side, stable, and, take a wide flat width of wire bonding.

【0009】また、本発明の樹脂封止型半導体装置は、 Further, the resin-sealed semiconductor device of the present invention,
半導体素子が、半導体素子の一面に設けられたバンプを介してインナーリード部に搭載され、半導体素子とインナーリード部とが電気的に接続していることにより、ワイヤボンデイングの必要がなく、一括したボンデイングを可能としている。 Semiconductor element, is mounted on the inner lead portion via a bump formed on one surface of the semiconductor element, by the semiconductor element and the inner lead portion is electrically connected, there is no need for wire bonding, and bulk thereby making it possible to bonding.

【0010】 [0010]

【実施例】本発明の樹脂封止型半導体装置の実施例を図にそって説明する。 Examples of the resin encapsulated semiconductor device of the embodiment of the present invention will be described with reference to FIG. 先ず、実施例1を図1に示し、説明する。 First, Examples 1 to FIG. 1, will be described. 図1(a)は実施例1の樹脂封止型半導体装置の断面図であり、図1(b)(イ)は図1(a)のA1− 1 (a) is a sectional view of a resin sealed semiconductor device of Embodiment 1, FIG. 1 (b) (i) FIG. 1 (a) A1-
A2におけるインナーリード部の断面図で、図1(b) In cross-sectional view of the inner lead portion of A2, Fig. 1 (b)
(ロ)は図1(a)のB1−B2における端子柱部の断面図である。 (B) is a sectional view of the terminal pillar portion in line B1-B2 in FIG. 1 (a). 図1中、100は半導体装置、110は半導体素子、111は電極部(パッド)、120はワイヤ、130はリードフレーム、131はインナーリード、131Aaは第1面、131Abは第2面、131 In Figure 1, 100 is a semiconductor device, 110 a semiconductor element, the electrode portion (pad), 120 wire 111, the lead frame 130, 131 is the inner lead, 131aa first surface, 131ab the second surface, 131
Acは第3面、131Adは第4面、133は端子柱、 Ac is the third surface, 131Ad the fourth surface 133 is terminal post,
133Aは端子部、133Bは側面、140は封止用樹脂、150は絶縁接着材、160は補強用テープある。 133A is the terminal unit, 133B is a side, 140 denotes a sealing resin, 150 an insulating adhesive material 160 is reinforced tape.
本実施例1の樹脂封止型半導体装置においては、半導体素子110は、半導体素子の電極部(パッド)111側の面で電極部(パッド)111がインナーリード間に収まるようにして、インナーリード131に絶縁接着材1 In the resin sealed semiconductor device of the first embodiment, the semiconductor device 110, the electrode of the semiconductor element (pad) electrode portions in 111-side surface (the pad) 111 is to fit between the inner leads, the inner leads 131 an insulating adhesive 1
50を介して搭載固定されている。 It is mounted fixed through 50. そして、電極部11 The electrode portions 11
1は、ワイヤ120にて、インナーリード部131の先端の第2面131Abと電気的に結線されている。 1, by wire 120, which is the second surface 131Ab electrically connected at the tip of the inner lead portion 131. 本実施例1の半導体装置100と外部回路との電気的な接続は、端子柱133先端部に設けられた半球状の半田からなる端子部133Aを介してプリント基板等へ搭載されることにより行われる。 Electrical connection between the semiconductor device 100 and an external circuit of the first embodiment, row by being mounted to a printed circuit board or the like via the terminal portion 133A consisting of hemispherical solder provided on the terminal post 133 tip divide. 実施例1の半導体装置100に使用のリードフレーム130は、42%ニッケル−鉄合金を素材としたもので、そして、図6(a)に示すような形状をしたエッチングにより外形加工されたリードフレームを用いたものである。 The semiconductor device lead frame 130 use the 100 of Example 1, 42% nickel - iron alloy as hereinbefore a material and a lead frame which is trimmed by etching in the shape as shown in FIG. 6 (a) it is those that were used. 端子柱133他の部分より薄肉に形成されたインナーリード131をもつ。 From terminal post 133 other portions with inner leads 131 formed on the thin-walled. ダムバー136は樹脂封止する際のダムとなる。 Dam bar 136 is the dam during the resin encapsulation. 尚、図6 Incidentally, FIG. 6
(a)に示すような形状をしたエッチングにより外形加工されたリードフレームを、本実施例においては用いたが、インナーリード部131と端子柱部133以外は6 Outline processing leadframe by etching using a shape (a), the was used in this embodiment, other than the inner lead portion 131 and the terminal posts 133 6
最終的に不要なものであるから、特にこの形状に限定はされない。 Since those ultimately unnecessary, are not particularly limited to this shape. インナーリード部131の厚さtは40μ The thickness t of the inner lead portion 131 40μ
m、インナーリード部131以外の厚さt 0は0.15 m, the thickness t 0 of the non-inner lead portions 131 0.15
mmでリードフレーム素材の板厚のままである。 It remains of the plate thickness of the lead frame material in mm. また、 Also,
インナーリードピッチは0.12mmと狭いピッチで、 Inner lead pitch is 0.12mm and a narrow pitch,
半導体装置の多端子化に対応できるものとしている。 It is set to be able to handle the multi-terminal of semiconductor devices. インナーリード部131の第2面131Abは平坦状でワイヤボンデイィングし易い形状となっており、第3面1 Second surface 131Ab of the inner lead portion 131 has a wire bonderized Ii ring easily shape flat third surface 1
31Ac、第4面131Adはインナーリード側へ凹んだ形状をしており、第2ワイヤボンディング面を狭くしても強度的に強いものとしている。 31ac, fourth surface 131Ad has a shape recessed to the inner lead side, it is assumed the second wire strength to strong bonding surfaces and narrow. 尚、図6(b)は図6(a)のC1−C2における断面を示している。 Incidentally, FIG. 6 (b) shows a cross section taken along C1-C2 of FIG. 6 (a). 補強用テープ160はインナーリード部にヨレが発生しないように固定しておくものである。 Reinforcing tape 160 is intended to be fixed so as twisting does not occur to the inner lead portion. 尚、インナーリードの長さが短かい場合には直接図6(a)に示す形状のリードフレームをエッチング加工にして作製し、これに後述する方法により半導体素子を搭載して樹脂封止できるが、インナーリードが長く、インナーリードにヨレを生じ易い場合には直接図6(a)に示す形状にエッチング加工することは出来ないため、図6(c)(イ)に示すようにインナーリード先端部を連結部131Bにて固定した状態にエッチング加工した後、インナーリード13 Incidentally, the lead frame having the shape shown in direct view. 6 (a) when paddle short length of the inner leads manufactured by the etching, can be resin sealing by mounting a semiconductor element by a method described later in this , the inner lead is long, since it is not possible to etching the shape shown in direct view. 6 (a) if prone to twist the inner lead, the inner lead front end as shown in FIG. 6 (c) (i) after etching the parts in a fixed state by connecting portions 131B, inner lead 13
1部を補強テープ160で固定し(図6(c) One part was fixed in the reinforcing tape 160 (FIG. 6 (c)
(ロ))、次いでプレスにて、半導体装置作製の際には不要の連結部131Bを除去し、この状態で半導体素子を搭載して半導体装置を作製する。 (B)), followed by a press to remove the unwanted coupling portion 131B is in the semiconductor device fabricated to produce a semiconductor device by mounting a semiconductor element in this state. (図6(c) (FIG. 6 (c)
(ハ)) 図6(c)(ロ)中E1−E2はプレスにて切断するラインを示している。 (Iii)) FIG. 6 (c) (ii) in E1-E2 indicates a line to cut by a press.

【0011】次に本実施例1の樹脂封止型半導体装置の製造方法を図5に基づいて簡単に説明する。 [0011] Next a method of manufacturing a resin-sealed semiconductor device of the first embodiment will be briefly described with reference to FIG. 先ず、後述するエッチング加工にて作製され、不要の部分をカッテイング処理等で除去されたものを、インナーリード先端部薄肉部が図5で上になるようにして用意した。 First, it is produced in later-described etching, a what is removing unnecessary parts in Katteingu process or the like, the inner lead tip thin portion was prepared as made above in FIG. 尚、インナーリード131部の長さが長い場合には、必要に応じて、インナーリードの先端部がポリイミドテープによりテーピング固定されているものを用意する。 Incidentally, when the length of the inner leads 131 parts is long, optionally, the distal end portion of the inner lead is prepared what is taped fixed by polyimide tape. 次いで半導体素子110の電極部111側面を図5で下にして、 Then an electrode portion 111 side of the semiconductor element 110 and the bottom in FIG. 5,
インナーリード131間に納め、絶縁接着材150を介してインナーリード131に搭載固定した。 Housed between the inner lead 131, mounted fixed to the inner leads 131 via an insulating adhesive material 150. (図5 (Figure 5
(a)) 半導体素子110をリードフレーム130に接着固定した後、リードフレーム側130を半導体の上にして、半導体素子110の電極部111とインナーリード部13 (A)) after the semiconductor element 110 is bonded and fixed to the lead frame 130, and the lead frame side 130 on the semiconductor, the electrode portions 111 of the semiconductor element 110 and the inner lead portions 13
1の先端部とをワイヤ120にてボンデイング接続した。 And bonding connections and one of the distal end portion at the wire 120. (図5(b)) 次いで、通常の封止用樹脂140で樹脂封止を行った。 (FIG. 5 (b)) Then, resin sealing was conducted in the usual sealing resin 140.
(図5(c)) 樹脂による封止は所定の型を用いて行うが、半導体素子110のサイズで、且つ、リードフレームの端子柱の外側の面が若干樹脂から外部へ突出した状態で封止した。 Performing the sealing with (FIG. 5 (c)) resin using a predetermined mold, but the size of the semiconductor element 110, and, sealed in a state where the outer surface of the terminal post of the lead frame protrudes slightly from the resin to the outside It was sealed.
次いで、不要なリードフレーム130の封止用樹脂14 Then, unnecessary lead frame 130 sealing resin 14
0面から突出している部分をプレスにて切断し、端子柱133を形成するとともに端子柱133の側面133B The portion protruding from plane 0 was cut by a press, the side surface of the terminal post 133 to form a terminal post 133 133B
を形成した。 It was formed. (図5(d)) この時、切断されるリードフレームのラインには、切断がし易いように、切り欠きを設けておくと良い。 (FIG. 5 (d)) At this time, the line of the lead frame to be cut, in order to facilitate cutting, and it is advisable to provide a notch. 特に、 In particular,
これらの切り欠きはエッチング時に、併せて加工しておけば手間が省ける。 These notches at the time of etching, time and effort can be saved if by working together. 図6に示すリードフレーム110のダムバー136、フレーム部137等が除去される。 Dam bars 136 of the lead frame 110 shown in FIG. 6, the frame unit 137 and the like are removed. この後、リードフレームの端子柱の外側の面に半田からなる端子部133Aを作製して半導体装置を作製した。 Thereafter, a semiconductor device was produced to prepare a terminal portion 133A made of solder on the surface of the outer side of terminal post of the lead frame.
(図5(e)) この半田からなる端子部133Aは外部回路基板と接続する際に、接続し易いように設けてあるが特に設けなくても良い。 (FIG. 5 (e)) the terminal portion 133A formed of the solder when connecting to an external circuit board, is provided for easy connection but may not be provided especially.

【0012】本発明の半導体装置に用いられるリードフレームの製造方法を以下、図にそって説明する。 [0012] The manufacturing method of a lead frame used in the semiconductor device of the present invention will be described with reference to FIG. 図8 Figure 8
は、本実施例1の樹脂封止型半導体装置に用いられたリードフレームの製造方法を説明するための、インナーリード先端部を含む要部における各工程断面図であり、ここで作製されるリードフレームを示す平面図である図6 Is for explaining the manufacturing method of the lead frame used in the resin-sealed-type semiconductor device of the first embodiment, a respective cross-sectional views of the main part including an inner lead tip portions, leads are produced here Figure is a plan view showing the frame 6
(a)のD1−D2部の断面部における製造工程図である。 Is a manufacturing process diagram in cross section of the D1-D2 parts of (a). 図8中、810はリードフレーム素材、820A、 In FIG. 8, 810 is a lead frame material, 820A,
820Bはレジストパターン、830は第一の開口部、 820B resist pattern, the first opening 830,
840は第二の開口部、850は第一の凹部、860は第二の凹部、870は平坦状面、880はエッチング抵抗層、131Aはインナーリード先端部、131Abはインナーリードの第2面を示す。 840 second opening, the first recess 850, second recess 860, 870 is planar side, 880 etch resistant layer, 131A are inner lead tip, 131ab is the second surface of the inner lead show. 先ず、42%ニッケル−鉄合金からなり、厚みが0.15mmのリードフレーム素材810の両面に、重クロム酸カリウムを感光剤とした水溶性カゼインレジストを塗布した後、所定のパターン版を用いて、所定形状の第一の開口部830、第二の開口部840をもつレジストパターン820A、82 First, 42% nickel - of iron alloy, on both sides of the thickness 0.15mm the leadframe material 810, after applying the potassium bichromate and a photosensitive agent soluble casein resist, using a predetermined pattern plate , the resist pattern 820A, 82 having a predetermined first opening 830 of the shape, the second opening 840
0Bを形成した。 To form a 0B. (図8(a)) 第一の開口部830は、後のエッチング加工においてリードフレーム素材810をこの開口部からベタ状にリードフレーム素材よりも薄肉に腐蝕するためのもので、レジストの第二の開口部840は、インナーリード先端部の形状を形成するためのものである。 (Fig. 8 (a)) the first opening 830, a lead frame material 810 in the etching process after intended to corrosion thinner than the lead frame material from the opening in a solid form, a second resist opening 840 is for forming the shape of the inner lead tip. 第一の開口部83 First opening 83
0は、少なくともリードフレーム810のンナーリード先端部形成領域を含むが、後工程において、テーピングの工程や、リードフレームを固定するクランプ工程で、 0 include, but N'narido tip formation region of at least the lead frame 810, in a later step, and taping step, a clamp step of fixing the lead frame,
ベタ状に腐蝕され部分的に薄くなった部分との段差が邪魔になる場合があるので、エッチングを行うエリアはインナーリード先端の微細加工部分だけにせず大きめにとる必要がある。 Since the step of a solid shape corrode partially thinned portion may become a hindrance, the area to be etched, it is necessary to take large without just microfabrication portion of the inner lead tip. 次いで、液温57°C、比重48ボーメの塩化第二鉄溶液を用いて、スプレー圧2.5kg/c Then, a liquid temperature 57 ° C, using a solution of ferric chloride having a specific gravity of 48 Baume, spray pressure 2.5 kg / c
2にて、レジストパターンが形成されたリードフレーム素材810の両面をエッチングし、ベタ状(平坦状) at m 2, both sides of the leadframe material 810 on which a resist pattern is formed by etching, solidly (flat)
に腐蝕された第一の凹部850の深さhがリードフレーム部材の約2/3程度に達した時点でエッチングを止めた。 The depth h of the first recess 850 which is corrosion stopped etching upon reaching approximately 2/3 of the lead frame member. (図8(b)) 上記第1回目のエッチングにおいては、リードフレーム素材810の両面から同時にエッチングを行ったが、必ずしも両面から同時にエッチングする必要はない。 In (Fig. 8 (b)) the first-time etching has been performed simultaneously etched from both sides of the lead frame material 810 need not necessarily be etched simultaneously from both sides. 少なくとも、インナーリード先端部形状を形成するための、 At least, for forming the inner lead tip portion shape,
所定形状の開口部をもつレジストパターン820Bが形成された面側から腐蝕液によるエッチング加工を行い、 Perform etching by etching solution from the resist pattern 820B is formed side having an opening of a predetermined shape,
腐蝕されたインナーリード先端部形成領域において、所定量エッチング加工し止めることができれば良い。 In corrosion is the inner lead tip portion formed regions, it is sufficient to stop a predetermined amount etched. 本実施例のように、第1回目のエッチングにおいてリードフレーム素材810の両面から同時にエッチングする理由は、両面からエッチングすることにより、後述する第2 As in this embodiment, the reason why simultaneously etched from both sides of the lead frame material 810 in the first round of etching, by etching from both sides, the later 2
回目のエッチング時間を短縮するためで、レジストパターン820B側からのみの片面エッチングの場合と比べ、第1回目エッチングと第2回目エッチングのトータル時間が短縮される。 In order to shorten the times th etching time, compared with the case of single-side etching of only from the resist pattern 820B side, total time of the first round etching and the second etching is shortened. 次いで、第一の開口部830側の腐蝕された第一の凹部850にエッチング抵抗層880 Then, the etching resistant layer 880 to the first recess 850 which is corrosion of the first opening portion 830 side
としての耐エッチング性のあるホットメルト型ワックス(ザ・インクテエック社製の酸ワックス、型番MR−W A resistance to etching as a hot-melt wax (The Inkuteekku manufactured by acid wax, model number MR-W
B6)を、ダイコータを用いて、塗布し、ベタ状(平坦状)に腐蝕された第一の凹部850に埋め込んだ。 The B6), by means of a die coater, coated, embedded in the first recess 850 which is corrosion solidly (flat). レジストパターン820B上も該エッチング抵抗層880に塗布された状態とした。 On the resist pattern 820B also has a state of being applied to the etch resistant layer 880. (図8(c)) エッチング抵抗層880を、レジストパターン820B The (Fig. 8 (c)) etch resistant layer 880, the resist pattern 820B
上全面に塗布する必要はないが、第一の凹部850を含む一部にのみ塗布することは難し為に、図8(c)に示すように、第一の凹部850とともに、第一の開口部8 Need not be applied on the entire surface, in order that the difficulty that only applied to a portion including a first recess 850, as shown in FIG. 8 (c), with the first recess 850, first opening part 8
30側全面にエッチング抵抗層880を塗布した。 It was applied etch resistant layer 880 to 30 side entire surface. 本実施例で使用したエッチング抵抗層880は、アルカリ溶解型のワックスであるが、基本的にエッチング液に耐性があり、エッチング時にある程度の柔軟性のあるものが、好ましく、特に、上記ワックスに限定されず、UV Etch resistant layer 880 used in this embodiment is a wax of an alkali soluble type, there is essentially resistant to the etching solution, those with a degree of flexibility in the etching, preferably, in particular, limited to the wax Sarezu, UV
硬化型のものでも良い。 It may be of curable. このようにエッチング抵抗層8 Thus etch resistant layer 8
80をインナーリード先端部の形状を形成するためのパターンが形成された面側の腐蝕された第一の凹部850 80 first recess 850 in which a pattern is corrosion of the formed surface side to form the shape of the inner lead tip portion
に埋め込むことにより、後工程でのエッチング時に第一の凹部850が腐蝕されて大きくならないようにしているとともに、高精細なエッチング加工に対しての機械的な強度補強をしており、スプレー圧を高く(2.5kg By embedding the, with the first recess 850 is prevented from becoming large corroded during etching in a subsequent step, it has a mechanical reinforcement of the high-definition etching, the spray pressure high (2.5kg
/cm 2以上)とすることができ、これによりエッチングが深さ方向に進行し易すくなる。 / Cm 2 or more) and it is possible to become thereby easier easily proceeds to etch the depth direction. この後、第2回目エッチングを行い、ベタ状(平坦状)に腐蝕された第一の凹部850形成面側からリードフレーム素材810をエッチングし、貫通させ、インナーリード先端部890を形成した。 This was followed a second time etching, etching the leadframe material 810 from the first recess 850 formed surface of which is corrosion solidly (flat), it is penetrated to form the inner lead tip 890. (図8(d)) 第1回目のエッチング加工にて作製された、リードフレーム面に平行なエッチング形成面は平坦であるが、この面を挟む2面はインナーリード側にへこんだ凹状である。 (FIG. 8 (d)) was produced in the first etching process, the etching formation surface parallel to the lead frame surface is flat, two surfaces sandwiching the surface is a concave recessed inner lead side . 次いで、洗浄、エッチング抵抗層880の除去、レジスト膜(レジストパターン820A、820B)の除去を行い、インナーリード先端部890が微細加工された図6(a)に示すリードフレームを得た。 Then, washing, removal of the etch resistant layer 880, the resist film (resist pattern 820A, 820B) performs removal, to obtain a lead frame shown in FIG. 6 to the inner lead tip portion 890 is microfabricated (a). エッチング抵抗層880とレジスト膜(レジストパターン820 Etch resistant layer 880 and a resist film (resist pattern 820
A、82B0)の除去は水酸化ナトリウム水溶液により溶解除去した。 A, 82B0) removal of dissolved removed by aqueous sodium hydroxide.

【0013】尚、上記のように、エッチングを2段階にわけて行うエッチング加工方法を、一般には2段エッチング加工方法といっており、特に、微細加工に有利な加工方法である。 [0013] Incidentally, as described above, the etching method of performing divided etched in two steps, generally is said that two-step etching method, in particular, is an advantageous working method for microfabrication. 本発明に用いた図6(a)、図6(b) 6 used in the present invention (a), FIG. 6 (b)
に示す、リードフレーム130の製造においては、2段エッチング加工方法と、パターン形状を工夫することにより部分的にリードフレーム素材を薄くしながら外形加工する方法とが伴行して採られている。 Shown in, in the production of the lead frame 130 includes a two-step etching method, and a method of trimmed are taken by BanKo while thinning the partially leadframe material by devising the pattern shape. 上記の方法によるインナーリード先端部131Aの微細化加工は、第二の凹部860の形状と、最終的に得られるインナーリード先端部の厚さtに左右されるもので、例えば、板厚t Microfabrication of the inner lead tip portion 131A according to the above method is intended to be left, right, and shape of the second recess 860, the thickness t of the inner lead tip finally obtained, for example, the thickness t
を50μmまで薄くすると、図8(e)に示す、平坦幅W1を100μmとして、インナーリード先端部ピッチpが0.15mmまで微細加工可能となる。 When thin to 50 [mu] m, shown in FIG. 8 (e), as 100μm flat width W1, the inner lead tip pitch p becomes fine processing until 0.15 mm. 板厚tを3 The thickness t 3
0μm程度まで薄くし、平坦幅W1を70μm程度とすると、インナーリード先端部ピッチpが0.12mm程度まで微細加工ができるが、板厚t、平坦幅W1のとり方次第ではインナーリード先端部ピッチpは更に狭いピッチまで作製が可能となる。 It thinned to about 0 .mu.m, when the flat width W1 of about 70 [mu] m, but the inner lead tip pitch p can microfabrication to about 0.12 mm, the plate thickness t, the inner lead tip pitch p depending-taking flat width W1 it is possible to produce up to pitch even smaller.

【0014】このようにエッチング加工にて、インナーリードの長さが短かい場合等、製造工程でインナーリードのヨレが発生しにくい場合には直接図6(a)に示す形状のリードフレーム得るが、インナーリードの長さが実施例1の場合に比べ長い場合はインナーリードにヨレが発生し易い為、図6(c)(イ)に示ように、インナーリード先端部から連結部131Bを設けてインナーリード先端部同士を繋げた形状にして形成したものをッチング加工にて得て、この後、半導体作製には不必要な連結部131Bをプレス等により切断除去して図6(a) [0014] In this way etching, etc. When paddle short length of the inner leads, but if the twist of the inner lead is unlikely to occur in the manufacturing process to obtain a lead frame having a shape shown in direct view 6 (a) since long when likely to occur are twisted to the inner lead is compared with the length example 1 of the inner lead, the shown so in FIG. 6 (c) (i), provided the connecting portion 131B from the inner lead tip portion obtaining one formed in the shape of connecting the inner lead tip portions at etching process, after the Te, the semiconductor fabrication is cut and removed by pressing or the like unnecessary coupling portion 131B FIGS. 6 (a)
に示す形状を得る。 Obtaining a shape shown in. 図7(a)、図7(b)に示すダイパッド235を有するリードフレーム230を作製する場合には、図7(c)(イ)に示すように、インナーリード231の先端に連結部231Bを設けてダイパッドと直接繋がった形状にエッチングにより外形加工した後に、プレス等により切断しても良い。 FIG. 7 (a), the case of manufacturing a lead frame 230 having a die pad 235 shown in FIG. 7 (b), as shown in FIG. 7 (c) (i), the connecting portion 231B to the front end of the inner lead 231 by etching in a shape directly connected to the die pad is provided after trimmed, it may be cut by a press or the like. 尚、図7(b)は図7(a)のC11−C21における断面図で、図7 In cross-sectional view of C11-C21 of FIG. 7 (b) FIG. 7 (a), 7
(c)中E11−E21は切断ラインを示している。 (C) in E11-E21 represents the cutting line. そして、めっきした後に切断除去すると、治具めっき方式でインナーリードをめっきする場合には、めっきの裏漏れがなく良い品質のリードフレームが得られる。 Then, when cut and removed after plating, when plating the inner leads by a jig plating method, a lead frame of good quality without the back leakage of the plating is obtained. 尚、前述のように、図6(c)に示すものを切断し、図6 Incidentally, as described above, cutting the one shown in FIG. 6 (c), 6
(a)に示す形状にする際には、図6(c)(ロ)に示すように、通常、補強のため補強用テープ160(ポリイミドテープ)を使用する。 When the shape shown in (a), as shown in FIG. 6 (c) (ii), typically use a reinforcing tape 160 (polyimide tape) for reinforcement. 図7(c)に示すものを切断する場合も同様である。 The same applies when cutting as shown in FIG. 7 (c). 図6(c)(ロ)の状態で、 In the state of FIG. 6 (c) (ii),
プレス等により連結部131Bを切断除去するが、半導体素子は、テープをつけた状態のままで、リードフレームに搭載され、そのまま樹脂封止される。 Cleaves removing the connecting portion 131B by press or the like, a semiconductor device, in the state in which with the tape, is mounted on the lead frame and sealed it with resin.

【0015】本実施例1の半導体装置に用いられたリードフレームのインナーリード先端部131Aの断面形状は、図9(イ)に示すようになっており、エッチング平坦面131Ab側の幅W1は反対側の面の幅W2より若干大きくなっており、W1、W2(約100μm)ともこの部分の板厚さ方向中部の幅Wよりも大きくなっている。 The cross-sectional shape of the inner lead tip portion 131A of the lead frame used in the semiconductor device of the first embodiment is as shown in FIG. 9 (b), the width W1 of the etched flat surface 131Ab side opposite has become slightly larger than the width W2 of the side surfaces, it is greater than W1, W2 (about 100 [mu] m) Tomoko portion of the plate thickness direction central width W. このようにインリーリード先端部の両面は広くなった断面形状であるため、図8(ロ)に示すように、どちらの面を用いても半導体素子(図示せず)とインナーリード先端部131Aとワイヤ120A、120Bによる結線(ボンデイング)がし易すいものとなっているが、 Because this way is a cross-sectional shape both surfaces became widely Inn Lee lead tip, as shown in FIG. 8 (b), (not shown) semiconductor device be used either side with the inner lead tip portion 131A a wire 120A, while connection (bonding) is has become easy crowded due 120B,
本実施例の場合はエッチング面側(図9(ロ)(a)) For this embodiment the etching surface (FIG. 9 (b) (a))
をボンデイング面としている。 It is a bonding surface. 図中131Abはエッチング加工による平坦面、131Aaはリードフレーム素材面、121A、121Bはめっき部である。 Figure 131Ab is a flat surface by etching, 131aa lead frame material surface, 121A, 121B is plated portion. エッチング平坦状面がアラビの無い面であるため、図9(ロ)の(a)の場合は、特に結線(ボンデイング)適性が優れる。 For etching flat surface is a surface without arabinogalactan, the case of FIG. 9 (b) of (a), excellent especially connection (bonding) suitability. 図9(ハ)は図10に示す加工方法にて作製されたリードフレームのインナーリード先端部831Cと半導体素子(図示せず)との結線(ボンデイング)を示すものであるが、この場合もインナーリード先端部931C Figure 9 (c) is shows the connection (bonding) between the inner lead tip portion 831C and the semiconductor device lead frame made by the processing method shown in FIG. 10 (not shown), the inner Again lead tip 931C
の両面は平坦ではあるが、この部分の板厚方向の幅に比べ大きくとれない。 The double-sided some flat, but made large compared to the width of the plate thickness direction of this part. また両面ともリードフレーム素材面である為、結線(ボンデイング)適性は本実施例のエッチング平坦面より劣る。 Also since both sides a leadframe material surface, connection (bonding) suitability inferior etching a flat surface in this embodiment. 図9(ニ)はプレスによりインナーリード先端部を薄肉化した後にエッチング加工によりインナーリード先端部931D、931Eを加工したものの、半導体素子(図示せず)との結線(ボンデイング)を示したものであるが、この場合はプレス面側が図に示すように平坦になっていないため、どちらの面を用いて結線(ボンデイング)しても、図9(ニ)の(a)、(b)に示すように結線(ボンデイング)の際に安定性が悪く品質的にも問題となる場合が多い。 Figure 9 (d) is an inner lead tip portion 931D by etching after thinning the inner lead tip portions by press, but were processed 931E, shows the connection (bonding) of the semiconductor element (not shown) there is, shown for this case is pressing surface is not flattened, as shown in figure, by connecting (bonding) with either side, FIG. 9 of (d) (a), (b) as is often the stability during the connection (bonding) is also a problem in poor quality manner.

【0016】次に実施例1の樹脂封止型半導体装置の変形例を挙げる。 [0016] Next modified examples of the resin sealed semiconductor device of the first embodiment. 図2(a)は実施例1の樹脂封止型半導体装置の変形例の断面図であり、図2(c)は変形例半導体装置の外観を示すもので、図2(c)(ロ)は下(底)側から見た図で、図2(c)(イ)は正面図で、 2 (a) is a cross-sectional view of a modification of the resin-encapsulated semiconductor device of Embodiment 1, FIG. 2 (c) shows the appearance of a variant semiconductor device, and FIG. 2 (c) (ii) is a view seen from below (bottom) side, FIG. 2 (c) (b) is a front view,
図2(b)は図1(a)のA1−A2に対応する位置での端子柱の断面図である。 Figure 2 (b) is a sectional view of a terminal post at a position corresponding to the A1-A2 of FIG. 1 (a). 変形例半導体装置は、実施例1の半導体装置とは端子部133Aが異なるもので、端子部は端子柱133の先端側を樹脂140から突出したようにしており、且つ、先端部の表面には溝133cが設けられており、溝を設けた状態で表面には半田を塗膜した状態にする、そして実装する際には、この溝133 Modification semiconductor device, in which the terminal portions 133A differs from the semiconductor device of the first embodiment, the terminal portion has a distal end side of the terminal post 133 as protruding from the resin 140, and, on the surface of the tip portion groove 133c is provided with, on the surface in a state in which a groove in a state that the coating film of the solder, and at the time of mounting, the groove 133
c部を通り半田が行き渡るようにしている。 Through the c section solder is to go around. 変形例の半導体体装置100Aは、端子部133A以外は、実施例1の半導体装置と同じである。 The semiconductor body apparatus 100A of modified example, except the terminal portion 133A is the same as the semiconductor device of the first embodiment.

【0017】次いで、実施例2の樹脂封止型半導体装置を挙げる。 [0017] Then, given resin sealing type semiconductor device of the second embodiment. 図3(a)は実施例2の樹脂封止型半導体装置の断面図であり、図3(b)は図3(a)のA3−A 3 (a) is a sectional view of a resin sealed semiconductor device of Example 2, A3-A in FIG. 3 (b) FIGS. 3 (a)
4におけるインナーリード部の断面図で、図3(c) In cross-sectional view of the inner lead portion of 4, FIG. 3 (c)
(イ)は図3(a)のB3−B4における端子柱部の断面図である。 (B) is a sectional view of the terminal pillar portion in B3-B4 of FIG. 3 (a). 図3中、200は半導体装置、210は半導体素子、211は電極部(パッド)、220はワイヤ、230はリードフレーム、231はインナーリード、231Aaは第1面、231Abは第2面、231 In Figure 3, 200 semiconductor device, 210 denotes a semiconductor element, 211 is the electrode portion (pad), 220 wire, 230 a lead frame, 231 inner leads, 231Aa first surface, 231Ab the second surface, 231
Acは第3面、231Adは第4面、233は端子柱部、233Aは端子部、233Bは側面、235はダイパッド、240は封止用樹脂、250は絶縁接着材、2 Ac is the third surface, 231Ad the fourth surface 233 is the terminal pillar portion, 233A is the terminal unit, 233B is a side, 235 a die pad, 240 a sealing resin, 250 an insulating adhesive material, 2
50Aは接着材、260は補強用テープある。 50A is adhesive, 260 is a reinforcing tape. 本実施例2の場合も、実施例1と同様に、半導体素子210は、 Also in this second embodiment, in the same manner as in Example 1, the semiconductor element 210,
半導体素子の電極部(パッド)211側の面で電極部(パッド)211がインナーリード間に収まるようにして、インナーリード231に絶縁接着材250を介して搭載固定されており、電極部211は、ワイヤ220にて、インナーリード部231の先端の第2面231Ab Electrode of the semiconductor element (pad) 211 side surface in the electrode portion (pad) 211 is to fit between the inner leads are mounted fixed via an insulating adhesive material 250 to the inner lead 231, the electrode 211 , by wire 220, the second surface 231Ab of the tip of the inner lead portions 231
と電気的に結線されているが、リードフレームにダイパッド235を有するもので、半導体素子210の電極部211はインナーリード部231とダイパッド235間に設けらている。 Although electrically being connected with, one having a die pad 235 to the lead frame, the electrode portions 211 of the semiconductor device 210 is found provided between the inner lead portion 231 and the die pad 235. また、本実施例2の場合も、実施例1 Also in the case of the second embodiment, Example 1
と同様に、半導体装置200と外部回路との電気的な接続は、端子柱233先端部に設けられた半球状の半田からなる端子部233Aを介してプリント基板等へ搭載されることにより行われる。 The same manner, electrical connection between the semiconductor device 200 and the external circuit, carried out by being mounted to a printed circuit board or the like via the terminal portion 233A consisting of hemispherical solder provided on the terminal post 233 tip and . 本実施例においては、ダイパッド235と半導体素子210を接着する接着材250 In the present embodiment, the adhesive 250 for bonding the die pad 235 and the semiconductor element 210
Aを導電性としており、且つ、ダイパッド235と端子柱部233とはインナーリード(吊りリード)にて接続されていることにより、半導体素子にて発生した熱をダイパッドを介して外部回路へ放散させることができる。 Has a conductivity A, and, by being connected by an inner lead (suspension leads) and the die pad 235 and the terminal posts 233, to dissipate to the outside circuit through the die pad the heat generated by the semiconductor element be able to.
尚、接着材250Aを導電性の接着材と必ずしもする必要はないが、ダイパッド235を端子柱部233を介してグランドラインに接続すると、半導体素子210がノイズに強くなるとともに、ノイズを受けない構造となる。 Although not necessarily required to be a conductive adhesive material an adhesive 250A, Connecting die pad 235 to the ground line via the terminal posts 233, together with the semiconductor device 210 becomes resistant to noise, it is not subject to noise structure to become.

【0018】実施例2の半導体装置に使用のリードフレーム230も、実施例1にて使用のリードフレームと同様に、42%ニッケル−鉄合金を素材としたものであるが、、図7(a)、図7(b)に示すように、ダイパッド235を有する形状をしており、端子柱233部分より薄肉に形成されたインナーリード231をもつ。 The semiconductor device lead frame 230 used in Example 2, similar to the lead frame used in Example 1, 42% nickel - but in which the iron alloy was material ,, view 7 (a ), as shown in FIG. 7 (b), it has a shape with the die pad 235, having inner leads 231 formed thinner than the terminal post 233 portion. インナーリード部231の厚さは40μm、端子柱233厚さは0.15mmである。 The thickness of the inner lead 231 40 [mu] m, the terminal post 233 thickness of 0.15 mm. そして、インナーリードピッチは0.12mmと狭いピッチで、半導体装置の多端子化に対応できるものとしている。 The inner lead pitch is 0.12mm and narrow pitch, it is assumed to accommodate a multi-terminal of semiconductor devices. インナーリード部23 Inner lead portion 23
1の第2面231Abは平坦状でワイヤボンディングし易い形状となっており、第3面231Ac、第4面23 1 of the second surface 231Ab is a wire bonding easily shape flat third surface 231Ac, fourth surface 23
1Adはインナーリード側へ凹んだ形状をしており、第2ワイヤボンディング面を狭くしても強度的に強いものとしている。 1Ad has a shape recessed to the inner lead side, it is assumed the second wire strength to strong bonding surfaces and narrow. また、実施例2の樹脂封止型半導体装置の作製は、実施例1の場合とほぼ同じ工程にて行う。 Also, the production of the resin-encapsulated semiconductor device of Example 2 is carried out in substantially the same process as in Example 1.

【0019】実施例2の樹脂封止型半導体装置の変形例としては、図2に示す実施例1の変形例の場合と同様に、端子柱233の先端部に溝233C(図3(c) [0019] As a modification of the resin-encapsulated semiconductor device of Example 2, as in the modification of the first embodiment shown in FIG. 2, the grooves in the tip portion of the terminal post 233 233C (FIG. 3 (c)
(ロ))を設け、封止用樹脂240から、突出させて、 The (b)) provided from the sealing resin 240, is protruded,
端子柱の先端部をそのまま端子233Aにしたものが挙げられる。 That the distal end portion of the terminal post as the terminal 233A and the like.

【0020】次いで、実施例3の樹脂封止型半導体装置を挙げる。 [0020] Then, given resin sealing type semiconductor device of the third embodiment. 図4(a)は実施例3の樹脂封止型半導体装置の断面図であり、図3(b)は図4(a)のA5−A 4 (a) is a sectional view of a resin sealed semiconductor device of Example 3, A5-A in FIG. 3 (b) FIGS. 4 (a)
6におけるインナーリード部の断面図で、図3(c) In cross-sectional view of the inner lead portion of 6, FIG. 3 (c)
(イ)は図3(a)のB5−B6における端子柱部の断面図である。 (B) is a sectional view of the terminal pillar portion in B5-B6 of FIG. 3 (a). 図4中、300は半導体装置、310は半導体素子、311はバンプ、330はリードフレーム、 In Figure 4, 300 is a semiconductor device, 310 denotes a semiconductor element, 311 is a bump, the lead frame 330,
331はインナーリード、331Aaは第1面、331 331 inner leads, 331Aa the first surface, 331
Abは第2面、331Acは第3面、331Adは第4 Ab the second surface, 331Ac the third surface, 331Ad fourth
面、333は端子柱部、333Aは端子部、333Bは側面、335はダイパッド、340は封止用樹脂、36 Surface, 333 terminal pillar portion, 333A is the terminal unit, 333B is a side, 335 a die pad, the 340 sealing resin, 36
0は補強用テープある。 0 is reinforcing tape. 本実施例の半導体装置300の場合は、実施例1や実施例2の場合と異なり、半導体素子310はバンプ311を持つもので、バンプ311を直接インナーリード330に搭載固定し、半導体素子3 If the semiconductor device 300 of this embodiment, unlike the first and second embodiments, the semiconductor device 310 is intended to have a bump 311, mounted fixed bumps 311 directly to the inner lead 330, the semiconductor device 3
10とインナーリード310とを電気的に結線するものである。 And 10 and the inner lead 310 is for electrically connection. また、本実施例3の場合も、実施例1や実施例2の場合と同様に、半導体装置300と外部回路との電気的な接続は、端子柱333先端部に設けられた半球状の半田からなる端子部333Aを介してプリント基板等へ搭載されることにより行われる。 Also in the case of the third embodiment, as in the case of Examples 1 and 2, the electrical connection between the semiconductor device 300 and the external circuit, terminal post 333 tip hemispherical solder provided It is performed by being mounted to a printed circuit board or the like via the terminal portion 333A consisting of.

【0021】実施例3の半導体装置に使用のリードフレーム330も、実施例1や実施例2にて使用のリードフレームと同様に、42%ニッケル−鉄合金を素材としたもので、図6(a)、図6(b)に示すような形状をしており、リードフレーム素材と同じ厚さの端子柱部33 The lead frame 330 of the semiconductor device to use third embodiment also, similarly to the lead frame used in Example 1 and Example 2, 42% nickel - obtained by a material of an iron alloy, FIG. 6 ( a), and FIG. 6 (has a shape as shown in b), the lead frame material with the same thickness terminal pillar portion 33
3他の部分より薄肉に形成されたインナーリード先端部331Aをもつ。 3 with the inner lead tip portion 331A which is formed to be thinner than other portions. インナーリード先端部331Aの厚さは40μm、インナーリード先端部331A以外の厚さは0.15mmで、強度的には後工程に充分耐えるものとなっている。 The thickness of the inner lead tip portion 331A is 40 [mu] m, at 0.15mm thickness than the inner lead tip portion 331A, the strength has become to withstand sufficiently the subsequent process. そして、インナーリードピッチは0.1 Then, the inner lead pitch is 0.1
2mmと狭いピッチで、半導体装置の多端子化に対応できるものとしている。 In 2mm and narrow pitch, it is assumed to accommodate a multi-terminal of semiconductor devices. インナーリード先端部331Aの第2面331Abは平坦状でワイヤボンデイィングし易い形状となっており、第3面331Ac、第4面331 Second surface 331Ab of the inner lead tip portion 331A is a wire bonderized Ii ring easily shape flat third surface 331Ac, fourth surface 331
Adはインナーリード側へ凹んだ形状をしており、第2 Ad has a shape recessed to the inner lead side, the second
ワイヤボンディング面を狭くしても強度的に強いものとしている。 Even by narrowing the wire bonding surface it is assumed strength stronger. また、実施例3の樹脂封止型半導体装置の作製も、実施例1の場合とほぼ同じ工程にて行うが、ダイパッド335に半導体素子を搭載し固定した後に、封止用樹脂にて樹脂封止する。 Also, production of the resin-encapsulated semiconductor device of Example 3, is carried out in substantially the same process as in Example 1, after the semiconductor element mounted and fixed to the die pad 335, the resin sealing by the sealing resin to stop.

【0022】実施例3の樹脂封止型半導体装置の変形例としては、図2に示す実施例1の変形例の場合と同様に、端子柱333の先端部に溝333C(図4(c) [0022] As a modification of the resin-encapsulated semiconductor device of the third embodiment, as in the modification of the first embodiment shown in FIG. 2, the grooves in the tip portion of the terminal post 333 333C (FIG. 4 (c)
(ロ))を設け、封止用樹脂340から、突出させて、 The (b)) provided from the sealing resin 340, is protruded,
端子柱の先端部をそのまま端子333Aにしたものが挙げられる。 That the distal end portion of the terminal post as the terminal 333A and the like.

【0023】 [0023]

【発明の効果】本発明の樹脂封止型半導体装置は、上記のように、リードフレームを用いた樹脂封止型半導体装置において、多端子化に対応でき、且つ、実装性良い半導体装置の提供を可能としている。 [Effect of the Invention The resin-sealed semiconductor device of the present invention, as described above, in the resin sealing type semiconductor device using a lead frame, can support multi-terminal of, and provide implementation of good semiconductor device It is made possible. 本発明の樹脂封止型半導体装置は、これと同時に、従来の図11(b)に示すアウターリードを持つリードフレームを用いた場合のようにダムバーのカット工程や、ダムバーの曲げ工程を必要としないため、アウターリードのスキューの問題や、平坦性(コープラナリティー)の問題を皆無としている。 Resin-sealed semiconductor device of the present invention, at the same time, and cutting process of the dam bar as in the case of using a lead frame having outer leads shown in the prior art in FIG. 11 (b), requiring dam bars bending step because it does not, problems and skew of the outer lead, has been completely eliminated the problem of flatness (Coop Rana Rithy). また、QFPやBGAに比べるとパッケージ内部の配線長が短かくなるため、寄生容量が小さくなり伝搬遅延時間を短くすることを可能にしている。 Further, since the wiring length inside the package than the QFP or BGA is shorter, which allows the parasitic capacitance is shorter becomes the propagation delay time smaller.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】実施例1の樹脂封止型半導体装置の断面図 FIG. 1 is a cross-sectional view of a resin sealed semiconductor device of Example 1

【図2】実施例1の樹脂封止型半導体装置の変形例の図 Figure variant of Figure 2 resin-sealed semiconductor device of Example 1

【図3】実施例2の樹脂封止型半導体装置の断面図 3 is a cross-sectional view of a resin sealed semiconductor device of Example 2

【図4】実施例3の樹脂封止型半導体装置の断面図 Sectional view of a resin sealed semiconductor device in FIG. 4 Example 3

【図5】実施例1の樹脂封止型半導体装置の作製工程を説明するための図 Diagram for a manufacturing process is described in [5] a resin sealed semiconductor device of Example 1

【図6】本発明の樹脂封止型半導体装置に用いられるリードフレームの図 6 is a diagram of a lead frame used in a resin sealed semiconductor device of the present invention

【図7】本発明の樹脂封止型半導体装置に用いられるリードフレームの図 [7] Figure of a lead frame used in a resin sealed semiconductor device of the present invention

【図8】本発明の樹脂封止型半導体装置に用いられるリードフレームの作製方法を説明するための図 Diagram for the manufacturing method will be described of a lead frame used in a resin sealed semiconductor device of the present invention; FIG

【図9】インナーリード先端部でのワイボンデイングの結線状態を示す図 9 is a diagram showing a connection state of the wire bonding of an inner lead tip portion

【図10】従来のリードフレームのエッチング製造工程を説明するための図 Figure 10 is a view for explaining an etching process of manufacturing the conventional lead frame

【図11】樹脂封止型半導体装置及び単層リードフレームの図 [11] Figure of resin-sealed semiconductor device and a single-layer lead frame

【符号の説明】 DESCRIPTION OF SYMBOLS

100、100A、200、300 樹脂封止型半導体装置 110、210、310 半導体素子 111、211、311 電極(パッド) 120、220、320 ワイヤ 120A、120B ワイヤ 121A、121B めっき部 130、230、330 リードフレーム 131、231、331 インナーリード 131Aa、231Aa、331Aa 第1面 131Ab、231Ab、331Ab 第2面 131Ac、231Ac、331Ac 第3面 131Ad、231Ad、331Ad 第4面 131B、231B 連結部 133、233、333 端子柱 133A 端子部 133B 側面 133C 溝 136、236 ダムバー 137、237 フレーム(枠)部 140、240、340 封止用樹脂 150 絶縁性接着材 160、260、3 100, 100A, 200 and 300 resin-encapsulated semiconductor device 110, 210, 310 semiconductor devices 111, 211, 311 electrode (pad) 120, 220, 320 wire 120A, 120B wire 121A, 121B plating portion 130, 230, 330 lead frame 131,231,331 inner lead 131Aa, 231Aa, 331Aa first surface 131Ab, 231Ab, 331Ab second surface 131Ac, 231Ac, 331Ac third surface 131Ad, 231Ad, 331Ad fourth surface 131B, 231B connecting portion 133,233,333 terminal post 133A terminal portion 133B side 133C grooves 136 and 236 a dam bar 137 and 237 frames (frame) unit 140, 240, 340 sealing resin 150 insulating adhesive material 160,260,3 0 補強用テープ 235 ダイパッド 810 リードフレーム素材 820A、820B レジストパターン 830 第一の開口部 840 第二の開口部 850 第一の凹部 860 第二の凹部 870 平坦状面 880 エッチング抵抗層 920C、920D、920E ワイヤ 921C、921D、921E めっき部 931D、931E インナーリード先端部 931Aa リードフレーム素材面 931Ac コイニング面 1010 リードフレーム素材 1020 フオトレジスト 1030 レジストパターン 1040 インナーリード 1110 リードフレーム 1111 ダイパッド 1112 インナーリード 1112A インナーリード先端部 1113 アウターリード 1114 ダムバー 1115 フレーム部(枠部) 1120 半導体素子 1121 0 reinforcing tape 235 die pad 810 leadframe material 820A, 820B resist pattern 830 first opening 840 second opening 850 first recess 860 second recess 870 flat surface 880 etch resistant layer 920C, 920D, 920E wire 921C, 921D, 921E plating unit 931D, 931E inner lead tip portions 931Aa leadframe material surface 931Ac coining surfaces 1010 leadframe material 1020 photoresist 1030 resist pattern 1040 inner lead 1110 leadframe 1111 die pad 1112 an inner lead 1112A inner lead tip 1113 outer leads 1114 dam bar 1115 frame portion (frame portion) 1120 semiconductor element 1121 極部(パッド) 1130 ワイヤ 1140 封止用樹脂 Extreme portion (pad) 1130 wire 1140 sealing resin

Claims (6)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 2段エッチング加工によりインナーリードの厚さがリードフレーム素材の厚さよりも薄肉に外形加工されたリードフレームを用い、外形寸法をほぼ半導体素子に合わせて封止用樹脂により樹脂封止したCSP [Claim 1] using the lead frame thickness of the inner lead is trimmed to be thinner than the thickness of the leadframe material by two-step etching process, a resin sealed by sealing resin combined external dimensions substantially the semiconductor element CSP that sealed were
    (ChipSize Package)型の半導体装置であって、前記リードフレームは、リードフレーム素材よりも薄肉のインナーリードと、該インナーリードに一体的に連結したリードフレーム素材と同じ厚さの外部回路と接続するための柱状の端子柱とを有し、且つ、端子柱はインナーリードの外部側においてインナーリードに対して厚み方向に直交し、かつ半導体素子搭載側と反対側に設けられており、端子柱の先端面に半田等からなる端子部を設け、端子部を封止用樹脂部から露出させ、端子柱の外部側の側面を封止用樹脂部から露出させており、半導体素子は、半導体素子の電極部を有する面にて、インナーリード部に絶縁接着材を介して搭載されており、半導体素子の電極部はインナーリード間に設けられ、半導体素子搭載側と A (ChipSize Package) type semiconductor device, the lead frame is connected to the thin inner lead than the lead frame material, and an external circuit of the same thickness as that of the leadframe material which is integrally connected to the inner leads and a columnar terminal post for, and, terminal post is perpendicular to the thickness direction with respect to the inner lead at the outer side of the inner lead, and is provided on the opposite side of the semiconductor element mounting side, the terminal post the terminal portion comprising the front end surface of a solder or the like is provided, to expose the terminal portions from the sealing resin portion, the external side surface of the terminal post and is exposed from the sealing resin portion, the semiconductor element, the semiconductor element at the surface having the electrode portion, is mounted through an insulating adhesive material on the inner lead portion, the electrode of the semiconductor element is provided between the inner leads, the semiconductor element mounting side は反対側のインナーリード先端面とワイヤにて電気的に結線されていることを特徴とする樹脂封止型半導体装置。 Resin-sealed semiconductor device characterized by being electrically connected at the opposite side of the inner lead front end surface and the wire.
  2. 【請求項2】 2段エッチング加工によりインナーリードの厚さがリードフレーム素材の厚さよりも薄肉に外形加工されたリードフレームを用い、外形寸法をほぼ半導体素子に合わせて封止用樹脂により樹脂封止したCSP 2. Using a lead frame thickness of the inner lead is trimmed to be thinner than the thickness of the leadframe material by two-step etching process, a resin sealed by sealing resin combined external dimensions substantially the semiconductor element CSP that sealed were
    (ChipSize Package)型の半導体装置であって、前記リードフレームは、リードフレーム素材よりも薄肉のインナーリードと、該インナーリードに一体的に連結したリードフレーム素材と同じ厚さの外部回路と接続するための柱状の端子柱とを有し、且つ、端子柱はインナーリードの外部側においてインナーリードに対して厚み方向に直交し、かつ半導体素子搭載側と反対側に設けられており、端子柱の先端の一部を封止用樹脂部から露出させて端子部とし、端子柱の外部側の側面を封止用樹脂部から露出させており、半導体素子は、半導体素子の電極部を有する面にて、インナーリード部に絶縁接着材を介して搭載されており、半導体素子の電極部はインナーリード間に設けられ、半導体素子搭載側とは反対側のインナーリ A (ChipSize Package) type semiconductor device, the lead frame is connected to the thin inner lead than the lead frame material, and an external circuit of the same thickness as that of the leadframe material which is integrally connected to the inner leads and a columnar terminal post for, and, terminal post is perpendicular to the thickness direction with respect to the inner lead at the outer side of the inner lead, and is provided on the opposite side of the semiconductor element mounting side, the terminal post some of the tip is exposed from the sealing resin portion and the terminal portion, an external side surface of the terminal post and is exposed from the sealing resin portion, the semiconductor element, the surface having the electrodes of the semiconductor element Te, is mounted through an insulating adhesive material on the inner lead portion, the electrode of the semiconductor element is provided between the inner lead, In'nari opposite to the semiconductor element mounting side ード先端面とワイヤにて電気的に結線されていることを特徴とする樹脂封止型半導体装置。 Resin-sealed semiconductor device characterized by being electrically connected at over de tip surface and the wire.
  3. 【請求項3】 請求項1ないし2において、リードフレームはダイパッドを有しており、半導体素子はその電極部をインナーリード部とダイパッド部との間に設けていることを特徴とする樹脂封止型半導体装置。 3. The method of claim 1 or 2, the lead frame has a die pad, the semiconductor element is resin-sealed, characterized in that is provided between the inner lead and the die pad portion and the electrode portion type semiconductor device.
  4. 【請求項4】 2段エッチング加工によりインナーリードの厚さがリードフレーム素材の厚さよりも薄肉に外形加工されたリードフレームを用い、外形寸法をほぼ半導体素子に合わせて封止用樹脂により樹脂封止したCSP 4. Using a lead frame thickness of the inner lead is trimmed to be thinner than the thickness of the leadframe material by two-step etching process, a resin sealed by sealing resin combined external dimensions substantially the semiconductor element CSP that sealed were
    (ChipSize Package)型の半導体装置であって、前記リードフレームは、リードフレーム素材よりも薄肉のインナーリードと、該インナーリードに一体的に連結したリードフレーム素材と同じ厚さの外部回路と接続するための柱状の端子柱とを有し、且つ、端子柱はインナーリードの外部側においてインナーリードに対して厚み方向に直交し、かつ半導体素子搭載側と反対側に設けられており、端子柱の先端面に半田等からなる端子部を設け、端子部を封止用樹脂部から露出させ、端子柱の外部側の側面を封止用樹脂部から露出させており、半導体素子は、半導体素子の一面に設けられたバンプを介してインナーリード部に搭載され、半導体素子とインナーリード部とが電気的に接続していることを特徴とする樹脂封止型半導 A (ChipSize Package) type semiconductor device, the lead frame is connected to the thin inner lead than the lead frame material, and an external circuit of the same thickness as that of the leadframe material which is integrally connected to the inner leads and a columnar terminal post for, and, terminal post is perpendicular to the thickness direction with respect to the inner lead at the outer side of the inner lead, and is provided on the opposite side of the semiconductor element mounting side, the terminal post the terminal portion comprising the front end surface of a solder or the like is provided, to expose the terminal portions from the sealing resin portion, the external side surface of the terminal post and is exposed from the sealing resin portion, the semiconductor element, the semiconductor element mounted on the inner lead portion via a bump formed on one surface, the resin-encapsulated semiconductor of the semiconductor element and the inner lead portion, characterized in that electrically connected 体装置。 Body apparatus.
  5. 【請求項5】 2段エッチング加工によりインナーリードの厚さがリードフレーム素材の厚さよりも薄肉に外形加工されたリードフレームを用い、外形寸法をほぼ半導体素子に合わせて封止用樹脂により樹脂封止したCSP 5. Using a lead frame thickness of the inner lead is trimmed to be thinner than the thickness of the leadframe material by two-step etching process, a resin sealed by sealing resin combined external dimensions substantially the semiconductor element CSP that sealed were
    (ChipSize Package)型の半導体装置であって、前記リードフレームは、リードフレーム素材よりも薄肉のインナーリードと、該インナーリードに一体的に連結したリードフレーム素材と同じ厚さの外部回路と接続するための柱状の端子柱とを有し、且つ、端子柱はインナーリードの外部側においてインナーリードに対して厚み方向に直交し、かつ半導体素子搭載側と反対側に設けられており、端子柱の先端の一部を封止用樹脂部から露出させて端子部とし、端子柱の外部側の側面を封止用樹脂部から露出させており、半導体素子は、半導体素子の一面に設けられたバンプを介してインナーリード部に搭載され、半導体素子とインナーリード部とが電気的に接続していることを特徴とする樹脂封止型半導体装置。 A (ChipSize Package) type semiconductor device, the lead frame is connected to the thin inner lead than the lead frame material, and an external circuit of the same thickness as that of the leadframe material which is integrally connected to the inner leads and a columnar terminal post for, and, terminal post is perpendicular to the thickness direction with respect to the inner lead at the outer side of the inner lead, and is provided on the opposite side of the semiconductor element mounting side, the terminal post some of the tip is exposed from the sealing resin portion and the terminal portion, the outer side surface of the terminal post and is exposed from the sealing resin portion, the semiconductor element is bump formed on one surface of the semiconductor element through mounted on the inner lead portion, a resin-sealed semiconductor device characterized by a semiconductor element and the inner lead portion is electrically connected.
  6. 【請求項6】 請求項1ないし5において、インナーリードは、断面形状が略方形で第1面、第2面、第3面、 6. The method according to claim 1 to 5, inner leads, a first surface cross-sectional shape with a substantially rectangular, the second surface, the third surface,
    第4面の4面を有しており、かつ第1面はリードフレーム素材と同じ厚さの他の部分の一方の面と同一平面上にあって第2面に向き合っており、第3面、第4面はインナーリードの内側に向かって凹んだ形状に形成されていることを特徴とする樹脂封止型半導体装置。 It has four surfaces of the fourth surface, and the first surface is opposite the second surface be on one face flush with the other parts of the same thickness as that of the lead frame material, a third surface , fourth surface is resin-sealed semiconductor device characterized by being formed in recessed toward the inside of the inner lead.
JP7176898A 1995-06-21 1995-06-21 Resin sealed semiconductor device Pending JPH098207A (en)

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