CN116741649A - Semiconductor packaging method and packaging structure - Google Patents
Semiconductor packaging method and packaging structure Download PDFInfo
- Publication number
- CN116741649A CN116741649A CN202310328064.3A CN202310328064A CN116741649A CN 116741649 A CN116741649 A CN 116741649A CN 202310328064 A CN202310328064 A CN 202310328064A CN 116741649 A CN116741649 A CN 116741649A
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- Prior art keywords
- photoresist
- semiconductor chip
- semiconductor
- island
- lead frame
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 108
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 86
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 230000008878 coupling Effects 0.000 claims abstract description 4
- 238000010168 coupling process Methods 0.000 claims abstract description 4
- 238000005859 coupling reaction Methods 0.000 claims abstract description 4
- 239000003292 glue Substances 0.000 abstract description 17
- 238000011068 loading method Methods 0.000 abstract description 11
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 4
- 238000005507 spraying Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000004090 dissolution Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- HUWSZNZAROKDRZ-RRLWZMAJSA-N (3r,4r)-3-azaniumyl-5-[[(2s,3r)-1-[(2s)-2,3-dicarboxypyrrolidin-1-yl]-3-methyl-1-oxopentan-2-yl]amino]-5-oxo-4-sulfanylpentane-1-sulfonate Chemical compound OS(=O)(=O)CC[C@@H](N)[C@@H](S)C(=O)N[C@@H]([C@H](C)CC)C(=O)N1CCC(C(O)=O)[C@H]1C(O)=O HUWSZNZAROKDRZ-RRLWZMAJSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
Abstract
The application provides a semiconductor packaging method and a packaging structure, wherein the packaging method comprises the following steps: coating photoresist on the surface of the base island of the lead frame; a semiconductor chip is attached to the position, coated with photoresist, on the surface of the base island, and the redundant photoresist overflows out of the semiconductor chip; removing photoresist overflowed out of the semiconductor chip; and electrically coupling and plastic packaging the lead frame and the semiconductor chip. The application solves the problem of controlling the glue amount in the process of loading the chip, improves the reliability of the packaging structure, has lower precision requirement on the glue amount, and is beneficial to improving the production efficiency.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging method and a semiconductor packaging structure.
Background
Chip packaging, i.e., semiconductor packaging, is a technique for packaging integrated circuits with insulating plastic or ceramic materials, and is an important part of the overall integrated circuit manufacturing process. The chip package plays roles of placing, fixing, sealing, protecting the chip and enhancing heat dissipation performance, and can isolate external pollution and damage of external force to the chip.
In recent years, semiconductor packages have been increasingly miniaturized, and lead frames have been also miniaturized as a part of the package junctions. In general, a lead frame includes a substrate, and islands and pins formed in the substrate, the islands being used to carry chips, and reducing the size of the islands is one way to reduce the size of the lead frame.
In the semiconductor packaging process, the chip is generally mounted and fixed on the base island of the lead frame by using adhesive (e.g. conductive adhesive), and the chip mounting process is generally implemented by using a dispensing or spraying process in the conventional process. However, for small-sized islands, the size of the islands is only slightly larger than the size of the chip (for example, the distance between the chip boundary and the island boundary is smaller than 100 um), so that the adhesive amount of the adhesive is difficult to control when dispensing or spraying, or the adhesive amount is less to cause poor bonding force between the chip and the islands, layering problem occurs, or the adhesive amount is more to cause overflow of the adhesive, bridging and adhesion to the back of the frame and other problems occur, and the reliability or electrical performance of the packaging structure is affected.
Accordingly, there is a need to provide an improved solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the application provides a semiconductor packaging method and a semiconductor packaging structure, which can solve the problem of controlling the glue amount in the chip mounting process and eliminate the adverse effect of too much or too little glue amount on the reliability of the packaging structure.
According to a first aspect of the present application, there is provided a semiconductor packaging method comprising:
coating photoresist on the surface of the base island of the lead frame;
a semiconductor chip is attached to the position, on the surface of the base island, of which the photoresist is coated, and the redundant photoresist overflows out of the semiconductor chip;
removing the photoresist overflowed out of the semiconductor chip;
and electrically coupling and plastic packaging the lead frame and the semiconductor chip.
Optionally, the photoresist is a positive photoresist.
Optionally, removing the photoresist that overflows outside the semiconductor chip includes:
exposing the surface of the base island on which the semiconductor chip is attached;
and dissolving and removing the positive photoresist overflowed out of the semiconductor chip after exposure treatment by using a developing solution.
Optionally, the photoresist is a negative photoresist.
Optionally, removing the photoresist that overflows outside the semiconductor chip includes:
and dissolving and removing the negative photoresist which overflows outside the semiconductor chip and is not subjected to exposure treatment by using a developing solution.
Optionally, the first surface of the semiconductor chip is attached to the surface of the base island, and when the photoresist is coated on the surface of the base island of the lead frame, the surface size of the photoresist coated on the surface of the base island is larger than the surface size of the first surface.
Optionally, the first surface of the semiconductor chip is attached to the surface of the base island, and when the photoresist is coated on the surface of the base island of the lead frame, the volume of the photoresist coated on the surface of the base island is larger than the product of the surface area of the first surface and the predetermined thickness.
Optionally, a distance between at least one boundary of the semiconductor chip and a corresponding boundary of the island is less than 100um.
According to a second aspect of the present application, there is provided a semiconductor package structure comprising:
a lead frame including a base island and a plurality of pins isolated from the base island;
the semiconductor chip is attached to the surface of the base island through photoresist and is electrically coupled with the plurality of pins;
and the plastic package body is used for packaging the lead frame and the semiconductor chip.
Optionally, the photoresist is a positive photoresist or a negative photoresist.
Optionally, a distance between at least one boundary of the semiconductor chip and a corresponding boundary of the island is less than 100um.
The technical scheme of the application has the beneficial effects that at least:
in the technical scheme provided by the embodiment of the application, the chip loading and fixing of the semiconductor chip on the base island are realized by adopting the photoresist, and compared with the existing chip loading scheme, the chip loading and fixing method can ensure firm combination between the semiconductor chip and the base island by coating enough photoresist during chip loading, so that the layering problem is avoided, the requirement on the precision of the glue output is lower, a small glue spraying nozzle is not required to be specially selected, and the generation efficiency is improved; in addition, based on the chemical characteristic that the photoresist is soluble under certain conditions, the overflow part of the photoresist overflowing outside the semiconductor chip can be easily removed, and the problems of bridging, adhesion to the back of the frame and the like caused by the overflow in the prior art are solved ， The reliability of the package structure is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
Fig. 1 illustrates a top view of a semiconductor package structure provided in accordance with an embodiment of the present application;
fig. 2 a-2 d illustrate schematic cross-sectional views of the semiconductor package of fig. 1 at various stages of packaging along AA'.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. The application may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
In addition, the same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations of relative positional relationships and are not intended to represent true proportions.
The semiconductor Package structure disclosed In the present application is, for example, a Package structure such as QFN (Quad flat No-lead), SOP (Small Outline Package ), ESOP (Exposed-Pad SmallOutline Package, bare pad small outline Package), DFN (Dual flat No-lead), PDFN (Power Dual Flat No-lead, dual flat No-lead power Package), DIP (Dual In-line Package), SOT (Small Outline Transistor, small outline transistor Package), or the like. The packaging structure disclosed by the application can be applied to various terminal devices, such as smart phones, smart televisions, smart television set-top boxes, personal computers (personal computer, PCs), wearable devices, smart broadband and other terminal devices. It should be noted that the encapsulation structure proposed by the embodiments of the present application is intended to include, but not be limited to, application in these and any other suitable types of terminal devices.
As shown in fig. 1, fig. 2a, fig. 2b, fig. 2c, and fig. 2d, the semiconductor package structure disclosed in the embodiment of the application includes: the semiconductor device includes a lead frame 10, a semiconductor chip 20, a plurality of leads 50, and a molding compound 40.
The lead frame 10 includes a base island 11 and a plurality of leads 12 disposed around the periphery of the base island 11 and separated from the base island 11. The semiconductor chip 20 is fixedly mounted on the upper surface of the base island 11 and is electrically coupled to the plurality of pins 12 through a plurality of leads 50. The plastic package body 40 encapsulates the lead frame 10, the semiconductor chip 20, and the plurality of leads 50 for package protection.
The base island 11 includes a first surface (such as an upper surface) and a second surface (such as a lower surface) opposite to each other, the first surface of the base island 11 is used for carrying the semiconductor chip 20, the second surface of the base island 11 can leak from the bottom surface of the package structure after the subsequent plastic packaging is completed, and the base island 11 can also serve as a pin of the semiconductor chip to realize a corresponding function, such as grounding, while enhancing the heat dissipation performance. As an example, only one land 11 and one semiconductor chip 20 carried on the land are illustrated in the present embodiment and the related drawings, but it should be understood that the number of lands in the lead frame 10 may be one or more, and the number of semiconductor chips that each land can carry may be one or more, where "a plurality" herein includes two.
The plurality of pins 12 are distributed at intervals on the periphery of the substrate 11, and after the packaging is completed, the plurality of pins 12 can be exposed from the side surface and/or the bottom surface of the plastic package body 40. The islands 11 may be formed, for example, of a metallic material such as aluminum to enhance heat dissipation to the semiconductor chip carried thereon.
The semiconductor chip 20 attached to the upper surface of the base island 11 includes, for example, at least one of a power chip and a normal chip. The semiconductor chip 20 includes a first surface (e.g. a back surface) and a second surface (e.g. a front surface) opposite to each other, in this embodiment, the first surface of the semiconductor chip 20 is fixedly attached to the upper surface of the substrate 11 through the photoresist 30, and the second surface of the semiconductor chip 20 is provided with a plurality of electrodes or electrode terminals electrically coupled to the corresponding plurality of leads 12 through the plurality of leads 50.
The plurality of leads 50 are metal leads such as gold wires, copper wires, and the like.
In this embodiment, the photoresist 30 is selected to mount the semiconductor chip 20 on the upper surface of the island 11, and the photoresist 30 is only present in the area directly below the first surface of the semiconductor chip 20 in the packaged structure after the packaging is completed, so that the situation that the photoresist overflows the island 11 is avoided. Alternatively, the photoresist 30 selected in the embodiment of the present application may be a positive photoresist or a negative photoresist.
The dicing process of the semiconductor chip 20 based on the photoresist 30 will be described in detail below with reference to fig. 2a to 2 d:
first, as shown in fig. 2a, a photoresist 30 is coated on the upper surface of the island 11 of the lead frame.
In some embodiments, the surface size of the photoresist 30 coated on the upper surface of the base island 11 is larger than the surface size of the first surface of the semiconductor chip 20 to be mounted. In other embodiments, the volume of the photoresist 30 coated on the upper surface of the island 11 is greater than the product of the surface area of the first surface of the semiconductor chip to be mounted and the predetermined thickness (i.e., the thickness of the photoresist 30 directly under the semiconductor chip after the mounting is completed). In this way, a firm bond between the semiconductor chip 20 and the island 11 can be ensured when mounting the semiconductor chip.
As an example, photoresist 30 may be coated on the upper surface of the island 11 in a sampled-to-spot manner. It can be appreciated that the specific glue amount of the photoresist 30 coated on the surface of the base island 11 is not strictly limited in each embodiment of the present application, so long as the foregoing requirement is met, that is, the precision requirement of the glue outlet amount of the glue dispensing device is lower, and the glue dispensing device does not need to select a small glue nozzle intentionally, so that the packaging efficiency can be improved.
Next, as shown in fig. 2b, the semiconductor chip 20 is mounted on the upper surface of the island 11 at a position where the photoresist 30 is coated, and the excess photoresist is overflowed outside the semiconductor chip 20.
In order to ensure that the bonding force between the semiconductor chip 20 and the island 11 is not poor and delamination problems due to the small amount of the photoresist during the mounting process are not occurred by taking an example that the semiconductor chip 20 is mounted at a position where the photoresist 30 is coated on the upper surface of the island 11 in such a manner that the first surface (e.g., the back surface) of the semiconductor chip 20 faces the island 11, the amount of the photoresist 30 as defined in the foregoing embodiments may be used so that the amount of the photoresist 30 coated on the upper surface of the island 11 is sufficient to fill the area under the first surface of the semiconductor chip 20 during the mounting, and there may be an excessive portion of the photoresist 30 that overflows outside the semiconductor chip 20.
Next, as shown in fig. 2c, the photoresist 30 overflowing the semiconductor chip 20 is removed;
alternatively, the photoresist 30 coated on the upper surface of the island 11 may be positive photoresist or negative photoresist.
When the positive photoresist is selected, the semiconductor chip 20 may be used as a mask, and the upper surface of the island 11 on which the semiconductor chip 20 is mounted may be subjected to exposure treatment using, for example, ultraviolet light or deep ultraviolet light, so that the positive photoresist 30 overflowing from the semiconductor chip 20 is chemically decomposed, and then the exposed positive photoresist portion overflowing from the semiconductor chip 20 is removed by dissolution with a developer. In this process, since the positive photoresist directly under the semiconductor chip 20 is not irradiated with ultraviolet light or deep ultraviolet light, it is not dissolved in the developing solution.
When the negative photoresist is selected, the unexposed negative photoresist that overflows the semiconductor chip 20 can be directly removed by dissolution with a developer. The process has fewer process flows because of no exposure operation, but requires strict control of the amount of developer to avoid excessive dissolution of the negative photoresist located directly under the semiconductor chip 20.
From the foregoing, it can be seen that, although the photoresist overflow occurs in the corresponding step of fig. 2b, the overflowed photoresist can be removed well. That is, the application can well solve the problem of glue overflow in the chip loading process, on the basis, various problems caused by too much or too little glue amount are effectively avoided, so that the glue amount control in the chip loading process is simpler, and the reliability of the packaging structure is improved.
Finally, as shown in fig. 2d, the lead frame 10 and the semiconductor chip 20 are electrically coupled and encapsulated.
As an example, referring to fig. 1, an electrical coupling between a semiconductor chip 20 and a plurality of pins 12 in a lead frame 10 may be implemented using a wire bonding process. And the lead frame 10 and the semiconductor chip 20 may be plastic-encapsulated with a material having insulating properties and strong binding force, such as epoxy, to form the plastic-encapsulated body 40, completing the encapsulation.
It can be appreciated that the package structure and the package method disclosed in the embodiments of the present application can be applied to a small-sized island, for example, the island 11 satisfies that the distance l1 between at least one boundary of the semiconductor chip 20 and the corresponding boundary of the island 11 is smaller than 100um, so as to solve the problem that the small-sized island is prone to glue overflow. Of course, the technical scheme disclosed by the application is not limited to be applied to the small-size base island.
In summary, in the technical scheme provided by the embodiment of the application, the chip loading and fixing of the semiconductor chip on the base island are realized by adopting the photoresist, and compared with the existing chip loading scheme, the chip loading method can ensure firm combination between the semiconductor chip and the base island by coating enough photoresist during chip loading, so that the layering problem is avoided, the requirement on the precision of the glue output is lower, a small glue spraying nozzle is not required to be specially selected, and the generation efficiency is improved; in addition, based on the chemical characteristic that the photoresist is soluble under certain conditions, the overflow part of the photoresist overflowing outside the semiconductor chip can be easily removed, and the problems of bridging, adhesion to the back of the frame and the like caused by the overflow in the prior art are solved ， The reliability of the package structure is improved.
Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present application and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present application.
Claims (11)
1. A semiconductor packaging method, comprising:
coating photoresist on the surface of the base island of the lead frame;
a semiconductor chip is attached to the position, on the surface of the base island, of which the photoresist is coated, and the redundant photoresist overflows out of the semiconductor chip;
removing the photoresist overflowed out of the semiconductor chip;
and electrically coupling and plastic packaging the lead frame and the semiconductor chip.
2. The semiconductor packaging method of claim 1, wherein the photoresist is a positive photoresist.
3. The semiconductor packaging method of claim 2, wherein removing the photoresist that overflows outside the semiconductor chip comprises:
exposing the surface of the base island on which the semiconductor chip is attached;
and dissolving and removing the positive photoresist overflowed out of the semiconductor chip after exposure treatment by using a developing solution.
4. The semiconductor packaging method of claim 1, wherein the photoresist is a negative photoresist.
5. The semiconductor packaging method of claim 4, wherein removing the photoresist that overflows outside the semiconductor chip comprises:
and dissolving and removing the negative photoresist which overflows outside the semiconductor chip and is not subjected to exposure treatment by using a developing solution.
6. The semiconductor packaging method according to any one of claims 1 to 5, wherein a first surface of the semiconductor chip is mounted on the island surface, and when the photoresist is coated on the island surface of the lead frame, a surface size of the photoresist coated on the island surface is set to be larger than a surface size of the first surface.
7. The semiconductor packaging method according to any one of claims 1 to 5, wherein a first surface of the semiconductor chip is mounted on the land surface, and when the photoresist is coated on the land surface of the lead frame, a volume of the photoresist coated on the land surface is set to be larger than a product of a surface area of the first surface and a predetermined thickness.
8. The semiconductor packaging method of claim 1, wherein a distance between at least one boundary of the semiconductor chip and a corresponding boundary of the island is less than 100um.
9. A semiconductor package structure, comprising:
a lead frame including a base island and a plurality of pins isolated from the base island;
the semiconductor chip is attached to the surface of the base island through photoresist and is electrically coupled with the plurality of pins;
and the plastic package body is used for packaging the lead frame and the semiconductor chip.
10. The semiconductor package structure of claim 9, wherein the photoresist is a positive photoresist or a negative photoresist.
11. The semiconductor package structure of claim 9, wherein a distance between at least one boundary of the semiconductor chip and a corresponding boundary of the island is less than 100um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310328064.3A CN116741649A (en) | 2023-03-22 | 2023-03-22 | Semiconductor packaging method and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310328064.3A CN116741649A (en) | 2023-03-22 | 2023-03-22 | Semiconductor packaging method and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116741649A true CN116741649A (en) | 2023-09-12 |
Family
ID=87910329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310328064.3A Pending CN116741649A (en) | 2023-03-22 | 2023-03-22 | Semiconductor packaging method and packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116741649A (en) |
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2023
- 2023-03-22 CN CN202310328064.3A patent/CN116741649A/en active Pending
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