KR20010060879A - Ball grid array package and manufacturing method thereof - Google Patents

Ball grid array package and manufacturing method thereof Download PDF

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Publication number
KR20010060879A
KR20010060879A KR1019990063337A KR19990063337A KR20010060879A KR 20010060879 A KR20010060879 A KR 20010060879A KR 1019990063337 A KR1019990063337 A KR 1019990063337A KR 19990063337 A KR19990063337 A KR 19990063337A KR 20010060879 A KR20010060879 A KR 20010060879A
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KR
South Korea
Prior art keywords
semiconductor chip
connection terminal
lead frame
grid array
package
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KR1019990063337A
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Korean (ko)
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변형직
Original Assignee
윤종용
삼성전자 주식회사
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Priority to KR1019990063337A priority Critical patent/KR20010060879A/en
Publication of KR20010060879A publication Critical patent/KR20010060879A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A method for manufacturing a ball grid array package is provided to improve reliability of a junction by adhering a solder ball, and to give adaptability to multi pins by making the pattern of plating. CONSTITUTION: Photoresist is applied on a lead frame. A metal pattern and a connection terminal are formed by a conductive metal material. A semiconductor chip(25) having an integrated circuit is adhered to the lead frame. The semiconductor chip and the connection terminal of the lead frame are wire-bonded. A package body(31) is formed by molding compound to encapsulate the semiconductor chip, the bonding wire(29) and the bonding portion. The lead frame is completely eliminated by an etching process, and an external terminal is formed in the connection terminal.

Description

볼 그리드 어레이 패키지와 그 제조 방법{Ball grid array package and manufacturing method thereof}Ball grid array package and manufacturing method

본 발명은 반도체 칩 패키지에 관한 것으로서, 더욱 상세하게는 볼 형태의 외부 입출력 단자가 일면에 배열되어 있는 볼 그리드 어레이(ball grid array) 패키지와 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package, and more particularly, to a ball grid array package having a ball type external input / output terminal arranged on one surface thereof, and a manufacturing method thereof.

반도체 소자와 그에 대한 패키지 기술은 상호 부합되어 고밀도화, 고속도화, 소형화 및 박형화를 목표로 계속적인 발전을 거듭해 왔다. 패키지 구조에 있어서 핀 삽입형에서 표면실장형으로 급격히 진행되어 회로기판에 대한 실장밀도를 높여 왔으며, 최근에는 베어 칩(bare chip)의 특성을 그대로 패키지 상태에서 유지하면서도 취급이 용이하고 패키지 크기가 크게 줄어든 칩 크기 패키지(CSP; Chip Scale Package)가 여러 제조 회사에서 개발되어 있으며 계속적인 연구가 활발히 진행되고 있다.Semiconductor devices and their packaging technologies have been matched to each other and have continued to develop with the goal of increasing density, high speed, miniaturization and thinning. The package structure has been rapidly advanced from the pin insertion type to the surface mount type, thereby increasing the mounting density of the circuit board. In recent years, the bare chip characteristics have been kept in the package state, while being easily handled and the package size has been greatly reduced. Chip Scale Packages (CSPs) have been developed by several manufacturing companies and are being actively researched.

도 1은 종래 기술에 따른 반도체 칩 패키지의 일 예를 나타낸 단면도로서, 후지쯔(Fujitsu)사의 범프 칩 캐리어(bump chip carrier)이다.1 is a cross-sectional view showing an example of a semiconductor chip package according to the prior art, which is a bump chip carrier of Fujitsu.

도 1을 참조하면, 이 반도체 칩 패키지(100)는 패키지 몸체의 밑면으로 반도체 칩(125)과 본딩 와이어(129)로 연결된 범프가 노출되어 있는 구조를 가지고 있다. 반도체 칩과 본딩 와이어 및 범프는 성형 수지로 형성된 패키지 몸체에 의해 외부환경으로부터 보호된다.Referring to FIG. 1, the semiconductor chip package 100 has a structure in which bumps connected to the semiconductor chip 125 and the bonding wire 129 are exposed to the bottom surface of the package body. The semiconductor chip, the bonding wire and the bump are protected from the external environment by the package body formed of the molding resin.

이와 같은 반도체 칩 패키지는 리드프레임을 하프 에칭(half etching)하고 그 하프 에칭된 부분에 외부 입출력 단자로 사용되는 범프를 형성하여 패키지 몸체를 형성한 후 리드프레임을 제거하여 제조된다.Such a semiconductor chip package is manufactured by half etching a lead frame, forming bumps to be used as external input / output terminals on the half etched portion to form a package body, and then removing the lead frame.

그러나, 이와 같은 반도체 칩 패키지의 경우에 가장 큰 문제점으로는 외부 입출력 단자로 사용되는 범프의 높이가 낮기 때문에 외부 기판에 실장할 때 접합 부분에서 크랙(crack)이 발생하기 쉬우며, 리드프레임을 하프 에칭하고 그 에칭된 부분에 범프를 도금으로 형성하기 때문에 핀 수에 많은 제약을 받아 다 핀 패키지적용이 불가능하다. 그리고, 하프 에칭된 도금된 홈에 직접 와이어 본딩(wire bonding)이 불가능하여 먼저 스터드 범프(stud bump)를 형성한 다음 그 위에 와이어 본딩하기 때문에 공정이 매우 복잡하다고 할 수 있다.However, in the case of such a semiconductor chip package, the biggest problem is that the bumps used as external input / output terminals have a low height, so that cracks are likely to occur at the joints when mounted on an external substrate, and the lead frame is half Since etching and plating the bumps on the etched portions are subject to a large number of fins, it is impossible to apply the fin package. In addition, since wire bonding is not directly possible on the half-etched plated grooves, a stud bump is first formed and then wire bonded thereon, thereby making the process very complicated.

본 발명의 목적은 크랙의 발생을 방지하고 다 핀 패키지 적용이 가능하며 공정이 단순한 구조의 볼 그리드 어레이 패키지와 그 제조 방법을 제공하는 데에 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a ball grid array package having a structure capable of preventing cracks, applying a multi-pin package, and having a simple process.

도 1은 종래 기술에 따른 반도체 칩 패키지의 일 예를 나타낸 단면도,1 is a cross-sectional view showing an example of a semiconductor chip package according to the prior art;

도 2 내지 도 6b는 본 발명에 따른 볼 그리드 어레이 패키지의 일 실시예의 제조 공정별 단면도이다.2 to 6b are cross-sectional views of manufacturing processes of an embodiment of a ball grid array package according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10; 볼 그리드 어레이 패키지 21; 리드프레임10; Ball grid array package 21; Leadframe

22; 포토 레지스트(photo resist) 23; 도금 패턴22; Photo resist 23; Plating pattern

25; 반도체 칩 27; 접착제25; Semiconductor chip 27; glue

29; 본딩 와이어(bonding wire) 31; 패키지 몸체29; Bonding wire 31; Package body

33; 솔더 볼(solder ball) 50; 적층 칩 패키지33; Solder ball 50; Laminated chip package

이와 같은 목적을 달성하기 위한 본 발명에 따른 볼 그리드 어레이 패키지는, 집적회로가 형성된 반도체 칩과, 상기 반도체 칩과 본딩와이어로 와이어 본딩되어 있는 접속 단자와, 상기 접속단자의 밑면에 형성되어 있는 외부 접속 단자, 및 상기 반도체 칩과 본딩 와이어를 봉지하고 밑면을 제외한 상기 접속 단자의 외주면을 봉지하는 패키지 몸체를 포함하는 것을 특징으로 한다.The ball grid array package according to the present invention for achieving the above object is a semiconductor chip formed with an integrated circuit, a connection terminal wire-bonded with the semiconductor chip and the bonding wire, and an external formed on the bottom surface of the connection terminal And a package body encapsulating the connection terminal and the semiconductor chip and the bonding wire and encapsulating the outer circumferential surface of the connection terminal except the bottom surface.

또한, 상기 목적을 달성하기 위한 본 발명에 따른 볼 그리드 어레이 패키지 제조 방법은, ⒜ 리드프레임에 포토 레지스트(photo resist)를 도포하고 도전성 금속 재질로 금속패턴과 접속 단자를 형성하는 단계와, ⒝ 집적회로가 형성된 반도체 칩을 리드프레임에 부착시키고 반도체 칩과 리드프레임의 접속단자를 와이어 본딩하는 단계와, ⒞ 반도체 칩과 본딩 와이어(bonding wire) 및 그 접합 부위를 봉지 하도록 성형 수지로 패키지 몸체를 형성하는 단계, 및 ⒟ 리드프레임을 에칭으로 완전히 제거하고 접속 단자에 외부 접속단자를 형성하는 단계를 포함하는 것을 특징으로 한다.In addition, a method for manufacturing a ball grid array package according to the present invention for achieving the above object, the step of applying a photo resist (⒜ photoresist) to the lead frame and forming a metal pattern and connection terminals made of a conductive metal material, Attaching a semiconductor chip having a circuit to the lead frame and wire bonding the connecting terminal of the semiconductor chip and the lead frame, and (i) forming a package body with a molding resin so as to seal the semiconductor chip, the bonding wire and the bonding portion thereof; And removing the lead frame completely by etching and forming external connection terminals in the connection terminals.

이하 첨부 도면을 참조하여 본 발명에 따른 볼 그리드 어레이 패키지와 그 제조 방법을 보다 상세하게 설명하고자 한다.Hereinafter, a ball grid array package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

도 2 내지 도 6b는 본 발명에 따른 볼 그리드 어레이 패키지의 일 실시예의 제조 공정별 단면도이다.2 to 6b are cross-sectional views of manufacturing processes of an embodiment of a ball grid array package according to the present invention.

도 2와 도 3을 참조하면, 먼저 리드프레임(21)에 포토 레지스트(22)를 도포하고 금속패턴(도시 안됨)과 접속 단자(23)를 형성한다. 이때, 금속패턴과 접속 단자(23)는 금(Au), 팔라듐(Pd), 니켈(Ni), 납(Pb) 등의 금속으로 두껍게 도금한다.2 and 3, first, a photoresist 22 is coated on the lead frame 21 to form a metal pattern (not shown) and a connection terminal 23. At this time, the metal pattern and the connection terminal 23 are thickly plated with metals such as gold (Au), palladium (Pd), nickel (Ni), and lead (Pb).

도 4a를 참조하면, 그 다음 반도체 칩(25)을 접착제(27)를 사용하여 리드프레임(21)에 부착시키고 반도체 칩(25)과 리드프레임(21)의 접속 단자(23)가 전기적으로 연결되도록 본딩 와이어(29)로 와이어 본딩을 한다. 이때, 도 4b에서와 같이 하부의 반도체 칩(25a) 위에 그 보다는 작은 크기의 반도체 칩(25b)을 적층하여 두 개의 반도체 칩(25a,25b)을 내재하도록 구성하는 것도 가능하다.Referring to FIG. 4A, the semiconductor chip 25 is then attached to the leadframe 21 using an adhesive 27, and the semiconductor chip 25 and the connection terminal 23 of the leadframe 21 are electrically connected to each other. The wire bonding is performed with the bonding wire 29 as much as possible. In this case, as shown in FIG. 4B, a semiconductor chip 25b having a smaller size may be stacked on the lower semiconductor chip 25a to include two semiconductor chips 25a and 25b.

도 5를 참조하면, 와이어 본딩이 완료되면 반도체 칩(25)과 본딩 와이어(29) 및 그 접합 부위를 봉지 하도록 에폭시 성형 수지와 같은 수지 봉지재로 패키지 몸체(31)를 형성한다. 이에 의해 전기적 동작의 신뢰성이 외부환경으로부터 확보된다.Referring to FIG. 5, when the wire bonding is completed, the package body 31 is formed of a resin encapsulating material such as an epoxy molding resin to seal the semiconductor chip 25, the bonding wire 29, and a bonding portion thereof. This ensures reliability of electrical operation from the external environment.

도 6a를 참조하면, 그 다음으로 리드프레임(21)을 에칭으로 완전히 제거하고 외부 접속단자로서 솔더 볼(33)을 부착한다. 패키지 몸체(31)의 밑면으로는 접속 단자(23)의 밑면과 반도체 칩(25) 밑면의 접착제(27)가 노출되는 형태가 된다. 노출된 접속 단자(23)의 밑면에 솔더 볼(33)을 부착시키면 본 발명의 볼 그리드 어레이 패키지(10)가 제조된다. 도 4b의 상태에서 와이어 본딩과 패키지 몸체 성형 공정을 완료한 후 솔더 볼(33)을 부착하면 도 6b는 두 개의 반도체 칩(25a,25b)을 내재하여 구성되는 적층 칩 패키지(50)의 제조가 완료된다.Referring to FIG. 6A, the lead frame 21 is then completely removed by etching and solder balls 33 are attached as external connection terminals. The bottom of the package body 31 is a form in which the bottom of the connection terminal 23 and the adhesive 27 of the bottom of the semiconductor chip 25 are exposed. Attaching the solder ball 33 to the bottom surface of the exposed connection terminal 23, the ball grid array package 10 of the present invention is manufactured. When the solder balls 33 are attached after the wire bonding and package body forming processes are completed in the state of FIG. 4B, FIG. 6B shows that the manufacture of the laminated chip package 50 including two semiconductor chips 25a and 25b is performed. Is done.

이렇게 완성된 플라스틱 재질의 볼 그리드 어레이 패키지는 리드프레임에 패턴을 형성하고 그 위에 도금을 한 다음 와이어 본딩을 하여 와이어 본딩 공정 단순화를 가능하게 하고, 베이스 리드 프레임을 완전히 에칭한 다음 도금된 접속 단자에 솔더 볼을 부착함으로써 일반적인 볼 그리드 어레이 형태와 같은 솔더 접합 신뢰성을 갖게 할 수 있다. 또한, 리드프레임 상에 패턴을 형성한 후 도금을 하기 때문에 핀 수에 제약을 받지 않아 다 핀 적용이 가능하며, 기존에 사용되고 있는 기판으로 인쇄회로기판이나 필름을 사용하지 않기 때문에 더욱 신뢰성 있는 패키지 구현이 가능하다고 할 수 있다.The finished plastic ball grid array package can be patterned on the leadframe, plated on it, and wire-bonded to simplify the wire bonding process, fully etch the base leadframe and then onto the plated connection terminals. By attaching the solder balls, the solder joint reliability as in the form of a general ball grid array can be obtained. In addition, since the plating is performed after forming a pattern on the lead frame, it is possible to apply all the pins without being limited by the number of pins. Since the printed circuit board or film is not used as the existing board, more reliable package is realized. This can be said to be possible.

이상과 같은 본 발명에 의한 볼 그리드 어레이 패키지와 그 제조 방법에 따르면, 공정 단순화를 기할 수 있고, 솔더 볼을 부착함으로서 접합 신뢰성을 향상시킬 수 있다. 또한 도금의 패턴이 제작 가능하기 때문에 다 핀 적용에도 문제가 없는 플라스틱 볼 그리드 어레이 패키지 구현이 가능하다고 할 수 있다.According to the ball grid array package and the manufacturing method thereof according to the present invention as described above, the process can be simplified, and the bonding reliability can be improved by attaching solder balls. In addition, since the plating pattern can be manufactured, it is possible to realize a plastic ball grid array package without any problem for multi-pin application.

Claims (3)

집적회로가 형성된 반도체 칩과, 상기 반도체 칩과 본딩와이어로 와이어 본딩되어 있는 접속 단자와, 상기 접속단자의 밑면에 형성되어 있는 외부 접속 단자, 및 상기 반도체 칩과 본딩 와이어를 봉지하고 밑면을 제외한 상기 접속 단자의 외주면을 봉지하는 패키지 몸체를 포함하는 것을 특징으로 하는 볼 그리드 어레이 패키지.A semiconductor chip in which an integrated circuit is formed, a connection terminal wire-bonded with the semiconductor chip and a bonding wire, an external connection terminal formed on the bottom surface of the connection terminal, and the semiconductor chip and the bonding wire, except for the bottom surface Ball grid array package comprising a package body for sealing the outer peripheral surface of the connection terminal. ⒜ 리드프레임에 포토 레지스트를 도포하고 도전성 금속 재질로 금속패턴과 접속 단자를 형성하는 단계와, ⒝ 집적회로가 형성된 반도체 칩을 리드프레임에 부착시키고 반도체 칩과 리드프레임의 접속단자를 와이어 본딩하는 단계와, ⒞ 반도체 칩과 본딩 와이어 및 그 접합 부위를 봉지 하도록 성형 수지로 패키지 몸체를 형성하는 단계, 및 ⒟ 리드프레임을 에칭으로 완전히 제거하고 접속 단자에 외부 접속단자를 형성하는 단계를 포함하는 것을 특징으로 하는 볼 그리드 어레이 패키지 제조 방법.(B) applying photoresist to the lead frame and forming a metal pattern and a connection terminal made of a conductive metal material; (c) attaching a semiconductor chip having an integrated circuit to the lead frame and wire bonding the connection terminal of the semiconductor chip and the lead frame. And (iii) forming a package body with a molding resin to encapsulate the semiconductor chip and the bonding wire and the bonding portion thereof; and (iii) completely removing the lead frame by etching and forming external connection terminals at the connection terminals. Ball grid array package manufacturing method. 제 2항에 있어서, 상기 ⒜ 단계는 접속 단자에 도전성 금속 재질로 도금하는 단계를 더 포함하는 것을 특징으로 하는 볼 그리드 어레이 패키지 제조 방법.3. The method of claim 2, wherein the step (c) further comprises plating a connection terminal with a conductive metal material.
KR1019990063337A 1999-12-28 1999-12-28 Ball grid array package and manufacturing method thereof KR20010060879A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030082177A (en) * 2002-04-17 2003-10-22 주식회사 칩팩코리아 Chip scale package and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030082177A (en) * 2002-04-17 2003-10-22 주식회사 칩팩코리아 Chip scale package and method for fabricating the same

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