TWI838125B - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
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- TWI838125B TWI838125B TW112105429A TW112105429A TWI838125B TW I838125 B TWI838125 B TW I838125B TW 112105429 A TW112105429 A TW 112105429A TW 112105429 A TW112105429 A TW 112105429A TW I838125 B TWI838125 B TW I838125B
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- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 238000004806 packaging method and process Methods 0.000 claims description 64
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
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- 238000000465 moulding Methods 0.000 abstract description 4
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- 229910052751 metal Inorganic materials 0.000 description 3
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 229910052737 gold Inorganic materials 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
本揭露是有關於一種半導體封裝及其製造方法。The present disclosure relates to a semiconductor package and a manufacturing method thereof.
隨著電子產品的小型化,手持產品之市場不斷擴張。主要受手機及數位助理市場之驅動,所述裝置之製造商正面臨著產品體積壓縮以及更多類個人電腦功能之需求的挑戰。而額外增加之功能僅能藉由高性能之邏輯積體電路結合增加之記憶體容量來達成。為因應此種挑戰,更小之印製電路板將為表面黏著元件製造商設計產品帶來了壓力。As electronic products become smaller, the market for handheld products continues to expand. Driven primarily by the mobile phone and digital assistant markets, manufacturers of these devices are facing the challenge of product size compression and the need for more personal computer functions. The additional functions can only be achieved through high-performance logic integrated circuits combined with increased memory capacity. In response to this challenge, smaller printed circuit boards will put pressure on surface mount component manufacturers to design products.
現今手持產品市場中,許多廣泛使用之元件開始從有引腳形式向無引腳形式過渡。使得電子元件越來朝向節省印製電路板空間來設計。因此節省出的額外空間可用於配置附加的裝置功能所需之元件。In today's handheld product market, many widely used components are beginning to transition from pinned to pinless forms. This has led to electronic components being designed to save printed circuit board space. The extra space saved can be used to configure components required for additional device functions.
現行廣泛使用的四方平面無引腳封裝(QFN, Quad Flat No leads)或雙面無引腳封裝(DFN, Dual Flat No-Lead)等無引腳封裝結構大多是單面具有電連接墊,以作為對外連接的端子,因而只能進行平面式(2D)的封裝體上板作業,而無法執行立體(3D)的堆疊設置,導致此種封裝結構的功能及效能難以進一步擴充。Most of the widely used leadless package structures such as Quad Flat No Leads (QFN) or Dual Flat No-Lead (DFN) have electrical connection pads on one side as terminals for external connections. Therefore, they can only perform planar (2D) package mounting operations, but cannot perform three-dimensional (3D) stacking settings, making it difficult to further expand the functions and performance of this package structure.
本揭露提供一種半導體封裝及其製造方法,其可讓原本導線架的半導體封裝達到立體堆疊的目的,更可提升半導體封裝的功能及效能。The present disclosure provides a semiconductor package and a manufacturing method thereof, which can achieve the purpose of three-dimensional stacking of the original lead frame semiconductor package and can also improve the function and performance of the semiconductor package.
本揭露的一種半導體封裝包括導線架、多個導電柱以及晶片。導線架包括晶片座以及多個引腳。多個導電柱設置於多個引腳上並電性連接多個引腳。晶片設置於晶片座上並電性連接多個引腳。封裝膠體包覆晶片、導線架以及多個導電柱,其中封裝膠體暴露多個引腳的下表面以及多個導電柱的頂表面。A semiconductor package disclosed herein includes a lead frame, a plurality of conductive pillars, and a chip. The lead frame includes a chip seat and a plurality of pins. The plurality of conductive pillars are disposed on the plurality of pins and electrically connected to the plurality of pins. The chip is disposed on the chip seat and electrically connected to the plurality of pins. A packaging colloid covers the chip, the lead frame, and the plurality of conductive pillars, wherein the packaging colloid exposes the lower surfaces of the plurality of pins and the top surfaces of the plurality of conductive pillars.
本揭露的一種半導體封裝的製造方法包括下列步驟。提供導線架,其中導線架包括晶片座以及的多個引腳;提供多個導電柱於多個引腳上並使多個導電柱電性連接多個引腳;設置晶片於晶片座上並使晶片電性連接多個引腳;以及形成封裝膠體以包覆晶片、導線架以及多個導電柱。The present invention discloses a method for manufacturing a semiconductor package, comprising the following steps: providing a lead frame, wherein the lead frame comprises a chip base and a plurality of pins; providing a plurality of conductive posts on the plurality of pins and electrically connecting the plurality of conductive posts to the plurality of pins; placing a chip on the chip base and electrically connecting the chip to the plurality of pins; and forming a packaging colloid to cover the chip, the lead frame and the plurality of conductive posts.
基於上述,本揭露的半導體封裝中之導電柱可依所需而設置於導線架的至少部分引腳上,將晶片設置於導線架的晶片座上,並使封裝膠體暴露引腳的下表面以及導電柱的頂表面。如此配置,被封裝膠體所暴露的引腳的下表面以及導電柱的頂表面可分別與其他的元件電性連接,因而使半導體封裝得以於封裝膠體的上下兩側分別堆疊其他的基板或封裝件,以達到立體堆疊的目的,更可提升半導體封裝的功能及效能。Based on the above, the conductive pillars in the semiconductor package disclosed in the present invention can be arranged on at least part of the pins of the lead frame as needed, and the chip is arranged on the chip seat of the lead frame, and the packaging colloid exposes the lower surface of the pins and the top surface of the conductive pillars. In this configuration, the lower surface of the pins and the top surface of the conductive pillars exposed by the packaging colloid can be electrically connected to other components respectively, so that the semiconductor package can be stacked on the upper and lower sides of the packaging colloid respectively. Other substrates or packaging components can be stacked to achieve the purpose of three-dimensional stacking, and the function and performance of the semiconductor package can be improved.
有關本揭露之前述及其他技術內容、特點與功效,在以下配合參考圖式之各實施例的詳細說明中,將可清楚的呈現。以下實施例中所提到的方向用語,例如:「上」、「下」、「前」、「後」、「左」、「右」等,僅是參考附加圖式的方向。因此,使用的方向用語是用來說明,而並非用來限制本揭露。並且,在下列各實施例中,相同或相似的元件將採用相同或相似的標號。The above-mentioned and other technical contents, features and effects of the present disclosure will be clearly presented in the detailed description of each embodiment with reference to the drawings below. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used for explanation, not for limiting the present disclosure. In addition, in the following embodiments, the same or similar components will adopt the same or similar labels.
圖1至圖7是依照本揭露的一實施例的一種半導體封裝的製造方法的流程剖面示意圖。在一些實施例中,半導體封裝的製造方法可包括下列步驟。首先,請參照圖1,提供導線架110,其中,導線架110包括晶片座112以及多個引腳114。在本實施例中,引腳114可環繞晶片座112而設置於晶片座112的外圍。在一實施例中,導線架110可經由對金屬層進行蝕刻製程而形成圖案化之導線架。Figures 1 to 7 are schematic cross-sectional views of a process of manufacturing a semiconductor package according to an embodiment of the present disclosure. In some embodiments, the method for manufacturing a semiconductor package may include the following steps. First, referring to Figure 1, a
接著,請參照圖2,提供多個導電柱120於多個引腳114上,並使導電柱120電性連接對應的引腳114。導電柱120可由導電材料,例如銅、金、銀、鈦、鎢、鋁及/或其類似物所形成。在本實施例中,導電柱120可為預成型之結構,並經由焊料層130而將導電柱120附接於對應的引腳114上。在本實施例中,導電柱120可為銅柱或上述其他可能導電材料所形成的金屬柱。在一實施例中,導電柱120可例如透過取放機構(pick and place)而選擇性的設置於所對應之引腳114或全部之引腳114上。Next, please refer to Figure 2, provide a plurality of
具體而言,設置導電柱120於多個引腳114上的步驟可包括下列步驟。首先,提供焊料層130於導電柱120與對應的引腳114之間。在一實施例中,焊料層130可先設置於對應的引腳114上,再將導電柱120置放於焊料層130上。當然,在其他實施例中,也可先將焊料層130設置於導電柱120的底表面,再將設置有焊料層130的導電柱120設置於對應的引腳114上。本揭露並不以此為限。在一些實施例中,焊料層130可使用例如電鍍或化學鍍的鍍覆、網板印刷、塗佈或其類似者設置於導電柱120與對應的引腳114之間。接著,可進行迴焊製程,以將導電柱120與對應的引腳114經由焊料層130而接合。在本實施例中,焊料層130可為無鉛焊料、錫膏等任何可接受迴焊的導電材料。在一實施例中,在提供焊料層130之前,更可先塗佈助焊劑(flux)於導電柱120與對應的引腳114之間。助焊劑可在後續的迴焊製程中於焊料層130的表面形成薄膜以隔絕空氣,讓焊料層130不易氧化。當然,本實施例僅用以舉例說明,本揭露並不限定導電柱120與焊料層130的形成方式。Specifically, the step of disposing the
接著,請參照圖3,設置晶片140於晶片座112上,並使晶片140電性連接對應的引腳114。在一實施例中,晶片140可包括多個接點142,其可形成於晶片140的主動表面S1上。在本實施例中,晶片140可包括顯示驅動器電路積體電路(integrated circuit;IC)、影像感測器積體電路、記憶體積體電路、邏輯積體電路、類比積體電路、超高頻(ultra-high frequency;UHF)積體電路或射頻(radio frequency;RF)積體電路,但本揭露並不僅限於此。在本實施例中,晶片140可例如通過打線接合的方式設置於導線架110上並電性連接至對應的引腳114。具體來說,半導體封裝更可包括多條導線150,其中,晶片140包括具有多個接點142的主動表面S1以及相對於主動表面S1的背表面S2,且晶片140以背表面S2設置於晶片座112上,再以導線150連接於晶片140的接點142與導線架110的引腳114之間,以電性連接晶片140與導線架110。在本實施例中,晶片140可經由晶粒貼合膜(die attach film, DAF)貼附至晶片座112上。當然,本揭露並不限制晶片140設置於晶片座112上並與對應的引腳114電性連接的方法。Next, referring to FIG. 3 , a
值得注意的是,於前述實施例中,本揭露中的導電柱120是先設置於對應的引腳114後再進行設置晶片140及打線接合製程,但本揭露並不限於此。於其它可行之實施例中,晶片140、導電柱120及接線接合之製程可視所需而調整製程順序。舉例來說,本揭露可先放置晶片140於晶片座112上,再設置導電柱120於對應之引腳114上,之後,再進行打線接合以將晶片140電性連接至引腳114。或者,亦可先放置晶片140於晶片座112上後進行打線接合,接著,再放置導電柱120於對應引腳114上,如此,亦屬於本揭露之運用範疇。It is worth noting that in the aforementioned embodiments, the
接著,請參照圖4,形成封裝膠體160以包覆晶片140、導線架110以及導電柱120。封裝膠體160可例如透過塑模(molding)製程而形成。在本實施例中,導線150也被包覆於封裝膠體160內。舉例而言,封裝膠體160可包括環氧樹脂(epoxy resin)。在本實施例中,封裝膠體160在此階段可以是全面性地包覆晶片140、導線150以及導電柱120,並且封裝膠體160暴露晶片座112以及引腳114的下表面。Next, referring to FIG. 4 , a
接著,請參照圖5,對封裝膠體160進行減薄製程,以使封裝膠體160暴露導電柱120的頂表面。在本實施例中,可利用減薄治具50對封裝膠體160進行化學機械拋光、雷射減薄及/或研磨等減薄製程,直到暴露出導電柱120的頂表面為止。換句話說,本實施例可利用化學機械拋光、雷射減薄及/或研磨等減薄製程來移除導電柱120的頂表面上方的封裝膠體160,以使導電柱120的頂表面與封裝膠體160的頂表面實質上共平面。如此,封裝膠體160可至少暴露引腳114的下表面以及導電柱120的頂表面。至此,封裝件100的製作方法可大致完成。Next, referring to FIG. 5 , the
請接續參考圖5及圖6,在一些實施例中,由於如圖5所示的封裝件100的封裝膠體160至少暴露了引腳114的下表面以及導電柱120的頂表面,因此,封裝件100可於其上下兩側在分別與其他的元件電性連接。舉例而言,在圖6的實施例中,可再將基板200設置於封裝件100的封裝膠體160的底表面,並與引腳114形成電性連接。在一實施例中,基板200包括多個電性接點232,其分別與被封裝膠體160所暴露的引腳114的下表面連接。在本實施例中,基板200更可包括多個電性導通孔234以及多個電性接點236,其中,電性接點232與電性接點236可分別設置於基板200的相對兩表面,而電性導通孔234則可延伸通過基板200以電性連接於電性接點232與電性接點236之間,如此,電性接點232、電性導通孔234與電性接點236等導電元件可共同組成電傳導路徑230,以電性連通基板200的相對兩表面。在本實施例中,基板200可包括電路板、中介板(interposer)、晶圓等可與封裝件100電性連接的電子元件。Please continue to refer to Figures 5 and 6. In some embodiments, since the
在一實施例中,基板200更可選擇性的包括上散熱墊222、下散熱墊226以及散熱通孔224,其中,上散熱墊222與下散熱墊226可分別設置於基板200的相對兩表面(上下兩表面),而散熱通孔224則可延伸通過基板200以連接於上散熱墊222與下散熱墊226之間,以使上散熱墊222與下散熱墊226之間形成熱耦接。在一實施例中,上散熱墊222可與晶片座112接觸以形成熱耦接,如此,晶片140所產生的熱能便可往下傳導至晶片座112,再經由上散熱墊222、散熱通孔224以及下散熱墊226所形成的熱傳導路徑220而傳導至基板200的下表面,以幫助晶片140進行散熱。在本實施例中,上散熱墊222、下散熱墊226以及散熱通孔224可與基板200的其他電性元件(例如電性接點232、236以及電性導通孔234等)電性絕緣。於另一可行之實施例中,上散熱墊222、散熱通孔224以及下散熱墊226亦可做為其它非為電性連接之線路,例如是接地或防靜電線路等,而非侷限於散熱用途。In one embodiment, the
接著,請參照圖7,在本實施例中,設置上封裝件100a於封裝膠體160的頂表面,且上封裝件100a包括多個電性接點170,分別與被封裝膠體160所暴露的導電柱120的頂表面連接。在本實施例中,上封裝件100a可與封裝件100的結構大致相似(也包括導線架、晶片、導線、封裝膠體等元件)。然而,在其他實施例中,上封裝件100a也可以是與封裝件100的結構完全不同的封裝件,只要其電性接點170可與封裝件100的導電柱120電性連接即可。至此,半導體封裝10的製作方法可大致完成。Next, please refer to FIG. 7. In this embodiment, an
圖8是依照本揭露的一實施例的一種半導體封裝的剖面示意圖。在此必須說明的是,本實施例的半導體封裝10a與前述實施例的半導體封裝10相似。以下將針對本實施例的半導體封裝10a與前述實施例的半導體封裝10的差異做說明。FIG8 is a cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present disclosure. It should be noted that the semiconductor package 10a of the present embodiment is similar to the
在本實施例中,半導體封裝10a的上封裝件300可以是與封裝件100的結構完全不同的封裝件。上封裝件300可包括上基板310、上晶片320、上凸塊330以及上封裝膠體340等元件。具體而言,上晶片320設置於上基板310上,並可例如透過覆晶接合的方式通過上凸塊330與上基板310電性連接。上封裝膠體340設置於上基板310上並包封上晶片320與上凸塊330於其內。In this embodiment, the
在一實施例中,疊設於封裝件100上的封裝件300可例如包括記憶體裝置等半導體裝置,所述半導體裝置可例如用於為封裝件100內的晶片140提供所儲存的資料。在此種實施例中,晶片140可包括記憶體控制模組,所述記憶體控制模組可對封裝件300的記憶體裝置提供控制功能。然而,本實施例僅用以舉例說明,本揭露並不限制疊設於封裝件100上的封裝件的種類與功能。In one embodiment, the
圖9是依照本揭露的一實施例的一種半導體封裝的部分元件的上視示意圖。以下將針對本實施例的封裝件100與前述實施例的封裝件的差異做說明。Fig. 9 is a top view of some components of a semiconductor package according to an embodiment of the present disclosure. The differences between the
請參照圖9,在本實施例中,引腳114包括多個第一引腳1141以及至少一第二引腳1142,其中,多個導電柱120分別設置於多個第一引腳1141上。在一實施例中,導電柱120不設置於第二引腳1142上。也就是說,導電柱120並非設置於所有的引腳114上,而是依實際電性需求而具選擇性地設置於部分的引腳114上,在電路設計上具有一可調整的彈性。此外,在本實施例中,晶片140的接點142可沿著晶片140的相對兩側而設置,而引腳114及對應的導電柱120也對應地位於晶片140的相對兩側,使其可經由導線150分別與對應的接點142連接。然而,在其他實施例中,晶片140的接點142也可環繞晶片140的所有邊緣而設置,例如沿著晶片140的四個側邊而設置。如此,引腳114及對應的導電柱120也對應地環繞晶片140的四周而設置,使其可經由導線150分別與對應的接點142連接。本揭露並不局限於此。Please refer to FIG. 9 . In this embodiment, the
圖10是依照本揭露的一實施例的一種半導體封裝的導電柱的示意圖。以下將針對本實施例的導電柱120a與前述實施例的導電柱120的差異做說明。10 is a schematic diagram of a conductive pillar of a semiconductor package according to an embodiment of the present disclosure. The difference between the
請參照圖2及圖10,在本實施例中,導電柱120a可包括銅柱核心122以及焊料層124。具體而言,提供導電柱120a的方法可包括下列步驟。首先,形成焊料層124於導電柱120a的銅柱核心122上,使焊料層124至少包覆銅柱核心122的側表面。在本實施例中,焊料層124可為錫層,其可例如透過電鍍的方式形成以包覆銅柱核心122的側表面。在本實施例中,電鍍而形成的焊料層124的厚度約介於10微米(μm)至20微米之間,例如約15微米。在一實施例中,形成焊料層124之後可再於導電柱120a或對應的引腳114上塗佈助焊劑,其可在後續的迴焊製程中於焊料層124的表面形成薄膜以隔絕空氣,讓焊料層124不易氧化。接著,進行迴焊製程,以使導電柱120a與對應的引腳114經由焊料層124而接合。當然,本揭露並不限制導電柱的形成方法。在其他實施例中,導電柱也可藉由直接在導線架上提供圖案化光阻層以及晶種層,以通過電鍍直接將導電柱形成於導線架的引腳上。Please refer to Figures 2 and 10. In the present embodiment, the
圖11至圖13是依照本揭露的一實施例的一種半導體封裝的製造方法的流程剖面示意圖。以下將針對本實施例的半導體封裝製造方法與前述實施例的半導體封裝製造方法的差異做說明。11 to 13 are schematic cross-sectional views of a process of manufacturing a semiconductor package according to an embodiment of the present disclosure. The differences between the semiconductor package manufacturing method of this embodiment and the semiconductor package manufacturing method of the aforementioned embodiment will be described below.
請先參照圖11,在本實施例中,晶片140是經由覆晶接合的方式設置於晶片座112a上。具體而言,晶片座112a是由多個引腳114a分別往導線架110a的中央區域延伸的多個延伸部112a所組成,且晶片140的多個接點分別連接多個延伸部112a。換句話說,導線架110a包括多個引腳114a環繞導線架110a的中心點設置,且各個引腳114a包括往此中心點的方向延伸的延伸部112a。這些環繞此中心點的延伸部112a共同組成供晶片140設置的晶片座112a。如此,晶片140便可經由多個凸塊180以覆晶接合的方式設置於晶片座112上。Please refer to FIG. 11 . In the present embodiment, the
接著,如前述實施例所述,提供多個導電柱120於多個引腳114a上,並使導電柱120電性連接對應的引腳114a。在本實施例中,導電柱120可為預成型之結構,並經由焊料層130而將導電柱120附接於對應的引腳114上。在本實施例中,導電柱120可為銅柱或上述其他可能材料所形成的金屬柱。在本實施例中,焊料層130可設置於導電柱120與對應的引腳114a之間。在一些實施例中,焊料層130可使用例如電鍍或化學鍍的鍍覆、網板印刷、塗佈或其類似者設置於導電柱120與對應的引腳114a之間。接著,可進行迴焊製程,以將導電柱120與對應的引腳114a經由焊料層130而接合。在本實施例中,焊料層130可為無鉛焊料、錫膏等任何可接受迴焊的導電材料。在一實施例中,在提供焊料層130之前,更可先塗佈助焊劑(flux)於導電柱120與對應的引腳114a之間。Next, as described in the aforementioned embodiment, a plurality of
接著,設置晶片140於晶片座112a上,並使晶片140電性連接對應的引腳114a。如同前述實施例之說明,晶片140覆晶設置於晶片座112a的時間點可早於導電柱120設置於導線架110a之前。也就是說,晶片140可先經由覆晶接合而設置於晶片座112a上,之後再將導電柱120設置於導線架110a的多個引腳114a上。本揭露並不限制晶片140與導電柱120的設置順序。在本實施例中,晶片140是例如通過覆晶接合的方式設置於導線架110a的晶片座112a上,並電性連接至對應的引腳114a。在本實施例中,晶片140是經由多個凸塊180接合於晶片座112a(多個引腳114a的多個延伸部)上。當然,本揭露並不限制晶片140設置於晶片座112a上的方法。Next, the
接著,請參照圖12,形成封裝膠體160以包覆晶片140、導線架110a以及導電柱120。舉例而言,封裝膠體160可包括環氧樹脂(epoxy resin)。在本實施例中,封裝膠體160在此階段可以是全面性地包覆晶片140以及導電柱120,並且封裝膠體160包覆至少部分導線架110a且暴露導線架110a的下表面。Next, referring to FIG. 12 , a
接著,請參照圖13,對封裝膠體160進行減薄製程,以使封裝膠體160暴露導電柱120的頂表面。在本實施例中,可對封裝膠體160進行化學機械拋光、雷射減薄及/或研磨等減薄製程,直到暴露出導電柱120的頂表面為止。如此,封裝膠體160可至少暴露導線架110a的下表面以及導電柱120的頂表面。Next, referring to FIG. 13 , the
請參照圖14,圖14是依照本揭露的一實施例的一種半導體封裝的剖面示意圖,其與前述實施例的半導體封裝的差異在於形成圖案化線路層190於封裝膠體160的頂表面,且圖案化線路層190與導電柱120電性連接。如此,封裝件100a的製作方法便可大致完成,且封裝件100a可經由被暴露出的導線架110a的下表面以及連接導電柱120的圖案化線路層190而分別與不同的元件形成電性連接。Please refer to FIG. 14, which is a cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present disclosure. The difference between the semiconductor package and the semiconductor package of the aforementioned embodiment is that a patterned
請參照圖15,圖15是依照本揭露的一實施例的一種半導體封裝的剖面示意圖。在本實施例中,設置於導線架110a上的晶片可包括彼此堆疊的多個晶片140a、140b。並且,晶片140a、140b是例如通過覆晶接合的方式彼此堆疊而設置於導線架110a的晶片座112a上。在本實施例中,晶片140a是經由多個凸塊180接合於晶片座112a(多個引腳114a的多個延伸部)上,而晶片140b是經由多個凸塊180接合於晶片140a上。當然,本揭露並不限制晶片140a、140b設置於晶片座112a上的方法。Please refer to Figure 15, which is a cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present disclosure. In this embodiment, the chip disposed on the
圖16是依照本揭露的一實施例的一種半導體封裝的剖面示意圖。以下將針對本實施例的半導體封裝與前述實施例的半導體封裝的差異做說明。Fig. 16 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. The difference between the semiconductor package of this embodiment and the semiconductor package of the aforementioned embodiment will be described below.
請參照圖16,在本實施例中,在形成封裝件100b之後,更可設置另一上封裝件100c於封裝件100b上,且上封裝件100c包括多個電性接點170,分別與被封裝膠體160所暴露的導電柱120的頂表面連接。在本實施例中,上封裝件100c可與封裝件100b的結構大致相似(也包括導線架、彼此堆疊的多個晶片、凸塊、封裝膠體等元件)。然而,在其他實施例中,上封裝件100c也可以是與封裝件100b的結構完全不同的封裝件,只要其電性接點170可與封裝件100b的導電柱120電性連接即可。Please refer to FIG. 16 . In this embodiment, after the
綜上所述,本揭露的半導體封裝將導電柱依電性連接所需而具有可選擇性及可調整性的特性,依所需而設置於導線架的引腳上,將晶片設置於導線架的晶片座上,並使封裝膠體暴露引腳的下表面以及導電柱的頂表面。如此配置,被封裝膠體所暴露的引腳的下表面以及導電柱的頂表面可分別與其他的元件電性連接,因而使半導體封裝得以於封裝膠體的上下兩側分別堆疊其他的基板或封裝件,以達到立體堆疊的目的,更可提升半導體封裝的功能及效能。In summary, the semiconductor package disclosed in the present invention has the characteristics of selectivity and adjustability according to the needs of electrical connection, and is arranged on the pins of the lead frame as needed, and the chip is arranged on the chip seat of the lead frame, and the packaging colloid exposes the lower surface of the pins and the top surface of the conductive pillars. In this configuration, the lower surface of the pins and the top surface of the conductive pillars exposed by the packaging colloid can be electrically connected to other components respectively, so that the semiconductor package can be stacked on the upper and lower sides of the packaging colloid respectively. Other substrates or packaging components are stacked to achieve the purpose of three-dimensional stacking, and the function and performance of the semiconductor package can be improved.
10、10a:半導體封裝
50:減薄治具
100、100a、100b:封裝件
100a、100c、300:上封裝件
110、110a:導線架
112、112a:晶片座
112a:延伸部
114、114a:引腳
1141:第一引腳
1142:第二引腳
120、120a:導電柱
122:銅柱核心
124、130:焊料層
140、140a、140b:晶片
142:接點
150:導線
160:封裝膠體
180:凸塊
190:圖案化線路層
200:基板
222:上散熱墊
224:散熱通孔
226:下散熱墊
232、236、170:電性接點
234:電性導通孔
310:上基板
320:上晶片
330:上凸塊
340:上封裝膠體
S1:主動表面
S2:背表面
10, 10a: semiconductor package
50: thinning
圖1至圖7是依照本揭露的一實施例的一種半導體封裝的製造方法的流程剖面示意圖。 圖8是依照本揭露的一實施例的一種半導體封裝的剖面示意圖。 圖9是依照本揭露的一實施例的一種半導體封裝的部分元件的上視示意圖。 圖10是依照本揭露的一實施例的一種半導體封裝的導電柱的示意圖。 圖11至圖14是依照本揭露的一實施例的一種半導體封裝的製造方法的流程剖面示意圖。 圖15是依照本揭露的一實施例的一種半導體封裝的剖面示意圖。 圖16是依照本揭露的一實施例的一種半導體封裝的剖面示意圖。 Figures 1 to 7 are schematic cross-sectional diagrams of a process of manufacturing a semiconductor package according to an embodiment of the present disclosure. Figure 8 is a schematic cross-sectional diagram of a semiconductor package according to an embodiment of the present disclosure. Figure 9 is a schematic top view of a portion of components of a semiconductor package according to an embodiment of the present disclosure. Figure 10 is a schematic diagram of a conductive column of a semiconductor package according to an embodiment of the present disclosure. Figures 11 to 14 are schematic cross-sectional diagrams of a process of manufacturing a semiconductor package according to an embodiment of the present disclosure. Figure 15 is a schematic cross-sectional diagram of a semiconductor package according to an embodiment of the present disclosure. Figure 16 is a schematic cross-sectional diagram of a semiconductor package according to an embodiment of the present disclosure.
100:封裝件 100:Packaging parts
110:導線架 110: Conductor frame
112:晶片座 112: Wafer holder
114:引腳 114: Pins
120:導電柱 120: Conductive column
130:焊料層 130: Solder layer
140:晶片 140: Chip
150:導線 150: Conductor wire
160:封裝膠體 160: Packaging colloid
50:減薄治具 50:Thinning fixture
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