KR100424611B1 - Low profile optically-sensitive semiconductor package - Google Patents

Abstract

A low profile photosensitive semiconductor device comprising a substrate having an opening is disclosed. The cover plate is bonded to the first surface of the substrate in such a manner that the photosensitive semiconductor chip is attached to the first surface of the substrate through the opening of the substrate. Immediately after the semiconductor chip is electrically connected to the substrate, a first encapsulant having a through hole connected to the opening of the substrate is formed on the second surface of the substrate. Thereafter, a sealing plate is attached to the first encapsulant to seal the through hole to seal seal the semiconductor chip from the atmosphere. A second encapsulant is formed on the first surface of the substrate such that the ends of the conductive elements and the outer surface of the cover plate are exposed to the top surface of the second encapsulant and coplanar with the second encapsulant top surface.

Thus, a satisfactory manufacturing plane of the semiconductor device can be obtained and the overall height of the semiconductor device can be effectively reduced.

Description

Low profile photosensitive semiconductor package

The present invention relates to a photosensitive semiconductor package, and more particularly, to a photosensitive semiconductor package capable of sensing external light emitted by the semiconductor chip into the package.

Typical semiconductor devices usually enclose a semiconductor chip with an opaque molding resin, which protects the enclosed semiconductor chip from chemical reactions with the external atmosphere as well as mechanical protection to prevent damage to the semiconductor chip from external impacts. However, in the case of photosensitive semiconductor devices such as image sensing or ultraviolet erasable EP-ROM packages, it is necessary to receive external light for the semiconductor chip. To achieve this, the structure of such a photosensitive semiconductor device is designed in such a way that external light can reach internal components of the device so that light emitted into the device can be sensed by the photosensitive semiconductor chip.

There are general photosensitive semiconductor devices of many different shapes. One of them is shown in FIG. 4, which shows a semiconductor device 3, which semiconductor chip is attached to the substrate 30 and electrically connected to the substrate 30 via gold wires 34. And (32). The semiconductor chip 32 is positioned in the frame 36 mounted on the substrate 30, and the transparent cover plate 38 is attached to the frame 36 so that external light is enclosed in the semiconductor device 3. 32) while sealing the semiconductor chip 32 and the gold wire 34 from the atmosphere while being diverged into the atmosphere.

However, the structure of the semiconductor device 3 has the following disadvantages. The overall height of the semiconductor device 3 is the height of the solder ball 39, the thickness of the substrate 30 and the semiconductor chip 32, the height of the wireloop of the gold wire 34 on the semiconductor chip 32. The gap between the top of the gold wire 34 wire loop and the cover plate 38 and the thickness of the cover plate 38 are difficult to reduce. As a result, this height limitation hardly meets the requirements of low profile semiconductor devices. In addition, the semiconductor chip 32, the frame 36, and the solder balls 39 are mounted on the top surface and the bottom surface of the substrate 30, respectively. Because they have different coefficients of thermal expansion, the substrate 30 tends to wrap due to substantial temperature changes during the temperature cycle and reliability tests. Torsion of the substrate 30 results in the separation of the substrate 30 from the semiconductor chip 32 as well as the loss of flatness of the solder balls 39. As a result, the electrical connection between the solder balls 39 and an external device such as a printed circuit board cannot be made completely and effectively, thereby adversely affecting the external connection performance of the semiconductor device 3.

Accordingly, an object of the present invention is to provide a low-shape, photosensitive semiconductor device that can effectively reduce the overall thickness of the semiconductor device.

Another object of the present invention is to provide a low-shape, photosensitive semiconductor device capable of effectively preventing the occurrence of delamination by improving the mechanical strength of the semiconductor device.

It is still another object of the present invention to provide a low profile, photosensitive semiconductor device having improved heat dissipation efficiency than a conventional semiconductor device.

It is another object of the present invention to provide a low profile, photosensitive semiconductor device capable of ensuring the quality of electrical connection of solder balls with external devices.

Another object of the present invention is to provide a low-profile, photosensitive semiconductor device that can effectively reduce the thickness of the semiconductor device and the cost of manufacturing the substrate.

In accordance with the above and other objects, the present invention proposes a novel low-shape, photosensitive semiconductor device. A low profile, photosensitive semiconductor device is formed through a substrate for electrical connection with an opening, a first surface, a second surface facing the first surface, a plurality of conductive traces formed on the second surface and conductive traces. A substrate having a plurality of conductive vias; A cover member attached on the first surface of the substrate to cover the end of the opening; A semiconductor chip located in the opening of the substrate and attached to the cover member; A plurality of first conductive elements for electrically connecting the semiconductor chip to conductive traces on the substrate; A first encapsulant formed on a second surface of the substrate for encapsulating conductive traces; A sealing member attached to a first encapsulant for sealing the opening to sealably separate the semiconductor chip and the first conductive elements from the atmosphere; A plurality of second conductive elements formed on the first surface of the substrate for electrical connection with the conductive vias; And a second encapsulant formed on the first surface of the substrate in such a manner that the cover member and the second conductive elements are exposed such that the outer surface of the cover member and the terminals of each second conductive element are formed on the outer surface of the second encapsulant. To the same height as

The cover member may be a silicone film, an epoxy resin tape, a polyamide tape or a tape made of a film or similar material. Alternatively, the cover plate may be a heat spreader made of heat dissipating metal such as copper, aluminum, copper alloy or aluminum alloy. In order to improve heat dissipation efficiency, a thermally conductive adhesive may be used to attach the semiconductor chip to the cover member.

The sealing member may be made of transparent glass, plastic or metallic material to cover the opening formed in the central region of the first encapsulant interconnecting the openings of the substrate. This prevents contact of the semiconductor chip and the first conductive elements with the atmosphere. A transparent resin material can also be used for use as a sealing member for encapsulation of the semiconductor chip and the first conductive members to fill up the openings of the substrate and the first encapsulant. Since the sealing member formed of the transparent resin is light transmissive, the semiconductor chip can receive external light and react.

The first conductive elements are preferably gold wires. Solder balls may be used as the second conductive elements so that conventional solder ball injection methods may be used to electrically connect the solder balls to conductive vias of the substrate. Note that the second conductive elements may be in the form of connecting lumps formed by copper, lead, alloys thereof or other similar metals or conductive metals such as alloys thereof. In this case, connecting lumps may be mounted on the first surface of the substrate by conventional printing techniques to electrically connect conductive vias of the substrate. After the second conductive elements are formed at a predetermined position on the first surface of the substrate, the second conductive portion is formed over the first surface of the substrate such that the second conductive elements and the cover plate are exposed to the second encapsulant in a second conductive manner. Elements and cover member are enclosed. Thus, a general grinding method can be used to reduce the overall thickness of the device obtained to polish the second encapsulant, the second conductive elements and / or the cover plate. As a result, not only can the overall height of the packaged product be reduced effectively, but the exposed surfaces of the cover member as well as the outer surface of the second encapsulant and the exposed ends of the second conductive elements can be coplanar with one another.

The present invention will be more fully understood from the following detailed description of the preferred embodiments with reference to the accompanying drawings.

1 is a cross sectional view of a first embodiment of a semiconductor device according to the present invention;

FIG. 2 is a cross-sectional view of a first embodiment of a semiconductor device according to the present invention, different from that shown in FIG. 1, used to show a plate completely covering the first encapsulant. FIG.

3 is a cross sectional view of a second embodiment of semiconductor device according to the present invention;

4 is a cross-sectional view of a typical photosensitive semiconductor device.

First embodiment

As shown in FIG. 1, the semiconductor device 1 includes a substrate 10 having an opening 100 formed in the center thereof. The substrate 10 penetrates the first surface 101, the second surface 102, the plurality of conductive traces 103 formed on the second surface 102, and the first surface 101. ) And a plurality of conductive vias 104 interconnecting the second surface 102. Since conductive traces 103 and conductive vias 104 are formed in a general manner, a detailed description thereof is not provided herein. Conductive vias 104 are formed for electrical connection with conductive traces 103. The cover plate 11 is attached on the first surface 101 of the substrate 10 in such a way that the opening 100 termination on the first surface 101 of the substrate 10 is sealed by the cover plate 11. . This allows the photosensitive semiconductor chip 12 to be attached to the cover plate 11 by silver paste 13 via an opening 100 opening end on the second surface 102 of the substrate 10. The semiconductor chip 12 is accommodated in the opening 100 of the substrate 10.

As mentioned above, the cover plate 11 is a heat spreader made of a metal such as copper or a tape made of a resin material such as polyamide resin. When the cover plate 11 is formed as a heat spreader, heat generated in the semiconductor chip 12 can be transferred to the cover plate 11 to dissipate directly into the atmosphere. Therefore, the heat dissipation efficiency of the semiconductor device 1 can be increased.

While the semiconductor chip 12 is attached to a predetermined position on the cover plate 11, a plurality of gold wires 14 for electrically connecting the conductive traces 103 on the substrate 10 to the semiconductor chip 12. ) Is used. Electrical connections between the semiconductor chip 12 and the substrate 10 may be made by conventional tape automated bonding techniques.

After the wire bonding of the gold wires 14 is completed, a resin compound is applied on the second surface of the substrate 10 by a general printing method or a similar method to form a first encapsulant 15, and a first encapsulation. The agent completely encloses the second surface 102 of the substrate 10, leaving an uncovered portion of the second surface 102 to which the opening 100 and the gold wire 14 are connected. The conductive encapsulation 103 is not in contact with the atmosphere by the first encapsulant 15 to prevent oxidation of the conductive trace 103 by air or moisture. Immediately after the formation of the first encapsulant 15, the through holes 150 are formed to leave the area of the second surface 102 on which the gold wires 14 are to be left exposed to the through holes 150. And is connected to the opening 100. Since the first encapsulant 15 is formed on the second surface 102 of the substrate 10 by a common printing method, the thickness H extends beyond the second surface 102 of the substrate 10. It can be satisfactorily controlled to a degree somewhat higher than the height h representing the height of the wireloop of the wire 14. Therefore, the thickness H of the first encapsulant 15 can be effectively reduced as compared with the ball height of the solder balls mounted on the bottom surface of the substrate in the general ball grid arrayed semiconductor device shown in FIG. 4. have. This also avoids the exposure of the gold wire 14 to the first encapsulant 15.

In order to prevent the semiconductor chip 12 and the gold wire 14 accommodated in the opening 100 from coming into contact with atmospheric and external moisture, a transparent sealing plate 16 is attached to the first encapsulant 15 by an adhesive and penetrates therethrough. The hole 150 is hermetically sealed, thereby separating the semiconductor chip 12 and the gold wires 14 from the atmosphere while allowing external light to be emitted to the semiconductor chip 12.

A plurality of connecting lumps 17 are mounted in alignment on the first surface 101 of the substrate 10 by the usual printing method and are exposed to the first surface 101 of the substrate 104. Electrical connections of the corresponding terminations. This is because the semiconductor chip 12 is connected to, for example, a printed circuit board through a route consisting of gold wires 14, conductive traces 103, conductive vias 104 and connecting lumps 17. Allow to be electrically connected to external devices (not shown) such as a PCB.

After the connecting lumps 17 are mounted on the substrate 10, a second encapsulant 18 is formed on the first surface 101 of the substrate 10 by means of an encapsulating material such as an epoxy resin to form the connecting lumps. The field 17 and the cover plate 11 are sealed. The ends 170 of the connecting lumps 17 and the outer surface 110 of the cover plate 11 are exposed to the second encapsulant 18 or alternatively the connecting lumps 17 and the cover plate ( The second encapsulant 18 is formed in such a way that 11 is completely covered, followed by a grinding process on the second encapsulant 18, thus providing the ends of the connecting lumps 17 with the ends. The thickness of the second encapsulant 18 is reduced to the extent that the outer surface 110 of the cover plate 11 is exposed to the second encapsulant. Immediately after formation of the second encapsulant 18, the upper surface 180 of the second encapsulant 18 is flush with the ends of the connecting lumps 17 and the outer surface 110 of the cover plate 11. do. However, in order to further reduce the overall height of the semiconductor device 1, immediately after forming the second encapsulant 18 to expose the connecting lumps 17 and the cover plate 11 to the second encapsulant, the second encapsulation Post to simultaneously polish the second encapsulant 18, the connecting lumps 17 and the cover plate 11 in the direction towards the substrate 10 until the appropriate and set thickness of the 18th is reached. ) Polishing may be performed. When the upper surface 180 of the second encapsulant 18, the ends 170 of the connecting lumps 17 and the outer surface 110 of the cover plate 11 are co-planarly positioned. The semiconductor device 1 is a satisfactory fabrication plane that provides a guaranteed electrical connection between the terminations 170 of the connection lumps 17 and an external device such as a printed circuit board by means of surface mount technology. It is formed with a manufacturing plane. This is because each connecting lump 17 can be completely and effectively connected to the corresponding connecting pads formed on the external device. As a result, the semiconductor device of the present invention can be manufactured better than the prior art and solves the problem of incomplete electrical connection due to insufficient planarity of the plane formed by the termination of the solder balls of the general BGA semiconductor device. Solve effectively.

On the other hand, the second encapsulant 18 and the first encapsulant 15 are formed on the first surface 101 and the second surface 102 of the substrate 10, respectively. This kind of structure not only increases the mechanical strength of the device itself, but also the first encapsulant 15 and the second encapsulant 18 applied to the substrate 10 during temperature cycles and high temperature conditions under operation. Eliminate thermal stress caused by Therefore, warpage of the semiconductor device of the present invention can be effectively eliminated, and delamination between the semiconductor chip 12 and the cover plate 11 can be prevented, thereby effectively improving the yield and reliability of the packaged product.

Moreover, the semiconductor chip 12 is located in the opening 100 of the substrate 10 and the thickness of the first encapsulant 15 is smaller than the thickness of the general solder ball and the thickness of the second encapsulant 18 is also a general semiconductor chip. Since the semiconductor device 1 of the present invention is smaller than the thickness of the semiconductor device 1 of the present invention, the semiconductor device is bonded to the upper surface of the substrate and the solder ball is injected into the bottom surface of the substrate provides a low shape semiconductor device having a lower height than the prior art BGA semiconductor device do.

Further, since the second encapsulant 18 and the first encapsulant 15 are formed on the first surface 101 and the second surface 102 of the substrate 10, respectively, the mechanical strength increases accordingly. As a result, the thickness of the substrate 10 can be reduced to reduce the manufacturing cost of the device without weakening the mechanical strength of the device.

Meanwhile, as shown in FIG. 2, the sealing plate 16 of the semiconductor device 1 according to the first embodiment may have a size sufficient to cover the entirety of the first encapsulant 15 and the through hole 150. have. This can make the adhesion of the sealing plate 16 to the first encapsulant 15 easier.

Second embodiment

3 is a cross sectional view of a second embodiment of semiconductor device according to the present invention; As shown in the figure, the semiconductor device 2 of the second embodiment has the sealing plate 16 described in the first embodiment for sealingly separating the semiconductor chip 22 and the gold wires 24 from the atmosphere. It has a structure substantially the same as the structure described in the first embodiment except that the resin body 26 is used instead. The resin body 26 is formed of a transparent resin material that can fill the through hole 250 and the opening 200 of the first encapsulant 25. Immediately after the resin body 26 is cured, the resin body can completely enclose the semiconductor chip 22 and the gold wire 24 in order not to expose the semiconductor chip and the gold wire to the atmosphere. On the other hand, tin, lead, lead alloy or directly bonded on the first surface 201 of the substrate 20 by a common solder ball injection method to electrically connect to the conductive vias 204 of the substrate 20 Solder balls 27 formed of tin alloy are used. After the second encapsulant 28 is formed on the first surface 201 of the substrate 20 to encapsulate the cover plate 21, the solder balls 27 and the second encapsulant 28, the polishing treatment is performed. The thickness of the second encapsulant 28 and the solder balls 27 is reduced to the same height as the cover plate 21. Thus, this exposes the upper surface 280 of the second encapsulant 28 and the termination 270 of the solder balls 27 to the outer surface 210 of the cover plate 21 and is flush with the outer surface of the cover plate. To be in.

The present invention has been described using exemplary preferred embodiments. However, it will be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. Accordingly, the claims should be accorded the broadest description so as to encompass an arrangement similar to all such variations.

Claims (11)

An opening formed through the substrate, a first surface, an opposing second surface, a plurality of conductive traces formed on the second surface and a plurality of conductive vias formed through the substrate, each conductive trace A substrate in electrical connection with one of the conductive vias; A cover member mounted on the first surface of the substrate to cover the end of the substrate opening; A semiconductor chip attached to the cover plate in such a manner that the semiconductor chip is received in the opening of the substrate; A plurality of first conductive elements for electrically connecting the semiconductor chip to the substrate through the opening; A first encapsulant formed on the second surface of the substrate for encapsulating conductive traces on the second surface of the substrate, leaving the openings of the substrate uncovered; A sealing member attached to the first encapsulant to seal and separate the semiconductor chip and the first conductive elements from the atmosphere to seal the opening of the substrate; A plurality of second conductive elements connected to the first surface of the substrate and electrically connected to the conductive vias of the substrate; And The substrate for encapsulating the cover plate and the second conductive elements in such a manner that the outer surface of the cover member and the end of the second conductive elements are exposed to the upper surface of the second encapsulant and flush with the upper surface of the second encapsulant. A low profile photosensitive semiconductor device comprising a second encapsulant formed on a first surface of the substrate. The semiconductor device according to claim 1, wherein the cover member is formed as a tape made of a resin material. The semiconductor device of claim 1, wherein the cover member is a heat spreader made of a thermally conductive metal. The semiconductor device according to claim 1, wherein the sealing member is transparent and attached to the first encapsulant for sealingly sealing a through hole formed in the first encapsulant and interconnected to an opening of a substrate. The semiconductor device according to claim 1, wherein the sealing member is transparent and is joined to the first sealing agent to seal the opening of the substrate to completely cover the first sealing agent. The semiconductor device according to claim 1, wherein the sealing member is formed as a resin body made of a transparent resin for filling an opening of a substrate in order to seal the semiconductor chip and the first conductive element. The semiconductor device of claim 1, wherein the first conductive elements are gold wires. The semiconductor device of claim 1, wherein the second conductive elements are solder balls. The semiconductor device of claim 1, wherein the second conductive elements are connection lumps. The semiconductor device of claim 9, wherein the connection lumps are formed of a conductive metal. The semiconductor device of claim 1, wherein the thickness of the first encapsulant is higher than the height of the first conductive elements extending onto the second surface of the substrate.