KR100567045B1 - A package - Google Patents

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KR100567045B1
KR100567045B1 KR1019990011586A KR19990011586A KR100567045B1 KR 100567045 B1 KR100567045 B1 KR 100567045B1 KR 1019990011586 A KR1019990011586 A KR 1019990011586A KR 19990011586 A KR19990011586 A KR 19990011586A KR 100567045 B1 KR100567045 B1 KR 100567045B1
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South Korea
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lead
input
package
semiconductor chip
lead portion
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KR1019990011586A
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Korean (ko)
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KR20000065370A (en
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하성권
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주식회사 하이닉스반도체
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Priority to KR1019990011586A priority Critical patent/KR100567045B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Abstract

본 발명은 반도체 패키지에 관한 것으로써, 종래의 BLP형 패키지(Bottom Lead Package)에서 다핀 구조를 갖는 BLP형 패키지를 형성하기 위해서는 입출력 패드의 개수를 증가시켜야 하나, 입출력 패드의 개수 증가에 따라 패키지의 크기도 커지게 되어 CSP형 패키지(Chip Size Package)를 실현하기 어려운 문제점이 있었던 바, 본 발명인 반도체 패키지는 다수개의 입출력 패드를 가진 반도체 칩과; 상기 반도체 칩이 부착되고, 상기 입출력 패드와 제 1 와이어를 통해 상호 전기적으로 연결되는 제 1 리드와; 상기 제 1 리드과 상호 절연되어 적층되며, 상기 제 1 리드와 연결된 상기 입출력 패드 외의 입출력 패드에 상호 전기적으로 제 2 와이어를 통해 연결되는 제 2 리드와; 상기 반도체 칩과 제 1 및 제 2 와이어를 밀봉하되, 상기 제 1 리드 및 제 2 리드의 일부를 노출시키는 몰딩재를 포함하여 이루어져 다핀 구조이면서 CSP형 패키지(Chip Size Package)를 실현시킬 수 있는 효과가 있다.The present invention relates to a semiconductor package, and in order to form a BLP type package having a multi-pin structure in a conventional BLP type package (Bottom Lead Package), the number of input / output pads should be increased, but as the number of input / output pads increases, The size of the semiconductor package has a problem that it is difficult to realize a CSP type package (Chip Size Package), the semiconductor package of the present invention comprises a semiconductor chip having a plurality of input and output pads; A first lead attached to the semiconductor chip and electrically connected to the input / output pad and the first wire; A second lead which is mutually insulated from and stacked with the first lead and is electrically connected to an input / output pad other than the input / output pad connected to the first lead through a second wire; Sealing the semiconductor chip and the first and second wires, including a molding material for exposing a portion of the first lead and the second lead is made of a multi-pin structure and CSP-type package (Chip Size Package) effect that can be realized There is.

반도체 패키지Semiconductor package

Description

반도체 패키지{A package}Semiconductor Package {A package}

제 1 도는 종래의 BLP 구조를 나타낸 단면도이고,1 is a cross-sectional view showing a conventional BLP structure,

제 2a, 2b 도는 본 발명의 BLP 구조를 나타낸 단면도 및 상면도이고,2a, 2b is a cross-sectional view and a top view showing the BLP structure of the present invention,

제 3a, 3b 도는 본 발명의 BLP에서 적층된 리드 프레임의 단면도 및 상면도이고,3a, 3b is a cross-sectional view and a top view of a lead frame laminated in the BLP of the present invention,

제 4 도는 본 발명인 BLP에서 적층된 리드 프레임과 반도체 칩의 입출력 패드와의 연결을 보인 도면이다.4 is a view illustrating a connection between a lead frame stacked in the BLP according to the present invention and an input / output pad of a semiconductor chip.

■ 도면의 주요부분에 대한 간략한 부호설명 ■■ Brief description of the main parts of the drawing ■

10,100 : 반도체 칩 11,101 : 와이어10,100: semiconductor chip 11,101: wire

12,102 : 입출력 패드 13,103 : 절연접착재 12,102: input / output pad 13,103: insulation adhesive

14,104 : 리드 15 : 몰딩재 14,104: lead 15: molding material

본 발명은 반도체 패키지에 관한 것으로써, 특히, 기존 리드 프레임의 인너리드부에 인너리드를 절연 적층시켜 리드 프레임의 인너리드부를 이중 적층된 구조로 하여 다핀 구조이면서 크기가 작은 반도체 패키지이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having a multi-pin structure and a small size in which the inner lead portion of the lead frame is insulated and laminated to the inner lead portion of the existing lead frame.

일반적으로 최근 반도체 패키지는 집적회로의 고집적화에 따라 다수개의 리드를 갖 게 되고, 또한 각기 다른 실장방식 및 기능상의 요구에 따라 다양한 형태로 제작되고 있다. 이러한 다양한 반도체 패키지 가운데 BLP(Bottom Lead Package)형은 리드가 패키지의 저면에 형성되어 있으며, 이와같은 BLP 형에서 리드와 반도체칩을 서로 결합하는 방법으로는 리드 위에 반도체 칩을 접착시키고, 칩과 리드를 서로 전기적으로 연결시킨 다음 몰딩하여 고정하는 LOC(Lead On Chip)형이 사용된다.In general, semiconductor packages have a plurality of leads due to the high integration of integrated circuits, and are also manufactured in various forms according to different mounting methods and functional requirements. Among these various semiconductor packages, the BLP (Bottom Lead Package) type has a lead formed on the bottom of the package. In the BLP type, a method of bonding the lead and the semiconductor chip to each other is to bond the semiconductor chip onto the lead, Lead On Chip (LOC) type is used, which is electrically connected to each other and then molded and fixed.

제 1 도는 종래의 BLP형 패키지의 구조를 설명하기 위한 단면도로써, 종래의 BLP형 패키지는 절연 접착제(13)를 사용한 다이본딩(Die bonding)을 통해 반도체 칩(10)의 표면에 리드(14)가 부착고정되고, 와이어(11)를 이용한 와이어 본딩(wire bonding)을 통해 반도체 칩(10)에 형성된 다수개의 입출력 패드(12)와 리드(14)의 인너 리드(inner lead)부분이 상호 전기적으로 연결된다.1 is a cross-sectional view illustrating a structure of a conventional BLP type package. The conventional BLP type package has a lead 14 on the surface of the semiconductor chip 10 through die bonding using an insulating adhesive 13. Is attached and fixed, and a plurality of input / output pads 12 and inner lead portions of the lead 14 formed on the semiconductor chip 10 are electrically connected to each other through wire bonding using the wire 11. Connected.

또한, 리드(14)에 다이 본딩된 반도체 칩(10) 및 리드(14)와 반도체 칩(10)에 와이어 본딩된 와이어(11)를 외부의 물리적 또는 화학적 충격으로부터 보호하도록 반도체 칩과 와이어를 에폭시 수지등의 몰딩재(15)를 사용하여 몰딩시켜 보호한다.Also, the semiconductor chip and the wire may be epoxy-protected to protect the semiconductor chip 10 bonded to the lead 14 and the wire 11 wired to the lead 14 and the semiconductor chip 10 from external physical or chemical impacts. It is molded and protected using a molding material 15 such as resin.

이때, 몰딩재(15)의 저면에는 리드(14)의 아우터 리드(outer lead)부분이 노출되는데, 노출된 아우터 리드부분은 몰딩재(15)의 하부 표면과 노출된 아우터 리드의 표면이 동일한 평면을 이루도록 형성시킨다.In this case, an outer lead portion of the lead 14 is exposed on the bottom surface of the molding member 15, and the exposed outer lead portion has the same surface as the lower surface of the molding member 15 and the exposed outer lead portion. Form to achieve.

이러한 BLP형 패키지는 몰딩재(15)의 외부로 노출된 리드(14)가 인쇄회로기판(Printed circuit board; 이하 PCB)에 솔더링(soldering)되어 BLP의 실장이 이루어진다.In the BLP type package, the lead 14 exposed to the outside of the molding material 15 is soldered to a printed circuit board (hereinafter, referred to as a PCB) to mount the BLP.

그러나, 반도체 칩이 점차로 고집적화됨에 따라 반도체 칩의 입출력 패드의 수가 점차로 증가되는데, 이러한 입출력 패드의 증가에 따라 다핀 구조를 갖는 패키지를 형성하기 위해 리드의 개수가 점차로 증가되어야 한다.However, as the semiconductor chip is increasingly integrated, the number of input / output pads of the semiconductor chip gradually increases, and as the number of input / output pads increases, the number of leads must be gradually increased to form a package having a multi-pin structure.

따라서, 패드 개수와 리드 개수의 증가에 따라 반도체 패키지의 크기도 동시에 커지게 되어 반도체 패키지의 경박단소(輕薄短小)가 불가능해져 CSP(Chip Size Package)구현이 어려운 문제점이 있다.Therefore, as the number of pads and leads increases, the size of the semiconductor package is also increased at the same time, making it impossible to make thin and small the semiconductor package, which makes it difficult to implement a chip size package (CSP).

이에 본 발명은 입출력 패드와 리드의 수가 증가되더라도 경박단소한 반도체 패키지를 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a light and simple semiconductor package even if the number of input / output pads and leads is increased.

따라서, 상기 목적을 달성하기 위한 본 발명에 따른 반도체 패키지는 다수개의 입출력 패드를 가진 반도체 칩과; 인너 리드부와 아웃터 리드부로 구성되어 상기 인너 리드부의 일측이 상기 반도체 칩에 부착되면서 상기 입출력 패드와 제 1 와이어를 통해 전기적으로 연결되는 제 1 리드와; 인너 리드부와 아웃터 리드부로 구성되어 상기 제 1 리드 상에 절연되게 적층되며 상기 인너 리드부의 일측이 상기 다수개의 입출력 패드 중 상기 제 1 리드의 인너 리드부와 전기적으로 연결되지 않은 입출력 패드와 제 2 와이어를 통해 전기적으로 연결되는 제 2 리드와; 상기 제 1 리드 및 제 2 리드 각각의 아웃터 리드가 외부에 노출되도록 인너 리드부를 포함하여 상기 반도체 칩과 제 1 및 제 2 와이어를 밀봉하는 몰딩재를 포함하되, 상기 제 1 리드의 아웃터 리드부는 상기 몰딩재의 측부 양측면으로 돌출되고, 상기 제 2 리드의 아웃터 리드부는 상기 몰딩재의 하부 표면으로 노출된다.Accordingly, a semiconductor package according to the present invention for achieving the above object includes a semiconductor chip having a plurality of input and output pads; A first lead having an inner lead portion and an outer lead portion, the one side of the inner lead portion being attached to the semiconductor chip and electrically connected to the input / output pad and the first wire; An input / output pad comprising a inner lead portion and an outer lead portion and insulated on the first lead, and having one side of the inner lead portion not electrically connected to the inner lead portion of the first lead among the plurality of input / output pads; A second lead electrically connected through a wire; And a molding material sealing the semiconductor chip and the first and second wires, including an inner lead part to expose the outer lead of each of the first lead and the second lead, wherein the outer lead part of the first lead is The sides of the molding material protrude to both sides, and the outer lead portion of the second lead is exposed to the lower surface of the molding material.

삭제delete

상기에서 제 1 리드의 아웃터 리드부와 상기 제 2 리드의 아웃터 리드부는 동일한 평면상에 놓이도록 절곡된다.In the above, the outer lead portion of the first lead and the outer lead portion of the second lead are bent to lie on the same plane.

이하, 첨부된 도면을 참조하여 본 발명인 반도체 패키지의 바람직한 일실시예를 설명하면 다음과 같다.Hereinafter, a preferred embodiment of a semiconductor package according to the present invention will be described with reference to the accompanying drawings.

제 2a, 2b 도는 본 발명의 BLP 구조를 나타낸 단면도 및 상면도이고, 제 3a,3b 도는 본 발명의 BLP에서 이중적층된 리드프레임을 나타낸 단면도 및 상면도이고, 제 4 도는 이중 적층된 리드프레임과 반도체 칩의 입출력 패드가 서로 연결되는 것을 보인 도면이다.2a, 2b is a cross-sectional view and a top view showing a BLP structure of the present invention, 3a, 3b is a cross-sectional view and a top view showing a double laminated lead frame in the BLP of the present invention, Figure 4 is a double stacked lead frame and It is a view showing that input and output pads of a semiconductor chip are connected to each other.

본 발명인 BLP형 패키지는 다수개의 입출력 패드(102a,102b)를 가진 반도체 칩(100)과, 반도체 칩이 다이본딩(Die bonding)으로 부착 고정되며, 입출력 패드와 와이어(101a,101b)가 와이어 본딩(Wire bonding)를 통해 상호 전기적으로 연결되는 리드부(104a,104b)와, 반도체 칩(100)과 와이어(101a,101b)를 에폭시 수지로 밀봉하여 외부의 물리적 또는 화학적 충격으로부터 보호하되, 리드부의 일부가 외부로 노출되도록 밀봉하는 밀봉재(15)를 포함하여 이루어진다.In the BLP type package of the present invention, the semiconductor chip 100 having a plurality of input / output pads 102a and 102b and the semiconductor chip are fixed by die bonding, and the input / output pad and the wires 101a and 101b are wire-bonded. The lead portions 104a and 104b and the semiconductor chips 100 and the wires 101a and 101b electrically connected to each other through wire bonding are sealed with an epoxy resin to protect them from external physical or chemical shocks, It comprises a sealing material 15 for sealing so that a portion is exposed to the outside.

본 발명의 BLP에서 적층된 리드 프레임의 단면도 및 상면도인 제 2a,2b도를 참조하면, 반도체 칩이 고정 접착되는 리드부(104a,104b)는 절연 접착 테이프 또는 절연 접착제 등의 절연 접착재(13)를 통해 반도체 칩(100)이 실장 및 고정되는 제 1 리드(104a)와, 제 1 리드가 절연 접착테이프 또는 절연 접착제 등의 절연 접착재(103)를 통해 부착 고정되는 제 2 리드(104b)로 이루어진 이중 적층구조이다.Referring to FIGS. 2A and 2B, which are cross-sectional views and top views of lead frames stacked in the BLP of the present invention, the lead portions 104a and 104b to which the semiconductor chip is fixedly bonded may be formed of an insulating adhesive material such as an insulating adhesive tape or an insulating adhesive 13. And a first lead 104a on which the semiconductor chip 100 is mounted and fixed, and a second lead 104b attached and fixed through an insulating adhesive 103 such as an insulating adhesive tape or an insulating adhesive. It is a double laminated structure.

제 2 리드(104b)의 폭은 제 1 리드(104a)의 폭과 동일한 폭으로 하되, 길이는 제 1 리드(104a)의 길이보다 작게 형성함이 바람직하다.The width of the second lead 104b is equal to the width of the first lead 104a, but the length is preferably smaller than the length of the first lead 104a.

제 1 리드(104a)는 밀봉재(15)를 기준으로 인너 리드부와 아웃터 리드부로 각각 구분되고, 인너 리드부는 와이어 본딩을 통해 반도체 칩의 입출력 패드(102b)와 상호 전기적으로 연결되며 아웃터 리드부는 밀봉재(15)의 양측면으로 일정거리 돌출되게 형성된다. The first lead 104a is divided into an inner lead portion and an outer lead portion based on the sealant 15. The inner lead portion is electrically connected to the input / output pad 102b of the semiconductor chip through wire bonding, and the outer lead portion is sealed. It is formed to protrude a predetermined distance to both sides of the (15).

또한, 제 2 리드(104b)도 제 1 리드(104a)와 동일하게 밀봉재(15)를 기준으로 인너 리드부와 아웃터 리드부로 구분되는데, 인너 리드부는 제 1 리드(104a)와 연결되는 반도체 칩의 입출력 패드(102b)를 제외한 나머지 입출력 패드(102a)와 상호 전기적으로 연결되며, 아웃터 리드부는 밀봉재(15)의 하부 표면과 동일한 평면상으로 노출되게 형성된다.In addition, the second lead 104b is also divided into an inner lead portion and an outer lead portion based on the sealing material 15, similarly to the first lead 104a, and the inner lead portion of the semiconductor chip connected to the first lead 104a. It is electrically connected to the remaining input / output pad 102a except for the input / output pad 102b, and the outer lead portion is formed to be exposed on the same plane as the lower surface of the sealing material 15.

제 1 리드(104a)의 아웃터 리드부는 포밍(forming)을 통해 절곡되어 지는데, 제 2 리드(104b)의 아웃터 리드부와 동일한 평면상에 놓이도록 절곡된다.The outer lead portion of the first lead 104a is bent through forming, and is bent to lie on the same plane as the outer lead portion of the second lead 104b.

따라서, 제 1 리드(104a) 및 제 2 리드(104b)의 아웃터 리드부는 인쇄회로기판(PCB)에 솔더링(soldering)되어 실장된다.Accordingly, the outer lead portions of the first lead 104a and the second lead 104b are soldered to the printed circuit board PCB to be mounted.

이러한 구성으로 이루어진 본 발명인 BLP형 패키지는 입출력 패드(102a,102b)의 수가 증가되더라도 패키지의 크기를 변화시키지 않고, 다수개의 입출력 패드(102a,102b)와 리드(104a,104b)를 서로 와이어 본딩시켜 전기적으로 연결시킬 수 있게 된다.The BLP package according to the present invention having such a configuration does not change the size of the package even when the number of the input / output pads 102a and 102b is increased, thereby wire-bonding the plurality of input / output pads 102a and 102b and the leads 104a and 104b to each other. It can be connected electrically.

즉, 리드의 인너리드 부분이 제 1 리드(104a)와 제 2 리드(104b)로 각각 분리된 이중 적층구조이고, 제 1 리드(104a)와 제 2 리드(104b)를 각각 반도체 칩의 서로 다 른 입출력 패드(102a,102b)에 연결시킬 수 있게 되기 때문에 반도체 칩의 입출력 패드의 수가 증가하더라도 반도체 패키지의 크기를 크게 하지 않고 다핀 구조의 반도체 패키지를 제공할 수 있다.That is, the inner lead portion of the lead is a double stacked structure in which the first lead 104a and the second lead 104b are separated, respectively, and the first lead 104a and the second lead 104b are respectively different from each other of the semiconductor chip. Since it is possible to connect to other input / output pads 102a and 102b, even if the number of input / output pads of a semiconductor chip is increased, a semiconductor package having a multi-pin structure can be provided without increasing the size of the semiconductor package.

상기에서 상굴한 바와 같이, 본 발명인 반도체 패키지는 리드의 인너리드부분에 또 다른 인너리드를 적층시키고, 각각의 인너리드에 서로 다른 입출력 패드를 와이어 본딩시켜 연결함으로써 단위면적당 많은 수의 입출력 패드를 리드의 인너리드부분에 전기적으로 연결시킬 수 있게 된다.As described above, in the semiconductor package according to the present invention, another inner lead is stacked on the inner lead portion of the lead, and a different number of input / output pads are wire-bonded to each inner lead to connect a large number of input / output pads per unit area. It can be electrically connected to the inner lead of.

따라서, 다핀 구조를 가지면서 CSP(Chip Size Package)를 실현시킬 수 있는데 그 잇점이 있다.Therefore, it is possible to realize a chip size package (CSP) while having a multi-pin structure.

Claims (3)

반도체 패키지에 있어서,In a semiconductor package, 다수개의 입출력 패드를 가진 반도체 칩과;A semiconductor chip having a plurality of input / output pads; 인너 리드부와 아웃터 리드부로 구성되어 상기 인너 리드부의 일측이 상기 반도체 칩에 부착되면서 상기 입출력 패드와 제 1 와이어를 통해 전기적으로 연결되는 제 1 리드와;A first lead having an inner lead portion and an outer lead portion, the one side of the inner lead portion being attached to the semiconductor chip and electrically connected to the input / output pad and the first wire; 인너 리드부와 아웃터 리드부로 구성되어 상기 제 1 리드 상에 절연되게 적층되며 상기 인너 리드부의 일측이 상기 다수개의 입출력 패드 중 상기 제 1 리드의 인너 리드부와 전기적으로 연결되지 않은 입출력 패드와 제 2 와이어를 통해 전기적으로 연결되는 제 2 리드와;An input / output pad comprising a inner lead portion and an outer lead portion and insulated on the first lead, and having one side of the inner lead portion not electrically connected to the inner lead portion of the first lead among the plurality of input / output pads; A second lead electrically connected through a wire; 상기 제 1 리드 및 제 2 리드 각각의 아웃터 리드가 외부에 노출되도록 인너 리드부를 포함하여 상기 반도체 칩과 제 1 및 제 2 와이어를 밀봉하는 몰딩재를 포함하되,It includes a molding material for sealing the semiconductor chip and the first and second wire including an inner lead portion so that the outer lead of each of the first lead and the second lead is exposed to the outside, 상기 제 1 리드의 아웃터 리드부는 상기 몰딩재의 측부 양측면으로 돌출되고, 상기 제 2 리드의 아웃터 리드부는 상기 몰딩재의 하부 표면으로 노출되는 반도체 패키지.The outer lead portion of the first lead protrudes from both side surfaces of the molding material, and the outer lead portion of the second lead is exposed to the lower surface of the molding material. 삭제delete 청구항 1 에 있어서, 상기 제 1 리드의 아웃터 리드부와 상기 제 2 리드의 아웃터리드부는 동일한 평면상에 놓이도록 절곡된 것이 특징인 반도체 패키지.The semiconductor package according to claim 1, wherein the outer lead portion of the first lead and the outer lead portion of the second lead are bent to lie on the same plane.
KR1019990011586A 1999-04-02 1999-04-02 A package KR100567045B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254456A (en) * 1985-07-31 1987-03-10 Nec Corp Lead frame for semiconductor device
KR940012585A (en) * 1992-11-24 1994-06-23 문정환 Multichip Package and Manufacturing Method
KR970024090A (en) * 1995-10-07 1997-05-30 문정환 Semiconductor package
KR19980025623A (en) * 1996-10-04 1998-07-15 황인길 Semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254456A (en) * 1985-07-31 1987-03-10 Nec Corp Lead frame for semiconductor device
KR940012585A (en) * 1992-11-24 1994-06-23 문정환 Multichip Package and Manufacturing Method
KR970024090A (en) * 1995-10-07 1997-05-30 문정환 Semiconductor package
KR19980025623A (en) * 1996-10-04 1998-07-15 황인길 Semiconductor package

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