JPH098205A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPH098205A
JPH098205A JP17049095A JP17049095A JPH098205A JP H098205 A JPH098205 A JP H098205A JP 17049095 A JP17049095 A JP 17049095A JP 17049095 A JP17049095 A JP 17049095A JP H098205 A JPH098205 A JP H098205A
Authority
JP
Japan
Prior art keywords
inner lead
lead
semiconductor device
lead frame
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17049095A
Other languages
Japanese (ja)
Inventor
Junichi Yamada
淳一 山田
Masaru Sasaki
賢 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP17049095A priority Critical patent/JPH098205A/en
Publication of JPH098205A publication Critical patent/JPH098205A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To provide a resin sealed semicnductor device which can cope with the increased number of terminals and the positional deviations and flatness problems of outer leads. CONSTITUTION: Each inner lead of a resin sealed semiconductor device has a lead frame material united with the inner lead in one body and a columnar terminal pillar 133 which has the same thickness as the lead frame material has and is used for connecting the inner lead to an external circuit and the terminal pillar 133 is provided in the direction perpendicular to the thickness direction of the inner lead on the outside of the inner lead and has a terminal section composed of solder, etc., on its front end face. The terminal section and the external side face of the terminal pillar are exposed from the sealing resin section. The inner lead formed in a square cross section has a first surface 131Aa, a second surface 131Ab, a third surface 131Ac, and a fourth surface 131Ad and the first surface 131Aa is formed in the same plane with one surface of the other part having the same thickness as the lead frame material has and is counterposed to the second surface 131Ab. The third and fourth surfaces 131Ac and 131Ad are recessed toward the inside of the inner lead.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は，半導体装置の多端子化
に対応でき、且つ、アウターリードの位置ズレ（スキュ
ー）やアウターリードの平坦性（コプラナリティー）の
問題に対応できる、リードフレームを用いた樹脂封止型
半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a lead frame capable of coping with the increase in the number of terminals of a semiconductor device, and of addressing the positional deviation (skew) of the outer leads and the flatness (coplanarity) of the outer leads. The present invention relates to a resin-sealed semiconductor device used.

【０００２】[0002]

【従来の技術】従来より用いられている樹脂封止型の半
導体装置（プラスチックリードフレームパッケージ）
は、一般に図１５（ａ）に示されるような構造であり、
半導体素子１５２０を搭載するダイパッド部１５１１や
周囲の回路との電気的接続を行うためのアウターリード
部１５１３、アウターリード部１５１３に一体となった
インナーリード部１５１２、該インナーリード部１５１
２の先端部と半導体素子１５２０の電極パッド１５２１
とを電気的に接続するためのワイヤ１５３０、半導体素
子１５２０を封止して外界からの応力、汚染から守る樹
脂１５４０等からなっており、半導体素子１５２０をリ
ードフレームのダイパッド１５１１部等に搭載した後
に、樹脂１５４０により封止してパッケージとしたもの
で、半導体素子１５２０の電極パッド１５２１に対応で
きる数のインナーリード１５１２を必要とするものであ
る。そして、このような樹脂封止型の半導体装置の組立
部材として用いられる（単層）リードフレームは、一般
には図１５（ｂ）に示すような構造のもので、半導体素
子を搭載するためのダイパッド１５１１と、ダイパッド
１５１１の周囲に設けられた半導体素子と結線するため
のインナーリード１５１２、該インナーリード１５１２
に連続して外部回路との結線を行うためのアウターリー
ド１５１３、樹脂封止する際のダムとなるダムバー１５
１４、リードフレーム１５１０全体を支持するフレーム
（枠）部１５１５等を備えており、通常、コバール、４
２合金（４２％ニッケル−鉄合金）、銅系合金のような
導電性に優れた金属を用い、プレス法もしくはエッチン
グ法により形成されていた。尚、図１５（ｂ）（ロ）
は、図１５（ｂ）（イ）に示すリードフレーム平面図の
Ｆ１−Ｆ２における断面図である。2. Description of the Related Art Conventionally used resin-encapsulated semiconductor devices (plastic lead frame packages)
Generally has a structure as shown in FIG.
An outer lead portion 1513 for electrically connecting to a die pad portion 1511 on which the semiconductor element 1520 is mounted, a peripheral circuit, an inner lead portion 1512 integrated with the outer lead portion 1513, and the inner lead portion 151.
2 and the electrode pad 1521 of the semiconductor element 1520
And a resin 1540 for sealing the semiconductor element 1520 to protect the semiconductor element 1520 from external stress and contamination, and the semiconductor element 1520 is mounted on the die pad 1511 portion of the lead frame. Later, it is sealed with resin 1540 to form a package, which requires a number of inner leads 1512 corresponding to the electrode pads 1521 of the semiconductor element 1520. A (single layer) lead frame used as an assembly member of such a resin-sealed semiconductor device generally has a structure as shown in FIG. 15B, and has a die pad for mounting a semiconductor element. 1511, an inner lead 1512 for connecting to a semiconductor element provided around the die pad 1511, and the inner lead 1512
Outer lead 1513 for connecting to an external circuit continuously, and dam bar 15 serving as a dam for resin sealing
14, a frame portion 1515 for supporting the entire lead frame 1510, and the like.
It was formed by a pressing method or an etching method using a metal having excellent conductivity such as 2 alloy (42% nickel-iron alloy) and copper alloy. Incidentally, FIG. 15 (b) (b)
FIG. 16 is a sectional view taken along line F1-F2 of the lead frame plan view shown in FIGS.

【０００３】このようなリードフレームを利用した樹脂
封止型の半導体装置（プラスチックリードフレームパッ
ケージ）においても、電子機器の軽薄短小化の時流と半
導体素子の高集積化に伴い、小型薄型化かつ電極端子の
増大化が顕著で、その結果、樹脂封止型半導体装置、特
にＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）及び
ＴＱＦＰ（Ｔｈｉｎ Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａ
ｇｅ）等では、リードの多ピン化が著しくなってきた。
上記の半導体装置に用いられるリードフレームは、微細
なものはフオトリソグラフイー技術を用いたエッチング
加工方法により作製され、微細でないものはプレスによ
る加工方法による作製されるのが一般的であったが、こ
のような半導体装置の多ピン化に伴い、リードフレーム
においても、インナーリード部先端の微細化が進み、当
初は、微細なものに対しては、プレスによる打ち抜き加
工によらず、リードフレーム部材の板厚が０．２５ｍｍ
程度のものを用い、エッチング加工で対応してきた。こ
のエッチング加工方法の工程について以下、図１４に基
づいて簡単に述べておく。先ず、銅合金もしくは４２％
ニッケル−鉄合金からなる厚さ０．２５ｍｍ程度の薄板
（リードフレーム素材１４１０）を十分洗浄（図１４
（ａ））した後、重クロム酸カリウムを感光剤とした水
溶性カゼインレジスト等のフオトレジスト１４２０を該
薄板の両表面に均一に塗布する。（（図１４（ｂ）） 次いで、所定のパターンが形成されたマスクを介して高
圧水銀灯でレジスト部を露光した後、所定の現像液で該
感光性レジストを現像して（図１４（ｃ））、レジスト
パターン１４３０を形成し、硬膜処理、洗浄処理等を必
要に応じて行い、塩化第二鉄水溶液を主たる成分とする
エッチング液にて、スプレイにて該薄板（リードフレー
ム素材１４１０）に吹き付け所定の寸法形状にエッチン
グし、貫通させる。（図１４（ｄ）） 次いで、レジスト膜を剥膜処理し（図１４（ｅ））、洗
浄後、所望のリードフレームを得て、エッチング加工工
程を終了する。このように、エッチング加工等によって
作製されたリードフレームは、更に、所定のエリアに銀
メッキ等が施される。次いで、洗浄、乾燥等の処理を経
て、インナーリード部を固定用の接着剤付きポリイミド
テープにてテーピング処理したり、必要に応じて所定の
量タブ吊りバーを曲げ加工し、ダイパッド部をダウンセ
ットする処理を行う。しかし、エッチング加工方法にお
いては、エッチング液による腐蝕は被加工板の板厚方向
の他に板幅（面）方向にも進むため、その微細化加工に
も限度があるのが一般的で、図１４に示すように、リー
ドフレーム素材の両面からエッチングするため、ライン
アンドスペース形状の場合、ライン間隔の加工限度幅
は、板厚の５０〜１００％程度と言われている。又、リ
ードフレームの後工程等のアウターリードの強度を考え
た場合、一般的には、その板厚は約０．１２５ｍｍ以上
必要とされている。この為、図１４に示すようなエッチ
ング加工方法の場合、リードフレームの板厚を０．１５
ｍｍ〜０．１２５ｍｍ程度まで薄くすることにより、ワ
イヤボンデイングのための必要な平坦幅７０〜８０μｍ
を確保し、０．１６５ｍｍピッチ程度の微細なインナー
リード部先端のエッチングによる加工を達成してきた
が、これが限度とされていた。Even in a resin-sealed semiconductor device (plastic lead frame package) using such a lead frame, the size and thickness of electrodes and electrodes have been reduced due to the trend of electronic devices becoming lighter, thinner, shorter and smaller, and higher integration of semiconductor elements. The number of terminals is remarkably increased, and as a result, a resin-sealed semiconductor device, particularly a QFP (Quad Flat Package) and a TQFP (Thin Quad Flat Package).
In the case of ge) and the like, the increase in the number of pins on the lead has become remarkable.
The lead frame used in the above-mentioned semiconductor device is generally manufactured by an etching method using a photolithographic technique for fine ones, and is generally manufactured by a pressing method for non-fine ones. With the increase in the number of pins of such semiconductor devices, miniaturization of the tips of the inner lead portions also progresses in the lead frame. Initially, for fine ones, the lead frame member Thickness is 0.25mm
We have dealt with the etching process by using some grade. The steps of this etching method will be briefly described below with reference to FIG. First, copper alloy or 42%
Thoroughly clean a thin plate (lead frame material 1410) made of a nickel-iron alloy and having a thickness of about 0.25 mm (Fig. 14).
After (a)), a photoresist 1420 such as a water-soluble casein resist using potassium dichromate as a photosensitizer is uniformly applied to both surfaces of the thin plate. ((FIG. 14 (b)) Next, after exposing the resist portion with a high-pressure mercury lamp through a mask on which a predetermined pattern is formed, the photosensitive resist is developed with a predetermined developing solution (FIG. 14 (c)). ), A resist pattern 1430 is formed, and a film hardening process, a cleaning process, etc. are performed as necessary, and the thin plate (lead frame material 1410) is sprayed on the thin plate (lead frame material 1410) with an etching solution containing a ferric chloride aqueous solution as a main component. By spraying, etching is performed to a predetermined size and shape to penetrate the resist film (FIG. 14D). Then, the resist film is stripped (FIG. 14E), and after cleaning, a desired lead frame is obtained to perform an etching process. In this way, the lead frame manufactured by the etching process is further subjected to silver plating in a predetermined area, etc. Then, after undergoing treatments such as washing and drying, the inner frame is finished. The tape part is taped with an adhesive-attached polyimide tape for fixing, or the tab suspension bar is bent by a predetermined amount if necessary, and the die pad part is downset. Is corroded by the etching solution not only in the plate thickness direction of the plate to be processed but also in the plate width (plane) direction, so that the miniaturization is generally limited, and as shown in FIG. Since the lead frame material is etched from both sides, in the case of the line and space shape, the processing limit width of the line interval is said to be about 50 to 100% of the plate thickness. In consideration of the strength, the plate thickness is generally required to be about 0.125 mm or more. Therefore, in the case of the etching processing method as shown in FIG. The thickness of the plate is 0.15
mm to 0.125 mm, the required flat width 70 to 80 μm for wire bonding
Has been achieved, and the processing by etching the tip of the fine inner lead portion with a pitch of about 0.165 mm has been achieved, but this has been the limit.

【０００４】しかしながら、近年、樹脂封止型半導体装
置は、小パッケージでは、電極端子であるインナーリー
ドのピッチが０．１６５ｍｍピッチを経て、既に０．１
５〜０．１３ｍｍピッチまでの狭ピッチ化要求がでてき
た事と、エッチング加工において、リード部材の板厚を
薄くした場合には、アセンブリ工程や実装工程といった
後工程におけるアウターリードの強度確保が難しいとい
う点から、単にリード部材の板厚を薄くしてエッチング
加工を行う方法にも限界が出てきた。However, in recent years, in the resin-sealed type semiconductor device, in a small package, the pitch of the inner leads, which are the electrode terminals, has been 0.165 mm, and is already 0.1.
There is a demand for a narrower pitch of 5 to 0.13 mm, and when the thickness of the lead member is reduced in the etching process, it is possible to secure the strength of the outer lead in the post process such as the assembly process and the mounting process. From the point of difficulty, there is a limit to the method of simply reducing the plate thickness of the lead member and performing the etching process.

【０００５】これに対応する方法として、アウターリー
ドの強度を確保したまま微細化を行う方法で、インナー
リード部分をハーフエッチングもしくはプレスにより薄
くしてエッチング加工を行う方法が提案されている。し
かし、プレスにより薄くしてエッチング加工をおこなう
場合には、後工程においての精度が不足する（例えば、
めっきエリアの平滑性）、ボンデイング、モールデイン
グ時のクランプに必要なインナーリードの平坦性、寸法
精度が確保されない、製版を２度行なわなければならな
い等製造工程が複雑になる、等問題点が多くある。そし
て、インナーリード部分をハーフエッチングにより薄く
してエッチング加工を行う方法の場合にも、製版を２度
行なわなければならず、製造工程が複雑になるという問
題があり、いずれも実用化には、未だ至っていないのが
現状である。As a method for dealing with this, there has been proposed a method of miniaturizing while maintaining the strength of the outer leads, and a method of etching the inner leads by thinning them by half etching or pressing. However, if the thickness is reduced by pressing and etching is performed, the accuracy in the subsequent process is insufficient (for example,
(Smoothness of plating area), flatness of inner leads required for clamping during bonding and molding, dimensional accuracy is not secured, and the plate making process must be performed twice, which complicates the manufacturing process. is there. Also, in the case of a method in which the inner lead portion is thinned by half etching and etching is performed, plate making must be performed twice, and there is a problem that the manufacturing process becomes complicated. The current situation is that it has not arrived yet.

【０００６】[0006]

【発明が解決しようとする課題】一方、半導体装置の多
端子化に伴いインナーリードピッチが狭くなる為、半導
体装置を実装する際に、アウターリードの位置ズレ（ス
キュー）や平坦性（コプラナリティー）の良し悪しが大
きな問題となってきた。本発明は、このような状況のも
と、多端子化に対応でき、且つ、アウターリードの位置
ズレ（スキュー）や平坦性（コプラナリティー）の問題
にも対応できる半導体装置の提供をしようとするもので
ある。On the other hand, since the inner lead pitch becomes narrower as the number of terminals of the semiconductor device increases, the positional deviation (skew) and flatness (coplanarity) of the outer lead when mounting the semiconductor device. The good and bad have become big problems. Under the circumstances, the present invention intends to provide a semiconductor device which can cope with the increase in the number of terminals and can also deal with the positional deviation (skew) of the outer leads and the flatness (coplanarity). It is a thing.

【０００７】[0007]

【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、２段エッチング加工によりインナーリードの
厚さがリードフレーム素材の厚さよりも薄肉に外形加工
されたリードフレームを用いた半導体装置であって、前
記リードフレームは、リードフレーム素材よりも薄肉の
インナーリードと、該インナーリードに一体的に連結し
たリードフレーム素材と同じ厚さの外部回路と接続する
ための柱状の端子柱とを有し、且つ、端子柱はインナー
リードの外部側においてインナーリードに対して厚み方
向に直交して設けられており、端子柱の先端面に半田等
からなる端子部を設け、端子部を封止用樹脂部から露出
させ、端子柱の外部側の側面を封止用樹脂部から露出さ
せており、インナーリードは、断面形状が略方形で第１
面、第２面、第３面、第４面の４面を有しており、かつ
第１面はリードフレーム素材と同じ厚さの他の部分の一
方の面と同一平面上にあって第２面に向き合っており、
第３面、第４面はインナーリードの内側に向かって凹ん
だ形状に形成されていることを特徴とするものである。
また、本発明の樹脂封止型半導体装置は、２段エッチン
グ加工によりインナーリードの厚さがリードフレーム素
材の厚さよりも薄肉に外形加工されたリードフレームを
用いた半導体装置であって、前記リードフレームは、リ
ードフレーム素材よりも薄肉のインナーリードと、該イ
ンナーリードに一体的に連結したリードフレーム素材と
同じ厚さの外部回路と接続するための柱状の端子柱とを
有し、且つ、端子柱はインナーリードの外部側において
インナーリードに対して厚み方向に直交して設けられて
おり、端子柱の先端の一部を封止用樹脂部から露出させ
て端子部とし、端子柱の外部側の側面を封止用樹脂部か
ら露出させており、インナーリードは、断面形状が略方
形で第１面、第２面、第３面、第４面の４面を有してお
り、かつ第１面はリードフレーム素材と同じ厚さの他の
部分の一方の面と同一平面上にあって第２面に向き合っ
ており、第３面、第４面はインナーリードの内側に向か
って凹んだ形状に形成されていることを特徴とするもの
である。そして、上記において、半導体素子は、インナ
ーリード部間に収まり、該半導体素子の電極部（パッ
ド）はワイヤにてインナーリードと電気的に結線されて
いることを特徴とするものである。また、該リードフレ
ームはダイパッドを有し、半導体素子はダイパッド上に
搭載、固定されていることを特徴とするものであり、該
リードフレームはダイパッドを持たないもので、半導体
素子はインナーリードとともに補強用テープにより固定
されていることを特徴とするものである。また、上記に
おいて、リードフレームはダイパッドを持たないもの
で、半導体素子はインナーリードとともに補強固定用テ
ープにより固定されていることを特徴とするものであ
る。また、上記において、半導体素子は、半導体素子の
電極部（パッド）側の面をインナーリードの第２面に絶
縁性接着材により固定されており、該半導体素子の電極
部（パッド）はワイヤによりインナーリードの第１面と
電気的に結線されていることを特徴とするものである。
また、上記において、半導体素子は、バンプによりイン
ナーリードの第２面に固定され、電気的にインナーリー
ドと接続していることを特徴とするものである。尚、上
記において、端子柱の先端面に半田等からなる端子部を
設け、端子部を封止用樹脂部から露出させる場合、半田
等からなる端子部は封止用樹脂部から突出したものが一
般的であるが、必ずしも突出する必要はない。また、端
子柱部の外部側の側面を封止用樹脂部から露出させて、
そのまま用いる場合もあるが、封止用樹脂部から露出さ
れて部分を接着材等を介して保護枠で覆っても良い。The resin-sealed semiconductor device of the present invention is a semiconductor device using a lead frame in which the thickness of the inner leads is processed by two-step etching to be thinner than the thickness of the lead frame material. In the device, the lead frame includes an inner lead that is thinner than the lead frame material, and a columnar terminal pillar that is integrally connected to the inner lead and that is connected to an external circuit having the same thickness as the lead frame material. And the terminal post is provided on the outer side of the inner lead in a direction orthogonal to the thickness direction of the inner lead, and the terminal part made of solder or the like is provided on the tip surface of the terminal post to seal the terminal part. The inner lead is exposed from the stopper resin portion, and the outer side surface of the terminal pillar is exposed from the sealing resin portion. The inner lead has a substantially rectangular cross-sectional shape.
Surface, the second surface, the third surface, and the fourth surface, and the first surface is flush with one surface of the other portion having the same thickness as the lead frame material. Facing two sides,
The third surface and the fourth surface are formed so as to be recessed toward the inner side of the inner lead.
The resin-encapsulated semiconductor device of the present invention is a semiconductor device using a lead frame in which the thickness of an inner lead is externally processed by a two-step etching process to be thinner than the thickness of a lead frame material. The frame has an inner lead that is thinner than the lead frame material, and a columnar terminal pillar that is integrally connected to the inner lead and that has a columnar terminal pillar for connecting to an external circuit that has the same thickness as the lead frame material. The pillar is provided on the outer side of the inner lead in a direction orthogonal to the inner lead in the thickness direction. A part of the tip of the terminal pillar is exposed from the encapsulating resin portion to form the terminal portion. Of the inner lead is exposed from the sealing resin portion, and the inner lead has a substantially rectangular cross-sectional shape and has four surfaces of a first surface, a second surface, a third surface, and a fourth surface, and One side Of the other part of the same thickness as the core frame material, which is flush with one surface of the other part and faces the second surface, and the third and fourth surfaces are formed in a shape recessed toward the inner side of the inner lead. It is characterized by that. Further, in the above, the semiconductor element is fitted between the inner lead portions, and the electrode portion (pad) of the semiconductor element is electrically connected to the inner lead by a wire. Further, the lead frame has a die pad, and the semiconductor element is mounted and fixed on the die pad. The lead frame has no die pad, and the semiconductor element is reinforced with inner leads. It is characterized by being fixed with a tape for use. Further, in the above, the lead frame does not have a die pad, and the semiconductor element is fixed together with the inner lead by a reinforcing fixing tape. Further, in the above, in the semiconductor element, the surface on the electrode portion (pad) side of the semiconductor element is fixed to the second surface of the inner lead with an insulating adhesive material, and the electrode portion (pad) of the semiconductor element is connected by a wire. It is characterized in that it is electrically connected to the first surface of the inner lead.
Further, in the above, the semiconductor element is fixed to the second surface of the inner lead by a bump and electrically connected to the inner lead. In the above, when a terminal portion made of solder or the like is provided on the tip surface of the terminal pillar and the terminal portion is exposed from the sealing resin portion, the terminal portion made of solder or the like should be projected from the sealing resin portion. Generally, it is not always necessary to project. Also, by exposing the outer side surface of the terminal pillar portion from the sealing resin portion,
Although it may be used as it is, the exposed portion from the sealing resin portion may be covered with a protective frame via an adhesive or the like.

【０００８】[0008]

【作用】本発明の樹脂封止型半導体装置は、上記のよう
に構成することにより、リードフレームを用いた樹脂封
止型半導体装置において、多端子化に対応でき、且つ、
従来の図１３（ｂ）に示す単層リードフレームを用いた
場合のように、アウターリードのフオーミング工程を必
要としないため、これらの工程に起因して発生していた
アウターリードのスキューの問題やアウターリードの平
坦性（コープラナリティー）の問題を全く無くすことが
できる半導体装置の提供を可能とするものである。詳し
くは、２段エッチング加工によりインナーリードの厚さ
が素材の厚さよりも薄肉に外形加工された、即ち、イン
ナーリードを微細に加工された多ピンのリードフレーム
を用いることにより、半導体装置の多端子化に対応でき
るものとしている。更に、後述する、図１１に示す２段
エッンチングにより作製された、リードフレームを用い
ることにより、インナーリード部の第２面は平坦性を確
保でき、ワイヤボンデイング性の良いものとしている。
また第１面も平坦面で、第３面、第４面はインナーリー
ド側に凹状であるためインナーリード部は、安定してお
り、且つ、ワイヤボンデイングの平坦幅を広くとれる。The resin-encapsulated semiconductor device of the present invention, which is configured as described above, can accommodate multiple terminals in the resin-encapsulated semiconductor device using the lead frame, and
Unlike the case of using the conventional single-layer lead frame shown in FIG. 13B, since the outer lead forming process is not required, the problem of the outer lead skew caused by these processes and (EN) It is possible to provide a semiconductor device capable of completely eliminating the problem of flatness (coplanarity) of outer leads. More specifically, by using a multi-pin lead frame in which the thickness of the inner lead is thinned by the two-step etching process to be thinner than the thickness of the material, that is, the inner lead is finely processed, the multi-pin lead frame is manufactured. It is supposed to be compatible with terminals. Furthermore, by using a lead frame manufactured by the two-step etching shown in FIG. 11, which will be described later, the second surface of the inner lead portion can secure the flatness and the wire bonding property is good.
Further, the first surface is also a flat surface, and the third surface and the fourth surface are concave toward the inner lead side, so that the inner lead portion is stable and the flat width of the wire bonding can be widened.

【０００９】[0009]

【実施例】本発明の樹脂封止型半導体装置の実施例を図
にそって説明する。先ず、実施例１の樹脂封止型半導体
装置を図１、図２に示し、説明する。図１（ａ）は実施
例１の樹脂封止型半導体装置の断面図であり、図１
（ｂ）は図１（ａ）のＡ１−Ａ２におけるインナーリー
ド部の断面図で、図１（ｃ）は図１（ａ）のＢ１−Ｂ２
における端子柱部の断面図で、図２（ａ）は実施例１の
樹脂封止型半導体装置の斜視図であり、図２（ｂ）はそ
の正面図を、図２（ｃ）は下面図を示している。図１、
図２中、１００は半導体装置、１１０は半導体素子、１
１１は電極部（パッド）、１２０はワイヤ、１３０はリ
ードフレーム、１３１はインナーリード、１３１Ａａは
第１面、１３１Ａｂは第２面、１３１Ａｃは第３面、１
３１Ａｄは第４面、１３３は端子柱部、１３３Ａは端子
部、１３３Ｂは側面、１３３Ｓは先端面、１３５はダイ
パッド、１４０は封止用樹脂である。本実施例１の樹脂
封止型半導体装置においては、図１（ａ）に示すよう
に、半導体素子１１０は、インナーリード間に収まり、
且つ、半導体素子は、図１（ａ）で半導体素子１１０の
電極部（パッド）１１１を上にして、半導体素子１１０
の電極部（パッド）１１１側の面とは反対側の面にてダ
イパッド１３５上に搭載され、固定されている。そし
て、電極部（パッド）１１１はインナーリード１３１の
第２面１３１Ａｂにてワイヤ１２０により、電気的に結
線されている。本実施例１の半導体装置１００と外部回
路との電気的な接続は、端子柱１３３の先端面１３３Ｓ
に設けられた半球状の半田からなる端子部１３３Ａを介
してプリント基板等へ搭載されることにより行われる。
尚、実施例１の半導体装置において、必らずしも保護枠
１８０を設ける必要はなく、図１（ｄ）に示すような保
護枠１８０を設けない構造のままでも良い。Embodiments of the resin-sealed semiconductor device of the present invention will be described with reference to the drawings. First, a resin-encapsulated semiconductor device of Example 1 is shown and described in FIGS. 1A is a cross-sectional view of the resin-sealed semiconductor device according to the first embodiment.
1B is a cross-sectional view of the inner lead portion taken along line A1-A2 of FIG. 1A, and FIG. 1C is taken along line B1-B2 of FIG.
2A is a cross-sectional view of the terminal pillar portion in FIG. 2, FIG. 2A is a perspective view of the resin-sealed semiconductor device of the first embodiment, FIG. 2B is a front view thereof, and FIG. Is shown. Figure 1,
In FIG. 2, 100 is a semiconductor device, 110 is a semiconductor element, and 1 is a semiconductor device.
11 is an electrode part (pad), 120 is a wire, 130 is a lead frame, 131 is an inner lead, 131Aa is the first surface, 131Ab is the second surface, 131Ac is the third surface, 1
31Ad is a fourth surface, 133 is a terminal pillar portion, 133A is a terminal portion, 133B is a side surface, 133S is a tip surface, 135 is a die pad, and 140 is a sealing resin. In the resin-encapsulated semiconductor device of the first embodiment, as shown in FIG. 1A, the semiconductor element 110 fits between the inner leads,
In addition, the semiconductor element is such that the electrode portion (pad) 111 of the semiconductor element 110 is faced up in FIG.
Is fixed and mounted on the die pad 135 on the surface opposite to the surface on the side of the electrode portion (pad) 111. The electrode portion (pad) 111 is electrically connected by the wire 120 on the second surface 131Ab of the inner lead 131. The electrical connection between the semiconductor device 100 according to the first embodiment and the external circuit is performed by the tip surface 133S of the terminal column 133.
It is carried out by being mounted on a printed circuit board or the like through a terminal portion 133A made of hemispherical solder provided on the.
In the semiconductor device of the first embodiment, it is not always necessary to provide the protective frame 180, and the structure as shown in FIG.

【００１０】実施例１の半導体装置１００に使用のリー
ドフレーム１３０は、４２％ニッケル−鉄合金を素材と
したもので、そして、図９（ａ）に示すような形状をし
た、エッチングにより外形加工されたリードフレーム１
３０Ａを用いたものであり、端子柱部１３３部分や他の
部分の厚さより薄肉に形成されたインナーリード部１３
１をもつ。ダムバー１３６は樹脂封止する際のダムとな
る。尚、図９（ａ）に示すような形状をした、エッチン
グにより外形加工されたリードフレーム１３０Ａを、本
実施例においては用いたが、インナーリード部１３１と
端子柱部１３３以外は最終的に不要なものであるから、
特にこの形状に限定はされない。インナーリード部１３
１の厚さｔは４０μｍ、インナーリード部１３１以外の
厚さｔ0 は０．１５ｍｍでリードフレーム素材の板厚の
ままである。インナーリード部１３１以外の板厚は０．
１５ｍｍに限らず更に薄い０．１２５ｍ〜０．５０ｍｍ
程度でも良い。また、インナーリードピッチは０．１２
ｍｍと狭いピッチで、半導体装置の多端子化に対応でき
るものとしている。インナーリード部１３１の第２面１
３１Ａｂは平坦状でワイヤボンデイィングし易い形状と
なっており、図１（ｂ）に示すように、第３面１３１Ａ
ｃ、第４面１３１Ａｄはインナーリード側へ凹んだ形状
をしており、第２面１３１Ａｂ（ワイヤボンディング
面）を狭くしても強度的に強いものとしている。The lead frame 130 used in the semiconductor device 100 of the first embodiment is made of 42% nickel-iron alloy as a material, and has a shape as shown in FIG. Lead frame 1
30A is used, and the inner lead portion 13 formed thinner than the thickness of the terminal pillar portion 133 and other portions.
Has 1. The dam bar 136 serves as a dam for resin sealing. Although the lead frame 130A having a shape as shown in FIG. 9A and processed by etching has been used in this embodiment, it is finally unnecessary except for the inner lead portion 131 and the terminal pillar portion 133. Because it is
The shape is not particularly limited. Inner lead 13
The thickness t of No. 1 is 40 μm, and the thickness t 0 other than the inner lead portion 131 is 0.15 mm, which is the same as the thickness of the lead frame material. The plate thickness other than the inner lead portion 131 is 0.
Not only 15 mm but thinner 0.125 m to 0.50 mm
It may be a degree. The inner lead pitch is 0.12
The pitch is as narrow as mm so that it can cope with multi-terminals of semiconductor devices. Second surface 1 of inner lead portion 131
31Ab is flat and has a shape that facilitates wire bonding, and as shown in FIG.
c, the fourth surface 131Ad has a shape recessed toward the inner lead side, and is strong in strength even if the second surface 131Ab (wire bonding surface) is narrowed.

【００１１】本実施例においては、インナーリード１３
１の長さが短かく、インナーリード１３１部にヨレが発
生しずらい為、直接図９（ａ）に示すような、インナー
リード先端がそれぞれ分離された形状のリードフレーム
をエッチング加工にして作製し、これに後述する方法に
より半導体素子を搭載して樹脂封止している。インナー
リード１３１が長く、インナーリード１３１部にヨレを
生じ易い場合には、直接図９（ａ）に示す形状にエッチ
ング加工することは出来ないため、図９（ｃ）（イ）に
示すようにインナーリード先端部を連結部１３１Ｂにて
固定した状態にエッチング加工した後、インナーリード
１３１部を補強テープ１６０で固定し（図９（ｃ）
（ロ））、次いでプレスにて、半導体装置作製の際には
不要の連結部１３１Ｂを除去し、この状態で半導体素子
を搭載して半導体装置を作製する。（図９（ｃ）
（ハ））In this embodiment, the inner lead 13
Since the length of 1 is short and it is difficult for the inner lead 131 to be twisted, the lead frame having a shape in which the inner lead tips are separated as shown in FIG. Then, a semiconductor element is mounted thereon and resin-sealed by the method described later. When the inner lead 131 is long and the inner lead 131 is liable to be twisted, the shape cannot be directly etched into the shape shown in FIG. 9A, and therefore, as shown in FIG. 9C and FIG. After etching the inner lead tip portion with the connecting portion 131B fixed, the inner lead 131 portion is fixed with the reinforcing tape 160 (FIG. 9C).
(B)) Then, by pressing, unnecessary connecting portions 131B are removed when the semiconductor device is manufactured, and a semiconductor element is mounted in this state to manufacture a semiconductor device. (Fig. 9 (c)
(C))

【００１２】次に本実施例１の樹脂封止型半導体装置の
製造方法を図８に基づいて簡単に説明する。先ず、後述
するエッチング加工にて外形加工された、図９（ａ）に
示すリードフレーム１３０Ａを、インナーリード１３１
先端の第２面１３１Ａｂが図８で上になるようにして用
意した。（図８（ａ）） 次いで半導体素子１１０の電極部１１１側の面を図８で
上にして、半導体素子をダイパッド１３５上に搭載、固
定した。（図８（ｂ）） 半導体素子１１０をダイパッド１３５に固定した後、半
導体素子１１０の電極部１１１とインナーリード部１３
１先端の第２面とをワイヤ１２０にてボンデイング接続
した。（図８（ｃ）） 次いで、通常の封止用樹脂１４０で樹脂封止を行った
後、不要なリードフレーム１３０の樹脂１４０面から突
出している部分をプレスにて切断し、端子柱１３３を形
成するとともに端子柱１３３の側面１３３Ｂを形成し
た。（図８（ｄ）） 図９に示すリードフレーム１３０Ａのダムバー１３６、
フレーム部１３７等を除去した。この後、リードフレー
ムの端子柱の外側の面に半球状の半田からなる端子部１
３３Ａを作製して半導体装置を作製した。（図８
（ｅ）） 次いで、保護枠１８０を接着材１９０を介して端子柱の
側面を覆うように、外周全体に設けた。（図８（ｆ）） 尚、保護枠１８０は、半導体装置の補強の為と、端子柱
の側面が露出することにより封止用樹脂と端子柱の隙間
から水分が入り半導体装置にクラックが入り破損してし
まうことがないようにする為に設けたものであるが、必
ずしも必要としない。また、樹脂による封止は所定の型
を用いて行うが、半導体素子１１０のサイズで、且つ、
リードフレームの端子柱の外側の面が若干樹脂から外部
へ突出した状態で封止した。Next, a method of manufacturing the resin-sealed semiconductor device of the first embodiment will be briefly described with reference to FIG. First, the lead frame 130A shown in FIG.
It was prepared so that the second surface 131Ab at the tip end faced upward in FIG. (FIG. 8A) Next, the surface of the semiconductor element 110 on the side of the electrode portion 111 was turned up in FIG. 8, and the semiconductor element was mounted and fixed on the die pad 135. (FIG. 8B) After fixing the semiconductor element 110 to the die pad 135, the electrode portion 111 and the inner lead portion 13 of the semiconductor element 110 are formed.
Bonding connection was made with the wire 120 to the second surface at one end. (FIG. 8C) Next, after performing the resin sealing with the normal sealing resin 140, the portion of the unnecessary lead frame 130 protruding from the resin 140 surface is cut by a press to form the terminal pillar 133. The side surface 133B of the terminal post 133 was formed together with the formation. (FIG. 8 (d)) The dam bar 136 of the lead frame 130A shown in FIG.
The frame portion 137 and the like were removed. Then, the terminal portion 1 made of hemispherical solder is formed on the outer surface of the terminal post of the lead frame.
33A was manufactured to manufacture a semiconductor device. (FIG. 8
(E) Next, the protective frame 180 was provided on the entire outer periphery so as to cover the side surface of the terminal column via the adhesive 190. (FIG. 8 (f)) The protective frame 180 reinforces the semiconductor device, and the side surface of the terminal pillar is exposed, so that moisture enters from the gap between the sealing resin and the terminal pillar and the semiconductor device is cracked. It is provided to prevent damage, but is not always necessary. Further, although the sealing with the resin is performed using a predetermined mold, the size of the semiconductor element 110 and
The lead frame was sealed in a state where the outer surface of the terminal column was slightly projected from the resin to the outside.

【００１３】本発明の半導体装置に用いられるリードフ
レームの製造方法を以下、図にそって説明する。図１１
は、本実施例１の樹脂封止型半導体装置に用いられたリ
ードフレームの製造方法を説明するための、インナーリ
ード先端部を含む要部における各工程断面図であり、こ
こで作製されるリードフレームを示す平面図である図９
（ａ）のＤ１−Ｄ２部の断面部における製造工程図であ
る。図１１中、１１１０はリードフレーム素材、１１２
０Ａ、１１２０Ｂはレジストパターン、１１３０は第一
の開口部、１１４０は第二の開口部、１１５０は第一の
凹部、１１６０は第二の凹部、１１７０は平坦状面、１
１８０はエッチング抵抗層を示す。先ず、４２％ニッケ
ル−鉄合金からなり、厚みが０．１５ｍｍのリードフレ
ーム素材１１１０の両面に、重クロム酸カリウムを感光
剤とした水溶性カゼインレジストを塗布した後、所定の
パターン版を用いて、所定形状の第一の開口部１１３
０、第二の開口部１１４０をもつレジストパターン１１
２０Ａ、１１２０Ｂを形成した。（図１１（ａ）） 第一の開口部１１３０は、後のエッチング加工において
リードフレーム素材１１１０をこの開口部からベタ状に
リードフレーム素材よりも薄肉に腐蝕するためのもの
で、レジストの第二の開口部１１４０は、インナーリー
ド先端部の形状を形成するためのものである。第一の開
口部１１３０は、少なくともリードフレーム１１１０の
ンナーリード先端部形成領域を含むが、後工程におい
て、テーピングの工程や、リードフレームを固定するク
ランプ工程で、ベタ状に腐蝕され部分的に薄くなった部
分との段差が邪魔になる場合があるので、エッチングを
行うエリアはインナーリード先端の微細加工部分だけに
せず大きめにとる必要がある。次いで、液温５７°Ｃ、
比重４８ボーメの塩化第二鉄溶液を用いて、スプレー圧
２．５ｋｇ／ｃｍ2 にて、レジストパターンが形成され
たリードフレーム素材１１１０の両面をエッチングし、
ベタ状（平坦状）に腐蝕された第一の凹部１１５０の深
さｈがリードフレーム部材の約２／３程度に達した時点
でエッチングを止めた。（図１１（ｂ）） 上記第１回目のエッチングにおいては、リードフレーム
素材１１１０の両面から同時にエッチングを行ったが、
必ずしも両面から同時にエッチングする必要はない。本
実施例のように、第１回目のエッチングにおいてリード
フレーム素材１１１０の両面から同時にエッチングする
理由は、両面からエッチングすることにより、後述する
第２回目のエッチング時間を短縮するためで、レジスト
パターン９２０Ｂ側からのみの片面エッチングの場合と
比べ、第１回目エッチングと第２回目エッチングのトー
タル時間が短縮される。次いで、第一の開口部１１３０
側の腐蝕された第一の凹部１５００にエッチング抵抗層
１１８０としての耐エッチング性のあるホットメルト型
ワックス（ザ・インクテエック社製の酸ワックス、型番
ＭＲ−ＷＢ６）を、ダイコータを用いて、塗布し、ベタ
状（平坦状）に腐蝕された第一の凹部１１５０に埋め込
んだ。レジストパターン１１２０Ａ上も該エッチング抵
抗層１１８０に塗布された状態とした。（図１１
（ｃ）） エッチング抵抗層１１８０を、レジストパターン１１２
０Ａ上全面に塗布する必要はないが、第一の凹部１１５
０を含む一部にのみ塗布することは難し為に、図１１
（ｃ）に示すように、第一の凹部１１５０とともに、第
一の開口部１１３０側全面にエッチング抵抗層１１８０
を塗布した。本実施例で使用したエッチング抵抗層１１
８０は、アルカリ溶解型のワックスであるが、基本的に
エッチング液に耐性があり、エッチング時にある程度の
柔軟性のあるものが、好ましく、特に、上記ワックスに
限定されず、ＵＶ硬化型のものでも良い。このようにエ
ッチング抵抗層１１８０をインナーリード先端部の形状
を形成するためのパターンが形成された面側の腐蝕され
た第一の凹部１１５０に埋め込むことにより、後工程で
のエッチング時に第一の凹部１１５０が腐蝕されて大き
くならないようにしているとともに、高精細なエッチン
グ加工に対しての機械的な強度補強をしており、スプレ
ー圧を高く（２．５ｋｇ／ｃｍ2 以上）とすることがで
き、これによりエッチングが深さ方向に進行し易すくな
る。この後、第２回目のエッチングを行い、ベタ状（平
坦状）に腐蝕された第二の凹部１１６０形成面側からリ
ードフレーム素材１１１０をエッチングし、貫通させ、
インナーリード先端部１３１Ａを形成した。（図１１
（ｄ）） 第１回目のエッチング加工にて作製された、リードフレ
ーム面に平行なエッチング形成面は平坦であるが、この
面を挟む２面はインナーリード側にへこんだ凹状であ
る。次いで、洗浄、エッチング抵抗層９８０の除去、レ
ジスト膜（レジストパターン１１２０Ａ、１１２０Ｂ）
の除去を行い、インナーリード先端部１３１Ａが微細加
工された図９（ａ）に示すリードフレーム１３０Ａを得
た。エッチング抵抗層１１８０とレジスト膜（レジスト
パターン１１２０Ａ、１１２Ｂ０）の除去は水酸化ナト
リウム水溶液により溶解除去した。A method of manufacturing a lead frame used in the semiconductor device of the present invention will be described below with reference to the drawings. FIG.
4A to 4C are cross-sectional views of each step in the main part including the tip of the inner lead for explaining the method of manufacturing the lead frame used in the resin-sealed semiconductor device of the first embodiment. FIG. 9 is a plan view showing the frame.
It is a manufacturing-process figure in the cross section of D1-D2 part of (a). In FIG. 11, 1110 is a lead frame material, 112
0A, 1120B are resist patterns, 1130 is a first opening, 1140 is a second opening, 1150 is a first recess, 1160 is a second recess, 1170 is a flat surface, 1
Reference numeral 180 denotes an etching resistance layer. First, after applying a water-soluble casein resist using potassium dichromate as a photosensitizer on both surfaces of a lead frame material 1110 having a thickness of 0.15 mm and made of 42% nickel-iron alloy, a predetermined pattern plate was used. , The first opening 113 having a predetermined shape
0, a resist pattern 11 having a second opening 1140
20A and 1120B were formed. (FIG. 11A) The first opening 1130 is used to corrode the lead frame material 1110 through the opening in a later etching process so as to be solid and thinner than the lead frame material. The opening 1140 is for forming the shape of the tip of the inner lead. The first opening 1130 includes at least a region for forming the inner lead tip of the lead frame 1110, but is corroded in a solid shape and partially thinned in a taping process or a clamp process for fixing the lead frame in a later process. Since there is a case where the step difference with the open portion interferes, it is necessary to make the etching area large rather than only the finely processed portion of the tip of the inner lead. Next, the liquid temperature is 57 ° C,
Using a ferric chloride solution having a specific gravity of 48 Baume, the lead frame material 1110 on which the resist pattern is formed is etched on both sides at a spray pressure of 2.5 kg / cm 2 .
The etching was stopped when the depth h of the first recess 1150, which was corroded into a solid (flat) shape, reached about 2/3 of the lead frame member. (FIG. 11B) In the first etching, the lead frame material 1110 was simultaneously etched from both sides.
It is not always necessary to etch from both sides simultaneously. The reason why the lead frame material 1110 is simultaneously etched from both sides in the first etching as in the present embodiment is that the etching is performed from both sides to shorten the second etching time, which will be described later. Compared with the case of single-sided etching only from the side, the total time of the first etching and the second etching is shortened. Then, the first opening 1130
A hot-melt type wax having etching resistance (an acid wax manufactured by The Inktech Corporation, model number MR-WB6) as an etching resistance layer 1180 is applied to the first corroded first recess 1500 on the side by using a die coater. , And was buried in the first recess 1150 which was corroded into a solid (flat) shape. The resist pattern 1120A was also applied to the etching resistance layer 1180. (FIG. 11
(C)) The etching resistance layer 1180 is formed on the resist pattern 112.
Although it is not necessary to apply it to the entire surface of 0A, the first recess 115
Since it is difficult to apply only to a part including 0, FIG.
As shown in (c), the etching resistance layer 1180 is formed on the entire surface of the first opening 1130 side together with the first recess 1150.
Was applied. Etching resistance layer 11 used in this example
80 is an alkali-soluble wax, but it is preferable that it is basically resistant to an etching solution and has some flexibility during etching. In particular, the wax is not limited to the above wax, and a UV curable wax is also usable. good. As described above, the etching resistance layer 1180 is embedded in the corroded first recess 1150 on the surface side where the pattern for forming the shape of the inner lead tip portion is formed, so that the first recess is formed at the time of etching in a later step. In addition to preventing corrosion of 1150 and making it large, mechanical strength reinforcement for high-definition etching processing enables high spray pressure (2.5 kg / cm 2 or more). As a result, etching becomes easier to proceed in the depth direction. After that, a second etching is performed to etch the lead frame material 1110 from the side where the second recess 1160 is formed which is corroded into a solid (flat) shape, and to penetrate the lead frame material 1110.
The inner lead tip portion 131A was formed. (FIG. 11
(D)) The etched surface parallel to the lead frame surface produced by the first etching process is flat, but the two surfaces sandwiching this surface are concave toward the inner lead. Then, cleaning, removal of the etching resistance layer 980, resist film (resist patterns 1120A, 1120B)
Was removed to obtain a lead frame 130A shown in FIG. 9A in which the inner lead tip portion 131A was finely processed. The etching resistance layer 1180 and the resist film (resist patterns 1120A and 112B0) were removed by dissolution with a sodium hydroxide aqueous solution.

【００１４】上記、図１１に示すリードフレームの製造
方法は、本実施例に用いられる、インナーリード先端部
を薄肉に形成したリードフレームをエッチング加工によ
り製造する方法で、特に、図１に示す、インナーリード
先端の第１面１３１Ａａを薄肉部以外の他の部分と同一
面に、第２面１３１Ａｂと対向させて形成し、且つ、第
３面１３１Ａｃ、第４面１３１Ａｄをインナーリードの
内側に向かって凹んだ形状にするエッチング加工方法で
ある。後述する実施例３の半導体装置のようにバンプを
用いて半導体素子をインナーリードの第２面１３１Ａｂ
に搭載し、インナーリードと電気的に接続する場合に
は、第２面１３１Ａｂをインナーリード側に凹んだ形状
に形成した方がバンプ接続の際の許容度が大きくなる
為、図１２に示すエッチング加工方法が採られる。図１
２に示すエッチング加工方法は、第１回目のエッチング
工程までは、図１１に示す方法と同じであるが、エッチ
ング抵抗層１１８０を第二の凹部１１６０側に埋め込ん
だ後、第一の凹部１１５０側から第２回目のエッチング
を行い、貫通させる点で異なっている。但し、第１回目
のエッチングにて、第二開口部１１４０からのエッチン
グを充分に行っておく。図１２に示すエッチング加工方
法によって得られたリードフレームのインナーリード先
端の断面形状は、図６（ｂ）に示すように、第２面３３
１Ａｂがインナーリード側にへこんだ凹状になる。The method of manufacturing the lead frame shown in FIG. 11 is a method of manufacturing a lead frame used in the present embodiment, in which the inner lead tips are formed to be thin, by etching, particularly, as shown in FIG. The first surface 131Aa at the tip of the inner lead is formed on the same surface as the portion other than the thin portion so as to face the second surface 131Ab, and the third surface 131Ac and the fourth surface 131Ad are directed toward the inner side of the inner lead. It is an etching method that makes a concave shape. A semiconductor element is mounted on the second surface 131Ab of the inner lead by using a bump as in a semiconductor device of Example 3 described later.
If the second surface 131Ab is recessed toward the inner lead side, the tolerance at the time of bump connection becomes larger, so that the etching shown in FIG. The processing method is adopted. FIG.
The etching processing method shown in FIG. 2 is the same as the method shown in FIG. 11 up to the first etching step, but after the etching resistance layer 1180 is embedded in the second concave portion 1160 side, the first concave portion 1150 side is formed. The second difference is that the second etching is performed and the holes are penetrated. However, the etching from the second opening 1140 is sufficiently performed in the first etching. As shown in FIG. 6B, the cross-sectional shape of the inner lead tip of the lead frame obtained by the etching method shown in FIG.
1Ab has a concave shape that is recessed toward the inner lead side.

【００１５】尚、上記図１１、図１２に示すエッチング
加工方法のように、エッチングを２段階にわけて行うエ
ッチング加工方法を、一般には２段エッチング加工方法
といっており、微細加工に有利な加工方法である。本発
明に用いた図９（ａ）に示す、リードフレーム１３０Ａ
の製造においては、２段エッチング加工方法と、パター
ン形状を工夫することにより部分的にリードフレーム素
材を薄くしながら外形加工をする方法とが伴行して採ら
れており、リードフレーム素材を薄くした部分において
は、特に、微細な加工ができるようにしている。図１
１、図１２に示す、上記の方法においては、インナーリ
ード先端部１３１Ａの微細化加工は、第二の凹部１１６
０の形状と、最終的に得られるインナーリード先端部の
厚さｔに左右されるもので、例えば、板厚ｔを５０μｍ
まで薄くすると、図１１（ｅ）に示す、平坦幅Ｗ１を１
００μｍとして、インナーリード先端部ピッチｐが０．
１５ｍｍまで微細加工可能となる。板厚ｔを３０μｍ程
度まで薄くし、平坦幅Ｗ１を７０μｍ程度とすると、イ
ンナーリード先端部ピッチｐが０．１２ｍｍ程度まで微
細加工ができるが、板厚ｔ、平坦幅Ｗ１のとり方次第で
はインナーリード先端部ピッチｐは更に狭いピッチまで
作製が可能となる。ちなみに、インナーリード先端部ピ
ッチｐを０．０８ｍｍ、板厚２５μｍで平坦幅４０μｍ
程度が確保できる。Incidentally, an etching processing method in which etching is divided into two stages like the etching processing method shown in FIGS. 11 and 12 is generally called a two-step etching processing method, which is advantageous for fine processing. It is a processing method. The lead frame 130A used in the present invention and shown in FIG.
In the manufacturing of, the two-step etching processing method and the method of externally processing while partially thinning the lead frame material by devising the pattern shape are adopted together, and the lead frame material is made thin. In particular, fine processing can be performed in the portion that is formed. FIG.
In the above method shown in FIG. 1 and FIG. 12, the fine processing of the inner lead tip portion 131A is performed by the second recess 116.
It depends on the shape of 0 and the thickness t of the finally obtained inner lead tip. For example, the plate thickness t is 50 μm.
If it is made thin, the flat width W1 shown in FIG.
When the inner lead tip pitch p is 0.
Fine processing is possible up to 15 mm. If the plate thickness t is reduced to about 30 μm and the flat width W1 is set to about 70 μm, fine processing can be performed to the inner lead tip end pitch p of about 0.12 mm. However, depending on how to set the plate thickness t and the flat width W1, the inner lead The tip pitch p can be made to a narrower pitch. By the way, the inner lead tip pitch p is 0.08 mm, the plate thickness is 25 μm, and the flat width is 40 μm.
The degree can be secured.

【００１６】このようにエッチング加工にてリードフレ
ームを作製する際、インナーリードの長さが短かい場合
等、製造工程でインナーリードのヨレが発生しにくい場
合には、直接図９（ａ）に示す形状のリードフレームエ
ッチング加工にて得るが、インナーリードの長さが長
く、インナーリードにヨレが発生し易い場合には、図９
（ｃ）（イ）に示ように、インナーリード先端部から連
結部１３１Ｂを設け、インナーリード先端部同士を繋げ
た形状にして形成したものを得て、半導体装置作製には
不必要な連結部１３１Ｂをプレス等により切断除去して
図９（ａ）に示す形状を得る。尚、前述のように、図９
（ｃ）（イ）に示すものを切断し、図９（ａ）に示す形
状にする際には、図９（ｃ）（ロ）に示すように、通
常、補強のため補強テープ１６０（ポリイミドテープ）
を使用する。図９（ｃ）（ロ）の状態で、プレス等によ
り連結部１３１Ｂを切断除去するが、半導体素子は、テ
ープをつけた状態のままで、リードフレームに搭載さ
れ、そのまま樹脂脂封止される。尚、Ｅ１１−Ｅ１２は
切断部分を示すものである。When the lead frame is manufactured by the etching process as described above, if the inner lead is less likely to be twisted in the manufacturing process, such as when the inner lead is short in length, the structure shown in FIG. Although it is obtained by the lead frame etching process of the shape shown, if the inner lead is long and the inner lead is apt to be twisted,
(C) As shown in (a), a connecting portion 131B is provided from the inner lead tip portion to obtain a shape in which the inner lead tip portions are connected to each other, and a connecting portion unnecessary for manufacturing a semiconductor device is obtained. 131B is cut and removed by a press or the like to obtain the shape shown in FIG. As described above, FIG.
When cutting the shape shown in (c) and (a) into the shape shown in FIG. 9 (a), as shown in FIGS. 9 (c) and (b), the reinforcing tape 160 (polyimide) is usually used for reinforcement. tape)
To use. In the state shown in FIGS. 9C and 9B, the connecting portion 131B is cut and removed by a press or the like, but the semiconductor element is mounted on the lead frame with the tape still attached, and is sealed with resin as it is. . In addition, E11-E12 shows a cut part.

【００１７】本実施例１の半導体装置に用いられたリー
ドフレームのインナーリード部１３１の断面形状は、図
１３（イ）（ａ）に示すようになっており、エッチング
平坦面１３１Ａｂ側の幅Ｗ１はほぼ平坦で反対側の面の
幅Ｗ２より若干大きくくなっており、Ｗ１、Ｗ２（約１
００μｍ）ともこの部分の板厚さ方向中部の幅Ｗよりも
大きくなっている。このようにインリーリード先端部の
両面は広くなった断面形状であるため、どちらの面を用
いても半導体素子（図示せず）とインナーリード先端部
１３１Ａとワイヤ１２０Ａ、１２０Ｂによる結線（ボン
デイング）がし易いものとなっているが、本実施例の場
合はエッチング面側（図１３（ロ）（ａ））をボンデイ
ング面としている。図中、１３１Ａｂはエッチング加工
による平坦面、１３１Ａａはリードフレーム素材面、１
２１Ａ、１２１Ｂはめっき部である。エッチング平坦状
面がアラビの無い面であるため、図１３（ロ）の（ａ）
の場合は、特に結線（ボンデイング）適性が優れる。図
１３（ハ）は図１４に示す加工方法にて作製されたリー
ドフレームのインナーリード先端部１３３１Ｂと半導体
素子（図示せず）との結線（ボンデイング）を示すもの
であるが、この場合もインナーリード先端部１３３１Ｂ
の両面は平坦ではあるが、この部分の板厚方向の幅に比
べ大きくとれない。また両面ともリードフレーム素材面
である為、結線（ボンデイング）適性は本実施例のエッ
チング平坦面より劣る。図１３（ニ）はプレス（コイニ
ング）によりインナーリード先端部を薄肉化した後にエ
ッチング加工によりインナーリード先端部１３３１Ｃ、
１３３１Ｄを加工したものの、半導体素子（図示せず）
との結線（ボンデイング）を示したものであるが、この
場合はプレス面側が図に示すように平坦になっていない
ため、どちらの面を用いて結線（ボンデイング）して
も、図１１（ニ）の（ａ）、（ｂ）に示すように結線
（ボンデイング）の際に安定性が悪く品質的にも問題と
なる場合が多い。尚、１３３１Ａｂはコイニング面であ
るThe sectional shape of the inner lead portion 131 of the lead frame used in the semiconductor device of the first embodiment is as shown in FIG. 13 (a) (a), and the width W1 on the etching flat surface 131Ab side. Is almost flat and slightly larger than the width W2 of the opposite surface, and W1, W2 (about 1
(00 μm) is larger than the width W of the central portion in the plate thickness direction of this portion. As described above, since both sides of the tip of the lead-in lead have a widened cross-sectional shape, whichever surface is used, the semiconductor element (not shown), the tip 131A of the inner lead and the wires 120A and 120B are connected (bonded). Although it is easy to remove, in the case of this embodiment, the etching surface side (FIG. 13 (b) (a)) is used as the bonding surface. In the figure, 131Ab is a flat surface by etching, 131Aa is a lead frame material surface, 1
21A and 121B are plated parts. Since the flat etching surface is a surface free from arabic, (a) in FIG.
In the case of, the suitability for connection (bonding) is particularly excellent. FIG. 13C shows a connection (bonding) between the inner lead tip portion 1331B of the lead frame manufactured by the processing method shown in FIG. 14 and the semiconductor element (not shown). Lead tip 1331B
Although both sides of are flat, they cannot be made wider than the width of this portion in the plate thickness direction. Further, since both surfaces are lead frame material surfaces, the suitability for connection (bonding) is inferior to the flat etching surface of this embodiment. FIG. 13D shows an inner lead tip portion 1331C formed by etching after thinning the inner lead tip portion by pressing (coining).
A semiconductor element (not shown), although 1331D is processed
This shows the connection (bonding) with the wire. However, in this case, since the press surface side is not flat as shown in the figure, no matter which surface is used for the connection (bonding), As shown in (a) and (b) of), the stability is poor at the time of connection (bonding), which often causes a problem in terms of quality. Note that 1331 Ab is a coining surface.

【００１８】次に実施例１の樹脂封止型半導体装置の変
形例を挙げる。図３（ａ）〜図３（ｅ）は、それぞれ、
は実施例１の樹脂封止型半導体装置の変形例の断面図で
ある。図３（ａ）に示す変形例の半導体装置は、実施例
１の半導体装置とは、ダイパッド１３５の位置が異なる
もので、ダイパッド部１３５が外部に露出している。ダ
イパッド部１３５が外部に露出していることにより、実
施例１に比べ、熱の発散性が優れている。図３（ｂ）に
示す変形例の半導体装置も、ダイパッド部１３５が外部
に露出させているものであり、実施例１に比べ、熱の発
散性が優れている。実施例１や図３（ａ）に示す変形例
とは、半導体素子１１０の向きが異なり、ワイヤボンデ
イング面をリードフレームの第１面に設けている。図３
（ｃ）、図３（ｄ）、図３（ｅ）に示す変形例は、それ
ぞれ実施例１、図３（ａ）に示す変形例、図３（ｂ）に
示す変形例において、半球状の半田からなる端子部を設
けず、端子柱の面を直接端子部として用いているもので
あり、製造工程を簡略した構造となっている。Next, a modification of the resin-encapsulated semiconductor device of the first embodiment will be described. 3A to 3E respectively show
FIG. 6 is a cross-sectional view of a modified example of the resin-encapsulated semiconductor device of Example 1. The semiconductor device of the modification shown in FIG. 3A is different in the position of the die pad 135 from the semiconductor device of the first embodiment, and the die pad portion 135 is exposed to the outside. Since the die pad portion 135 is exposed to the outside, heat dissipation is superior to that in the first embodiment. Also in the semiconductor device of the modified example shown in FIG. 3B, the die pad portion 135 is exposed to the outside, and the heat dissipation property is superior to that of the first embodiment. The orientation of the semiconductor element 110 is different from that of the first embodiment and the modification shown in FIG. 3A, and the wire bonding surface is provided on the first surface of the lead frame. FIG.
The modified examples shown in (c), FIG. 3 (d), and FIG. 3 (e) are hemispherical in the modified example shown in Example 1, FIG. 3 (a), and the modified example shown in FIG. 3 (b), respectively. The terminal portion made of solder is not provided, and the surface of the terminal pillar is directly used as the terminal portion, and the manufacturing process is simplified.

【００１９】次いで、実施例２の樹脂封止型半導体装置
を挙げる。図４（ａ）は実施例２の樹脂封止型半導体装
置の断面図であり、図４（ｂ）は図４（ａ）のＡ３−Ａ
４におけるインナーリード部の断面図で、図４（ｃ）は
図４（ａ）のＢ３−Ｂ４における端子柱部の断面図であ
る。尚、実施例２の半導体装置の外観は実施例１とほぼ
同じとなる為、図は省略した。図３中、２００は半導体
装置、２１０は半導体素子、２１１は電極部（パッ
ド）、２２０はワイヤ、２３０はリードフレーム、２３
１はインナーリード、２３１Ａａは第１面、２３１Ａｂ
は第２面、２３１Ａｃは第３面、２３１Ａｄは第４面、
２３３は端子柱部、２３３Ａは端子部、２３３Ｂは側
面、２３３Ｓは上端面、２４０は封止用樹脂、２７０は
補強固定用テープある。本実施例２の半導体装置におい
ては、リードフレーム２３０はダイパッドを持たないも
ので、半導体素子２１０はインナーリード２３１ととも
に補強固定用テープ２７０により固定されており、半導
体素子２１０は、半導体素子の電極部（パッド）２１１
側はワイヤ２２０により、インナーリード２３１の第２
面２３１Ａｂと結線されている。本実施例２の場合も、
実施例１場合と同様に、半導体装置２００と外部回路と
の電気的な接続は、端子柱２３３の先端部に設けられた
半球状の半田からなる端子部２３３Ａを介してプリント
基板等へ搭載されることにより行われる。Next, the resin-sealed semiconductor device of the second embodiment will be described. FIG. 4A is a cross-sectional view of the resin-sealed semiconductor device of the second embodiment, and FIG. 4B is A3-A of FIG.
4C is a cross-sectional view of the inner lead portion, and FIG. 4C is a cross-sectional view of the terminal pillar portion at B3-B4 in FIG. 4A. The external appearance of the semiconductor device of the second embodiment is almost the same as that of the first embodiment, so the drawing is omitted. In FIG. 3, 200 is a semiconductor device, 210 is a semiconductor element, 211 is an electrode portion (pad), 220 is a wire, 230 is a lead frame, and 23.
1 is an inner lead, 231Aa is the first surface, 231Ab
Is the second surface, 231Ac is the third surface, 231Ad is the fourth surface,
233 is a terminal pillar portion, 233A is a terminal portion, 233B is a side surface, 233S is an upper end surface, 240 is a sealing resin, and 270 is a reinforcing and fixing tape. In the semiconductor device according to the second embodiment, the lead frame 230 does not have a die pad, the semiconductor element 210 is fixed together with the inner lead 231 by the reinforcing fixing tape 270, and the semiconductor element 210 is the electrode portion of the semiconductor element. (Pad) 211
The second side of the inner lead 231 is connected to the second side by the wire 220.
It is connected to the surface 231Ab. Also in the case of the second embodiment,
As in the case of the first embodiment, the electrical connection between the semiconductor device 200 and the external circuit is mounted on a printed circuit board or the like via the terminal portion 233A made of hemispherical solder provided at the tip of the terminal pillar 233. It is done by

【００２０】また、本実施例２の半導体装置は、図１０
（ａ）、１０（ｂ）に示す、ダイパッドを持たない、エ
ッチングにより外形加工されたリードフレーム２３０Ａ
を用いたもので、その製造方法は実施例１とほぼ同じ工
程であるが、異なる点は、実施例１の場合には半導体素
子をインナーリードに固定した状態でワイヤボンデイン
グを行い、樹脂封止しているのに対し、本実施例２の場
合には、半導体素子２１０をインナーリード２３１とと
もに補強固定用テープ２７０上に固定した状態で、ワイ
ヤボンデイング工程を行い、樹脂封止している点であ
る。尚、樹脂封止後のプレスによる不要部分の切断、端
子部の形成は、実施例１と同様である。図１０（ａ）に
示すリードフレーム２３０Ａを得るには、図９（ａ）に
示すリードフレーム１３０Ａを得た場合と同様にして得
る。即ち、図１０（ｃ）（イ）に示すエッチング加工さ
れた後のものを切断し、図１０（ａ）に示す形状にする
る。この際、図１０（ｃ）（ロ）に示すように、通常、
補強のため補強テープ２６０（ポリイミドテープ）を使
用する。In addition, the semiconductor device of the second embodiment is shown in FIG.
(A), (b) shown in FIG. 10 (b), the lead frame 230A having no die pad and processed by etching
The manufacturing method is almost the same as that of the first embodiment, except that in the first embodiment, the semiconductor element is fixed to the inner lead, wire bonding is performed, and resin sealing is performed. On the other hand, in the case of the second embodiment, the wire bonding process is performed in the state where the semiconductor element 210 is fixed on the reinforcing fixing tape 270 together with the inner lead 231, and the resin sealing is performed. is there. Incidentally, the cutting of the unnecessary portion and the formation of the terminal portion by the press after the resin sealing is the same as in the first embodiment. To obtain the lead frame 230A shown in FIG. 10A, the lead frame 230A shown in FIG. 9A is obtained in the same manner. That is, the material after the etching process shown in FIGS. 10C and 10A is cut into the shape shown in FIG. At this time, as shown in FIG.
A reinforcing tape 260 (polyimide tape) is used for reinforcement.

【００２１】図５（ａ）〜図５（ｃ）は、実施例２の半
導体装置の変形例半導体装置の断面図である。図５
（ａ）に示す変形例半導体装置は、半導体素子の向きが
図５（ａ）で、電極部を有する面を下側にしている点、
およびワイヤボンデイング面をリードフレームの第１面
に設けている点で実施例２の半導体装置と異なる。図５
（ｂ）、図５（ｃ）に示す変形例半導体装置は、それぞ
れ実施例２の半導体装置、図５（ａ）に示す変形例の半
導体装置において、半球状の半田からなる端子部を設け
ず、端子柱の面を直接端子部として用いているものであ
る。保護枠がなく、端子柱２３３の側面２３３Ｂを側面
に露出している為、テスタ等での信号のチエックがし易
い構造となっている。FIGS. 5A to 5C are cross-sectional views of a modified semiconductor device of the second embodiment. FIG.
In the modified semiconductor device shown in (a), the orientation of the semiconductor element is as shown in FIG. 5 (a), and the surface having the electrode portion is on the lower side.
Also, the semiconductor device according to the second embodiment is different in that the wire bonding surface is provided on the first surface of the lead frame. FIG.
The modified semiconductor devices shown in (b) and (c) of FIG. 5 are the same as those of the semiconductor device of Example 2 and the modified semiconductor device shown in (a) of FIG. The surface of the terminal pillar is directly used as the terminal portion. Since there is no protective frame and the side surface 233B of the terminal column 233 is exposed to the side surface, the structure is such that a signal can be easily checked by a tester or the like.

【００２２】次いで、実施例３の樹脂封止型半導体装置
を挙げる。図６（ａ）は実施例３の樹脂封止型半導体装
置の断面図であり、図６（ｂ）は図６（ａ）のＡ５−Ａ
６におけるインナーリード部の断面図で、図６（ｃ）は
図６（ａ）のＢ５−Ｂ６における端子柱部の断面図であ
る。尚、実施例３の半導体装置の外観も実施例１とほぼ
同じとなる為、図は省略した。図６中、３００は半導体
装置、３１０は半導体素子、３１２はバンプ、３３０は
リードフレーム、３３１はインナーリード、３３１Ａａ
は第１面、３３１Ａｂは第２面、３３１Ａｃは第３面、
３３１Ａｄは第４面、３３３は端子柱部、３３３Ａは端
子部、３３３Ｂは側面、３３３Ｓはは上端面、３４０は
封止用樹脂、３５０は補強用テープである。本実施例３
の半導体装置においては、半導体素子３１０は、バンプ
３１１によりインナーリード３３１の第２面３３１Ａｂ
に固定され、電気的にインナーリード３３１と接続して
いる。リードフレーム３３０は、図１０（ａ）、図１０
（ｂ）に示す外形のもので、図１１に示すエッチング加
工により作製されたものを用いている。図１３（イ）
（ｂ）に示すように、インナーリード３３１の両面の幅
Ｗ１Ａ、Ｗ２Ａ（約１００μｍ）ともこの部分の板厚さ
方向中部の幅ＷＡよりも大きくなっており、且つ、イン
ナーリード３３１の第２面３３１Ａｂはインナーリード
の内側に向かって凹んだ形状で、第１面３３１Ａａが平
坦であることより、インナーリードの微細化に対応でき
るとともに、インナーリード３３１の第２面３３１Ａｂ
において、半導体素子とバンプにて電気的に接続する際
には、図１３（ロ）（ｂ）のように接続がし易いものと
している。また、本実施例３の場合も、実施例１や実施
例２の場合と同様に、半導体装置３００と外部回路との
電気的な接続は、端子柱３３３先端部に設けられた半球
状の半田からなる端子部３３３Ａを介してプリント基板
等へ搭載されることにより行われる。Next, the resin-sealed semiconductor device of the third embodiment will be described. FIG. 6A is a cross-sectional view of the resin-sealed semiconductor device of the third embodiment, and FIG. 6B is A5-A of FIG. 6A.
6 is a cross-sectional view of the inner lead portion in FIG. 6, and FIG. 6C is a cross-sectional view of the terminal pillar portion in B5-B6 of FIG. 6A. The external appearance of the semiconductor device of the third embodiment is almost the same as that of the first embodiment, so the drawing is omitted. In FIG. 6, 300 is a semiconductor device, 310 is a semiconductor element, 312 is a bump, 330 is a lead frame, 331 is an inner lead, 331Aa.
Is the first surface, 331Ab is the second surface, 331Ac is the third surface,
331Ad is a fourth surface, 333 is a terminal pillar portion, 333A is a terminal portion, 333B is a side surface, 333S is an upper end surface, 340 is a sealing resin, and 350 is a reinforcing tape. Example 3
In the semiconductor device of No. 3, the semiconductor element 310 has the second surface 331Ab of the inner lead 331 by the bump 311.
And is electrically connected to the inner lead 331. The lead frame 330 is shown in FIGS.
The outer shape shown in (b) is used, which is produced by the etching process shown in FIG. Fig. 13 (a)
As shown in (b), both widths W1A and W2A (about 100 μm) of both surfaces of the inner lead 331 are larger than the width WA of the middle portion in the plate thickness direction of this portion, and the second surface of the inner lead 331 is 331Ab has a shape that is recessed toward the inner side of the inner lead, and the first surface 331Aa is flat, which makes it possible to respond to miniaturization of the inner lead and the second surface 331Ab of the inner lead 331.
In the case of electrically connecting the semiconductor element with the bump, the connection is made easy as shown in FIGS. 13B and 13B. Also in the case of the third embodiment, as in the case of the first and second embodiments, the semiconductor device 300 and the external circuit are electrically connected to each other by using a hemispherical solder provided at the tip of the terminal column 333. It is carried out by mounting it on a printed circuit board or the like through a terminal portion 333A consisting of.

【００２３】実施例３の半導体装置は、実施例１の半導
体装置の場合とは異なり、図１２に示すエッチングによ
り外形加工されたリードフレームを用いたものである
が、半導体装置自体の作製方法はほぼ同じ工程である。
異なる点は、実施例１の半導体装置の場合には半導体素
子をインナーリードに固定した状態でワイヤボンデイン
グを行い、樹脂封止しているのに対し、本実施例３の半
導体装置の場合には、半導体素子３１０をインナーリー
ド３３１にバンプを介して固定して電気的に接続した状
態で樹脂封止している点である。尚、樹脂封止後のプレ
スによる不要部分の切断、端子部の形成は、実施例１の
半導体装置の場合と同じである。Unlike the semiconductor device of the first embodiment, the semiconductor device of the third embodiment uses a lead frame whose outer shape is processed by etching as shown in FIG. It is almost the same process.
The difference is that in the case of the semiconductor device of the first embodiment, wire bonding is performed with the semiconductor element fixed to the inner lead and resin sealing is performed, whereas in the case of the semiconductor device of the third embodiment, The point is that the semiconductor element 310 is fixed to the inner lead 331 via a bump and electrically connected, and is resin-sealed. Incidentally, the cutting of the unnecessary portion and the formation of the terminal portion by pressing after the resin sealing are the same as in the case of the semiconductor device of the first embodiment.

【００２４】図６（ｄ）は、実施例３の半導体装置の変
形例半導体装置の断面図である。図６（ｄ）に示す変形
例半導体装置は、実施例３の半導体装置において、半球
状の半田からなる端子部を設けず、端子柱の面を直接端
子部として用いているものである。保護枠を無くして端
子柱３３３の側面３３３Ｂを側面に露出している為、テ
スタ等での信号のチエックがし易い構造となっている。
更にこの端子柱３３３の側面３３３Ｂを傾斜させると上
部からチエックし易い構造とすることもできる。FIG. 6D is a sectional view of a modified semiconductor device of the semiconductor device of the third embodiment. The modified semiconductor device shown in FIG. 6D is the same as the semiconductor device of the third embodiment, except that the terminal portion made of hemispherical solder is not provided and the surface of the terminal pillar is directly used as the terminal portion. Since the side surface 333B of the terminal column 333 is exposed to the side surface without the protective frame, the structure is such that a signal can be easily checked by a tester or the like.
Further, by tilting the side surface 333B of the terminal column 333, it is possible to make the structure in which it is easy to check from above.

【００２５】次いで、実施例４の樹脂封止型半導体装置
を挙げる。図７（ａ）は実施例４の樹脂封止型半導体装
置の断面図であり、図７（ｂ）は図７（ａ）のＡ７−Ａ
８におけるインナーリード部の断面図で、図６（ｃ）は
図６（ａ）のＢ７−Ｂ８における端子柱部の断面図であ
る。尚、実施例４の半導体装置の外観も実施例１とほぼ
同じとなる為、図は省略した。図７中、４００は半導体
装置、４１０は半導体素子、４１１はパッド、４３０は
リードフレーム、４３１はインナーリード、４３１Ａａ
は第１面、４３１Ａｂは第２面、４３１Ａｃは第３面、
４３１Ａｄは第４面、４３３は端子柱部、４３３Ａは端
子部、４３３Ｂは側面、４３３Ｓは上端面、４４０は封
止用樹脂、４７０は絶縁性接着材である。本実施例の場
合は、半導体素子４１０のパッド３１１側の面をインナ
ーリード３３１の第２面４３１Ａｂに絶縁性接着材４７
０を介して固定し、パッド４１１とインナーリード４３
１の第１面４３１Ａａとをワイヤ４２０にて電気的に結
線したものである。使用するリードフレームは実施例３
等と同じ、図１０（ａ）、図１０（ｂ）に示す外観形状
のものを使用している。また、本実施例４の場合も、実
施例１や実施例２の場合と同様に、半導体装置４００と
外部回路との電気的な接続は、端子柱３３３先端部に設
けられた半球状の半田からなる端子部４３３Ａを介して
プリント基板等へ搭載されることにより行われる。Next, the resin-sealed semiconductor device of the fourth embodiment will be described. FIG. 7A is a cross-sectional view of the resin-sealed semiconductor device of Example 4, and FIG. 7B is A7-A of FIG. 7A.
6 is a cross-sectional view of the inner lead portion of FIG. 8, and FIG. 6C is a cross-sectional view of the terminal pillar portion taken along line B7-B8 of FIG. 6A. The external appearance of the semiconductor device of the fourth embodiment is almost the same as that of the first embodiment, and therefore the drawing is omitted. In FIG. 7, 400 is a semiconductor device, 410 is a semiconductor element, 411 is a pad, 430 is a lead frame, 431 is an inner lead, 431Aa.
Is the first surface, 431Ab is the second surface, 431Ac is the third surface,
431Ad is a fourth surface, 433 is a terminal pillar portion, 433A is a terminal portion, 433B is a side surface, 433S is an upper end surface, 440 is a sealing resin, and 470 is an insulating adhesive material. In the case of this embodiment, the surface of the semiconductor element 410 on the side of the pad 311 is attached to the second surface 431Ab of the inner lead 331 as the insulating adhesive 47.
0 through the pad 411 and the inner lead 43
The first surface 431Aa of No. 1 is electrically connected by the wire 420. The lead frame used in Example 3
The same external shape as shown in FIGS. 10 (a) and 10 (b) is used. Further, also in the case of the fourth embodiment, as in the case of the first and second embodiments, the semiconductor device 400 and the external circuit are electrically connected to each other by using a hemispherical solder provided at the tip of the terminal column 333. It is performed by being mounted on a printed circuit board or the like through a terminal portion 433A composed of.

【００２６】図７（ｄ）は、実施例４の半導体装置の変
形例半導体装置の断面図である。図７（ｄ）に示す変形
例半導体装置は、実施例４の半導体装置において、半球
状の半田からなる端子部を設けず、端子柱の面を直接端
子部として用いているものである。保護枠を無くして端
子柱４３３の側面４３３Ｂを側面に露出している為、テ
スタ等での信号のチエックがし易い構造となっている。FIG. 7D is a sectional view of a modified semiconductor device of the semiconductor device of the fourth embodiment. The modified semiconductor device shown in FIG. 7D is the same as the semiconductor device of the fourth embodiment, except that the terminal portion made of hemispherical solder is not provided and the surface of the terminal pillar is directly used as the terminal portion. Since the side surface 433B of the terminal column 433 is exposed to the side surface without the protective frame, the structure is such that a signal is easily checked by a tester or the like.

【００２７】[0027]

【発明の効果】本発明の樹脂封止型半導体装置は、上記
のように、リードフレームを用いた樹脂封止型半導体装
置において、多端子化に対応でき、且つ、従来の図１３
（ｂ）に示すアウターリードを持つリードフレームを用
いた場合のようにダムバーのカット工程や、ダムバーの
曲げ工程を必要としない、即ち、アウターリードのスキ
ューの問題や、平坦性（コープラナリティー）の問題を
皆無とできる半導体装置の提供を可能としている。ま
た、ＱＦＰやＢＧＡに比べるとパッケージ内部の配線長
が短かくなるため、寄生容量が小さくなり伝搬遅延時間
を短くすることを可能にしている。As described above, the resin-encapsulated semiconductor device of the present invention is capable of coping with multi-terminals in the resin-encapsulated semiconductor device using the lead frame, and has the conventional structure shown in FIG.
There is no need for a dam bar cutting step or a dam bar bending step as in the case of using a lead frame having outer leads shown in (b), that is, outer lead skew problems and flatness (coplanarity). It is possible to provide a semiconductor device that can eliminate the above problem. Further, since the wiring length inside the package is shorter than that of QFP or BGA, the parasitic capacitance is reduced and the propagation delay time can be shortened.

【図面の簡単な説明】[Brief description of drawings]

【図１】実施例１の樹脂封止型半導体装置の断面図FIG. 1 is a cross-sectional view of a resin-encapsulated semiconductor device according to a first embodiment.

【図２】実施例１の樹脂封止型半導体装置の斜視図及び
下面図FIG. 2 is a perspective view and a bottom view of the resin-encapsulated semiconductor device according to the first embodiment.

【図３】実施例１の樹脂封止型半導体装置の変形例の図FIG. 3 is a diagram of a modification of the resin-encapsulated semiconductor device according to the first embodiment.

【図４】実施例２の樹脂封止型半導体装置の断面図FIG. 4 is a cross-sectional view of a resin-sealed semiconductor device of Example 2.

【図５】実施例２の樹脂封止型半導体装置の変形例の図FIG. 5 is a diagram of a modification of the resin-encapsulated semiconductor device according to the second embodiment.

【図６】実施例３の樹脂封止型半導体装置の断面図FIG. 6 is a sectional view of a resin-encapsulated semiconductor device according to a third embodiment.

【図７】実施例４の樹脂封止型半導体装置の断面図FIG. 7 is a sectional view of a resin-encapsulated semiconductor device of Example 4.

【図８】実施例１の樹脂封止型半導体装置の作製工程を
説明するための図8A and 8B are views for explaining a manufacturing process of the resin-sealed semiconductor device according to the first embodiment.

【図９】本発明の樹脂封止型半導体装置に用いられるリ
ードフレームの図FIG. 9 is a diagram of a lead frame used in the resin-sealed semiconductor device of the present invention.

【図１０】本発明の樹脂封止型半導体装置に用いられる
リードフレームの図FIG. 10 is a diagram of a lead frame used in the resin-sealed semiconductor device of the present invention.

【図１１】本発明の樹脂封止型半導体装置に用いられる
リードフレームの作製方法を説明するための図FIG. 11 is a diagram illustrating a method for manufacturing a lead frame used in the resin-sealed semiconductor device of the present invention.

【図１２】本発明の樹脂封止型半導体装置に用いられる
リードフレームの作製方法を説明するための図FIG. 12 is a diagram for explaining a method for manufacturing a lead frame used in the resin-encapsulated semiconductor device of the present invention.

【図１３】インナーリード先端部でのワイボンデイング
の結線状態を示す図FIG. 13 is a diagram showing a wire bonding state at the tip of the inner lead.

【図１４】従来のリードフレームのエッチング製造工程
を説明するための図FIG. 14 is a view for explaining a conventional lead frame etching manufacturing process.

【図１５】樹脂封止型半導体装置及び単層リードフレー
ムの図FIG. 15 is a diagram of a resin-sealed semiconductor device and a single-layer lead frame.

【符号の説明】[Explanation of symbols]

１００、２００、３００、４００ 樹
脂封止型半導体装置 １１０、２１０、３１０、４１０ 半
導体素子 １１１、２１１、４１１ 電
極（パッド） ３１２ バ
ンプ １２０、２２０、４２０ ワ
イヤ １２０Ａ、１２０Ｂ ワ
イヤ １２１Ａ、１２１Ｂ め
っき部 １３０、２３０、３３０、４３０ リ
ードフレーム １３１、２３１、３３１、４３１ イ
ンナーリード １３１Ａａ、２３１Ａａ、３３１Ａａ、４３１Ａａ 第
１面 １３１Ａｂ、２３１Ａｂ、３３１Ａｂ、４３１Ａｂ 第
２面 １３１Ａｃ、２３１Ａｃ、３３１Ａｃ、４３１Ａｃ 第
３面 １３１Ａｄ、２３１Ａｄ、３３１Ａｄ、４３１Ａｄ 第
４面 １３１Ｂ 連
結部 １３３、２３３、３３３、４３３ 端
子柱 １３３Ａ、２３３Ａ、３３３Ａ、４３３Ａ 端
子部 １３３Ｂ、２３３Ｂ、３３３Ｂ、４３３Ｂ 側
面 １３３Ｓ、２３３Ｓ、３３３Ｓ、４３３Ｓ 上
端面 １４０、２４０、３４０、４４０ 封
止用樹脂 １８０ 保
護枠 １９０ 接
着材 ２６０ 補
強用テープ ２７０ 補
強固定用テープ ３５０ 補
強用テープ ４７０ 絶
縁性接着材 １１１０ リ
ードフレーム素材 １１２０Ａ、１１２０Ｂ レ
ジストパターン １１３０ 第
一の開口部 １１４０ 第
二の開口部 １１５０ 第
一の凹部 １１６０ 第
二の凹部 １１７０ 平
坦状面 １１８０ エ
ッチング抵抗層 １３２０Ｂ、１３２０Ｃ、１３２０Ｄ ワ
イヤ １３２１Ｂ、１３２１Ｃ、１３２１Ｄ め
っき部 １３３１Ｂ、１３３１Ｃ、１３３１Ｄ イ
ンナーリード先端部 １３３１Ａａ リ
ードフレーム素材面 １３３１Ａｂ コ
イニング面 １４１０ リ
ードフレーム素材 １４２０ フ
オトレジスト １４３０ レ
ジストパターン １４４０ イ
ンナーリード １５１０ リ
ードフレーム １５１１ ダ
イパッド １５１２ イ
ンナーリード １５１２Ａ イ
ンナーリード先端部 １５１３ ア
ウターリード １５１４ ダ
ムバー １５１５ フ
レーム部（枠部） １５２０ 半
導体素子 １５２１ 電
極部（パッド） １５３０ ワ
イヤ １５４０ 封
止用樹脂100, 200, 300, 400 Resin-sealed semiconductor device 110, 210, 310, 410 Semiconductor element 111, 211, 411 Electrode (pad) 312 Bump 120, 220, 420 Wire 120A, 120B Wire 121A, 121B Plating part 130, 230, 330, 430 Lead frame 131, 231, 331, 431 Inner lead 131Aa, 231Aa, 331Aa, 431Aa First surface 131Ab, 231Ab, 331Ab, 431Ab Second surface 131Ac, 231Ac, 331Ac, 431Ac Third surface 131Ad, 231Ad, 231Ad, 331Ad, 431Ad Fourth surface 131B Connecting portion 133, 233, 333, 433 Terminal post 133A, 233A, 333A, 433A Terminal portion 133B, 233B, 333B, 433B Surface 133S, 233S, 333S, 433S Upper end surface 140, 240, 340, 440 Sealing resin 180 Protective frame 190 Adhesive 260 Reinforcing tape 270 Reinforcing fixing tape 350 Reinforcing tape 470 Insulating adhesive 1110 Lead frame material 1120A 1120B Resist pattern 1130 First opening 1140 Second opening 1150 First recess 1160 Second recess 1170 Flat surface 1180 Etching resistance layer 1320B, 1320C, 1320D Wire 1321B, 1321C, 1321D Plating part 1331B, 1331C , 1331D Inner lead tip 1331Aa Lead frame material surface 1331Ab Coining surface 1410 Lead frame material 1420 Photo resist 1430 Resist pattern 1 40 inner leads 1510 lead frame 1511 die pad 1512 an inner lead 1512A inner lead tip 1513 outer lead 1514 dam bar 1515 frame portion (frame portion) 1520 semiconductor element 1521 electrode portion (pad) 1530 wire 1540 sealing resin

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 ２段エッチング加工によりインナーリー
ドの厚さがリードフレーム素材の厚さよりも薄肉に外形
加工されたリードフレームを用いた半導体装置であっ
て、前記リードフレームは、リードフレーム素材よりも
薄肉のインナーリードと、該インナーリードに一体的に
連結したリードフレーム素材と同じ厚さの外部回路と接
続するための柱状の端子柱とを有し、且つ、端子柱はイ
ンナーリードの外部側においてインナーリードに対して
厚み方向に直交して設けられており、端子柱の先端面に
半田等からなる端子部を設け、端子部を封止用樹脂部か
ら露出させ、端子柱の外部側の側面を封止用樹脂部から
露出させており、インナーリードは、断面形状が略方形
で第１面、第２面、第３面、第４面の４面を有してお
り、かつ第１面はリードフレーム素材と同じ厚さの他の
部分の一方の面と同一平面上にあって第２面に向き合っ
ており、第３面、第４面はインナーリードの内側に向か
って凹んだ形状に形成されていることを特徴とする樹脂
封止型半導体装置。1. A semiconductor device using a lead frame in which the thickness of the inner lead is externally processed by a two-step etching process to be thinner than the thickness of the lead frame material, wherein the lead frame is more than the lead frame material. It has a thin inner lead and a columnar terminal column for connecting to an external circuit having the same thickness as the lead frame material integrally connected to the inner lead, and the terminal column is on the outer side of the inner lead. It is provided orthogonal to the inner lead in the thickness direction, the terminal part made of solder etc. is provided on the tip surface of the terminal post, the terminal part is exposed from the sealing resin part, and the side surface on the outer side of the terminal post Is exposed from the sealing resin portion, and the inner lead has a substantially rectangular cross-section and has four surfaces, a first surface, a second surface, a third surface, and a fourth surface, and Is a lead It is flush with one surface of the other part having the same thickness as the frame material and faces the second surface, and the third and fourth surfaces are formed in a shape recessed toward the inner side of the inner lead. The resin-encapsulated semiconductor device according to claim 1. 【請求項２】 ２段エッチング加工によりインナーリー
ドの厚さがリードフレーム素材の厚さよりも薄肉に外形
加工されたリードフレームを用いた半導体装置であっ
て、前記リードフレームは、リードフレーム素材よりも
薄肉のインナーリードと、該インナーリードに一体的に
連結したリードフレーム素材と同じ厚さの外部回路と接
続するための柱状の端子柱とを有し、且つ、端子柱はイ
ンナーリードの外部側においてインナーリードに対して
厚み方向に直交して設けられており、端子柱の先端の一
部を封止用樹脂部から露出させて端子部とし、端子柱の
外部側の側面を封止用樹脂部から露出させており、イン
ナーリードは、断面形状が略方形で第１面、第２面、第
３面、第４面の４面を有しており、かつ第１面はリード
フレーム素材と同じ厚さの他の部分の一方の面と同一平
面上にあって第２面に向き合っており、第３面、第４面
はインナーリードの内側に向かって凹んだ形状に形成さ
れていることを特徴とする樹脂封止型半導体装置。2. A semiconductor device using a lead frame in which the thickness of an inner lead is processed by a two-step etching process to be thinner than the thickness of a lead frame material, wherein the lead frame is more than the lead frame material. It has a thin inner lead and a columnar terminal column for connecting to an external circuit having the same thickness as the lead frame material integrally connected to the inner lead, and the terminal column is on the outer side of the inner lead. It is provided orthogonally to the inner lead in the thickness direction. A part of the tip of the terminal post is exposed from the encapsulation resin part to form the terminal part, and the external side surface of the terminal post is the encapsulation resin part. The inner lead has a substantially rectangular cross-sectional shape and has four surfaces, a first surface, a second surface, a third surface and a fourth surface, and the first surface is the same as the lead frame material. Thickness The other surface is flush with one surface of the other portion and faces the second surface, and the third surface and the fourth surface are formed in a concave shape toward the inner side of the inner lead. And a resin-encapsulated semiconductor device. 【請求項３】 請求項１ないし２において、半導体素子
はインナーリード間に収まり、該半導体素子の電極部は
ワイヤにてインナーリードと電気的に結線されているこ
とを特徴とする樹脂封止型半導体装置。3. The resin-sealed mold according to claim 1, wherein the semiconductor element is accommodated between the inner leads, and the electrode portion of the semiconductor element is electrically connected to the inner leads with a wire. Semiconductor device. 【請求項４】 請求項３において、リードフレームはダ
イパッドを有しており、半導体素子はダイパッド上に搭
載され、固定されていることを特徴とする樹脂封止型半
導体装置。4. The resin-sealed semiconductor device according to claim 3, wherein the lead frame has a die pad, and the semiconductor element is mounted and fixed on the die pad. 【請求項５】 請求項３において、リードフレームはダ
イパッドを持たないもので、半導体素子はインナーリー
ドとともに補強固定用テープにより固定されていること
を特徴とする樹脂封止型半導体装置。5. The resin-encapsulated semiconductor device according to claim 3, wherein the lead frame does not have a die pad, and the semiconductor element is fixed together with the inner lead by a reinforcing fixing tape. 【請求項６】 請求項１ないし２において、半導体素子
は半導体素子の電極部側の面をインナーリードの第２面
に絶縁性接着材により固定されており、該半導体素子の
電極部はワイヤによりインナーリードの第１面と電気的
に結線されていることを特徴とする樹脂封止型半導体装
置。6. The semiconductor element according to claim 1, wherein the surface of the semiconductor element on the side of the electrode portion is fixed to the second surface of the inner lead with an insulating adhesive, and the electrode portion of the semiconductor element is connected by a wire. A resin-encapsulated semiconductor device, which is electrically connected to a first surface of an inner lead. 【請求項７】 請求項１ないし２において、半導体素子
はバンプによりインナーリードの第２面に固定されて電
気的にインナーリードと接続していることを特徴とする
樹脂封止型半導体装置。7. The resin-sealed semiconductor device according to claim 1, wherein the semiconductor element is fixed to the second surface of the inner lead by a bump and electrically connected to the inner lead.
JP17049095A 1995-06-14 1995-06-14 Resin sealed semiconductor device Pending JPH098205A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17049095A JPH098205A (en) 1995-06-14 1995-06-14 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17049095A JPH098205A (en) 1995-06-14 1995-06-14 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH098205A true JPH098205A (en) 1997-01-10

Family

ID=15905935

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JPH098205A (en)

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US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
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US6274927B1 (en) 1999-06-03 2001-08-14 Amkor Technology, Inc. Plastic package for an optical integrated circuit device and method of making
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US6476478B1 (en) 1999-11-12 2002-11-05 Amkor Technology, Inc. Cavity semiconductor package with exposed leads and die pad
US6475827B1 (en) * 1999-10-15 2002-11-05 Amkor Technology, Inc. Method for making a semiconductor package having improved defect testing and increased production yield
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US6501161B1 (en) 1999-10-15 2002-12-31 Amkor Technology, Inc. Semiconductor package having increased solder joint strength
US6518659B1 (en) 2000-05-08 2003-02-11 Amkor Technology, Inc. Stackable package having a cavity and a lid for an electronic device
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
US6555899B1 (en) 1999-10-15 2003-04-29 Amkor Technology, Inc. Semiconductor package leadframe assembly and method of manufacture
US6586677B2 (en) 1999-08-25 2003-07-01 Amkor Technology, Inc. Plastic integrated circuit device package having exposed lead surface
US6605866B1 (en) 1999-12-16 2003-08-12 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6616436B1 (en) 1999-10-15 2003-09-09 Amkor Technology, Inc. Apparatus for manufacturing semiconductor packages
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6627976B1 (en) 1999-10-15 2003-09-30 Amkor Technology, Inc. Leadframe for semiconductor package and mold for molding the same
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US6667544B1 (en) 2000-06-30 2003-12-23 Amkor Technology, Inc. Stackable package having clips for fastening package and tool for opening clips
US6677662B1 (en) 1999-10-15 2004-01-13 Amkor Technology, Inc. Clamp and heat block assembly for wire bonding a semiconductor package assembly
US6677663B1 (en) 1999-12-30 2004-01-13 Amkor Technology, Inc. End grid array semiconductor package
US6686651B1 (en) 2001-11-27 2004-02-03 Amkor Technology, Inc. Multi-layer leadframe structure
US6696747B1 (en) 1999-10-15 2004-02-24 Amkor Technology, Inc. Semiconductor package having reduced thickness
US6700187B2 (en) 2001-03-27 2004-03-02 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US6713322B2 (en) 2001-03-27 2004-03-30 Amkor Technology, Inc. Lead frame for semiconductor package
US6730544B1 (en) 1999-12-20 2004-05-04 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6753597B1 (en) 1999-12-16 2004-06-22 Amkor Technology, Inc. Encapsulated semiconductor package including chip paddle and leads
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US6803645B2 (en) 2000-12-29 2004-10-12 Amkor Technology, Inc. Semiconductor package including flip chip
US6833609B1 (en) 1999-11-05 2004-12-21 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US6847103B1 (en) 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
US6853059B1 (en) 1999-10-15 2005-02-08 Amkor Technology, Inc. Semiconductor package having improved adhesiveness and ground bonding
US6858919B2 (en) 2000-03-25 2005-02-22 Amkor Technology, Inc. Semiconductor package
US6885086B1 (en) 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US6927478B2 (en) 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
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US7102216B1 (en) 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
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US8115298B2 (en) 1999-06-30 2012-02-14 Renesas Electronics Corporation Semiconductor device
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US8637965B2 (en) 1999-06-30 2014-01-28 Renesas Electronics Corporation Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US7804159B2 (en) 1999-06-30 2010-09-28 Renesas Electronics Corporation Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
KR100864781B1 (en) * 1999-06-30 2008-10-22 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device
US9484288B2 (en) 1999-06-30 2016-11-01 Renesas Technology Corporation Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
WO2001003186A1 (en) * 1999-06-30 2001-01-11 Hitachi, Ltd. Semiconductor device, method of manufacturing the same, and structure for mounting semiconductor device
US6586677B2 (en) 1999-08-25 2003-07-01 Amkor Technology, Inc. Plastic integrated circuit device package having exposed lead surface
US6627976B1 (en) 1999-10-15 2003-09-30 Amkor Technology, Inc. Leadframe for semiconductor package and mold for molding the same
US6616436B1 (en) 1999-10-15 2003-09-09 Amkor Technology, Inc. Apparatus for manufacturing semiconductor packages
US6853059B1 (en) 1999-10-15 2005-02-08 Amkor Technology, Inc. Semiconductor package having improved adhesiveness and ground bonding
US6646339B1 (en) 1999-10-15 2003-11-11 Amkor Technology, Inc. Thin and heat radiant semiconductor package and method for manufacturing
US6475827B1 (en) * 1999-10-15 2002-11-05 Amkor Technology, Inc. Method for making a semiconductor package having improved defect testing and increased production yield
US6677662B1 (en) 1999-10-15 2004-01-13 Amkor Technology, Inc. Clamp and heat block assembly for wire bonding a semiconductor package assembly
US6555899B1 (en) 1999-10-15 2003-04-29 Amkor Technology, Inc. Semiconductor package leadframe assembly and method of manufacture
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
US6696747B1 (en) 1999-10-15 2004-02-24 Amkor Technology, Inc. Semiconductor package having reduced thickness
US6501161B1 (en) 1999-10-15 2002-12-31 Amkor Technology, Inc. Semiconductor package having increased solder joint strength
US6833609B1 (en) 1999-11-05 2004-12-21 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6847103B1 (en) 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
US6476478B1 (en) 1999-11-12 2002-11-05 Amkor Technology, Inc. Cavity semiconductor package with exposed leads and die pad
US6753597B1 (en) 1999-12-16 2004-06-22 Amkor Technology, Inc. Encapsulated semiconductor package including chip paddle and leads
US6639308B1 (en) * 1999-12-16 2003-10-28 Amkor Technology, Inc. Near chip size semiconductor package
US6605866B1 (en) 1999-12-16 2003-08-12 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6730544B1 (en) 1999-12-20 2004-05-04 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6677663B1 (en) 1999-12-30 2004-01-13 Amkor Technology, Inc. End grid array semiconductor package
US6320251B1 (en) 2000-01-18 2001-11-20 Amkor Technology, Inc. Stackable package for an integrated circuit
US6404046B1 (en) 2000-02-03 2002-06-11 Amkor Technology, Inc. Module of stacked integrated circuit packages including an interposer
US6858919B2 (en) 2000-03-25 2005-02-22 Amkor Technology, Inc. Semiconductor package
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US6424031B1 (en) 2000-05-08 2002-07-23 Amkor Technology, Inc. Stackable package with heat sink
US6518659B1 (en) 2000-05-08 2003-02-11 Amkor Technology, Inc. Stackable package having a cavity and a lid for an electronic device
US6667544B1 (en) 2000-06-30 2003-12-23 Amkor Technology, Inc. Stackable package having clips for fastening package and tool for opening clips
US6803645B2 (en) 2000-12-29 2004-10-12 Amkor Technology, Inc. Semiconductor package including flip chip
US6927478B2 (en) 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
US6700187B2 (en) 2001-03-27 2004-03-02 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US6713322B2 (en) 2001-03-27 2004-03-30 Amkor Technology, Inc. Lead frame for semiconductor package
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US7102216B1 (en) 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6686651B1 (en) 2001-11-27 2004-02-03 Amkor Technology, Inc. Multi-layer leadframe structure
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US6885086B1 (en) 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US9054117B1 (en) 2002-11-08 2015-06-09 Amkor Technology, Inc. Wafer level package and fabrication method
US9406645B1 (en) 2002-11-08 2016-08-02 Amkor Technology, Inc. Wafer level package and fabrication method
US8691632B1 (en) 2002-11-08 2014-04-08 Amkor Technology, Inc. Wafer level package and fabrication method
US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
US10665567B1 (en) 2002-11-08 2020-05-26 Amkor Technology, Inc. Wafer level package and fabrication method
US8952522B1 (en) 2002-11-08 2015-02-10 Amkor Technology, Inc. Wafer level package and fabrication method
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
JP2005223331A (en) * 2004-02-04 2005-08-18 Samsung Electronics Co Ltd Lead frame, semiconductor chip package using the same, and manufacturing method of the semiconductor chip package
JP2006237450A (en) * 2005-02-28 2006-09-07 Sony Corp Semiconductor package and semiconductor device
US10811341B2 (en) 2009-01-05 2020-10-20 Amkor Technology Singapore Holding Pte Ltd. Semiconductor device with through-mold via
JP2010080971A (en) * 2009-11-25 2010-04-08 Dainippon Printing Co Ltd Resin sealed semiconductor device and production method thereof
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US10546833B2 (en) 2009-12-07 2020-01-28 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9324614B1 (en) 2010-04-06 2016-04-26 Amkor Technology, Inc. Through via nub reveal method and structure
US9159672B1 (en) 2010-08-02 2015-10-13 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8900995B1 (en) 2010-10-05 2014-12-02 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9082833B1 (en) 2011-01-06 2015-07-14 Amkor Technology, Inc. Through via recessed reveal structure and method
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US11043458B2 (en) 2011-11-29 2021-06-22 Amkor Technology Singapore Holding Pte. Ltd. Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode
US8981572B1 (en) 2011-11-29 2015-03-17 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9431323B1 (en) 2011-11-29 2016-08-30 Amkor Technology, Inc. Conductive pad on protruding through electrode
US9947623B1 (en) 2011-11-29 2018-04-17 Amkor Technology, Inc. Semiconductor device comprising a conductive pad on a protruding-through electrode
US10410967B1 (en) 2011-11-29 2019-09-10 Amkor Technology, Inc. Electronic device comprising a conductive pad on a protruding-through electrode
US10090228B1 (en) 2012-03-06 2018-10-02 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US10014240B1 (en) 2012-03-29 2018-07-03 Amkor Technology, Inc. Embedded component package and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
JP2015154042A (en) * 2014-02-19 2015-08-24 大日本印刷株式会社 Lead frame and manufacturing method therefor, and semiconductor device and manufacturing method therefor
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
JP2018085487A (en) * 2016-11-25 2018-05-31 マクセルホールディングス株式会社 Method of manufacturing semiconductor device and semiconductor device

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