JPH1174411A - Resin-sealed semiconductor device and circuit used in device thereof - Google Patents

Resin-sealed semiconductor device and circuit used in device thereof

Info

Publication number
JPH1174411A
JPH1174411A JP9247480A JP24748097A JPH1174411A JP H1174411 A JPH1174411 A JP H1174411A JP 9247480 A JP9247480 A JP 9247480A JP 24748097 A JP24748097 A JP 24748097A JP H1174411 A JPH1174411 A JP H1174411A
Authority
JP
Japan
Prior art keywords
terminal
circuit
semiconductor device
lead
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9247480A
Other languages
Japanese (ja)
Inventor
Shuichi Yamada
修一 山田
Makoto Nakamura
誠 中村
Takeshi Takeshita
毅志 竹下
Yutaka Yagi
裕 八木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP9247480A priority Critical patent/JPH1174411A/en
Priority to KR1019980029271A priority patent/KR100300666B1/en
Priority to US09/123,558 priority patent/US6359221B1/en
Publication of JPH1174411A publication Critical patent/JPH1174411A/en
Priority to US09/804,149 priority patent/US6465734B2/en
Priority to US09/987,855 priority patent/US6658734B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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    • H01L2224/321—Disposition
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To increase the occupying rate of a chip in the package size of a semiconductor substrate and to cope with the miniaturization of the substrate. SOLUTION: In a circuit 130A of a device 100, an inner terminal 131 and an outer terminal 132 of a semiconductor element 110 and a lead 133, which links the inner terminal 131 and the outer terminal 132 as a unitary body, are arranged independently to each other by a plurality of numbers in the approximately flat plane, and terminal surfaces of 131S for respective connection are arranged on both sides, which are different from each other. Furthermore, the inner terminal part 131 and the lead part 133 are formed thinner than the outer terminal 132. A terminal surface 132S of the outer terminal part 132 is made to protrude from the surface of the lead part 133. In the semiconductor element 110, the surface of the semiconductor element 110 that is opposite from the terminal parts 131 and 132 is bonded and fixed to a circuit 130A through an insulating layer 120 at the surface of the side of the terminal surface 131S of the inner terminal 131 inner than the inner terminal part 131 of a circuit part 130A and mounted on the circuit part 130A. A terminal (pad) 111 of the semiconductor element 110 and the terminal surface 131S of the inner terminal part 131 are electrically connected with a wire 140. Furthermore, a path of the outer terminal part 132 of the circuit part 130A is exposed to the outside and sealed with resin.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は，半導体素子を搭載
する樹脂封止型の半導体装置（プラスチックパッケー
ジ）に関し、特に、パッケージサイズの小型化に対応
し、その実装性を向上させることができる半導体装置と
その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device (plastic package) on which a semiconductor element is mounted, and more particularly to a semiconductor device capable of responding to a reduction in package size and improving its mountability. The present invention relates to an apparatus and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】近年、半導体装置は、高集積化、小型化
技術の進歩と電子機器の高性能化と軽薄短小化の傾向
（時流）から、ＬＳＩのＡＳＩＣに代表されるように、
ますます高集積化、高機能化になってきている。これに
伴い、リードフレームを用いた封止型の半導体装置にお
いても、その開発のトレンドが、ＳＯＪ（Ｓｍａｌｌ
Ｏｕｔｌｉｎｅ Ｊ−Ｌｅａｄｅｄ Ｐａｃｋａｇｅ）
やＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）のよ
うな表面実装型のパッケージを経て、ＴＳＯＰ（Ｔｈｉ
ｎ Ｓｍａｌｌ ＯｕｔｌｉｎｅＰａｃｋａｇｅ）の開
発による薄型化を主軸としたパッケージの開発へ、さら
にはパッケージ内部の構造を工夫しチップ収納効率向上
を目的としたＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈｉｐ）の構
造へと進展してきた。しかし、樹脂封止型半導体装置に
は、高集積化、高機能化とともに、更に一層の多ピン
化、薄型化、小型化が求められており、上記従来のパッ
ケージにおいてもチップ外周部分のリードの引き回しが
あるため、パッケージの小型化に限界が見えてきた。ま
た、ＴＳＯＰ等の小型パッケージにおいては、リードの
引き回し、ピンピッチから多ピン化に対しても限界が見
えてきた。2. Description of the Related Art In recent years, due to the progress of high integration and miniaturization technologies and the tendency of electronic devices to have higher performance and lighter, thinner and smaller size (current trend), semiconductor devices have been represented by LSI ASICs.
It is becoming more and more highly integrated and highly functional. Accordingly, the development trend of the encapsulated semiconductor device using the lead frame is also based on SOJ (Small).
Outline J-Leaded Package)
Through a surface mount type package such as QFP (Quad Flat Package) or TSOP (Thick Flat Package).
n Small Outline Package) has led to the development of a package whose main purpose is to reduce the thickness, and further to a LOC (Lead On Chip) structure for improving the chip storage efficiency by devising the internal structure of the package. However, resin-encapsulated semiconductor devices are required to have more pins, thinner, and smaller as well as higher integration and higher functionality. Due to the routing, the size reduction of packages has reached its limit. Further, in a small package such as TSOP, there is a limit to the number of pins due to lead routing and pin pitch.

【０００３】[0003]

【発明が解決しようとする課題】上記のように、更なる
樹脂封止型半導体装置の高集積化、高機能化が求められ
ており、樹脂封止型半導体装置の一層の多ピン化、薄型
化、小型化が求められている。本発明は、このような状
況のもと、パッケージサイズにおけるチップの占有率を
上げ、半導体装置の小型化に対応させ、回路基板への実
装面積を低減できる、即ち、回路基板への実装密度を向
上させることができる樹脂封止型半導体装置を提供しよ
うとするものである。As described above, further high integration and high functionality of the resin-encapsulated semiconductor device are required, so that the resin-encapsulated semiconductor device has more pins and is thinner. And miniaturization are required. Under such circumstances, the present invention can increase the occupancy rate of the chip in the package size, reduce the size of the semiconductor device, and reduce the mounting area on the circuit board. It is an object of the present invention to provide a resin-encapsulated semiconductor device that can be improved.

【０００４】[0004]

【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、半導体素子の端子と電気的に結線するための
内部端子部と、外部回路への接続のための外部端子部
と、前記内部端子部と外部端子部とを一体的に連結する
リード部とを略平面内に複数個、それぞれ互いに独立し
て配置し、且つ、内部端子部の半導体素子と接続するた
め端子面と、外部端子部の外部回路と接続するための端
子面とを、互いに異なる面側に配設した回路部であっ
て、その一面を全て、内部端子部の端子面に沿う一平面
上に設け、内部端子部、リード部は、外部端子部より薄
肉に形成され、外部端子部の端子面は、前記一平面側で
ない、リード部の面より突出されている回路部を設けた
もので、半導体素子は、半導体素子の端子部とは反対の
面を、回路部の内部端子部より内側の内部端子部の端子
面側の面において、回路部に絶縁層を介して接着固定し
て回路部に搭載され、半導体素子の端子部と回路部の内
部端子部の端子面とをワイヤにて電気的に接続してお
り、且つ、回路部の外部端子部の一部を外部に露出さ
せ、樹脂封止した樹脂封止型半導体装置である、または
前記樹脂封止型半導体装置の外部に露出した外部端子部
の面に、回路基板等への実装のための半田からなる外部
電極を設けた樹脂封止型半導体装置であることを特徴と
するものである。そして、上記において、一面を内部端
子部の端子面に沿い、且つ、外部端子部に接続し、内部
に延びる、外部端子部より薄肉の半導体素子搭載用リー
ドを設け、半導体素子は、半導体素子の端子部とは反対
の面を、絶縁層を介して接着固定して、少なくとも半導
体素子搭載用リードに搭載されていることを特徴とする
ものである。また、上記において、樹脂封止領域をほぼ
半導体素子の外形寸法にあわせたＣＳＰ（Ｃｈｉｐ Ｓ
ｉｚｅ Ｐａｃｋａｇｅ）としたことを特徴とするもの
である。According to the present invention, there is provided a resin-encapsulated semiconductor device comprising: an internal terminal portion for electrically connecting a terminal of a semiconductor element; an external terminal portion for connection to an external circuit; A plurality of lead portions for integrally connecting the internal terminal portion and the external terminal portion in a substantially plane, each of which is independently arranged, and a terminal surface for connecting to a semiconductor element of the internal terminal portion; A circuit part in which terminal surfaces for connecting to an external circuit of the external terminal part are arranged on different sides, and all of the surfaces are provided on one plane along the terminal surface of the internal terminal part. The terminal portion and the lead portion are formed to be thinner than the external terminal portion, and the terminal surface of the external terminal portion is provided with a circuit portion that is not on the one plane side and protrudes from the surface of the lead portion. The surface opposite to the terminal of the semiconductor element On the terminal surface side of the internal terminal part inside the part, it is mounted on the circuit part by bonding and fixing to the circuit part via an insulating layer, and the terminal part of the semiconductor element and the terminal surface of the internal terminal part of the circuit part are connected. A resin-encapsulated semiconductor device that is electrically connected by wires, and that exposes a part of the external terminal portion of the circuit portion to the outside, and is resin-encapsulated; or The present invention is characterized in that the semiconductor device is a resin-sealed semiconductor device in which external electrodes made of solder for mounting on a circuit board or the like are provided on a surface of an external terminal portion exposed to the outside. In the above, one surface is provided along the terminal surface of the internal terminal portion and connected to the external terminal portion, and a semiconductor element mounting lead thinner than the external terminal portion is provided, which extends inward. The surface opposite to the terminal portion is bonded and fixed via an insulating layer, and is mounted on at least a semiconductor element mounting lead. Further, in the above description, the CSP (Chip S) in which the resin sealing region substantially matches the external dimensions of the semiconductor element.
(size package).

【０００５】本発明の回路部材は、半導体素子の端子と
電気的に結線するための内部端子部と、外部回路への接
続のための外部端子部と、前記内部端子部と外部端子部
とを一体的に連結するリード部とを有し、これらを略平
面内に複数個、それぞれ互いに独立して配置し、前記リ
ード部に一体的に連結した前記リード部とは異なる、接
続リードを介してこれらの外側で、全体を保持する外枠
部とを備え、且つ内部端子部の端子面および外部端子の
端子面とを、互いに異なる面側に設けた樹脂封止型半導
体装置用回路部材であり、回路部材の内部端子部の端子
面側の面は全て素材面で、内部端子部、リード部および
接続リード部は、回路部材の素材の板厚よりも薄肉に形
成され、外部端子部は、回路部材の素材の板厚に形成さ
れており、外部端子部の外部回路と接続する側の端子面
は、素材面側でないリード部の面や接続リード部の面よ
り突出されているものであり、且つ、内部端子部は、半
導体素子搭載領域の外側に形成されていることを特徴と
するものである。[0005] A circuit member according to the present invention comprises an internal terminal for electrically connecting to a terminal of a semiconductor element, an external terminal for connection to an external circuit, and the internal terminal and the external terminal. A plurality of lead parts which are integrally connected to each other, each of which is independently arranged from each other in a substantially plane, and which is different from the lead part which is integrally connected to the lead part, via a connection lead. A circuit member for a resin-sealed semiconductor device, comprising an outer frame portion that holds the whole outside thereof, and a terminal surface of an internal terminal portion and a terminal surface of an external terminal provided on different surfaces. The surface on the terminal surface side of the internal terminal portion of the circuit member is a material surface, and the internal terminal portion, the lead portion, and the connection lead portion are formed to be thinner than the thickness of the material of the circuit member. The thickness of the circuit member material is The terminal surface on the side to be connected to the external circuit of the portion protrudes from the surface of the lead portion or the connection lead portion which is not the material surface side, and the internal terminal portion is located outside the semiconductor element mounting area. It is characterized by being formed.

【０００６】[0006]

【作用】本発明の樹脂封止型半導体装置は、上記のよう
な構成にすることにより、半導体装置におけるチップの
占有率を上げ、半導体装置の小型化に対応できるものと
している。即ち、半導体装置の回路基板への実装面積を
低減し、回路基板への実装密度の向上を可能としてい
る。外部端子部に一体的に連結した外部電極部を半田ボ
ールにて形成することにより、ＢＧＡ（Ｂａｌｌ Ｇｒ
ｉｄ Ａｒｒａｙ）タイプのようにすることもできる。
詳しくは、半導体素子の端子と電気的に結線するための
内部端子部と、外部回路への接続のための外部端子部
と、前記内部端子部と外部端子部とを一体的に連結する
リード部とを略平面内に複数個、それぞれ互いに独立し
て配置し、且つ、内部端子部の半導体素子と接続するた
め端子面と、外部端子部の外部回路と接続するための端
子面とを、互いに異なる面側に配設した回路部であっ
て、その一面を全て、内部端子部の端子面に沿う一平面
上に設け、内部端子部、リード部は、外部端子部より薄
肉に形成され、外部端子部の端子面は、前記一平面側で
ない、リード部の面より突出されている回路部を設けた
もので、半導体素子は、半導体素子の端子部とは反対の
面を、回路部の内部端子部より内側の内部端子部の端子
面側の面において、回路部に絶縁層を介して接着固定し
て回路部に搭載され、半導体素子の端子部と回路部の内
部端子部の端子面とをワイヤにて電気的に接続してお
り、且つ、回路部の外部端子部の一部を外部に露出さ
せ、樹脂封止した樹脂封止型半導体装置である、または
前記樹脂封止型半導体装置の外部に露出した外部端子部
の面に、回路基板等への実装のための半田からなる外部
電極を設けた樹脂封止型半導体装置であることにより、
これを達成している。そして、一面を内部端子部の端子
面に沿い、且つ、外部端子部に接続し、内部に延びる、
外部端子部より薄肉の半導体素子搭載用リードを設け、
半導体素子は、半導体素子の端子部とは反対の面を、絶
縁層を介して接着固定して、少なくとも半導体素子搭載
用リードに搭載されていることにより、半導体素子の搭
載を簡単に、且つ安定なものとできる。特に、樹脂封止
領域をほぼ半導体素子の外形寸法にあわせたＣＳＰ（Ｃ
ｈｉｐＳｉｚｅ Ｐａｃｋａｇｅ）とすることにより、
半導体装置の小型化に対応できる。The resin-encapsulated semiconductor device of the present invention has the above-described structure, so that the occupancy of the chip in the semiconductor device can be increased and the semiconductor device can be made smaller. That is, the mounting area of the semiconductor device on the circuit board is reduced, and the mounting density on the circuit board can be improved. By forming the external electrode portion integrally connected to the external terminal portion with a solder ball, a BGA (Ball Gr) is formed.
(id Array) type.
More specifically, an internal terminal portion for electrically connecting to a terminal of a semiconductor element, an external terminal portion for connection to an external circuit, and a lead portion for integrally connecting the internal terminal portion and the external terminal portion. Are arranged in a substantially plane, each independently of each other, and a terminal surface for connecting to the semiconductor element of the internal terminal portion and a terminal surface for connecting to the external circuit of the external terminal portion are mutually connected. A circuit portion disposed on a different surface side, all of which is provided on one plane along the terminal surface of the internal terminal portion, and the internal terminal portion and the lead portion are formed to be thinner than the external terminal portion. The terminal surface of the terminal portion is provided with a circuit portion protruding from the surface of the lead portion, which is not the one-plane side, and the semiconductor element has a surface opposite to the terminal portion of the semiconductor element inside the circuit portion. On the terminal surface side of the internal terminal part inside the terminal part, Is mounted on the circuit portion by bonding to the portion via an insulating layer, the terminal portion of the semiconductor element and the terminal surface of the internal terminal portion of the circuit portion are electrically connected by wires, and A part of the external terminal portion is exposed to the outside, and the resin-sealed semiconductor device is a resin-sealed semiconductor device, or the surface of the external terminal portion exposed to the outside of the resin-sealed semiconductor device is connected to a circuit board or the like. By being a resin-sealed semiconductor device provided with external electrodes made of solder for mounting,
This has been achieved. And one surface is connected to the external terminal portion along the terminal surface of the internal terminal portion and extends inside.
Provide semiconductor device mounting leads thinner than the external terminals,
The semiconductor element is mounted on at least the semiconductor element mounting lead by bonding and fixing the surface opposite to the terminal portion of the semiconductor element via an insulating layer, so that the mounting of the semiconductor element is easy and stable. It can be. In particular, the CSP (C
hipSize Package)
It can respond to miniaturization of semiconductor devices.

【０００７】本発明の回路部材は、上記のような構成に
することにより、上記本発明の樹脂封止型半導体装置の
製造に用いられるものであるが、ハーフエッチング加工
を併う通常のエッチング工程で作製することができる。The circuit member of the present invention, which has the above-described structure, is used for manufacturing the resin-encapsulated semiconductor device of the present invention. Can be produced.

【０００８】[0008]

【発明の実施の形態】本発明の樹脂封止型半導体装置を
図に基づいて説明する。図１は本発明の樹脂封止型半導
体装置の実施の形態の１例を示したもので、図１（ａ）
はその概略断面図であり、図１（ｂ）は外部電極側（図
１（ａ）のＡ０側）からみた図であり、図２は図１に示
す半導体装置の外部電極側および側面部を分かり易く示
した斜視図である。図３は図１に示す半導体装置の変形
例の断面図であり、図４は本発明の回路部材の概略図で
ある。図１、図２、図３、図４中、１００、１０１、１
０３は樹脂封止型半導体装置、１１０は半導体素子、１
１１は端子（パッド）、１２０は絶縁層、１２３は絶縁
性フィルム、１２５は接着剤層、１３０は回路部材、１
３０Ａは回路部、１３０Ｓは素材面、１３１は内部端子
部、１３１Ｓは端子面、１３２は外部端子部、１３２Ｓ
は端子面、１３３はリード、１３４は接続リード、１３
５は半導体素子搭載用リード、１３６は枠部、１４０は
ワイヤ、１５０は封止用樹脂、１６０は銀めっき、１７
０は半田からなる外部電極である。図１に示す樹脂封止
型半導体装置１００は、図４（ａ）に示す回路部材１３
０の点線内領域部Ｂ２のみを回路部１３０Ａとして樹脂
封止して用い、且つ回路部材１３０のそれ以外の部分は
分離して使用しないものであり、半導体素子１１０を、
端子（パッド）１１１側と反対の面側にて、回路部１３
０Ａの内部端子１３１の端子面１３１Ｓに沿う平面に、
絶縁層１２０を介して搭載し、半導体素子１１０の端子
（パッド）１１１と内部端子部１３１の端子面１３１Ｓ
とをワイヤ１４０にて電気的に接続し、且つ、外部端子
１３２の一部を外部に露出させ、全体を封止用樹脂１５
０で樹脂封止している。そして、外部に露出した外部端
子部の面１３２Ｓに、回路基板等への実装のための半田
からなる外部電極１７０を設けている。尚、端子面１３
１Ｓ表面にはワイヤボンディングのための銀めっき１６
０が施されてある。また、図１に示す半導体装置１００
は、図４に示す回路部材１３０を用いているため、接続
リード１３４をその内部に残す。DESCRIPTION OF THE PREFERRED EMBODIMENTS A resin-sealed semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 shows an example of an embodiment of a resin-sealed semiconductor device of the present invention.
FIG. 1B is a schematic cross-sectional view, FIG. 1B is a view as seen from the external electrode side (A0 side in FIG. 1A), and FIG. 2 is a view showing the external electrode side and side surfaces of the semiconductor device shown in FIG. It is the perspective view shown intelligibly. FIG. 3 is a sectional view of a modified example of the semiconductor device shown in FIG. 1, and FIG. 4 is a schematic view of a circuit member of the present invention. 1, FIG. 2, FIG. 3, and FIG.
03 is a resin-encapsulated semiconductor device, 110 is a semiconductor element, 1
11 is a terminal (pad), 120 is an insulating layer, 123 is an insulating film, 125 is an adhesive layer, 130 is a circuit member, 1
30A is a circuit portion, 130S is a material surface, 131 is an internal terminal portion, 131S is a terminal surface, 132 is an external terminal portion, 132S
Is a terminal surface, 133 is a lead, 134 is a connection lead, 13
5 is a semiconductor element mounting lead, 136 is a frame portion, 140 is a wire, 150 is a sealing resin, 160 is silver plating, 17
0 is an external electrode made of solder. The resin-sealed semiconductor device 100 shown in FIG. 1 has a circuit member 13 shown in FIG.
Only the area B2 within the dotted line of 0 is used as the circuit section 130A with resin sealing, and the other parts of the circuit member 130 are not used separately.
On the side opposite to the terminal (pad) 111 side, the circuit portion 13
0A on a plane along the terminal surface 131S of the internal terminal 131,
The terminal (pad) 111 of the semiconductor element 110 and the terminal surface 131S of the internal terminal portion 131 are mounted via the insulating layer 120.
Are electrically connected to each other by a wire 140, and a part of the external terminal 132 is exposed to the outside.
0 indicates resin sealing. The external electrode 170 made of solder for mounting on a circuit board or the like is provided on the surface 132S of the external terminal portion exposed to the outside. The terminal surface 13
Silver plating 16 for wire bonding on 1S surface
0 is given. Further, the semiconductor device 100 shown in FIG.
Uses the circuit member 130 shown in FIG. 4, so that the connection lead 134 is left inside.

【０００９】回路部１３０Ａは、図４（ａ）に示すよう
に、半導体素子１１０の端子１１１と電気的に結線する
ための内部端子部１３１と、外部回路への接続のための
外部端子部１３２と、内部端子部１３１と外部端子部１
３２とを一体的に連結するリード部１３３と、接続用リ
ード１３４とを略一平面内に複数個、それぞれ互いに独
立して配置するものである。尚、図４（ｂ）は、図４
（ａ）のＢ１領域を分かり易く示した斜視図である。回
路部１３０Ａは、図４（ｂ）に示すように、内部端子部
の端子面１３１Ｓ側の面を全て、素材面１３０Ｓとし、
略一平面上に形成されており、内部端子部１３１の端子
面１３１Ｓと外部端子部１３２の外部回路と接続するた
めの端子面１３２Ｓとを、回路部１３０Ａの互いに回路
部の異なる面側に設けている。そして、内部端子部１３
１、リード部１３３、接続リード部１３４は、外部端子
部１３２より薄肉に形成され、外部端子部１３２の端子
面１３２Ｓは、前記一平面側でない、端子部の面、リー
ド部の面、接続リードの面より突出されている。尚、図
４に示す回路部材１３０では、外部端子部１３２は回路
部材１３０の素材の厚さに形成され、内部端子部１３
１、リード部１３３、接続リード部１３４は、回路部材
１３０の素材の厚差より薄肉に形成されている。そし
て、内部端子部１３１の端子面１３１Ｓがある面（素材
面１３０Ｓ）と、半導体素子１１０の端子部１１１側と
反対の面とが絶縁層１２０を介して接着固定されてい
る。As shown in FIG. 4A, the circuit section 130A includes an internal terminal section 131 for electrically connecting to a terminal 111 of the semiconductor element 110, and an external terminal section 132 for connection to an external circuit. , The internal terminal 131 and the external terminal 1
A plurality of lead portions 133 for integrally connecting the P.32 and the connection leads 134 are arranged independently of each other in a substantially one plane. Incidentally, FIG.
It is the perspective view which showed B1 area | region of (a) clearly. As shown in FIG. 4B, the circuit portion 130 </ b> A has a material surface 130 </ b> S on the entire surface of the internal terminal portion on the terminal surface 131 </ b> S side.
A terminal surface 131S of the internal terminal portion 131 and a terminal surface 132S for connection to an external circuit of the external terminal portion 132 are provided on substantially different planes of the circuit portion 130A from each other. ing. And the internal terminal 13
1, the lead portion 133 and the connection lead portion 134 are formed to be thinner than the external terminal portion 132, and the terminal surface 132S of the external terminal portion 132 is not on the one plane side, the terminal portion surface, the lead portion surface, the connection lead. Projecting from the surface. In the circuit member 130 shown in FIG. 4, the external terminal 132 is formed to the thickness of the material of the circuit member 130 and the internal terminal 13
1. The lead portion 133 and the connection lead portion 134 are formed to be thinner than the thickness difference of the material of the circuit member 130. The surface of the internal terminal portion 131 having the terminal surface 131S (material surface 130S) and the surface of the semiconductor element 110 opposite to the terminal portion 111 are bonded and fixed via the insulating layer 120.

【００１０】接続リード１３４は、半導体装置作製の際
に、図４（ａ）に示す回路部材１３０の枠部１３６と分
離し易いように、外部端子部１３２よりも薄肉に形成す
る。The connection lead 134 is formed thinner than the external terminal 132 so as to be easily separated from the frame 136 of the circuit member 130 shown in FIG.

【００１１】回路部１３０Ａの材質としては４２合金
（Ｎｉ４２％のＦｅ合金）、銅合金等が用いられ、絶縁
層１２０としては、図１に示すように絶縁性フィルム１
２３の両側に接着剤層１２５を設けたものや、市販のダ
イアタッチ剤が用いられる。As a material of the circuit portion 130A, a 42 alloy (Fe alloy of 42% Ni), a copper alloy, or the like is used. As the insulating layer 120, as shown in FIG.
An adhesive layer 125 provided on both sides of 23 or a commercially available die attach agent is used.

【００１２】図１に示す樹脂封止型半導体装置１００に
おいては、内部端子部１３１は、半導体素子の各辺（四
辺）に沿い、半導体素子領域の外側にそれぞれ設けられ
ている。そして、回路部１３０Ａの上に絶縁層１２０を
介して半導体素子１１０が載った構造で、ＣＯＬ（Ｃｈ
ｉｐ Ｏｎ Ｌｅａｄ）と言われる。また、図１に示す
樹脂封止型半導体装置１００においては、樹脂封止領域
を、半導体素子のサイズにほぼあわせた構造で、ＣＳＰ
（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）と言われるも
のである。尚、本発明の樹脂封止型半導体装置の実施の
形態としては、上記図１に示す、ＣＯＬタイプ、ＣＳＰ
タイプに特に限定されることはない。In the resin-sealed semiconductor device 100 shown in FIG. 1, the internal terminal portions 131 are provided along the sides (four sides) of the semiconductor element and outside the semiconductor element region. Then, in a structure in which the semiconductor element 110 is mounted on the circuit section 130A via the insulating layer 120, COL (Ch
ip On Lead). Also, in the resin-sealed semiconductor device 100 shown in FIG. 1, the CSP has a structure in which the resin-sealed region is substantially matched to the size of the semiconductor element.
(Chip Size Package). As an embodiment of the resin-sealed semiconductor device of the present invention, a COL type, CSP shown in FIG.
There is no particular limitation on the type.

【００１３】次いで、図１に示す半導体装置の変形例を
挙げる。図３（ａ）に示すものは、図１に示す半導体装
置の回路部１３０Ａに半導体素子搭載用リード１３５を
設けた構造で、これにより、半導体素子の回路部への固
定を確実にできるものとしている。半導体素子搭載用リ
ード１３５は、一面を内部端子部１３１の端子面１３１
Ｓに沿い、外部端子部に接続し、内部に延びるもので、
外部端子部より薄肉に形成されている。また、図３
（ｂ）に示すものは、図１に示す半導体装置１００にお
いて半田ボールからなる外部電極を設けない形態のもの
で、半田ペースト等のプリント基板との接続部を形成し
たものである。Next, a modification of the semiconductor device shown in FIG. 1 will be described. The structure shown in FIG. 3A has a structure in which a semiconductor element mounting lead 135 is provided on the circuit portion 130A of the semiconductor device shown in FIG. 1, and as a result, the semiconductor element can be securely fixed to the circuit portion. I have. One surface of the semiconductor element mounting lead 135 is connected to the terminal surface 131 of the internal terminal portion 131.
Along S, connect to the external terminal and extend inside.
It is formed thinner than the external terminal portion. FIG.
1B shows a semiconductor device 100 shown in FIG. 1 in which no external electrodes made of solder balls are provided, in which a connection portion with a printed board such as a solder paste is formed.

【００１４】次に、本発明の回路部材を図に基づいて説
明する。図４は本発明の回路部材の１例を示したもの
で、前述の通り、図４（ａ）は平面図、図４（ｂ）は、
図４（ａ）のＢ１部を拡大して示した拡大斜視図であ
る。尚、図４中の点線領域Ｂ２は、回路部材の半導体装
置作製の際に、樹脂封止して用いられる領域で、点線外
側の領域は最終的には分離除去される。図４に示す回路
部材１３０は、本発明の半導体装置の作製に用いられる
ものであり、図４（ａ）に示すように、半導体素子の端
子と電気的に結線するための内部端子部１３１と、外部
回路への接続のための外部端子部１３２と、内部端子部
１３１と外部端子部１３２とを一体的に連結するリード
部１３３とを有し、これらを略平面内に複数個、それぞ
れ互いに独立して配置し、且つ、前記リード部１３３と
は異なる接続リード１３４を介して内部端子部１３２と
一体的に連結し、これらの外側で、全体を保持する外枠
部１３６とを備え、且つ内部端子部１３１の端子面１３
１Ｓおよび外部端子部１３２の端子面１３２Ｓとを、互
いに異なる面側に設けている。そして、内部端子部１３
１の端子面１３１Ｓ側の、回路部材１３０の面は、全て
素材面１３０Ｓで、内部端子部１３１、リード部１３３
および接続リード部１３４は、回路部材の素材の板厚よ
りも薄肉に形成され、外部端子部１３２は、回路部材の
素材の板厚に形成されており、外部端子部１３２の外部
回路と接続する側の端子面１３２Ｓは、内部端子部の端
子面１３１Ｓとは反対側に形成され、素材面側でないリ
ード部の面１３３の面や接続リード部１３４の面より突
出されている。更に、内部端子部１３１は、半導体素子
搭載領域の外側に、形成されている。回路部材１３０の
材質としては４２合金（Ｎｉ４２％のＦｅ合金）、銅合
金等が用いられ、通常のリードフレームと同様、エッチ
ングにより外形加工できる。Next, a circuit member of the present invention will be described with reference to the drawings. FIG. 4 shows an example of the circuit member of the present invention. As described above, FIG. 4A is a plan view, and FIG.
It is the expansion perspective view which expanded and showed B1 part of FIG. 4 (a). The dotted area B2 in FIG. 4 is an area that is used by resin sealing when the semiconductor device of the circuit member is manufactured, and the area outside the dotted line is finally separated and removed. The circuit member 130 shown in FIG. 4 is used for manufacturing a semiconductor device of the present invention. As shown in FIG. 4A, an internal terminal portion 131 for electrically connecting to a terminal of a semiconductor element is provided. An external terminal portion 132 for connection to an external circuit, and a lead portion 133 for integrally connecting the internal terminal portion 131 and the external terminal portion 132. An outer frame portion 136 that is independently disposed, is integrally connected to the internal terminal portion 132 via a connection lead 134 different from the lead portion 133, and holds the entire outside of these, and Terminal surface 13 of internal terminal portion 131
1S and the terminal surface 132S of the external terminal portion 132 are provided on different surfaces. And the internal terminal 13
1, the surface of the circuit member 130 on the side of the terminal surface 131S is a material surface 130S, and the internal terminal portion 131 and the lead portion 133 are all provided.
The connection lead portion 134 is formed to be thinner than the thickness of the circuit member material, and the external terminal portion 132 is formed to have a plate thickness of the circuit member material, and is connected to an external circuit of the external terminal portion 132. The terminal surface 132S on the side is formed on the opposite side to the terminal surface 131S of the internal terminal portion, and protrudes from the surface of the lead portion 133 and the surface of the connection lead portion 134 which are not the material surface side. Further, the internal terminal portion 131 is formed outside the semiconductor element mounting area. As a material of the circuit member 130, a 42 alloy (Ni 42% Fe alloy), a copper alloy, or the like is used, and the outer shape can be processed by etching, similarly to a normal lead frame.

【００１５】次いで、図４に示す回路部材１３０の製造
方法の１例を、図５に基づいて説明する。尚、図５は、
説明を分かり易くするため、図４（ａ）に示す一点鎖線
Ｂ３−Ｂ４における断面のみを示している。先ず、４２
合金（Ｎｉ４２％のＦｅ合金）等からなる、回路部材の
素材である厚さ０．２ｍｍ程度の板材５１０を準備し、
板材５１０の両面を脱脂等を行い良く洗浄処理した（図
５（ａ））後、板材５１０の両面に感光性のレジスト５
２０を塗布し、乾燥する。（図５（ｂ）） 次いで、板材５１０の両面から所定のパターン版を用い
てレジストの所定の部分のみに露光を行った後、現像処
理し、レジストパターン５２１、５２２を形成する。
（図５（ｃ）） 内部端子部１３１、リード部１３３、接続リード部１３
４の形成領域においては、板材の一面側にレジストが覆
われていない。尚、レジストとてしは、特に限定はされ
ないが、重クロム酸カリウムを感光材としたガゼイン系
のレジストや、東京応化株式会社製のネガ型液状レジス
ト（ＰＭＥＲレジスト）等が使用できる。次いで、レジ
ストパターンを耐腐蝕性膜として、板材５１０の両面か
ら腐蝕液にてエッチングを行う。内部端子部、リード
部、接続リード部の形成領域においては、板材の一面側
のレジストが覆われていない為、片側からのみエッチン
グが進行する。（これを、ここではハーフエッチングと
言っている。） 板材５１０の表裏のエッチング量を加減することによ
り、薄肉部（内部端子部１３１）の厚さを調整すること
ができる。エッチングは、通常、腐蝕液として塩化第二
鉄水溶液を用い、板材の両面からスプレイエッチングに
て行う。エッチングにより、途中図５（ｄ）のようにな
り、更にエッチングが進行して、内部端子部１３１間が
分離された状態で、一面を板材５１０の素材面５１０Ｓ
とした状態で、内部端子部１３１、リード部１３３、接
続リード部１３４を板材５１０の素材の厚さより薄肉
に、且つ外部端子部１３２、外枠部１３６を板材５１０
の素材の厚さと同じ厚さに形成される。（図５（ｅ）） 次いで、レジストを剥離した後、図４に示す回路部材１
３０が得られる。（図５（ｆ）） 尚、生産性の面から、エッチング加工する際、複数個面
付けした状態で上記の工程を行う。Next, an example of a method for manufacturing the circuit member 130 shown in FIG. 4 will be described with reference to FIG. In addition, FIG.
In order to make the description easy to understand, only a cross section taken along a dashed-dotted line B3-B4 shown in FIG. First, 42
A plate material 510 having a thickness of about 0.2 mm, which is a material of a circuit member, made of an alloy (Fe alloy of Ni 42%) or the like is prepared.
After both surfaces of the plate member 510 are degreased or the like and thoroughly cleaned (FIG. 5A), a photosensitive resist 5 is applied to both surfaces of the plate member 510.
Apply 20 and dry. (FIG. 5B) Next, only predetermined portions of the resist are exposed from both sides of the plate member 510 using a predetermined pattern plate, and then developed to form resist patterns 521 and 522.
(FIG. 5C) Internal terminal portion 131, lead portion 133, connection lead portion 13
In the formation region of No. 4, the resist is not covered on one surface side of the plate material. The resist is not particularly limited, but a casein-based resist using potassium dichromate as a photosensitive material, a negative liquid resist (PMER resist) manufactured by Tokyo Ohka Co., Ltd., or the like can be used. Next, etching is performed from both sides of the plate material 510 with a corrosion liquid using the resist pattern as a corrosion-resistant film. Since the resist on one surface side of the plate material is not covered in the formation regions of the internal terminal portion, the lead portion, and the connection lead portion, the etching proceeds only from one side. (This is referred to as half etching here.) The thickness of the thin portion (the internal terminal portion 131) can be adjusted by adjusting the amount of etching on the front and back of the plate member 510. The etching is usually performed by spray etching from both sides of the plate using an aqueous solution of ferric chloride as a corrosion liquid. As shown in FIG. 5D, the etching is further performed, and the etching is further performed to separate the internal terminal portions 131.
In this state, the internal terminal portions 131, the lead portions 133, and the connection lead portions 134 are thinner than the thickness of the material of the plate member 510, and the external terminal portions 132 and the outer frame portion 136 are connected to the plate member 510.
It is formed to the same thickness as the thickness of the material. (FIG. 5E) Next, after the resist is removed, the circuit member 1 shown in FIG.
30 is obtained. (FIG. 5F) From the viewpoint of productivity, when performing the etching process, the above-described process is performed in a state where a plurality of the substrates are imposed.

【００１６】次に、図１に示す半導体装置１００の製造
方法を、図６に基づいて簡単に説明する。先ず、図５の
ようにして外形加工して作製された、図４に示す回路部
材１３０を用意する。（６（ａ）） 次いで、洗浄処理等を施した後、内部端子部１３１の端
子面１３１Ｓ側に銀めっき処理を行い、銀めっき部１６
０を設ける。（図６（ｂ）） 尚、銀めっきに代え、金めっきやパラジウムめっきでも
良い。次いで、半導体素子１１０を、回路部材１３０の
内部端子部１３１形成領域の内側領域で、且つ、回路部
材１３０の内部端子部１３１の端子面１３１Ｓ側の素材
面１３０Ｓに、半導体素子の端子面１１１側とは反対側
の面で、絶縁層１２０を介して回路部材１３０と接着固
定（搭載）する。（図６（ｃ）） 絶縁層１２０は、図１（ａ）に示すように絶縁性フィル
ム１２３の両面に接着材層１２５をもうけた構造のもの
等が挙げられるが、これに代え、市販のダイアタッチ剤
を用いても良い。そして、半導体素子１１０の端子１１
１と、内部端子部１３１の端子面１３１Ｓ（銀めっき部
１６０）とをワイヤ１４０にて電気的に接続する。（図
６（ｄ）） この後、外部端子部１３２の一部を外部に露出させ、全
体を封止用樹脂１５０で樹脂封止する。（図６（ｅ）） 更に、露出した外部端子部１３２の端子面１３２Ｓに、
半田めっき等の表面処理剤を施した後、半田ボールから
なる外部電極１７０を形成する。（図６（ｆ）） 次いで、回路部材１３０の各接続リード１３４をプレス
により切断し、外枠部１３６を除去する。（図６
（ｇ）） また、半田ボールからなる外部電極１７０のかわりに、
スクリーン印刷による半田ペースト塗布などで回路基板
と半導体装置との接続に必要な量の半田が得られるよう
にしても良い。Next, a method of manufacturing the semiconductor device 100 shown in FIG. 1 will be briefly described with reference to FIG. First, a circuit member 130 shown in FIG. 4, which is manufactured by processing the outer shape as shown in FIG. 5, is prepared. (6 (a)) Next, after performing a cleaning process or the like, a silver plating process is performed on the terminal surface 131S side of the internal terminal portion 131, and a silver plating portion 16 is formed.
0 is provided. (FIG. 6B) Note that gold plating or palladium plating may be used instead of silver plating. Next, the semiconductor element 110 is placed on the material surface 130S on the terminal surface 131S side of the internal terminal portion 131 of the circuit member 130 in the region inside the region where the internal terminal portion 131 of the circuit member 130 is formed. On the side opposite to the above, the circuit member 130 is bonded and fixed (mounted) via the insulating layer 120. (FIG. 6 (c)) As the insulating layer 120, as shown in FIG. 1 (a), an insulating film 123 having a structure in which an adhesive layer 125 is provided on both sides of the insulating film 123 is used. A die attach agent may be used. Then, the terminal 11 of the semiconductor element 110
1 is electrically connected to the terminal surface 131S (silver plating portion 160) of the internal terminal portion 131 by a wire 140. (FIG. 6D) Thereafter, a part of the external terminal 132 is exposed to the outside, and the whole is sealed with a sealing resin 150. (FIG. 6E) Further, the exposed terminal surface 132S of the external terminal portion 132
After applying a surface treatment agent such as solder plating, external electrodes 170 made of solder balls are formed. (FIG. 6F) Next, each connection lead 134 of the circuit member 130 is cut by a press, and the outer frame portion 136 is removed. (FIG. 6
(G)) Also, instead of the external electrode 170 made of a solder ball,
An amount of solder necessary for connection between the circuit board and the semiconductor device may be obtained by applying a solder paste by screen printing or the like.

【００１７】[0017]

【実施例】更に、本発明の回路部材の実施例を挙げて、
図４に基づいて説明する。４２合金（Ｎｉ４２％のＦｅ
合金）からなり、外部端子部の厚さ０．２ｍｍ、内部端
子部の厚さを０．０５ｍｍとする、図４に示す回路部材
１３０を、図５に示す加工方法にて作製して得た後、図
６に示す半導体装置の作製方法により、図１に示す半導
体装置を作製したが、品質的には特に問題はなかった。EXAMPLES Further, examples of the circuit member of the present invention will be described.
A description will be given based on FIG. Alloy 42 (Ni 42% Fe
4) having a thickness of the external terminal portion of 0.2 mm and a thickness of the internal terminal portion of 0.05 mm was obtained by manufacturing the circuit member 130 shown in FIG. 4 by the processing method shown in FIG. Thereafter, the semiconductor device shown in FIG. 1 was manufactured by the method for manufacturing a semiconductor device shown in FIG. 6, but there was no particular problem in quality.

【００１８】[0018]

【発明の効果】本発明は、上記のように、更なる樹脂封
止型半導体装置の高集積化、高機能化が求められる状況
のもと、半導体装置におけるチップの占有率を上げ、半
導体装置の小型化に対応させ、回路基板への実装面積を
低減できる、即ち、回路基板への実装密度を向上させる
ことができる導体装置の提供を可能としたものである。According to the present invention, as described above, under the situation where higher integration and higher functionality of a resin-encapsulated semiconductor device are required, the occupancy of chips in a semiconductor device is increased, Accordingly, it is possible to provide a conductor device capable of reducing the mounting area on a circuit board, that is, improving the mounting density on a circuit board, in accordance with the miniaturization of the device.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の樹脂封止型半導体装置の１例を示した
図FIG. 1 is a diagram showing an example of a resin-sealed semiconductor device of the present invention.

【図２】本発明の樹脂封止型半導体装置の１例の斜視図FIG. 2 is a perspective view of one example of a resin-sealed semiconductor device of the present invention.

【図３】本発明の樹脂封止型半導体装置の１例の変形例
の断面図FIG. 3 is a cross-sectional view of a modified example of one example of the resin-sealed semiconductor device of the present invention.

【図４】本発明の回路部材を示した図FIG. 4 is a view showing a circuit member of the present invention.

【図５】本発明の回路部材の製造工程図FIG. 5 is a manufacturing process diagram of the circuit member of the present invention.

【図６】本発明の樹脂封止型半導体装置の製造工程図FIG. 6 is a manufacturing process diagram of the resin-encapsulated semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

１００、１０１ 樹脂封止型半導体装置 １１０ 半導体素子 １１１ 端子（パッド） １２０ 絶縁層（絶縁性フィル
ム） １３０ 回路部材 １３０Ａ 回路部 １３０Ｓ 素材面 １３１ 内部端子部 １３１Ｓ 端子面 １３２ 外部端子部 １３２Ｓ 端子面 １３３ リード １３４ 接続リード １３５ 半導体素子搭載用リード
部 １３６ 枠部 １４０ ワイヤ １５０ 封止用樹脂 １６０ 銀めっき １７０ 半田からなる外部電極 ５１０ 板材 ５１０Ｓ 板材の素材面 ５２０ レジスト ５２１、５２２ レジストパターンREFERENCE SIGNS LIST 100, 101 resin-sealed semiconductor device 110 semiconductor element 111 terminal (pad) 120 insulating layer (insulating film) 130 circuit member 130A circuit portion 130S material surface 131 internal terminal portion 131S terminal surface 132 external terminal portion 132S terminal surface 133 lead 134 connection lead 135 semiconductor element mounting lead part 136 frame part 140 wire 150 sealing resin 160 silver plating 170 external electrode made of solder 510 plate material 510S plate material material surface 520 resist 521, 522 resist pattern

───────────────────────────────────────────────────── フロントページの続き (72)発明者 八木 裕 東京都新宿区市谷加賀町一丁目１番１号 大日本印刷株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Yagi 1-1-1 Ichigaya Kagacho, Shinjuku-ku, Tokyo Dai Nippon Printing Co., Ltd.

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子の端子と電気的に結線するた
めの内部端子部と、外部回路への接続のための外部端子
部と、前記内部端子部と外部端子部とを一体的に連結す
るリード部とを略平面内に複数個、それぞれ互いに独立
して配置し、且つ、内部端子部の半導体素子と接続する
ための端子面と、外部端子部の外部回路と接続するため
の端子面とを、互いに異なる面側に配設した回路部であ
って、その一面を全て、内部端子部の端子面に沿う一平
面上に設け、内部端子部、リード部は、外部端子部より
薄肉に形成され、外部端子部の端子面は、前記一平面側
でない、リード部の面より突出されている回路部を設け
たもので、半導体素子は、半導体素子の端子部とは反対
の面を、回路部の内部端子部より内側の内部端子部の端
子面側の面において、回路部に絶縁層を介して接着固定
して回路部に搭載され、半導体素子の端子部と回路部の
内部端子部の端子面とをワイヤにて電気的に接続してお
り、且つ、回路部の外部端子部の一部を外部に露出さ
せ、樹脂封止した樹脂封止型半導体装置である、または
前記樹脂封止型半導体装置の外部に露出した外部端子部
の面に、回路基板等への実装のための半田からなる外部
電極を設けた樹脂封止型半導体装置であることを特徴と
する樹脂封止型半導体装置。An internal terminal for electrically connecting to a terminal of a semiconductor element, an external terminal for connection to an external circuit, and integrally connecting the internal terminal and the external terminal. A plurality of lead portions are disposed in a substantially plane, each being independently arranged, and a terminal surface for connecting to a semiconductor element of an internal terminal portion, and a terminal surface for connecting to an external circuit of an external terminal portion. Are arranged on different sides of the circuit, and all of the surfaces are provided on one plane along the terminal surface of the internal terminal, and the internal terminal and the lead are formed thinner than the external terminal. The terminal surface of the external terminal portion is provided with a circuit portion that is not on the one plane side and protrudes from the surface of the lead portion, and the semiconductor element has a circuit surface opposite to the terminal portion of the semiconductor element. On the terminal surface side of the internal terminal part inside the internal terminal part The semiconductor device is mounted on the circuit portion by bonding and fixing to the circuit portion via an insulating layer, and the terminal portion of the semiconductor element and the terminal surface of the internal terminal portion of the circuit portion are electrically connected to each other by a wire; A part of the external terminal portion is exposed to the outside and is a resin-sealed semiconductor device sealed with resin, or a circuit board or the like is provided on the surface of the external terminal portion exposed to the outside of the resin-sealed semiconductor device. A resin-encapsulated semiconductor device provided with an external electrode made of solder for mounting on a semiconductor device. 【請求項２】 請求項１において、一面を内部端子部の
端子面に沿い、且つ、外部端子部に接続し、内部に延び
る、外部端子部より薄肉の半導体素子搭載用リードを設
け、半導体素子は、半導体素子の端子部とは反対の面
を、絶縁層を介して接着固定して、少なくとも半導体素
子搭載用リードに搭載されていることを特徴とする樹脂
封止型半導体装置。2. The semiconductor device according to claim 1, further comprising a semiconductor element mounting lead connected to one side along the terminal surface of the internal terminal portion, connected to the external terminal portion, and extending inward and thinner than the external terminal portion. Is a resin-encapsulated semiconductor device characterized in that a surface of a semiconductor element opposite to a terminal portion is bonded and fixed via an insulating layer and is mounted on at least a semiconductor element mounting lead. 【請求項３】 請求項１ないし２において、樹脂封止領
域をほぼ半導体素子の外形寸法にあわせたＣＳＰ（Ｃｈ
ｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）としたことを特徴と
する樹脂封止型半導体装置。3. The CSP (Ch) according to claim 1, wherein the resin-encapsulated region substantially matches the outer dimensions of the semiconductor element.
A resin-encapsulated semiconductor device, characterized in that the semiconductor device is an IP Size Package. 【請求項４】 半導体素子の端子と電気的に結線するた
めの内部端子部と、外部回路への接続のための外部端子
部と、前記内部端子部と外部端子部とを一体的に連結す
るリード部とを有し、これらを略平面内に複数個、それ
ぞれ互いに独立して配置し、前記リード部に一体的に連
結した前記リード部とは異なる、接続リードを介してこ
れらの外側で、全体を保持する外枠部とを備え、且つ内
部端子部の端子面および外部端子の端子面とを、互いに
異なる面側に設けた樹脂封止型半導体装置用回路部材で
あり、回路部材の内部端子部の端子面側の面は全て素材
面で、内部端子部、リード部および接続リード部は、回
路部材の素材の板厚よりも薄肉に形成され、外部端子部
は、回路部材の素材の板厚に形成されており、外部端子
部の外部回路と接続する側の端子面は、素材面側でない
リード部の面や接続リード部の面より突出されているも
のであり、且つ、内部端子部は、半導体素子搭載領域の
外側に形成されていることを特徴とする回路部材。4. An internal terminal for electrically connecting to a terminal of a semiconductor element, an external terminal for connection to an external circuit, and integrally connecting the internal terminal and the external terminal. Having a lead portion, a plurality of these in a substantially plane, each arranged independently of each other, different from the lead portion integrally connected to the lead portion, outside these via a connection lead, A circuit member for a resin-encapsulated semiconductor device comprising an outer frame portion for holding the whole, and a terminal surface of an internal terminal portion and a terminal surface of an external terminal provided on different surfaces. The surface of the terminal portion on the terminal side is all a material surface, the internal terminal portion, the lead portion and the connection lead portion are formed thinner than the thickness of the circuit member material, and the external terminal portion is formed of the circuit member material. It is formed with a thick plate and connects to the external circuit of the external terminal section The terminal surface on the side to be formed is projected from the surface of the lead portion or the surface of the connection lead portion which is not the material surface side, and the internal terminal portion is formed outside the semiconductor element mounting region. Characterized circuit members. 【請求項５】 請求項４において、一面を素材面に沿
い、且つ、外部端子部に接続し、内部に延びる回路部材
の素材の板厚よりも薄肉な半導体素子搭載用リードを設
けていることを特徴とする回路部材。5. The semiconductor device mounting lead according to claim 4, wherein one surface is provided along the material surface and connected to an external terminal portion, and the semiconductor device mounting lead is thinner than the thickness of the circuit member material extending inside. A circuit member characterized by the above-mentioned. 【請求項６】 ハーフエッチング加工により、外形加工
したものであることを特徴とする請求項４ないし５記載
の回路部材。6. The circuit member according to claim 4, wherein the outer shape is processed by half etching.
JP9247480A 1997-08-04 1997-08-29 Resin-sealed semiconductor device and circuit used in device thereof Pending JPH1174411A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP9247480A JPH1174411A (en) 1997-08-29 1997-08-29 Resin-sealed semiconductor device and circuit used in device thereof
KR1019980029271A KR100300666B1 (en) 1997-08-04 1998-07-21 Resin-sealed semiconductor device, circuit member used therefor and method of manufacturing circuit member
US09/123,558 US6359221B1 (en) 1997-08-04 1998-07-29 Resin sealed semiconductor device, circuit member for use therein
US09/804,149 US6465734B2 (en) 1997-08-04 2001-03-13 Resin sealed semiconductor device, circuit member for use therein and method of manufacturing circuit member
US09/987,855 US6658734B2 (en) 1997-08-04 2001-11-16 Method of manufacturing a circuit member for a resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9247480A JPH1174411A (en) 1997-08-29 1997-08-29 Resin-sealed semiconductor device and circuit used in device thereof

Publications (1)

Publication Number Publication Date
JPH1174411A true JPH1174411A (en) 1999-03-16

Family

ID=17164095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9247480A Pending JPH1174411A (en) 1997-08-04 1997-08-29 Resin-sealed semiconductor device and circuit used in device thereof

Country Status (1)

Country Link
JP (1) JPH1174411A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1189279A1 (en) * 2000-03-13 2002-03-20 Dai Nippon Printing Co., Ltd. Resin-sealed semiconductor device, circuit member used for the device, and method of manufacturing the circuit member
KR100404062B1 (en) * 2000-05-24 2003-11-03 산요덴키가부시키가이샤 Plate and method of manufacturing a semiconductor device
KR100457421B1 (en) * 1999-12-16 2004-11-16 앰코 테크놀로지 코리아 주식회사 semiconductor package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100457421B1 (en) * 1999-12-16 2004-11-16 앰코 테크놀로지 코리아 주식회사 semiconductor package
EP1189279A1 (en) * 2000-03-13 2002-03-20 Dai Nippon Printing Co., Ltd. Resin-sealed semiconductor device, circuit member used for the device, and method of manufacturing the circuit member
EP1189279A4 (en) * 2000-03-13 2006-04-12 Dainippon Printing Co Ltd Resin-sealed semiconductor device, circuit member used for the device, and method of manufacturing the circuit member
US7307347B2 (en) 2000-03-13 2007-12-11 Dai Nippon Printing Co., Ltd. Resin-encapsulated package, lead member for the same and method of fabricating the lead member
KR100404062B1 (en) * 2000-05-24 2003-11-03 산요덴키가부시키가이샤 Plate and method of manufacturing a semiconductor device

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