JPH11163024A - Semiconductor device and lead frame for assembling the same, and manufacture of the device - Google Patents

Semiconductor device and lead frame for assembling the same, and manufacture of the device

Info

Publication number
JPH11163024A
JPH11163024A JP9327947A JP32794797A JPH11163024A JP H11163024 A JPH11163024 A JP H11163024A JP 9327947 A JP9327947 A JP 9327947A JP 32794797 A JP32794797 A JP 32794797A JP H11163024 A JPH11163024 A JP H11163024A
Authority
JP
Japan
Prior art keywords
external electrode
semiconductor device
lead frame
electrode pad
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9327947A
Other languages
Japanese (ja)
Inventor
Shinichi Nakamura
信一 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP9327947A priority Critical patent/JPH11163024A/en
Publication of JPH11163024A publication Critical patent/JPH11163024A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which high reliability can be maintained, and high density can be attained with low costs, and a lead frame for assembling the semiconductor device, and a method for manufacturing a semiconductor device suited for down-sizing. SOLUTION: A semiconductor 1 is constituted of a semiconductor element 4 whose back face a die pad 2 is connected through insulating adhesive 3 with, outside electrode pad 7 connected through a wire 6 with an inside electrode 5 of the semiconductor element 4, solder ball 8 connected with the outside electrode pad 7, and resin 9 sealing those parts. Then, in this semiconductor device 1, the solder ball 8 is exposed through an opening 10 formed in the resin 9 so as to be connectable with another substrate.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置とこれ
を組み立てるためのリードフレーム、及び特にダウンサ
イジング化に好適の半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a lead frame for assembling the same, and a method of manufacturing a semiconductor device particularly suitable for downsizing.

【０００２】[0002]

【従来の技術】近年、携帯電話等に代表されるように、
電子機器のダウンサイジング化，低コスト化が推進され
ている。このため、そのような電子機器に用いられる半
導体装置の高密度化，軽量化，及び回路基板への高密度
実装化が図られている。又、電子機器の信頼性の向上も
望まれているため、半導体装置の高密度化，信頼性の向
上が求められている。更に、一方では、半導体装置の製
造コストの低減も望まれている。そこで、現在では、こ
れらの要求を全て満たす半導体装置が必要となってきて
いる。2. Description of the Related Art In recent years, as represented by mobile phones, etc.,
Downsizing and cost reduction of electronic devices are being promoted. For this reason, the density and weight of the semiconductor device used in such electronic equipment have been increased, and the density of the semiconductor device mounted on a circuit board has been increased. In addition, since the reliability of electronic devices is also desired to be improved, higher density and higher reliability of semiconductor devices are required. Furthermore, on the other hand, reduction in the manufacturing cost of the semiconductor device is also desired. Therefore, a semiconductor device that satisfies all of these requirements is now required.

【０００３】ところで、半導体装置の高密度化という観
点からは、フリップチップ方式の実装技術が知られてい
る。これは、半導体素子を裸のまま実装基板上に直接搭
載するため、高密度化と共に電気特性を向上させること
が可能となる。しかし、この方法では半導体素子が樹脂
封止されないため、耐熱性，機械的強度，及び耐湿性と
いった点に問題がある。By the way, from the viewpoint of increasing the density of a semiconductor device, a flip-chip type mounting technique is known. This is because the semiconductor element is directly mounted on the mounting substrate in a bare state, so that it is possible to increase the density and to improve the electrical characteristics. However, this method has problems in heat resistance, mechanical strength, and moisture resistance because the semiconductor element is not sealed with resin.

【０００４】これに対して、通常広く用いられている半
導体装置は、半導体素子を樹脂封止して構成されてお
り、耐熱性，機械的強度，耐久性といった点では問題は
ないものの、構造上実装面積を広くとる必要があるた
め、高密度化を達成することができないという欠点があ
る。On the other hand, a semiconductor device which is generally widely used is formed by encapsulating a semiconductor element with a resin, and has no problem in terms of heat resistance, mechanical strength, and durability. Since it is necessary to increase the mounting area, there is a disadvantage that high density cannot be achieved.

【０００５】近年、フリップチップ装置よりも実装密度
は低いものの、既存の半導体装置と同様に取り扱える、
ボール・グリット・アレイ（ＢＧＡ）やチップ・サイズ
・パッケージ（ＣＳＰ）が開発されている。しかしなが
ら、これらの半導体装置は、封止樹脂やプリント配線基
板等の絶縁層を介して、半導体素子と外部端子とを接続
することが必要になる。このため、絶縁層に開口部を設
け、この開口部に導体層を通してこれを導通経路としな
ければならず、この開口工程が半導体装置の製造工程の
大きなネックとなり、製造コストの上昇を招くことにな
る。又、半導体装置に回路基板が組み込まれる形となる
ことから、軽量化が図れないという問題も残る。In recent years, although the mounting density is lower than that of a flip chip device, it can be handled in the same manner as an existing semiconductor device.
Ball grit arrays (BGA) and chip size packages (CSP) have been developed. However, in these semiconductor devices, it is necessary to connect a semiconductor element and an external terminal via an insulating layer such as a sealing resin or a printed wiring board. For this reason, an opening must be provided in the insulating layer and a conductive layer must be formed through the conductor layer in the opening, and this opening step becomes a major bottleneck in the manufacturing process of the semiconductor device, and increases the manufacturing cost. Become. Further, since the circuit board is incorporated in the semiconductor device, there is still a problem that the weight cannot be reduced.

【０００６】[0006]

【発明が解決しようとする課題】そこで、本発明は、上
記のような従来技術の有する問題点に鑑み、高信頼性を
維持しつつも、高密度化を低コストで行える半導体装置
とこれを組み立てるためのリードフレーム、更にはダウ
ンサイジング化に好適の半導体装置の製造方法を提供す
ることを目的とする。SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention provides a semiconductor device capable of achieving high density at low cost while maintaining high reliability. An object of the present invention is to provide a method of manufacturing a lead frame for assembling, and further a semiconductor device suitable for downsizing.

【０００７】[0007]

【課題を解決するための手段】上記目的を達成するた
め、本発明は次のような特徴を備えている。In order to achieve the above object, the present invention has the following features.

【０００８】第１の発明は、半導体素子と、この半導体
素子の電極部と電気的に結合された外部電極パットと、
この外部電極パットに接合された半田ボールと、これら
を封入する樹脂とから構成し、少なくとも前記半田ボー
ルが他の基板と接合可能に露出するように樹脂封止した
半導体装置に関するものである。ここで、前記半導体素
子と前記外部電極パットとの接合は半田ボール等を介し
て直接接合する、いわゆるバンプ接合により行われる
が、従来のようにワイヤーによって行っても差し支えな
い。According to a first aspect of the present invention, there is provided a semiconductor device, and an external electrode pad electrically connected to an electrode portion of the semiconductor device.
The present invention relates to a semiconductor device comprising a solder ball bonded to the external electrode pad and a resin for encapsulating the solder ball, and resin-sealing at least so that the solder ball is exposed to be bonded to another substrate. Here, the bonding between the semiconductor element and the external electrode pad is performed by so-called bump bonding, in which bonding is directly performed via a solder ball or the like, but may be performed by a wire as in the related art.

【０００９】又、本発明の半導体装置を組み立てる工程
で用いるリードフレームのダイパットを形成する金属板
は半導体素子の背面に直接接合されるが、かかるダイパ
ットに半導体の封止の役割を担わせてもよい。尚、前記
の外部電極パット及びダイパットは、金，銀，パラジウ
ム，チタン，又はニッケルのうち少なくとも１種類の金
属を用いて形成することが好ましい。The metal plate forming the die pad of the lead frame used in the process of assembling the semiconductor device of the present invention is directly bonded to the back surface of the semiconductor element. Good. The external electrode pad and the die pad are preferably formed using at least one kind of metal among gold, silver, palladium, titanium and nickel.

【００１０】第２の発明は、前記第１の発明の半導体装
置を組み立てるために用いるリードフレームに関する。
このリードフレームは、用いられる半導体素子の電極数
と一致した数の外部電極パットを有し、この外部電極パ
ットを前記半導体素子の電極とは異なる材質を用いて構
成し、前記外部電極パットを突起部で支えるようにした
ことを特徴とする。[0010] The second invention relates to a lead frame used for assembling the semiconductor device of the first invention.
The lead frame has the same number of external electrode pads as the number of electrodes of the semiconductor element to be used. The external electrode pads are formed using a material different from the electrodes of the semiconductor element. It is characterized by being supported by the department.

【００１１】第３の発明も、同様に前記第１の発明の半
導体装置を組み立てるために用いるリードフレームに関
する。このリードフレームは、用いられる半導体素子の
電極数と少なくとも一致した数の外部電極パットを有
し、この外部電極パット及び前記半導体素子を搭載する
ためのダイパットを前記半導体素子の電極とは異なる材
質を用いて構成し、前記外部電極パットと前記ダイパッ
トを突起部で支えるようにしたことを特徴とするもので
ある。A third invention also relates to a lead frame used for assembling the semiconductor device of the first invention. This lead frame has external electrode pads of a number at least equal to the number of electrodes of the semiconductor element to be used, and a die pad for mounting the external electrode pads and the semiconductor element is made of a material different from the electrodes of the semiconductor element. The external electrode pad and the die pad are supported by protrusions.

【００１２】ここで、前記第２，第３の発明のリードフ
レームは鉄合金，銅，又は銅合金の何れかからなり、前
記の外部電極パット及びダイパットは何れも金，銀，パ
ラジウム，チタン，又はニッケルのうちの少なくとも１
種類の金属を用いて形成することが好ましい。尚、この
種のリードフレームは、ホトリソグラス法を用い、エッ
チングとメッキとを組み合わせれば容易に製造できる。The lead frame according to the second and third aspects of the present invention is made of any one of iron alloy, copper, and copper alloy, and the external electrode pad and the die pad are each made of gold, silver, palladium, titanium, Or at least one of nickel
It is preferable to use a different kind of metal. Note that this type of lead frame can be easily manufactured by using photolithography and combining etching and plating.

【００１３】第４の発明は、前記第２の発明のリードフ
レームを用いて前記第１の発明の半導体装置を製造する
方法である。この方法は、まず、前記第２の発明のダイ
パットを持たないリードフレームを用いる場合には、外
部電極パットと半導体素子の電極とをバンプ接合した
後、前記外部電極パットの一部が露出するような開口部
が形成されるように樹脂封止する。次いで、前記リード
フレームを溶解除去した後、前記外部電極パットが露出
している封止樹脂開口部に半田ボールを挿入してこの半
田ボールと前記外部電極パットとを接合する。A fourth invention is a method for manufacturing the semiconductor device of the first invention using the lead frame of the second invention. In this method, first, when the lead frame having no die pad according to the second invention is used, after the external electrode pad and the electrode of the semiconductor element are bump-bonded, a part of the external electrode pad is exposed. Resin sealing is performed so that an appropriate opening is formed. Next, after dissolving and removing the lead frame, a solder ball is inserted into the sealing resin opening where the external electrode pad is exposed, and the solder ball and the external electrode pad are joined.

【００１４】第５の発明は、前記第３の発明のリードフ
レームを用いて前記第１の発明の半導体装置を組み立て
る方法である。この方法は、まず、背面に絶縁性の接着
剤が塗布された半導体素子をリードフレームのダイパッ
トにボンディングする。次に、前記半導体素子の電極と
前記リードフレームの外部電極パットとをワイヤーボン
ディングで接合し、前記半導体素子，接合ワイヤー，外
部電極パットをこの外部電極パットの一部が露出するよ
うな開口部が形成されるように樹脂封止する。そして、
前記リードフレームを溶解除去し、前記外部電極パット
が露出している封止樹脂開口部に半田ボールを挿入して
この半田ボールと前記外部電極パットとを接合する。A fifth invention is a method for assembling the semiconductor device of the first invention using the lead frame of the third invention. In this method, first, a semiconductor element having an insulating adhesive applied to the back surface is bonded to a die pad of a lead frame. Next, the electrode of the semiconductor element and the external electrode pad of the lead frame are bonded by wire bonding, and the semiconductor element, the bonding wire, and the external electrode pad are formed with openings such that a part of the external electrode pad is exposed. Resin sealing to form. And
The lead frame is dissolved and removed, and a solder ball is inserted into a sealing resin opening where the external electrode pad is exposed, and the solder ball and the external electrode pad are joined.

【００１５】[0015]

【発明の実施の形態】本発明の半導体装置では、半導体
装置が基本的に樹脂で封止されているため、半導体装置
としての耐熱性及び機械的強度，耐湿性を向上させるこ
とができる。又、本発明の半導体装置では、リードフレ
ームに形成された突起部を溶解除去する過程で形成され
る開口部を介して、半田ボールを外部電極パットと接合
して実装基板との電気的な接続を行うため、絶縁層に導
通路を確保するための開口工程が不要となり、製造コス
トの上昇を抑えることができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the semiconductor device of the present invention, since the semiconductor device is basically sealed with a resin, the heat resistance, mechanical strength and moisture resistance of the semiconductor device can be improved. Further, in the semiconductor device of the present invention, the solder ball is joined to the external electrode pad through the opening formed in the process of dissolving and removing the protrusion formed on the lead frame, and the solder ball is electrically connected to the mounting board. This eliminates the need for an opening step for securing a conductive path in the insulating layer, thereby suppressing an increase in manufacturing cost.

【００１６】又、本発明では、半導体装置の組立時にリ
ードフレームを用いるが、後工程でそのリードフレーム
は溶解除去するため、半導体装置内部に外部電極パッ
ト、或いは外部電極パットとダイパットしか残らず、半
導体装置の大幅な軽量化が可能である。更に、本発明に
よれば、半導体素子を基板に実装する際に、ワイヤーボ
ンディングによる接合方法ではなく、バンプ接合を用い
ることにより、外部端子のピッチ幅を狭くすることが可
能となり、安価なチップ・サイズ・パッケージが得られ
る。又、本発明による半導体装置の製造技術は、従来よ
り行われているプラスチックパッケージ技術の延長で実
現できるものであり、従来の製品と比べても大きなコス
ト増を招くことはない。In the present invention, a lead frame is used at the time of assembling a semiconductor device. However, since the lead frame is dissolved and removed in a later step, only an external electrode pad or an external electrode pad and a die pad remain in the semiconductor device. The weight of the semiconductor device can be significantly reduced. Further, according to the present invention, when a semiconductor element is mounted on a substrate, the pitch width of external terminals can be reduced by using bump bonding instead of a bonding method by wire bonding. The size package is obtained. Further, the manufacturing technology of the semiconductor device according to the present invention can be realized by extension of the plastic packaging technology which has been conventionally performed, and does not cause a large increase in cost as compared with the conventional product.

【００１７】以下、図示した実施例に基づき本発明を詳
細に説明する。Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

【００１８】第１実施例 図１は本実施例にかかる半導体装置の構成を示す断面図
である。本実施例の半導体装置１は、背面にダイパット
２が絶縁性接着剤３により接合された半導体素子４と、
半導体素子４の内部電極５とワイヤー６により結合され
た外部電極パット７と、外部電極パット７に接合された
半田ボール８と、これらを封入する樹脂９とからなる。
そして、この半導体装置１では、樹脂９に形成された開
口部１０を介して、半田ボール８が図示しない他の基板
に接合可能に露出している。FIG. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment . The semiconductor device 1 of the present embodiment includes a semiconductor element 4 having a die pad 2 bonded to the back surface by an insulating adhesive 3,
It comprises an external electrode pad 7 connected to the internal electrode 5 of the semiconductor element 4 by a wire 6, a solder ball 8 joined to the external electrode pad 7, and a resin 9 for encapsulating them.
In the semiconductor device 1, the solder balls 8 are exposed through the openings 10 formed in the resin 9 so as to be joined to another substrate (not shown).

【００１９】図２は、図１に示した半導体装置１の組立
に用いるリードフレームの断面図である。このリードフ
レーム１１の形状が、前記半導体素子４に実装するダイ
パット２及び外部電極パット７の位置を決定している。
即ち、リードフレーム１１のダイパット２及び外部電極
パット７を支える部分が凸形状となっている。そして、
樹脂封止後リードフレーム１１を溶解除去させる過程で
前記開口部１０が形成されることになる。又、外部電極
パット７は、リードフレーム１１に凸部を形成するエッ
チングの際のレジストとして使用するため、前記開口部
１０の穴よりも大きい外部端子パットを形成できる。FIG. 2 is a sectional view of a lead frame used for assembling the semiconductor device 1 shown in FIG. The shape of the lead frame 11 determines the positions of the die pad 2 and the external electrode pad 7 mounted on the semiconductor element 4.
That is, a portion of the lead frame 11 that supports the die pad 2 and the external electrode pad 7 has a convex shape. And
The opening 10 is formed in the process of dissolving and removing the lead frame 11 after resin sealing. Further, since the external electrode pad 7 is used as a resist at the time of etching for forming a projection on the lead frame 11, an external terminal pad larger than the hole of the opening 10 can be formed.

【００２０】第２実施例 図３は本実施例にかかる半導体装置の構成を示す断面図
である。本実施例の半導体装置１２では、半導体素子４
の内部電極５と外部電極パット７とを接続する際に、ワ
イヤーボンディングによる接続方法ではなく、Ａｕバン
プ１３による接続方法を用いている。このため、チップ
・サイズ・パッケージが可能となる。 Second Embodiment FIG. 3 is a sectional view showing the structure of a semiconductor device according to the second embodiment . In the semiconductor device 12 of this embodiment, the semiconductor element 4
When the internal electrode 5 and the external electrode pad 7 are connected, a connection method using Au bumps 13 is used instead of a connection method using wire bonding. For this reason, a chip size package becomes possible.

【００２１】第３実施例 本実施例は半導体装置の組立時に用いるリードフレーム
の製造方法に関するものである。これを図４に基づき説
明する。先ず、図４（ａ）に示すリードフレームとなる
薄板２１に、同図（ｂ）に示すようにレジスト２２を塗
布する。本例では、板厚０．１２５ｍｍの銅材に厚さ２
５μｍのドライフィルムをレジスト２２としてラミネー
トして用いている。尚、薄板２１及びレジスト２２の材
料は、全て一般に用いられる材料である。 Third Embodiment This embodiment relates to a method for manufacturing a lead frame used in assembling a semiconductor device. This will be described with reference to FIG. First, as shown in FIG. 4B, a resist 22 is applied to a thin plate 21 serving as a lead frame shown in FIG. In this example, a copper material having a thickness of 0.125 mm has a thickness of 2 mm.
A 5 μm dry film is used as a resist 22 by lamination. The materials of the thin plate 21 and the resist 22 are all commonly used materials.

【００２２】次に、リードフレーム形状と位置決め穴を
描画したマスクでレジスト２２にパターンを焼き付けた
後、炭酸ナトリウム水溶液で現像し、第１のエッチング
のためのレジストパターン２３を形成する（図４
（ｃ））。更に、このレジストパターン２３を５５℃の
Ｂｅ塩化第二鉄水溶液でスプレーエッチングして、リー
ドフレーム２４の外形と、位置決め穴２４ａを形成する
（図４（ｄ））。この後、苛性ソーダでレジストを剥離
した後、再度材料に第１のエッチングと同様のドライフ
ィルムをラミネートした後に、第１のエンチングで形成
した位置決め穴２４ａを用いてマスク位置合わせした外
部電極パット形状を描画したマスクで露光を行い、炭酸
ナトリウム水溶液で現像し、メッキマスク２５を得る
（図４（ｅ））。次に、現像によってレジスト開口され
た部分にメッキ法で外部電極パット２６を形成する（図
４（ｆ））。Next, after a pattern is baked on the resist 22 with a mask in which the shape of the lead frame and the positioning holes are drawn, the resist 22 is developed with an aqueous solution of sodium carbonate to form a resist pattern 23 for the first etching (FIG. 4).
(C)). Further, the resist pattern 23 is spray-etched with a 55 ° C. aqueous solution of ferric chloride to form the outer shape of the lead frame 24 and the positioning holes 24 a (FIG. 4D). Thereafter, after the resist is peeled off with caustic soda, a dry film similar to that of the first etching is laminated on the material again, and the external electrode pad shape obtained by positioning the mask using the positioning holes 24a formed by the first etching is used. Exposure is performed with the drawn mask, and development is performed with a sodium carbonate aqueous solution to obtain a plating mask 25 (FIG. 4E). Next, an external electrode pad 26 is formed by plating on the portion where the resist is opened by development (FIG. 4F).

【００２３】尚、ここでは、パラジウム（ｐｄ）／ニッ
ケル（Ｎｉ）／パラジウム（ｐｄ）メッキを用いている
が、電極材料としては、後工程で使用する銅の溶解液に
腐食されず、且つワイヤーボンディング性と半田濡れ性
が確保されるものであることが必要である。又、本実施
例では、レジスト−メッキ法により電極の形成を行った
が、マスク−メッキ法や印刷による電極の形成も可能で
ある。In this case, palladium (pd) / nickel (Ni) / palladium (pd) plating is used. However, the electrode material is not corroded by a copper solution used in a later process, and is not corroded. It is necessary that bonding property and solder wettability be ensured. In this embodiment, the electrodes are formed by the resist-plating method. However, the electrodes can be formed by a mask-plating method or printing.

【００２４】更に、レジストを苛性ソーダで剥離した
後、再度材料に第１のエッチングと同様のドライフィル
ムをラミネートした後に、第１のエッチングで形成した
位置決め穴２４ａを用いてマスク位置合わせした第２の
エッチングで溶解するエリア形状が描画されたマスクを
用いて露光した後に炭酸ナトリウム水溶液で現像し、第
２のエッチングのレジストパターン２７を形成する（図
４（ｇ））。次に、過硫酸ナトリウム水溶液でハーフエ
ッチングするが、リードフレーム２４のレジストパター
ン２７が施された部分とメッキされた外部電極パット２
６の部分は、エッチングされずに所望の突起部２８，２
９が形成される（図４（ｈ））。その後、レジストを苛
性ソーダにて剥離し、本発明の半導体装置を組み立てる
ためのリードフレーム２４が得られる（図４（ｉ））。Further, after the resist was peeled off with caustic soda, a dry film similar to that of the first etching was laminated on the material again, and the second mask was positioned using the positioning holes 24a formed by the first etching. Exposure is performed using a mask on which the shape of an area to be dissolved by etching is drawn, and development is performed with an aqueous solution of sodium carbonate to form a resist pattern 27 for the second etching (FIG. 4G). Next, half-etching is performed with an aqueous solution of sodium persulfate. The portion of the lead frame 24 where the resist pattern 27 is formed and the plated external electrode pad 2 are formed.
6 are not etched and the desired projections 28, 2
9 is formed (FIG. 4H). Thereafter, the resist is stripped with caustic soda to obtain a lead frame 24 for assembling the semiconductor device of the present invention (FIG. 4 (i)).

【００２５】第４実施例 本実施例は、第３実施例のリードフレームを用いた第２
実施例の半導体装置の製造方法に関するものである。以
下、これを図５を用いて説明する。まず、図５（ａ）に
示すように、リードフレーム２４の突起部２８上の外部
電極パット２６と半導体素子３１の内部電極３２とをバ
ンプＡｕ１３により接合する。次に、これらを封止樹脂
３３により封止する（図５（ｂ））。その後、リードフ
レーム２４ごと樹脂封止された半導体装置を過硫酸ナト
リウム水溶液中に浸積して、リードフレーム２４を溶解
除去する（図５（ｃ））。そして、リードフレーム２４
を溶解除去する過程で形成された封止樹脂３３の開口部
３４に半田ボール３５を接合することにより、半導体装
置が完成する（図５（ｄ））。 Fourth Embodiment This embodiment is directed to a second embodiment using the lead frame of the third embodiment.
The present invention relates to a method for manufacturing a semiconductor device according to an embodiment. Hereinafter, this will be described with reference to FIG. First, as shown in FIG. 5A, the external electrode pads 26 on the protrusions 28 of the lead frame 24 and the internal electrodes 32 of the semiconductor element 31 are joined by the bumps Au13. Next, these are sealed with a sealing resin 33 (FIG. 5B). Thereafter, the semiconductor device sealed with resin together with the lead frame 24 is immersed in an aqueous solution of sodium persulfate to dissolve and remove the lead frame 24 (FIG. 5C). And the lead frame 24
The semiconductor device is completed by joining the solder balls 35 to the openings 34 of the sealing resin 33 formed in the process of dissolving and removing the semiconductor device (FIG. 5D).

【００２６】第５実施例 本実施例も第３実施例のリードフレームを用いた半導体
装置の製造方法に関するものであるが、第４実施例のも
のとは別の一例を示している。これを図６に基づき説明
する。まず、図６（ａ）に示すリードフレーム２４に、
背面に絶縁性の接着剤が塗布された半導体素子３１をボ
ンディングする（図６（ｂ））。次に、半導体素子３１
の内部電極３２とリードフレーム２４の突起部２８上の
外部電極パット２６とをワイヤー３６によりボンディン
グ接合する（図６（ｃ））。その後、半導体素子３１，
接合ワイヤー３６，外部電極パット２６を封止樹脂３３
により封止する（図６（ｄ））。更に、リードフレーム
２４ごと樹脂封止された半導体装置を過硫酸ナトリウム
水溶液中に浸積して、リードフレーム２４を溶解除去す
る（図６（ｅ））。そして、リードフレーム２４の溶解
除去の過程で形成された封止樹脂３３の開口部３４に半
田ボール３５を接合することにより、本発明の半導体装
置を製造することができる（図６（ｆ））。 Fifth Embodiment The present embodiment also relates to a method for manufacturing a semiconductor device using the lead frame of the third embodiment, but shows another example different from that of the fourth embodiment. This will be described with reference to FIG. First, the lead frame 24 shown in FIG.
The semiconductor element 31 coated with an insulating adhesive on the back surface is bonded (FIG. 6B). Next, the semiconductor element 31
The internal electrode 32 and the external electrode pad 26 on the protruding portion 28 of the lead frame 24 are bonded by wire 36 (FIG. 6C). After that, the semiconductor element 31,
The bonding wire 36 and the external electrode pad 26 are sealed with a sealing resin 33.
(FIG. 6D). Further, the semiconductor device sealed with resin together with the lead frame 24 is immersed in an aqueous solution of sodium persulfate to dissolve and remove the lead frame 24 (FIG. 6E). Then, by joining the solder ball 35 to the opening 34 of the sealing resin 33 formed in the process of dissolving and removing the lead frame 24, the semiconductor device of the present invention can be manufactured (FIG. 6F). .

【００２７】[0027]

【発明の効果】上述のように、本発明によれば、リード
フレーム及びリードフレーム実装技術を用いて高密度実
装が可能な半導体装置を提供できる。これにより、低コ
ストを維持しながらも、回路基板への実装密度の向上と
軽量化を可能にした半導体装置を提供できる。As described above, according to the present invention, a semiconductor device capable of high-density mounting using a lead frame and a lead frame mounting technique can be provided. Thus, it is possible to provide a semiconductor device capable of increasing the mounting density on a circuit board and reducing the weight while maintaining low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図１】第１実施例にかかる半導体装置の構成を示す断
面図である。FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment.

【図２】図１に示した半導体装置を組み立てるためのリ
ードフレームの断面図である。FIG. 2 is a sectional view of a lead frame for assembling the semiconductor device shown in FIG. 1;

【図３】第２実施例にかかる半導体装置の構成を示す断
面図である。FIG. 3 is a cross-sectional view illustrating a configuration of a semiconductor device according to a second example.

【図４】（ａ）〜（ｉ）は本発明の半導体装置を組み立
てるためのリードフレームの製造工程を説明するための
図である。FIGS. 4A to 4I are diagrams for explaining a manufacturing process of a lead frame for assembling the semiconductor device of the present invention.

【図５】（ａ）〜（ｄ）は本発明の半導体装置の製造方
法を説明するための図である。FIGS. 5A to 5D are views for explaining a method for manufacturing a semiconductor device according to the present invention;

【図６】（ａ）〜（ｆ）は本発明の半導体装置の製造方
法を説明するための図である。FIGS. 6A to 6F are views for explaining a method of manufacturing a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

１，１２ 半導体装置 ２ ダイパット ３ 絶縁性接着剤 ４，３１ 半導体素子 ５，３２ 内部電極 ６，３６ ワイヤー ７，２６ 外部電極パット ８，３５ 半田ボール ９，３３ 樹脂 １０，３４ 開口部 １１，２４ リードフレーム １３ Ａｕバンプ ２１ 薄板 ２２ レジスト ２３，２７ レジストパターン ２４ａ位置決め穴 ２５ メッキマスク ２８，２９ 突起部 DESCRIPTION OF SYMBOLS 1, 12 Semiconductor device 2 Die pad 3 Insulating adhesive 4, 31 Semiconductor element 5, 32 Internal electrode 6, 36 Wire 7, 26 External electrode pad 8, 35 Solder ball 9, 33 Resin 10, 34 Opening 11, 24 Lead Frame 13 Au bump 21 Thin plate 22 Resist 23, 27 Resist pattern 24a Positioning hole 25 Plating mask 28, 29 Projection

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子と、該半導体素子の電極部と
電気的に結合された外部電極パットと、該外部電極パッ
トに接合された半田ボールと、これらを封入する樹脂
と、により構成し、少なくとも前記半田ボールが他の基
板と接合可能に露出するように樹脂封止したことを特徴
とする半導体装置。1. A semiconductor device comprising: a semiconductor element; an external electrode pad electrically coupled to an electrode portion of the semiconductor element; a solder ball joined to the external electrode pad; A semiconductor device characterized by being resin-sealed so that at least the solder ball is exposed so as to be joined to another substrate. 【請求項２】 前記半導体素子と前記外部電極パットと
はバンプ接合により接合されていることを特徴とする請
求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor element and the external electrode pad are joined by bump joining. 【請求項３】 前記外部電極パットは、金，銀，パラジ
ウム，チタン，又はニッケルのうち少なくとも１種類の
金属を用いて形成されていることを特徴とする請求項１
又は２に記載の半導体装置。3. The external electrode pad is formed using at least one kind of metal among gold, silver, palladium, titanium, and nickel.
Or the semiconductor device according to 2. 【請求項４】 用いられる半導体素子の電極数と少なく
とも一致した数の外部電極パットを有し、該外部電極パ
ットは前記半導体素子の電極とは異なる材質を用いて構
成され、該外部電極パットを突起部で支えるようにした
ことを特徴とする請求項１乃至３の何れかに記載の半導
体装置を組み立てるためのリードフレーム。4. An external electrode pad having at least as many electrodes as the number of electrodes of the semiconductor element to be used, wherein the external electrode pads are formed using a material different from the electrodes of the semiconductor element. 4. The lead frame for assembling a semiconductor device according to claim 1, wherein the lead frame is supported by a projection. 【請求項５】 前記リードフレームは鉄合金，銅，又は
銅合金の何れかからなり、前記外部電極パットは金，
銀，パラジウム，チタン，又はニッケルのうちの少なく
とも１種類の金属を用いて形成されていることを特徴と
する請求項４に記載のリードフレーム。5. The lead frame is made of any one of iron alloy, copper, and copper alloy, and the external electrode pad is made of gold,
The lead frame according to claim 4, wherein the lead frame is formed using at least one kind of metal among silver, palladium, titanium, and nickel. 【請求項６】 請求項５又は６に記載のリードフレーム
の外部電極パットと半導体素子の電極とをバンプ接合し
た後前記外部電極パットの一部が露出するような開口部
が形成されるように樹脂封止し、次いで前記リードフレ
ームを溶解除去した後前記開口部に半田ボールを挿入し
該半田ボールと前記外部電極パットとを接合するように
した半導体装置の製造方法。6. An opening for exposing a part of the external electrode pad after bump bonding the external electrode pad of the lead frame and the electrode of the semiconductor element according to claim 5 or 6. A method of manufacturing a semiconductor device in which a resin ball is sealed and then the lead frame is dissolved and removed, and then a solder ball is inserted into the opening to join the solder ball and the external electrode pad. 【請求項７】 背面にダイパットが接合された半導体素
子と、該半導体素子の電極部と電気的に結合された外部
電極パットと、該外部電極パットに接合された半田ボー
ルと、これらを封入する樹脂と、により構成し、少なく
とも前記半田ボールが他の基板と接合可能に露出するよ
うに樹脂封止したことを特徴とする半導体装置。7. A semiconductor element having a die pad bonded to a back surface, an external electrode pad electrically connected to an electrode portion of the semiconductor element, a solder ball bonded to the external electrode pad, and encapsulating them. And a resin sealed so that at least the solder ball is exposed so as to be bonded to another substrate. 【請求項８】 前記半導体素子と前記外部電極パットと
はワイヤーボンディングにより接合されていることを特
徴とする請求項７に記載の半導体装置。8. The semiconductor device according to claim 7, wherein said semiconductor element and said external electrode pad are joined by wire bonding. 【請求項９】 前記外部電極パット及び前記半導体素子
の背面に接合されたダイパットは、金，銀，パラジウ
ム，チタン，又はニッケルのうちの少なくとも１種類の
金属を用いて形成されていることを特徴とする請求項７
又は８に記載の半導体装置。9. The external electrode pad and the die pad bonded to the back surface of the semiconductor element are formed using at least one kind of metal among gold, silver, palladium, titanium, and nickel. Claim 7
Or the semiconductor device according to 8. 【請求項１０】 用いられる半導体素子の電極数と少な
くとも一致した数の外部電極パットを有し、該外部電極
パット及び前記半導体素子を搭載するためのダイパット
は前記半導体素子の電極とは異なる材質を用いて構成さ
れ、該外部電極パット及びダイパットを突起部で支える
ようにしたことを特徴とする請求項７乃至９の何れかに
記載の半導体装置を組み立てるためのリードフレーム。10. An external electrode pad having at least as many electrodes as the number of electrodes of the semiconductor element to be used, and the external electrode pad and a die pad for mounting the semiconductor element are made of a material different from the electrode of the semiconductor element. 10. The lead frame for assembling a semiconductor device according to claim 7, wherein the external electrode pad and the die pad are supported by projections. 【請求項１１】 前記リードフレームは鉄合金，銅，又
は銅合金の何れかからなり、前記外部電極パット及びダ
イパットは金，銀，パラジウム，チタン，又はニッケル
のうちの少なくとも１種類の金属を用いて形成されてい
ることを特徴とする請求項１０に記載のリードフレー
ム。11. The lead frame is made of any one of an iron alloy, copper, and a copper alloy, and the external electrode pad and the die pad use at least one kind of metal among gold, silver, palladium, titanium, and nickel. The lead frame according to claim 10, wherein the lead frame is formed. 【請求項１２】 半導体素子を前記リードフレームのダ
イパットに接合し、次いで前記半導体素子の電極と前記
リードフレームの外部電極パットとをワイヤーボンディ
ングで接合し、前記半導体素子，接合ワイヤー，外部電
極パットを該外部電極パットの一部が露出するような開
口部が形成されるように樹脂封止した後前記リードフレ
ームを溶解除去し、前記開口部に半田ボールを挿入して
該半田ボールと前記外部電極パットとを接合するように
したことを特徴とする半導体装置の製造方法。12. A semiconductor device is bonded to a die pad of the lead frame, and then an electrode of the semiconductor device is bonded to an external electrode pad of the lead frame by wire bonding, and the semiconductor device, the bonding wire, and the external electrode pad are bonded. After sealing the resin so that an opening for exposing a part of the external electrode pad is formed, the lead frame is dissolved and removed, and a solder ball is inserted into the opening to form the solder ball and the external electrode. A method of manufacturing a semiconductor device, comprising joining a pad.
JP9327947A 1997-11-28 1997-11-28 Semiconductor device and lead frame for assembling the same, and manufacture of the device Pending JPH11163024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9327947A JPH11163024A (en) 1997-11-28 1997-11-28 Semiconductor device and lead frame for assembling the same, and manufacture of the device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9327947A JPH11163024A (en) 1997-11-28 1997-11-28 Semiconductor device and lead frame for assembling the same, and manufacture of the device

Publications (1)

Publication Number Publication Date
JPH11163024A true JPH11163024A (en) 1999-06-18

Family

ID=18204800

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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EP1187204A2 (en) * 2000-09-04 2002-03-13 Sanyo Electric Co., Ltd. Circuit device and method of manufacturing the same
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WO2003085729A1 (en) * 2002-04-11 2003-10-16 Koninklijke Philips Electronics N.V. Method of manufacturing an electronic device
WO2003085730A1 (en) 2002-04-11 2003-10-16 Koninklijke Philips Electronics N.V. Method of manufacturing an electronic device, and electronic device
EP1154478A3 (en) * 2000-05-09 2004-04-07 Sanyo Electric Co., Ltd. Sheet-like board member, lead frame, and manufacture of a semiconductor device
EP1191590A3 (en) * 2000-09-20 2004-04-14 SANYO ELECTRIC Co., Ltd. Semiconductor device and semiconductor module
EP1160858A3 (en) * 2000-05-24 2004-04-28 Sanyo Electric Co., Ltd. A board for manufacturing a bga and method of manufacturing semiconductor device using thereof
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Cited By (15)

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Publication number Priority date Publication date Assignee Title
US7276793B2 (en) 2000-01-31 2007-10-02 Sanyo Electric Co., Ltd. Semiconductor device and semiconductor module
US7173336B2 (en) 2000-01-31 2007-02-06 Sanyo Electric Co., Ltd. Hybrid integrated circuit device
EP1154478A3 (en) * 2000-05-09 2004-04-07 Sanyo Electric Co., Ltd. Sheet-like board member, lead frame, and manufacture of a semiconductor device
US7138296B2 (en) 2000-05-24 2006-11-21 Sanyo Electric Co., Ltd. Board for manufacturing a BGA and method of manufacturing semiconductor device using thereof
US6975022B2 (en) 2000-05-24 2005-12-13 Sanyo Electric Co., Ltd. Board for manufacturing a BGA and method of manufacturing semiconductor device using thereof
EP1160858A3 (en) * 2000-05-24 2004-04-28 Sanyo Electric Co., Ltd. A board for manufacturing a bga and method of manufacturing semiconductor device using thereof
EP1187204A2 (en) * 2000-09-04 2002-03-13 Sanyo Electric Co., Ltd. Circuit device and method of manufacturing the same
EP1187204A3 (en) * 2000-09-04 2004-05-06 Sanyo Electric Co., Ltd. Circuit device and method of manufacturing the same
US6963126B2 (en) 2000-09-06 2005-11-08 Sanyo Electric Co., Ltd. Semiconductor device with under-fill material below a surface of a semiconductor chip
EP1187205A3 (en) * 2000-09-06 2004-06-23 Sanyo Electric Co., Ltd. Chip scale package with thermally and electrically conductive pad and manufacturing method thereof
EP1191590A3 (en) * 2000-09-20 2004-04-14 SANYO ELECTRIC Co., Ltd. Semiconductor device and semiconductor module
WO2003085730A1 (en) 2002-04-11 2003-10-16 Koninklijke Philips Electronics N.V. Method of manufacturing an electronic device, and electronic device
WO2003085729A1 (en) * 2002-04-11 2003-10-16 Koninklijke Philips Electronics N.V. Method of manufacturing an electronic device
WO2003085728A1 (en) * 2002-04-11 2003-10-16 Koninklijke Philips Electronics N.V. Carrier, method of manufacturing a carrier and an electronic device
KR101003061B1 (en) * 2002-10-09 2010-12-22 미크로나스 게엠베하 Support device for monolithically integrated circuits

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