JPH08107127A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08107127A JPH08107127A JP23896394A JP23896394A JPH08107127A JP H08107127 A JPH08107127 A JP H08107127A JP 23896394 A JP23896394 A JP 23896394A JP 23896394 A JP23896394 A JP 23896394A JP H08107127 A JPH08107127 A JP H08107127A
- Authority
- JP
- Japan
- Prior art keywords
- tape carrier
- semiconductor device
- tab tape
- tab
- ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高放熱性、優れた電気
特性をもち小型化を図った半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which has high heat dissipation and excellent electric characteristics and is miniaturized.
【０００２】[0002]
【従来の技術】図５は従来構造のＢＧＡパッケージ型の
半導体装置である。ＢＧＡとはＢａｌｌ Ｇｒｉｄ Ａ
ｒｒａｙの意であり、ＢＧＡパッケージは多数のボール
端子がパッケージの底面に並んだ構造となっている。す
なわちＬＳＩチップ６がボンディングワイヤ３により多
層配線基板４の配線パターン７に接続され、多層配線パ
ターン８を経て、ボール５に至る構造である。ボール５
はモールド樹脂２による封止の後に、ハンダペースト印
刷法やボール振込法などにより取り付けられている。こ
こで、ハンダペースト法とは、はんだペーストを印刷後
リフローしてボールを形成する方法であり、ボール振込
法とは予め作った球形はんだボールを位置決めしてはん
だ付けする方法である。2. Description of the Related Art FIG. 5 shows a BGA package type semiconductor device having a conventional structure. What is BGA? Ball Grid A
The BGA package has a structure in which a large number of ball terminals are arranged on the bottom surface of the package. That is, the LSI chip 6 is connected to the wiring pattern 7 of the multilayer wiring substrate 4 by the bonding wire 3, and reaches the ball 5 via the multilayer wiring pattern 8. Ball 5
After sealing with the mold resin 2, is attached by a solder paste printing method, a ball transfer method, or the like. Here, the solder paste method is a method of forming a ball by reflowing a solder paste after printing, and the ball transfer method is a method of positioning and soldering a spherical solder ball made in advance.
【０００３】ＢＧＡ型半導体装置は基本的には多層配線
基板（ガラスエポキシ板）を用いる考えから出発した。
というのは、ワイヤボンディング法のため、基板上の配
線パッドはＬＳＩチップの周辺にしか設けられず、この
ために周辺から中央のボール端子に配線するために、多
層の配線基板が必要となる。配線基板技術では０．３mm
ピッチの配線が限界であるため、微細な配線の引き回し
には、必然的に多層としなければならないためである。The BGA type semiconductor device basically started from the idea of using a multilayer wiring board (glass epoxy board).
Because of the wire bonding method, the wiring pads on the substrate are provided only on the periphery of the LSI chip, and therefore, a multilayer wiring substrate is required for wiring from the periphery to the central ball terminal. 0.3mm in wiring board technology
This is because the pitch wiring is the limit, and in order to lay out fine wiring, it is inevitably necessary to form a multilayer.
【０００４】[0004]
【発明が解決しようとする課題】しかし、上述した従来
のＢＧＡ型半導体装置は、表面に浮いたワイヤを保護す
るために樹脂モールド封止が必要となったり、多層配線
基板を用いたりする必要等があるため、次のような多く
の欠点があった。However, in the above-mentioned conventional BGA type semiconductor device, resin mold sealing is necessary to protect the wires floating on the surface, and it is necessary to use a multilayer wiring board. There were many drawbacks because of:
【０００５】（１）モールド樹脂、基板を含むために、
パッケージが厚くなってしまう。(1) To include a mold resin and a substrate,
The package becomes thick.
【０００６】（２）樹脂モールドのために、放熱性が極
めて悪い。(2) Because of resin molding, heat dissipation is extremely poor.
【０００７】（３）基板にガラスエポキシ基板を用いる
ために、コストアップとなる。(3) Since the glass epoxy substrate is used as the substrate, the cost is increased.
【０００８】（４）チップとインナリードの接合はワイ
ヤボンディングのために、接合ピッチが広く、小型化の
障害となる。(4) Since the chip and the inner lead are bonded by wire bonding, the bonding pitch is wide, which is an obstacle to miniaturization.
【０００９】（５）パッケージが大きいために、ＭＣＭ
（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）への組込が不
可能である。(5) MCM due to the large package
Incorporation into the (Multi Chip Module) is impossible.
【００１０】本発明の目的は、ＴＡＢテープキャリアを
用いることによって、上述した従来技術の欠点を解消し
て、高放熱性で、電気特性に優れ、しかも小型でＭＣＭ
への組込を可能とするた安価な半導体装置を提供するこ
とにある。また、本発明の目的は、機械強度及び平坦性
を維持できる半導体装置を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art by using a TAB tape carrier, to provide high heat dissipation, excellent electrical characteristics, and a small MCM.
Another object of the present invention is to provide an inexpensive semiconductor device that can be incorporated into a semiconductor device. Another object of the present invention is to provide a semiconductor device capable of maintaining mechanical strength and flatness.
【００１１】[0011]
【課題を解決するための手段】本発明の半導体装置は、
絶縁性フィルムの表面にリードを形成したＴＡＢテープ
キャリアに、上記リードと電気的に接続される導電性ビ
アホールを形成し、上記ＴＡＢテープキャリアのリード
に半導体チップをＴＡＢ接続し、ＴＡＢ接続された半導
体チップと反対側のＴＡＢテープキャリアの導電性ビア
ホール端部にはんだボールを形成したものである。According to the present invention, there is provided a semiconductor device comprising:
A conductive via hole electrically connected to the lead is formed in a TAB tape carrier having a lead formed on the surface of an insulating film, a semiconductor chip is TAB connected to the lead of the TAB tape carrier, and a TAB-connected semiconductor is formed. A solder ball is formed at the end of the conductive via hole of the TAB tape carrier on the side opposite to the chip.
【００１２】また、本発明の半導体装置は、上記はんだ
ボールを、はんだペーストを印刷後リフローしてボール
を形成する印刷リフロー法、あるいは予め作った球形は
んだボールを位置決めしてはんだ付けするボール振込法
により設けたものである。In the semiconductor device of the present invention, the solder balls are printed by a solder paste and then reflowed to form balls, or a ball transfer method in which preformed spherical solder balls are positioned and soldered. It is provided by.
【００１３】また、本発明の半導体装置は、上記絶縁性
フィルムの半導体チップよりはみ出す外周部に、これを
補強する補強体を設けたものである。In the semiconductor device of the present invention, a reinforcing body is provided on the outer peripheral portion of the insulating film protruding from the semiconductor chip to reinforce the semiconductor chip.
【００１４】[0014]
【作用】半導体チップはベアチップのままなので、モー
ルド樹脂で封止する場合に比して放熱性が高く、またパ
ッケージ厚が薄くなる。また、半導体チップとの接続は
ワイヤボンディングではなく、ＴＡＢ接続によるので、
配線長が短くなり電気的特性に優れる。また、ＴＡＢ接
続によると、微細狭ピッチ接合が可能であり、リード配
線回りを縮小することができ、小型化が可能である。Since the semiconductor chip is a bare chip, the heat dissipation is higher and the package thickness is smaller than that when the semiconductor chip is sealed with the molding resin. Also, since the connection with the semiconductor chip is not wire bonding but TAB connection,
The wiring length is short and the electrical characteristics are excellent. In addition, the TAB connection enables fine and narrow pitch bonding, reduces the lead wire circumference, and enables miniaturization.
【００１５】[0015]
【実施例】以下、本発明の半導体装置の実施例を図面を
用いて説明する。図１は本実施例のＴＡＢテープキャリ
アをベースとしたＢＧＡパッケージにＬＳＩチップを搭
載した半導体装置の側面図を示す。Embodiments of the semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 shows a side view of a semiconductor device in which an LSI chip is mounted on a BGA package based on the TAB tape carrier of this embodiment.
【００１６】ＴＡＢテープキャリア１１は、絶縁性フィ
ルム１３の表面に銅箔からなる多数のリード１４が形成
されたものである。また、このＴＡＢテープキャリア１
１には、リード数に対応した数の導電性ビアホール９が
直接形成されている。この導電性ビアホール９は、図示
するように、ＬＳＩチップ６の搭載面を避けるように、
ＴＡＢテープキャリア１１の外周部に形成される。各導
電性ビアホール９には各リード１４の一端が導かれ、各
リード１４と電気的に接続されるようになっている。各
リード１４の他端はＬＳＩチップ６とＴＡＢ接続される
インナリード１０を構成する。The TAB tape carrier 11 has a large number of leads 14 made of copper foil formed on the surface of an insulating film 13. Also, this TAB tape carrier 1
1, the number of conductive via holes 9 corresponding to the number of leads is directly formed. The conductive via hole 9 is formed so as to avoid the mounting surface of the LSI chip 6 as shown in the drawing.
It is formed on the outer peripheral portion of the TAB tape carrier 11. One end of each lead 14 is guided to each conductive via hole 9 and electrically connected to each lead 14. The other end of each lead 14 constitutes an inner lead 10 that is TAB-connected to the LSI chip 6.
【００１７】各リード１４の他端であるインナリード１
０はＬＳＩチップ６とＴＡＢ接続されるが、このとき、
図１に示すように、ＬＳＩチップ６の接続部側を上向き
にしインナリード１０が上方に湾曲してその接続部がＬ
ＳＩチップ６に乗り上げるように接続しても、あるいは
図２に示すようにＬＳＩチップ６の接続部側をインナリ
ードと対向するように下向きにしてインナリード１０が
まっすぐのまま接続するようにしてもよい。The inner lead 1 which is the other end of each lead 14
0 is TAB connected to the LSI chip 6, but at this time,
As shown in FIG. 1, with the connecting portion side of the LSI chip 6 facing upward, the inner lead 10 is bent upward so that the connecting portion is L-shaped.
Even if the inner lead 10 is connected so as to ride over the SI chip 6, or as shown in FIG. 2, the connection side of the LSI chip 6 is faced downward so as to face the inner lead and the inner lead 10 is connected as it is. Good.
【００１８】そして、ＴＡＢ接続されたＬＳＩチップ６
と反対側のＴＡＢテープキャリア１１の各導電性ビアホ
ール９の端部にはんだボール５が形成され、この各はん
だボール５は導電性ビアホール９を介して、対応する各
インナリード１０に電気的に導通するようになってい
る。はんだボール５は、印刷リフロー法、あるいはボー
ル振込法によって形成する。Then, the TAB-connected LSI chip 6
Solder balls 5 are formed at the ends of the conductive via holes 9 of the TAB tape carrier 11 on the side opposite to the solder balls 5. The solder balls 5 are electrically connected to the corresponding inner leads 10 via the conductive via holes 9. It is supposed to do. The solder balls 5 are formed by a printing reflow method or a ball transfer method.
【００１９】このように本実施例は、ＬＳＩチップをイ
ンナリードと接続しているため、ワイヤボンディングに
よる接続に比較して配線長が短く電気特性に優れる。ま
た、ＬＳＩチップとリードとの接続がＴＡＢ接続のた
め、微細狭ピッチ接続が可能であり、インナリードの配
線周りの縮小化が可能となる。As described above, in this embodiment, since the LSI chip is connected to the inner leads, the wiring length is short and the electric characteristics are excellent as compared with the connection by wire bonding. Further, since the LSI chip and the lead are connected by the TAB connection, a fine narrow pitch connection is possible, and the inner lead wiring can be reduced in size.
【００２０】また、ワイヤを保護するための樹脂モール
ド封止を必要とせず、ＬＳＩチップはベアチップのまま
でよいので放熱性が高い。また、樹脂モールド封止や多
層配線基板を用いる必要がないので、パッケージ厚さを
薄くできる、しかも、ＴＡＢテープキャリアに導電性ビ
アホールを直接設け、そのビアホール端部にはんだボー
ルを形成し、このはんだボールとインナリードとを導電
性ビアホールで電気的に接続するようにしているので小
型化が図れる。さらに、安価なＴＡＢの製造プロセスを
適用できるために、材料コスト及び組立てコストの大幅
な低減が可能となる。Further, since the resin mold encapsulation for protecting the wire is not required and the LSI chip may be a bare chip, the heat dissipation is high. In addition, since it is not necessary to use resin mold sealing or a multilayer wiring board, the package thickness can be reduced, and moreover, conductive via holes are directly provided in the TAB tape carrier, and solder balls are formed at the ends of the via holes. Since the ball and the inner lead are electrically connected by the conductive via hole, the size can be reduced. Further, since a cheap TAB manufacturing process can be applied, material cost and assembly cost can be significantly reduced.
【００２１】次に上述したＴＡＢ−ＢＧＡパッケージ型
半導体装置の実施例をさらに具体的に説明する。Next, the embodiment of the TAB-BGA package type semiconductor device described above will be described more specifically.
【００２２】（具体例）ＬＳＩチップ６は、１３×１３
mm角で０．４mm厚のものを用意した。このＬＳＩチップ
６の表面の周辺部には、０．１mmの間隔で０．０８mm角
のアルミニウムチップ電極を形成した。チップ電極の数
は４００パッドである。このチップ電極の上に、ニッケ
ル、さらにその上に金めっきを施した。(Specific example) The LSI chip 6 has a size of 13 × 13.
A 0.4 mm thick square film was prepared. On the peripheral portion of the surface of the LSI chip 6, aluminum chip electrodes of 0.08 mm square were formed at intervals of 0.1 mm. The number of chip electrodes is 400 pads. Nickel was further plated on this chip electrode, and gold was further plated on it.
【００２３】一方、ＴＡＢテープキャリアは次のように
製造した。エポキシ系の接着剤（１９μｍ厚）を付けた
ポリイミドフィルム（７５μｍ厚×３５mm幅）の片面
に、３５μｍ厚の銅箔を貼り合わせた。ついで銅箔に、
外部リードの数だけパンチングでビアホール９を穿ち、
ビアホール内部を無電界銅めっきで被覆した。そして、
銅箔に、ＬＳＩチップ６のチップ電極との接続のための
インナリード１０と、これをビアホール９につなぐリー
ド１４とをフォトエッチング法で形成した。On the other hand, the TAB tape carrier was manufactured as follows. A 35 μm-thick copper foil was attached to one surface of a polyimide film (75 μm-thick × 35 mm-width) to which an epoxy adhesive (19 μm-thick) was attached. Then on copper foil,
Punch the via holes 9 by the number of external leads,
The inside of the via hole was covered with electroless copper plating. And
Inner leads 10 for connecting to the chip electrodes of the LSI chip 6 and leads 14 connecting the leads to the via holes 9 were formed on the copper foil by photoetching.
【００２４】このＴＡＢテープキャリアのインナリード
１０に錫を約０．５μｍ無電界めっき法で設けた後、Ｌ
ＳＩチップの金めっきチップ電極と錫めっきインナリー
ドとを位置合せし、５００℃×２秒の加熱で金と錫を共
晶接合させた。After providing tin on the inner lead 10 of this TAB tape carrier by electroless plating of about 0.5 μm, L
The gold-plated chip electrode of the SI chip and the tin-plated inner lead were aligned, and gold and tin were eutectic bonded by heating at 500 ° C. for 2 seconds.
【００２５】次にＬＳＩチップ６を接合させた面と反対
側のＴＡＢテープキャリア１１のビアホール９の端部
に、印刷法で共晶はんだペーストを塗布した後、リフロ
ーさせ、はんだボール５を作った。はんだボール５の径
は０．３mmφ、高さは０．２５mmである。Next, a eutectic solder paste was applied by a printing method to the end of the via hole 9 of the TAB tape carrier 11 on the side opposite to the surface on which the LSI chip 6 was joined, and then reflowed to form a solder ball 5. . The solder ball 5 has a diameter of 0.3 mm and a height of 0.25 mm.
【００２６】（変形例）上記具体例で構成したＴＡＢ−
ＢＧＡパッケージ型半導体装置では、ＬＳＩチップが搭
載された部分の絶縁性フィルムについては、その部分は
ＬＳＩチップで補強されているので特に強度、平坦性が
問題になることはない。しかし、ＬＳＩチップからはみ
出した絶縁性フィルムの外周部については、強度上、平
坦性の問題が生じる場合がある。したがって、上記具体
例と同様の方法で作成したＴＡＢテープキャリアを搭載
したＢＧＡパッケージの外周部、すなわち絶縁性フィル
ムの外周部に、必要に応じて、図３及び図４に示すよう
に、金属製の方形上の補強体１２をポリイミド系接着剤
で貼り付けて半導体装置を構成する。このよう補強体１
２を貼り付けることにより、半導体装置の機械強度及び
平坦性を確実に維持できる。(Modification) TAB-configured in the above specific example
In the BGA package type semiconductor device, the strength and flatness of the insulating film on the part where the LSI chip is mounted are not particularly problematic because the part is reinforced by the LSI chip. However, the outer peripheral portion of the insulating film protruding from the LSI chip may have a problem of flatness in terms of strength. Therefore, if necessary, as shown in FIGS. 3 and 4, the outer periphery of the BGA package, in which the TAB tape carrier prepared by the same method as the above example is mounted, that is, the outer periphery of the insulating film is made of metal. The rectangular reinforcing body 12 is attached with a polyimide adhesive to form a semiconductor device. Reinforcing body 1
By sticking 2, the mechanical strength and flatness of the semiconductor device can be reliably maintained.
【００２７】[0027]
【発明の効果】請求項１に記載の発明によれば、半導体
チップを接続するＴＡＢテープフィルムに、導電性ビア
ホールを形成してＢＧＡパッケージを構成するようにし
たので、高い放熱性をもち、電気特性に優れ、しかも小
型であるためＭＣＭへの組込も可能となる。According to the first aspect of the invention, since the conductive via holes are formed in the TAB tape film for connecting the semiconductor chips to form the BGA package, it has high heat dissipation and electrical characteristics. Since it has excellent characteristics and is small, it can be incorporated into an MCM.
【００２８】請求項２に記載の発明によれば、はんだボ
ールを印刷リフロー法、あるいはボール振込法によって
形成するので、はんだボールの形成が容易である。According to the second aspect of the invention, the solder balls are formed by the print reflow method or the ball transfer method, so that the solder balls can be easily formed.
【００２９】請求項３に記載の発明によれば、絶縁性フ
ィルムのチップよりはみ出す外周部にこれを補強する補
強体を設けたので、機械強度及び平坦性を維持できる。According to the third aspect of the present invention, since the reinforcing member for reinforcing the outer peripheral portion of the insulating film protruding from the chip is provided, mechanical strength and flatness can be maintained.
【図１】本発明の半導体装置の実施例を説明するための
ＴＡＢ−ＢＧＡパッケージ型半導体装置の概略側面。FIG. 1 is a schematic side view of a TAB-BGA package type semiconductor device for explaining an embodiment of a semiconductor device of the present invention.
【図２】本実施例の変形例を説明するためのＴＡＢ−Ｂ
ＧＡパッケージ型半導体装置の概略断面図。FIG. 2 is a TAB-B for explaining a modified example of the present embodiment.
FIG. 3 is a schematic cross-sectional view of a GA package type semiconductor device.
【図３】本発明の変形例を説明するためのＴＡＢ−ＢＧ
Ａパッケージ型半導体装置の斜視図。FIG. 3 is a TAB-BG for explaining a modified example of the present invention.
FIG. 3 is a perspective view of an A package type semiconductor device.
【図４】図３の側面図。FIG. 4 is a side view of FIG.
【図５】従来例のガラスエポキシ基板を使用したＢＧＡ
パッケージ型半導体装置の断面図。FIG. 5: BGA using a conventional glass epoxy substrate
Sectional drawing of a package type semiconductor device.
５ はんだボール ６ ＬＳＩチップ ９ 導電性ビアホール １０ インナリード １１ ＴＡＢテープキャリア １２ 補強体 １３ 絶縁性フィルム １４ リード 5 Solder Ball 6 LSI Chip 9 Conductive Via Hole 10 Inner Lead 11 TAB Tape Carrier 12 Reinforcement Body 13 Insulating Film 14 Lead
───────────────────────────────────────────────────── フロントページの続き (72)発明者 渡辺 勝 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masaru Watanabe 3-1-1 Sukegawa-cho, Hitachi-shi, Ibaraki Hitachi Cable Co., Ltd.
Claims (3)
ＴＡＢテープキャリアに、上記リードと電気的に接続さ
れる導電性ビアホールを形成し、上記ＴＡＢテープキャ
リアのリードに半導体チップをＴＡＢ接続し、ＴＡＢ接
続された半導体チップと反対側のＴＡＢテープキャリア
の導電性ビアホール端部にはんだボールを形成した半導
体装置。1. A TAB tape carrier having a lead formed on the surface of an insulating film is formed with a conductive via hole electrically connected to the lead, and a semiconductor chip is TAB connected to the lead of the TAB tape carrier. A semiconductor device in which a solder ball is formed at an end of a conductive via hole of a TAB tape carrier opposite to a TAB-connected semiconductor chip.
刷後リフローしてボールを形成する印刷リフロー法、あ
るいは予め作った球形はんだボールを位置決めしてはん
だ付けするボール振込法により設ける請求項１に記載の
半導体装置。2. The solder ball is provided by a printing reflow method of forming a ball by reflowing after printing a solder paste, or a ball transfer method of positioning and soldering a preformed spherical solder ball. Semiconductor device.
み出す外周部に、これを補強する補強体を設けた請求項
１または２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein a reinforcing body for reinforcing the insulating film is provided on an outer peripheral portion of the insulating film protruding from the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23896394A JPH08107127A (en) | 1994-10-03 | 1994-10-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23896394A JPH08107127A (en) | 1994-10-03 | 1994-10-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08107127A true JPH08107127A (en) | 1996-04-23 |
Family
ID=17037905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23896394A Pending JPH08107127A (en) | 1994-10-03 | 1994-10-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08107127A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997040532A3 (en) * | 1996-04-24 | 1998-02-26 | Amkor Electronics Inc | Molded flex circuit ball grid array and method of making |
| US5852870A (en) * | 1996-04-24 | 1998-12-29 | Amkor Technology, Inc. | Method of making grid array assembly |
| WO1999048145A1 (en) * | 1998-03-19 | 1999-09-23 | Hitachi, Ltd. | Semiconductor device, method for manufacturing the same, and mounting structure of the same |
| CN110919118A (en) * | 2019-10-31 | 2020-03-27 | 成都四威高科技产业园有限公司 | Welding method with welding surface provided with cavity |
-
1994
- 1994-10-03 JP JP23896394A patent/JPH08107127A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997040532A3 (en) * | 1996-04-24 | 1998-02-26 | Amkor Electronics Inc | Molded flex circuit ball grid array and method of making |
| US5852870A (en) * | 1996-04-24 | 1998-12-29 | Amkor Technology, Inc. | Method of making grid array assembly |
| US5859475A (en) * | 1996-04-24 | 1999-01-12 | Amkor Technology, Inc. | Carrier strip and molded flex circuit ball grid array |
| US5985695A (en) * | 1996-04-24 | 1999-11-16 | Amkor Technology, Inc. | Method of making a molded flex circuit ball grid array |
| US6124637A (en) * | 1996-04-24 | 2000-09-26 | Amkor Technology, Inc. | Carrier strip and molded flex circuit ball grid array and method of making |
| US6329606B1 (en) | 1996-04-24 | 2001-12-11 | Amkor Technology, Inc. | Grid array assembly of circuit boards with singulation grooves |
| WO1999048145A1 (en) * | 1998-03-19 | 1999-09-23 | Hitachi, Ltd. | Semiconductor device, method for manufacturing the same, and mounting structure of the same |
| CN110919118A (en) * | 2019-10-31 | 2020-03-27 | 成都四威高科技产业园有限公司 | Welding method with welding surface provided with cavity |
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