JP3230384B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of ball terminals or pin terminals on a bottom surface, and more particularly to a semiconductor device capable of mounting a multi-terminal chip by increasing the number of ball terminals or pin terminals. About.

[0002]

2. Description of the Related Art FIG. 8 shows a BGA package type semiconductor device having a conventional structure. What is BGA package?
In the meaning of the lid Array, the ball terminals 5 have a structure in which many ball terminals 5 are arranged on the bottom surface of the BGA package 1.
That is, the structure is such that the LSI chip 6 is connected to the wiring pattern 7 of the multilayer wiring board 4 by the bonding wires 3 and reaches the ball terminal 5 via the multilayer wiring pattern 8. The ball terminals 5 are attached by a printing reflow method, a ball transfer method, or the like after sealing with the mold resin 2.
Here, the printing reflow method is a method of forming a ball by printing and reflowing a solder paste, and the ball transfer method is a method of positioning and soldering a spherical solder ball prepared in advance.

[0003] The BGA package type semiconductor device basically started from the idea of using a multilayer wiring board (glass epoxy resin plate). This is because, due to the wire bonding method, wiring pads on the substrate are provided only at the periphery of the LSI chip. Therefore, a multilayer wiring substrate is required for wiring from the periphery to the central ball terminal. This is because 0.3 mm pitch wiring is the limit in the wiring board technology, and therefore, in order to route fine wiring, it is inevitable that a multilayer structure is required.

However, this device requires resin mold sealing to protect the wire floating on the surface,
Since it is necessary to use a multilayer wiring board, there are many disadvantages as follows.

(1) In order to include a mold resin and a substrate,
The package becomes thick.

(2) Due to the resin mold, heat radiation is extremely poor.

(3) The cost is increased because a glass epoxy substrate is used as the substrate.

(4) Since the bonding between the chip and the inner lead is performed by wire bonding, the bonding pitch is wide, which hinders miniaturization.

(5) Because the package is large, MCM
(Multi Chip Module) is not possible.

Therefore, a BGA package using a TAB tape carrier which does not have the above-mentioned disadvantages has been proposed. FIG. 9 is a sectional view and FIG. 10 is a bottom view. TA
The B tape carrier 20 is obtained by forming a wiring pattern made of copper foil on the insulating film 11, and the inner lead 14 which is one end of the wiring pattern is attached to the carrier 20.
And is connected to the chip electrode 13 of the LSI chip 6 attached to the insulating film 11. A ball-forming land 17 is formed at the other end of the wiring pattern.
There is a structure in which ball terminals 5 for external connection to a printed board or the like are provided there.

The TAB tape carrier 20 adhered to the LSI chip 6 does not exceed the area of the LSI chip 6 due to the restriction of the inner lead and the chip electrode connection. Therefore, the ball terminals 5 are provided only on the back surface of the LSI chip 6. It will be provided.

[0012]

The conventional TAB described above.
A BGA package type semiconductor device using a tape carrier has an advantage which is not provided by a device using a multilayer wiring board. However, since the ball terminals 5 for external connection are provided only on the back surface of the chip, the number of ball terminals is small. However, there is a disadvantage that it is impossible to mount a multi-terminal LSI.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art by mounting an LSI chip so that a ball terminal or a pin terminal can be formed. It is to provide a semiconductor device.

[0014]

According to the present invention, there is provided a semiconductor device comprising:
An LSI chip in which a number of chip electrodes are formed along the periphery of one surface of the chip; a chip having an area larger than that of the LSI chip, which is adhered to one surface of the chip , and a chip electrode on the one surface. a slit that exposed by forming the peripheral portion, by the slit and the insulating film in the outer portion is partitioned and formed to protrude from the inner portion and the chip corresponding to the chip rear surface, of the inner portion and outer portion of the insulating film are respectively <br/> formed on the surface, protruding end of each is on the slit, connected to the press-bent the tip electrode within the slit, and a wiring pattern having a terminal forming lands on the other end, the terminal forming And a ball terminal or a pin terminal for external connection formed on the land.

[0015]

When one end of the wiring pattern provided on the insulating film is projected out of the insulating film from only one direction, the ball terminal or the pin terminal formed at the other end of the wiring pattern can be provided only on the back surface of the chip. . However, if one end of the wiring pattern is projected from both directions so as to face each other, the ball terminal or the pin terminal can be provided not only on the back surface of the chip but also beyond the chip.

The present invention has been made based on such findings, and the present invention provides an insulating film which is provided with a slit for exposing a chip electrode on an insulating film to be attached to a chip and which is defined by the slit. Are provided with wiring patterns on the inside and outside. In this case, the ball terminal or the pin terminal can be provided not only on the inner portion of the insulating film corresponding to the back surface of the chip but also on the outer portion protruding from the chip. Therefore, the number of ball terminals or pin terminals is increased as compared with the case where one end of the wiring pattern is projected from one direction to the outside of the insulating film, so that a multi-terminal LSI can be mounted.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings. 1A and 1B are plan views of a BGA package type semiconductor device according to the present embodiment. FIG. 1A is a plan view of an LSI chip, and FIG. 1B is a bottom view of the semiconductor device.

As shown in FIG. 1A, the LSI chip 6
On one surface, a large number of chip electrodes 13 are provided along the periphery thereof.
Is formed. As shown in FIG. 1B, a TAB tape carrier 20 is attached to one surface of the LSI chip 6. The TAB tape carrier 20 has a larger area than the LSI chip 6, and the peripheral portion thereof is
It protrudes more than it.

A slit 18 for exposing the chip electrode 13 on one surface of the LSI chip 6 is formed in a peripheral portion of the insulating film 11 serving as a base of the TAB tape carrier 20. The slit 18 is formed in a rectangular shape according to the arrangement of the chip electrodes 13 as shown in the figure.
The insulating film 11 is defined by the slit 18 into an inner portion 21 corresponding to the chip back surface and an outer portion 22 protruding from the LSI chip 6.

A large number of wiring patterns 7 are formed on the surface of the insulating film 11, and inner leads as one end thereof are connected to the chip electrodes 13 of the LSI chip 6. As described above, the chip electrode 1 is provided around the insulating film 11.
Since the slit 18 for exposing the third electrode 3 is formed, the inner lead of the wiring pattern 7 can be routed from both left and right directions of the slit 18 and brought to the slit 18, and can be connected to the chip electrode 13 in the slit 18. Therefore, the wiring pattern 7 formed on the surface of the insulating film 11 can be formed not only on the inner portion 21 of the insulating film 11 but also on the outer portion 22. A terminal forming land 17 is formed at the other end of each wiring pattern 7, and a ball terminal 5 for external connection such as a PCB is formed thereon.

FIG. 2 is a side sectional view of the BGA package type semiconductor device of the above embodiment. The inner lead 14 of the wiring pattern extends over the slit 18 from both the left and right directions of the slit 18, is pushed into the slit 18, and is connected to the chip electrode 13.

After the connection, the slit 18 is sealed with a potting resin 16. For this sealing, a normal potting method used for sealing a TAB package can be applied. When the slit 18 is sealed, the slit 18
, That is, the connection between the chip electrode 13 and the inner lead 14 can be improved in moisture resistance, and the reliability of the semiconductor device can be improved.

As shown in FIG.
The outer part 22 of the LSI chip 6 is similar to the inner part 21 of the LSI chip 6.
Because it is not backed by, it may be weak in strength.
Therefore, reinforcement is performed with the reinforcement frame 10 as necessary. The reinforcing frame 10 is made of the insulating film 1 on the same side as the LSI chip 6.
1 and overlaid on the outer portion 22 and bonded with an adhesive 23. At this time, the reinforcing frame 10 may be bonded to the LSI chip 6.

As described above, according to this embodiment, not only the inner leads are made to project from the rear surface of the chip toward the outside of the slit but also from the outside toward the rear surface of the chip. It can be arranged not only directly below, but also at the periphery of the chip, so that multiple terminals can be arranged.

Next, the above-described embodiment will be described more specifically. Please refer to FIGS. 1 to 6 for the drawings.

(Embodiment 1) The LSI chip 6 has a size of 13 × 1
A 3 mm square and 0.4 mm thick one was prepared. In the peripheral portion of the surface of the LSI chip 6, a space of 0.08 mm
A corner aluminum chip electrode 13 is formed. The number of chip electrodes 13 is 400 pads. Nickel and gold were further plated on the chip electrode 13.

On the other hand, a TAB tape carrier was manufactured as follows. Epoxy adhesive 9, 15 (10 μm thick)
Attached polyimide film 11 (75 μm thickness x 35 mm
Width), a copper foil having a thickness of 35 μm was bonded. Next, a wiring pattern 7 including an inner lead 14, a solder terminal forming land 17 and an internal wiring pattern 12 for bonding to the chip electrode 13 of the LSI chip 6 was formed on the copper foil by photoetching.

The inner leads 14 protrude from the left and right of the slit 18 of the insulating film 11. Tin was provided on the inner lead 14 of the TAB tape carrier 20 by an electroless plating method of about 0.5 μm. Thereafter, the tin-plated inner lead 14 is pressed and bent into the slit 18 so as to be aligned with the gold-plated chip electrode 13 of the LSI chip 6, and
Eutectic bonding of gold and tin was performed by heating at 2 ° C. × 2 seconds. At this time, as shown in FIG. 5, the inner leads 14 were alternately protruded from the left and right sides of the slit 18 and were connected to the chip electrodes 13.

Next, the pattern was covered with a polyimide resin 24 to protect the wiring pattern 7 while leaving the terminal forming lands 17 formed at the other end of the wiring pattern 7.
Thereafter, a eutectic solder paste was applied to the exposed terminal forming lands 17 by a printing method. After application, reflow,
A solder ball terminal 5 was made. The diameter of the solder ball terminal is 0.3 mmφ and the height is 0.25 mm.

BG with this TAB tape carrier
In order to maintain mechanical strength and flatness, a metal rectangular reinforcing frame 10 was attached to the outer periphery of the A package with a polyimide adhesive 23. Next, the bonding portion of the inner lead 14 was sealed with an epoxy potting resin 16.

FIG. 3 is a view showing a T attached to an LSI chip.
FIG. 4 is an enlarged cross-sectional view of a connection portion of inner lead bonding when the AB tape carrier has three layers. That is, epoxy or polyimide adhesives 9, 15 on both surfaces.
The LSI chip 6 is adhered via the adhesive 9 on one side of the insulating film 11 coated with the copper foil, and the copper foil is adhered via the adhesive 15 on the other side. Then, the pattern wiring 7 is formed. Inner lead 1
4 is pressed and bent into a slit 18 formed in a TAB tape carrier having a three-layer structure, so that the pressing and bending angle is slightly larger than in the case of a two-layer structure described later.

FIG. 4 is an enlarged cross-sectional view of a connection portion when inner lead bonding is performed using a two-layer TAB tape carrier. Since no adhesive is formed on one side of the insulating film 11 on which the wiring pattern 7 is to be formed,
The wiring pattern 12 is formed by patterning a copper foil directly formed on one surface of the insulating film 11 by vapor deposition, sputtering, plating, or the like. Since the inner lead 14 is pressed and bent into the slit 18 formed in the TAB tape carrier having a two-layer structure, the bending angle is smaller than that in the case of three layers. Therefore, the chip electrode 13 of the inner lead 14 is more excellent than when the three-layer TAB tape carrier is used.
Positioning is easy and accuracy can be improved.

In any of the three layers and the two layers, the connection between the chip electrode and the inner lead in the slit could be reliably and favorably performed.

Example 2 The inner lead of a TAB tape carrier manufactured in the same manner as in Example 1 was not tin-plated but nickel-plated 2 μm and gold-plated 1 μm thereon. On the other hand, the surface treatment of the chip electrode 13 of the LSI chip was not performed and the aluminum electrode was left as it was. Next, the inner lead and the chip electrode were thermocompression-bonded together with ultrasonic waves using a single point bonder for each pair.
At this time, the inner leads were alternately connected to the chip electrodes from the left and right sides of the slit. After that, solder ball production,
The installation of the reinforcing frame, sealing with potting resin,
It was the same as the example. Also according to the second embodiment, the connection between the chip electrode and the inner lead could be performed reliably and well as in the first embodiment.

(Modifications) Embodiments 1 and 2
In both cases, the inner leads are connected alternately from the left and right, but they need not be connected alternately. As shown in FIG. 6, a plurality of leads may be connected continuously from the same direction for the convenience of wiring.

The connection terminals of a PCB or the like are not limited to ball terminals. For example, as shown in FIG.
It may be. The pin terminal 25 has a pedestal 26 at the base thereof, and the pedestal 26 is manufactured by a so-called forging method in which one end of the pin terminal 25 is crushed round. The pin terminal 25 and the pedestal 26 are made of Kovar, and the surface of the Kovar is plated with gold having a thickness of 1.0 μm.
Terminal forming land connection is performed using a low temperature eutectic temperature of 217 ° C. of n−10 to 40 wt% Au.

(Effects of Embodiment) As described above, according to the present embodiment, ball terminals or pin terminals can be formed on both the back surface and the outside of the LSI chip.
The mounting of the SI chip is possible. The BGA of the present invention
By using a package type semiconductor device, a multi-terminal L
The thin mounting of the SI becomes possible, which can contribute to the thinning of the device itself.

[0038]

According to the present invention, a slit for exposing a chip electrode is formed in an insulating film, and a wiring pattern is provided on both an inner portion and an outer portion of the insulating film defined by the slit . Each of the wiring patterns
The end protrudes above the slit and is bent in the slit
Re since the so that is connected to the tip electrode, not only the back surface of the chip, will be able to form a ball pin or pin terminal to the outside, it can be mounted multi-terminal chip by increasing the number of terminals And multi-terminal LSI
This makes it possible to reduce the thickness of the device itself and contribute to the reduction of the thickness of the device itself.

[Brief description of the drawings]

FIG. 1 is a bottom view of an LSI chip and a bottom view of a BGA package type semiconductor device for explaining an embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional view of the BGA package type semiconductor device of the present embodiment.

FIG. 3 is an enlarged cross-sectional view of a connection portion between a chip electrode and an inner lead when a three-layer TAB tape carrier according to the present embodiment is used.

FIG. 4 is an enlarged cross-sectional view of a connection portion between a chip electrode and an inner lead when a two-layer TAB tape carrier according to the present embodiment is used.

FIG. 5 is a plan view showing a connection example between a chip electrode and an inner lead according to the embodiment.

FIG. 6 is a plan view showing another connection example between the chip electrode and the inner lead according to the embodiment.

FIG. 7 is an enlarged cross-sectional view of a connection portion between a chip electrode and an inner lead in the case of a pin terminal according to the present embodiment.

FIG. 8 shows a BGA using a conventional glass epoxy substrate.
FIG. 3 is a cross-sectional view of a package type semiconductor device.

FIG. 9 shows a BG using a conventional TAB tape carrier.
FIG. 2 is a cross-sectional view of an A package type semiconductor device.

FIG. 10 is a bottom view of the semiconductor device of FIG. 9;

[Explanation of symbols]

 Reference Signs List 5 ball terminal 6 LSI chip 7 wiring pattern 11 insulating film 13 chip electrode 17 terminal forming land 18 slit 21 inner part 22 outer part

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-295935 (JP, A) JP-A-8-78484 (JP, A) JP-A-7-297320 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/60 H01L 23/12 H01L 23/50

Claims (8)

(57) [Claims] An LSI chip having a large number of chip electrodes formed along a peripheral portion of one surface of a chip, an LSI chip having an area larger than that of the LSI chip, affixed to one surface of the chip, and a chip electrode on the one surface. a slit that exposed by forming the peripheral portion, by the slit and the insulating film in the outer portion is partitioned and formed to protrude from the inner portion and the chip corresponding to the chip rear surface, of the inner portion and outer portion of the insulating film Each is formed on the surface, and one end of each is on the slit
To protrude, it is connected to the press-bent the tip electrode within the slit, and a wiring pattern having a terminal forming lands on the other end, and a ball pin or pin terminals for external connection formed on the terminal forming land A semiconductor device, comprising: 2. The insulating film protrudes from the chip.
On the outside, a reinforcement frame is provided to reinforce this.
The semiconductor device according to claim 1. 3. The insulating film is a polyimide film.
And glass epoxy film.
3. The semiconductor device according to claim 1. 4. The method according to claim 1, wherein the wiring pattern is an insulating film.
Adhesive such as epoxy or polyimide on the surface of
Is formed by patterning copper foil pasted through
The semiconductor device according to any one of claims 1 to 3 that. 5. The method according to claim 1, wherein the wiring pattern is directly formed on the copper foil.
Varnish coat imide and paste on one side of the LSI chip
Wear, and the semiconductor device according to any one of 3 claims 1 is configured by patterning the copper foil. 6. The wiring pattern is formed by vapor deposition, sputtering,
2. The method according to claim 1, wherein the copper foil directly formed on the surface of the insulating film with a stick or the like is formed by patterning.
3. The semiconductor device according to any one of 2 . 7. One end of the wiring pattern is formed by an ultrasonic connection method.
And semiconductor device according to any of the 6 claims 1 and is connected to the tip electrode by thermocompression bonding connection method. 8. The solder paste is printed on the ball terminals.
There is a printing reflow method that forms a ball after reflow
Or by positioning a pre-made spherical solder ball
The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is provided by a ball transfer method .