JP2000091488A - Resin-sealed semiconductor device and circuit member used therein - Google Patents

Resin-sealed semiconductor device and circuit member used therein

Info

Publication number
JP2000091488A
JP2000091488A JP27061798A JP27061798A JP2000091488A JP 2000091488 A JP2000091488 A JP 2000091488A JP 27061798 A JP27061798 A JP 27061798A JP 27061798 A JP27061798 A JP 27061798A JP 2000091488 A JP2000091488 A JP 2000091488A
Authority
JP
Japan
Prior art keywords
terminal
external terminal
die pad
resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27061798A
Other languages
Japanese (ja)
Inventor
Yuji Yamaguchi
雄二 山口
Masahito Sasaki
将人 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP27061798A priority Critical patent/JP2000091488A/en
Publication of JP2000091488A publication Critical patent/JP2000091488A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Abstract

PROBLEM TO BE SOLVED: To improve mounting density on a circuit substrate by a method, wherein a die pad provided with a plurality of suspended leads is electrically independently disposed at a substantially center part of a plane, the part of a projection part having an external terminal configuration provided on the reverse face is exposed to the outside, and a semiconductor element is mounted on a die pad surface by electrically insulating each other. SOLUTION: A die pad is electrically disposed independently at a substantially the center part of a plane, where a terminal part 4 is two-dimensionally disposed. A suspension lead 7 is electrically extended independently from four corners of the die pad, and a projection part 8 having an external terminal configuration is provided on the reverse face of the suspension lead 7. A face of the projection part 8 having an external terminal configuration is configured as the same face as the face of an external terminal 4B of the terminal part 4. Next, each terminal 52a of a semiconductor element 52 mounted on the die pad is connected to an internal terminal 4A (a silver-plated layer 5) of the terminal part 4 with a bonding wire 54. Then, the terminal part 4, the die pad, the suspension lead 7, the semiconductor element 52, and the bonding wire 54 are sealed with a sealing member 55, so that a part of the external terminal 4B and the projection part 8 having external terminal configuration is exposed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を搭載
した樹脂封止型の半導体装置とそれに用いられる回路部
材に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device having a semiconductor element mounted thereon and a circuit member used for the semiconductor device.

【0002】[0002]

【従来の技術】近年、半導体装置は、高集積化や小型化
技術の進歩、電気機器の高性能化と軽薄短小化の傾向
(時流)から、LSIのASICに代表されるように、
ますます高集積化、高機能化になってきている。
2. Description of the Related Art In recent years, semiconductor devices have been typified by LSI ASICs due to advances in high integration and miniaturization technologies, and the trend toward higher performance and lighter, thinner and smaller electric appliances (current trend).
It is becoming more and more highly integrated and highly functional.

【0003】これに伴い、リードフレームを用いた樹脂
封止型の半導体装置においても、その開発のトレンド
が、SOJ(Small Outline J−Lea
dedPackage)やQFP(Quad Flat
Package)のような表面実装型のパッケージを
経て、TSOP(Thin Small Outlin
e Package)の開発による薄型化を主軸とした
パッケージの小型化へ進展し、さらにはパッケージ内部
の3次元化によるチップ収納効率向上を目的としたLO
C(Lead On Chip)の構造へと進展してき
た。
Accordingly, the development trend of the resin-encapsulated semiconductor device using a lead frame is based on SOJ (Small Outline J-Lea).
dedPackage) or QFP (Quad Flat)
Through a surface mount type package such as a TSOP (Thin Small Outlin).
ePackage) has been developed to reduce the size of the package with a focus on thinning, and the LO for improving the chip storage efficiency by making the package three-dimensional.
C (Lead On Chip) structure has been developed.

【0004】[0004]

【発明が解決しようとする課題】しかし、樹脂封止型の
半導体装置パッケージには、高集積化、高機能化ととも
に、更に一層の多ピン化、薄型化、小型化が求められて
おり、上記従来のパッケージにおいても半導体素子外周
部分のリードの引き回しがあるため、パッケージの小型
化に限界が見えてきた。
However, resin-encapsulated semiconductor device packages are required to have higher integration, higher functionality, more pins, thinner, and smaller. Even in a conventional package, there is a limit to miniaturization of the package because there is a routing of a lead in an outer peripheral portion of the semiconductor element.

【0005】一方、小型化された樹脂封止型半導体装置
として、エリアアレー型のCSP(Chip Scal
e Package)が提案されている。このCSP
は、半田ボールを用いて回路基板上に搭載されるが、信
頼性の面で問題があったり、用いるポリイミド基板が高
価であるという問題があった。
On the other hand, as a miniaturized resin-sealed semiconductor device, an area array type CSP (Chip Scalp) is used.
ePackage) has been proposed. This CSP
Are mounted on a circuit board using solder balls, but there are problems in terms of reliability and a problem that a polyimide substrate to be used is expensive.

【0006】このため、上記のポリイミド基板を用いた
CSPに比べて信頼性と製造コストの点で有利であり、
かつ、チップサイズでの実装が可能なものとして、汎用
のリードフレームと同じ金属材料を用いた半導体装置の
開発が要望されている。
For this reason, it is advantageous in terms of reliability and manufacturing cost as compared with the CSP using a polyimide substrate, and
In addition, there is a demand for the development of a semiconductor device using the same metal material as a general-purpose lead frame as a device that can be mounted in a chip size.

【0007】本発明は、上記のような事情に鑑みてなさ
れたものであり、半導体素子の占有率が高く小型化が可
能で、回路基板への実装密度を向上させることができ、
さらに、多ピン化への対応が可能な樹脂封止型の半導体
装置と、この樹脂封止型半導体装置に用いられる回路部
材を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a high occupancy rate of a semiconductor element, can be reduced in size, and can improve a mounting density on a circuit board.
It is still another object of the present invention to provide a resin-sealed semiconductor device capable of coping with the increase in the number of pins and a circuit member used for the resin-sealed semiconductor device.

【0008】[0008]

【課題を解決するための手段】このような目的を達成す
るために、本発明の樹脂封止型半導体装置は、表面側に
内部端子を裏面側に外部端子を表裏一体的に有する複数
の端子部を略一平面内に二次元的に互いに電気的に独立
して配置し、端子部の内部端子と半導体素子の端子とを
ワイヤにて電気的に接続し、各端子部の外部端子の一部
を外部に露出させるように全体を樹脂封止した樹脂封止
型半導体装置において、複数個の前記端子部を二次元的
に配置する平面の略中央部に、複数の吊りリードを備え
たダイパッドが電気的に独立して配置され、前記複数の
吊りリードは前記端子部が二次元的に配置された平面内
に延びるとともに、裏面に外部端子形状凸部を備え、か
つ、該外部端子形状凸部の一部が外部に露出し、前記半
導体素子が前記ダイパッドの表面に電気的に絶縁して搭
載されたような構成とした。
In order to achieve the above object, a resin-encapsulated semiconductor device according to the present invention comprises a plurality of terminals having an internal terminal on the front side and an external terminal on the back side integrally formed front and back. Parts are arranged two-dimensionally and electrically independent of each other in a substantially plane, and the internal terminals of the terminal parts and the terminals of the semiconductor element are electrically connected by wires. In a resin-sealed semiconductor device in which the entire portion is resin-sealed so as to expose a portion to the outside, a die pad including a plurality of suspension leads substantially at a central portion of a plane on which a plurality of the terminal portions are two-dimensionally arranged Are electrically independently arranged, and the plurality of suspension leads extend in a plane in which the terminal portions are two-dimensionally arranged, and have an external terminal shape convex portion on the back surface, and the external terminal shape convex portion. A part of the part is exposed to the outside, and the semiconductor element It was electrically insulated as mounted in structure on the surface of the pad.

【0009】また、本発明の樹脂封止型半導体装置は、
前記ダイパッドの表面が前記端子部の内部端子の表面と
略一平面をなすような構成とした。
Further, the resin-encapsulated semiconductor device of the present invention comprises:
The surface of the die pad is substantially flush with the surface of the internal terminal of the terminal portion.

【0010】また、本発明の樹脂封止型半導体装置は、
前記ダイパッドが裏面に1個以上の外部端子形状凸部を
備え、該外部端子形状凸部の一部が外部に露出している
ような構成とした。
Further, the resin-encapsulated semiconductor device of the present invention comprises:
The die pad is provided with one or more external terminal-shaped protrusions on the back surface, and a part of the external terminal-shaped protrusions is exposed to the outside.

【0011】さらに、本発明の樹脂封止型半導体装置
は、外部に露出している外部端子および外部端子形状凸
部に半田からなる外部電極を設けたような構成とした。
Further, the resin-encapsulated semiconductor device of the present invention is configured such that external terminals exposed to the outside and external electrodes made of solder are provided on the external terminal-shaped projections.

【0012】本発明の回路部材は、樹脂封止型半導体装
置用の回路部材であって、外枠部材と、該外枠部材から
各々接続リードを介して相互に独立して突設された複数
の端子部と、前記外枠部材から複数の吊りリードを介し
て保持されたダイパッドとを備え、各端子部は表面側に
内部端子を裏面側に外部端子を表裏一体的に有し、前記
吊りリードは裏面に外部端子形状凸部を備え、前記外部
端子面と前記外部端子形状凸部面は略一平面上に位置し
ているような構成とした。
A circuit member according to the present invention is a circuit member for a resin-encapsulated semiconductor device. The circuit member includes an outer frame member and a plurality of protrusions independently protruding from the outer frame member via connection leads. And a die pad held from the outer frame member via a plurality of suspension leads, each terminal section having an internal terminal on the front side and external terminals on the back side integrally with the front and back, The lead was provided with an external terminal-shaped convex portion on the back surface, and the external terminal surface and the external terminal-shaped convex portion surface were located on substantially one plane.

【0013】また、本発明の回路部材は、前記ダイパッ
ドの表面が前記端子部の内部端子の表面と略一平面をな
すような構成とした。
Further, the circuit member of the present invention is configured such that the surface of the die pad is substantially flush with the surface of the internal terminal of the terminal portion.

【0014】また、本発明の回路部材は、前記ダイパッ
ドが裏面に1個以上の外部端子形状凸部を備え、該外部
端子形状凸部面と前記外部端子面は略一平面上に位置し
ているような構成とした。
Further, in the circuit member of the present invention, the die pad has one or more external terminal-shaped convex portions on the back surface, and the external terminal-shaped convex surface and the external terminal surface are positioned on substantially one plane. Configuration.

【0015】さらに、本発明の回路部材は、ダイパッド
の表面に電気絶縁性の両面接着テープが一体的に設けら
れているような構成とした。
Further, the circuit member of the present invention is configured such that an electrically insulating double-sided adhesive tape is integrally provided on the surface of the die pad.

【0016】このような本発明では、半導体素子の占有
率が向上するとともに、ダイパッドから延びる吊りリー
ドの裏面に設けられた外部端子形状凸部やダイパッドの
裏面に設けられた外部端子形状凸部が、半田ボールを使
わないLGA(Land Grid Array)のよ
うな回路基板への樹脂封止型半導体装置の搭載におい
て、端子部の外部端子と同様に回路基板へ接続されるこ
とにより、端子部の外部端子1個あたりの応力負荷を軽
減する作用をなし、また、半田ボールを用いたBGA
(Ball Grid Array)のような樹脂封止
型半導体装置の回路基板への搭載において、端子部の外
部端子と同様に半田ボールを介して回路基板へ接続され
ることにより、1個あたりの半田ボールへの応力負荷を
軽減する作用をなす。
According to the present invention, the occupancy of the semiconductor element is improved, and the external terminal-shaped projection provided on the back surface of the suspension lead extending from the die pad and the external terminal-shaped projection provided on the back surface of the die pad are provided. In mounting a resin-encapsulated semiconductor device on a circuit board such as an LGA (Land Grid Array) that does not use solder balls, the external part of the terminal part is connected to the circuit board in the same manner as the external terminal of the terminal part. BGA that reduces stress load per terminal and uses solder balls
When mounting a resin-encapsulated semiconductor device such as a (Ball Grid Array) on a circuit board, each of the solder balls is connected to the circuit board via a solder ball in the same manner as an external terminal of a terminal portion. It acts to reduce the stress load on the body.

【0017】[0017]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。本発明の回路部材 図1は本発明の回路部材の一実施形態を示す平面図、図
2は図1に示される回路部材のA−A線矢視における縦
断面図、図3は図1に示される回路部材のB−B線矢視
における縦断面図である。図1乃至図3において、本発
明の回路部材1は、外枠部材2と、この外枠部材2の内
側端辺2aから接続リード3を介して相互に独立して突
設された複数の端子部4と、外枠部材2の内側端辺2a
の所定の箇所(図示例では、外枠部材2の内側端辺2a
の四隅)から吊りリード7を介して配設されたダイパッ
ド6とを備えるものである。
Embodiments of the present invention will be described below with reference to the drawings. Plan view showing an embodiment of a circuit member for a circuit member Figure 1 the invention of the present invention, FIG. 2 is a longitudinal sectional view along A-A taken along the line of the circuit member shown in FIG. 1, FIG. 3 to FIG. 1 It is a longitudinal cross-sectional view in the BB line arrow of the circuit member shown. 1 to 3, a circuit member 1 according to the present invention includes an outer frame member 2 and a plurality of terminals projecting from an inner end 2 a of the outer frame member 2 via connection leads 3 independently of each other. Part 4 and inner edge 2a of outer frame member 2
At a predetermined location (in the illustrated example, the inner side edge 2a of the outer frame member 2)
And the die pad 6 disposed from the four corners) via the suspension leads 7.

【0018】外枠部材2は、外形形状および内側開口形
状が矩形の回廊形状であり、各接続リード3は外枠部材
2の内側端辺2aから同一平面内に突設されている。
The outer frame member 2 has a rectangular corridor having an outer shape and an inner opening shape, and each connection lead 3 is projected from the inner side 2a of the outer frame member 2 in the same plane.

【0019】端子部4は、接続リード3の先端に設けら
れ、表面側に内部端子4Aを裏面側に外部端子4Bを表
裏一体的に有している。図示例では、内部端子4A上に
銀めっき層5が設けられており、また、各外部端子4B
面は略同一平面上に位置している。
The terminal portion 4 is provided at the tip of the connection lead 3, and has an internal terminal 4A on the front side and an external terminal 4B on the rear side integrally. In the illustrated example, a silver plating layer 5 is provided on the internal terminals 4A, and the external terminals 4B
The surfaces are located on substantially the same plane.

【0020】ダイパッド6は端子4と同一の厚みをも
ち、上述のように外枠部材2の内側端辺2aの四隅から
延設された4本の吊りリード7に支持されている。この
吊りリード7の裏面には、外部端子形状凸部8が設けら
れており、この外部端子形状凸部8面は、外部端子4B
面と略同一平面上に位置している。
The die pad 6 has the same thickness as the terminal 4 and is supported by the four suspension leads 7 extending from the four corners of the inner end 2a of the outer frame member 2 as described above. An external terminal-shaped convex portion 8 is provided on the back surface of the suspension lead 7, and the external terminal-shaped convex portion 8
It is located on substantially the same plane as the surface.

【0021】このような回路部材1の材質は、42合金
(Ni41%のFe合金)、銅、銅合金等とすることが
できる。
The material of such a circuit member 1 can be 42 alloy (Ni 41% Fe alloy), copper, copper alloy or the like.

【0022】また、本発明の回路部材1は、ダイパッド
6の表面側6aに電気絶縁性の両面接着テープが一体的
に設けられたものであってもよい。両面接着テープは、
電気絶縁性のベースフィルムの両面に接着剤層を備えた
ものであり、例えば、ユーピレックス(宇部興産(株)
製の電気絶縁性フィルム)の両面にRXF((株)巴川
製紙所製の接着剤)層を備えたUX1W((株)巴川製
紙所製)のような両面接着テープを使用することができ
る。
The circuit member 1 of the present invention may be one in which an electrically insulating double-sided adhesive tape is integrally provided on the front side 6a of the die pad 6. Double-sided adhesive tape
It has an adhesive layer on both sides of an electrically insulating base film. For example, UPILEX (Ube Industries, Ltd.)
Double-sided adhesive tape such as UX1W (manufactured by Hamakawa Paper Co., Ltd.) having RXF (adhesive manufactured by Hamakawa Paper Mills) layers on both sides of an electrically insulating film (manufactured by Hamakawa Paper Mills) can be used.

【0023】図4は本発明の回路部材の他の実施形態を
示す図2相当の縦断面図、図5は同じく図3相当の縦断
面図である。図4および図5において、本発明の回路部
材11は、外枠部材12と、この外枠部材12の内側端
辺から接続リード13を介して相互に独立して突設され
た複数の端子部14と、外枠部材12の内側端辺の所定
の箇所(図示例では、外枠部材12の内側端辺の四隅)
から吊りリード17を介して配設されたダイパッド16
とを備えるものである。そして、端子部14は表面側に
内部端子14Aを裏面側に外部端子14Bを表裏一体的
に有し、吊りリード17の裏面には、外部端子形状凸部
18が設けられており、この外部端子形状凸部18面
は、外部端子14B面と略同一平面上に位置している。
FIG. 4 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the circuit member of the present invention, and FIG. 5 is a longitudinal sectional view equivalent to FIG. 4 and 5, a circuit member 11 according to the present invention includes an outer frame member 12 and a plurality of terminal portions protruding from the inner end of the outer frame member 12 via connection leads 13 independently of each other. 14 and predetermined locations on the inner edge of the outer frame member 12 (four corners of the inner edge of the outer frame member 12 in the illustrated example)
From a die pad 16 disposed via a suspension lead 17
Is provided. The terminal portion 14 has an internal terminal 14A on the front surface side and an external terminal 14B on the back surface integrally on the front and back sides, and an external terminal-shaped convex portion 18 is provided on the back surface of the suspension lead 17. The surface of the shape convex portion 18 is located on substantially the same plane as the surface of the external terminal 14B.

【0024】この回路部材11では、ダイパッド16は
端子部14の略半分の厚みをもち、表面側16aは端子
部14の内部端子14A面と略同一平面上に位置してい
る。
In this circuit member 11, the die pad 16 has a thickness that is approximately half the thickness of the terminal portion 14, and the front side 16a is located on substantially the same plane as the surface of the internal terminal 14A of the terminal portion 14.

【0025】図6は本発明の回路部材の他の実施形態を
示す図2相当の縦断面図である。図6において、本発明
の回路部材21は、外枠部材22と、この外枠部材22
の内側端辺から接続リード23を介して相互に独立して
突設された複数の端子部24と、外枠部材22の内側端
辺の所定の箇所(図示例では、外枠部材22の内側端辺
の四隅)から吊りリード(図示せず)を介して配設され
たダイパッド26とを備えるものである。そして、端子
部24は表面側に内部端子24Aを裏面側に外部端子2
4Bを表裏一体的に有し、図示しない吊りリードの裏面
には、回路部材1の吊りリード7と同様に、外部端子形
状凸部(図示せず)が設けられており、この外部端子形
状凸部面は、外部端子24B面と略同一平面上に位置し
ている。
FIG. 6 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the circuit member of the present invention. 6, a circuit member 21 of the present invention includes an outer frame member 22 and an outer frame member 22.
And a plurality of terminal portions 24 projecting independently from each other via connection leads 23 from the inner side of the outer frame member 22 at predetermined locations (in the illustrated example, the inner side of the outer frame member 22). A die pad 26 is provided from the four corners (ends) via suspension leads (not shown). The terminal section 24 has an internal terminal 24A on the front side and an external terminal 2A on the rear side.
4B are integrally formed on the front and back sides, and on the back surface of the suspension lead (not shown), an external terminal shape convex portion (not shown) is provided similarly to the suspension lead 7 of the circuit member 1. The component surface is located on substantially the same plane as the external terminal 24B surface.

【0026】この回路部材21では、ダイパッド26は
端子部24の略半分の厚みをもち、裏面側26bには複
数の外部端子形状凸部29が設けられている。このよう
な外部端子形状凸部29は、ダイパッド26の裏面側2
6bの外周部に沿って所定の間隔で設けることができ、
また、ダイパッド26の裏面側26bの中央に1個以上
設けてもよい。
In this circuit member 21, the die pad 26 has substantially half the thickness of the terminal portion 24, and a plurality of external terminal-shaped projections 29 are provided on the back surface 26b. Such an external terminal-shaped projection 29 is provided on the rear surface 2 of the die pad 26.
6b can be provided at predetermined intervals along the outer peripheral portion,
Also, one or more die pads 26 may be provided at the center of the back side 26b.

【0027】図7は本発明の回路部材の他の実施形態を
示す図2相当の縦断面図である。図7において、本発明
の回路部材31は、外枠部材32と、この外枠部材32
の内側端辺から接続リード33を介して相互に独立して
突設された複数の端子部34と、外枠部材32の内側端
辺の所定の箇所(図示例では、外枠部材32の内側端辺
の四隅)から吊りリード(図示せず)を介して配設され
たダイパッド36とを備えるものである。そして、端子
部34は表面側に内部端子34Aを裏面側に外部端子3
4Bを表裏一体的に有し、図示しない吊りリードの裏面
には、回路部材1の吊りリード7と同様に、外部端子形
状凸部(図示せず)が設けられており、この外部端子形
状凸部面は、外部端子34B面と略同一平面上に位置し
ている。
FIG. 7 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the circuit member of the present invention. 7, a circuit member 31 according to the present invention includes an outer frame member 32 and the outer frame member 32.
A plurality of terminal portions 34 projecting independently from each other through connection leads 33 from the inner side of the outer frame member 32 and a predetermined portion of the inner side of the outer frame member 32 (in the illustrated example, the inner side of the outer frame member 32). A die pad 36 is provided from the four corners (ends) via suspension leads (not shown). The terminal section 34 has an internal terminal 34A on the front side and an external terminal 3A on the rear side.
4B are integrally formed on the front and back sides, and on the back surface of the suspension lead (not shown), an external terminal shape convex portion (not shown) is provided similarly to the suspension lead 7 of the circuit member 1. The component surface is located on substantially the same plane as the external terminal 34B surface.

【0028】この回路部材31では、ダイパッド36は
端子部34と略同じ大きさで略半分の厚みをもち、裏面
側に外部端子形状凸部39が設けられ、すなわち、ダイ
パッド36は端子部34と略同じ形状を有している。
In this circuit member 31, the die pad 36 has substantially the same size and approximately half thickness as the terminal portion 34, and is provided with an external terminal-shaped convex portion 39 on the back surface side. They have substantially the same shape.

【0029】このような回路部材11,21,31の材
質は、42合金(Ni41%のFe合金)、銅、銅合金
等とすることができる。
The material of such circuit members 11, 21, 31 can be 42 alloy (Ni 41% Fe alloy), copper, copper alloy or the like.

【0030】また、本発明の回路部材11,21,31
は、ダイパッド16,26,36の表面側16a,26
a,36aに電気絶縁性の両面接着テープが一体的に設
けられたものであってもよい。両面接着テープは、電気
絶縁性のベースフィルムの両面に接着剤層を備えたもの
であり、例えば、ユーピレックス(宇部興産(株)製の
電気絶縁性フィルム)の両面にRXF((株)巴川製紙
所製の接着剤)層を備えたUX1W((株)巴川製紙所
製)のような両面接着テープを使用することができる。
The circuit members 11, 21, 31 of the present invention
Are the front sides 16a, 26 of the die pads 16, 26, 36.
a, 36a may be provided with an electrically insulating double-sided adhesive tape integrally provided. The double-sided adhesive tape is provided with an adhesive layer on both sides of an electrically insulating base film. For example, RXF (Hawakawa Paper Co., Ltd.) is provided on both sides of Upilex (an electrically insulating film manufactured by Ube Industries, Ltd.). A double-sided adhesive tape such as UX1W (manufactured by Hamakawa Paper Mills) having an adhesive (made in Japan) layer can be used.

【0031】尚、上述の回路部材1,11,21,31
における端子数、端子配列、吊りリード位置、外部端子
形状凸部の個数、配置等は例示であり、本発明の回路部
材はこれに限定されるものではない。例えば、1つの吊
りリードの裏面に複数の外部端子形状凸部を設けてもよ
い。本発明の樹脂封止型半導体装置 図8は図1乃至図3に示される本発明の回路部材を使用
した本発明の樹脂封止型半導体装置の一実施形態を示す
平面図であり、図9は図8に示される樹脂封止型半導体
装置のC−C線矢視における縦断面図であり、図10は
図8に示される樹脂封止型半導体装置のD−D線矢視に
おける縦断面図である。尚、半導体装置の構成を理解し
やすくするために、図8では後述する封止部材55を省
略し、図9および図10では封止部材55を仮想線(2
点鎖線)で示している。
The above-mentioned circuit members 1, 11, 21, 31
, The number of terminals, the arrangement of the terminals, the positions of the suspension leads, the number and arrangement of the external terminal-shaped protrusions, and the like are examples, and the circuit member of the present invention is not limited thereto. For example, a plurality of external terminal-shaped protrusions may be provided on the back surface of one suspension lead. Resin-sealed semiconductor device 8 of the present invention is a plan view showing an embodiment of a resin-sealed semiconductor device of the present invention using a circuit member of the invention shown in FIGS. 1 to 3, 9 FIG. 10 is a vertical cross-sectional view of the resin-encapsulated semiconductor device shown in FIG. 8 taken along line CC. FIG. 10 is a vertical cross-sectional view of the resin-encapsulated semiconductor device shown in FIG. FIG. In order to facilitate understanding of the configuration of the semiconductor device, a sealing member 55 to be described later is omitted in FIG. 8, and the sealing member 55 is indicated by a virtual line (2 in FIGS. 9 and 10).
(Dashed line).

【0032】図8乃至図10において、本発明の樹脂封
止型半導体装置51は、ダイパッド6の表面側6aに電
気絶縁性の両面接着テープ53を介して半導体素子52
がその端子面と反対の面を固着され搭載されている。搭
載されている半導体素子52の端子52aは、半導体素
子52の各辺に沿って配置されている。
8 to 10, a resin-sealed semiconductor device 51 according to the present invention has a semiconductor element 52 on the front side 6a of a die pad 6 with an electrically insulating double-sided adhesive tape 53 interposed therebetween.
Is fixedly mounted on the surface opposite to the terminal surface. The terminals 52 a of the mounted semiconductor element 52 are arranged along each side of the semiconductor element 52.

【0033】端子部4は、表面側に内部端子4Aを裏面
側に外部端子4Bを表裏一対的に有しており、各端子部
4は略一平面内に二次元的に互いに電気的に独立して配
置されている。
The terminal section 4 has a pair of internal terminals 4A on the front side and a pair of external terminals 4B on the back side, and the terminal sections 4 are two-dimensionally electrically independent of each other in substantially one plane. It is arranged.

【0034】また、ダイパッド6は、端子部4が二次元
的に配置されている平面の略中央に端子部4から電気的
に独立して配置されている。このダイパッド6の四隅か
らは、吊りリード7が、端子部4が二次元的に配置され
ている平面内に電気的に独立して延びており、この吊り
リード7の裏面には外部端子形状凸部8が設けられてい
る。この外部端子形状凸部8面は、上記の端子部4の外
部端子4B面と略同一面を構成している。
The die pad 6 is arranged at substantially the center of the plane on which the terminal portions 4 are two-dimensionally arranged, independently of the terminal portions 4. From four corners of the die pad 6, suspension leads 7 extend electrically independently in a plane where the terminal portions 4 are two-dimensionally arranged. A part 8 is provided. The surface of the external terminal-shaped projection 8 constitutes substantially the same surface as the surface of the external terminal 4B of the terminal portion 4.

【0035】また、ダイパッド6に搭載されている半導
体素子52の各端子52aは、端子部4の内部端子4A
(銀めっき層5)にボンディングワイヤ54によって接
続されている。
Each terminal 52a of the semiconductor element 52 mounted on the die pad 6 is connected to the internal terminal 4A of the terminal portion 4.
(Silver plating layer 5) is connected by a bonding wire 54.

【0036】そして、外部端子4Bの一部、および、外
部端子形状凸部8の一部を外部に露出させるように端子
部4、ダイパッド6、吊りリード7、半導体素子52お
よびボンディングワイヤ54が封止部材55により封止
されている。封止部材55は、樹脂封止型半導体装置に
使用されている公知の樹脂材料を用いて形成することが
できる。図示例では、外部に露出している外部端子4B
に半田からなる外部電極56が設けられ、また、外部に
露出している外部端子形状凸部8に半田からなる外部電
極57が設けられている。これにより、BGA(Bal
l GridArray)タイプの半導体装置となって
いる。
The terminal portion 4, the die pad 6, the suspension leads 7, the semiconductor element 52, and the bonding wires 54 are sealed so that a part of the external terminal 4B and a part of the external terminal shape projection 8 are exposed to the outside. It is sealed by the stop member 55. The sealing member 55 can be formed using a known resin material used for a resin-sealed semiconductor device. In the illustrated example, the external terminals 4B exposed to the outside
Is provided with an external electrode 56 made of solder, and an external electrode 57 made of solder is provided on the external terminal-shaped projection 8 exposed to the outside. Thereby, BGA (Bal
(1 Grid Array) type semiconductor device.

【0037】このような樹脂封止型半導体装置51で
は、外部電極56を用いて回路基板へ搭載する場合、半
導体装置51と回路基板との導通に寄与する外部電極5
6に加えて、ダミー電極である外部端子形状凸部8に設
けた外部電極57が存在することにより、1個あたりの
外部電極(半田ボール)への応力負荷が軽減される。
In such a resin-sealed semiconductor device 51, when the semiconductor device 51 is mounted on a circuit board using the external electrodes 56, the external electrodes 5 contributing to conduction between the semiconductor device 51 and the circuit board are provided.
In addition to 6, the presence of the external electrode 57 provided on the external terminal-shaped projection 8 serving as a dummy electrode reduces the stress load on each external electrode (solder ball).

【0038】また、上記のような半田からなる外部電極
56,57を設けていない本発明の樹脂封止型半導体装
置では、LGA(Land Grid Array)の
ような回路基板への樹脂封止型半導体装置の搭載におい
て、外部端子形状凸部8が端子部4の外部端子4Bと同
様に回路基板へ接続されることにより、端子部4の外部
端子1個あたりの応力負荷が軽減される。
In the resin-sealed semiconductor device of the present invention in which the external electrodes 56 and 57 made of solder are not provided, the resin-sealed semiconductor device such as an LGA (Land Grid Array) is mounted on a circuit board. In mounting the device, the external terminal-shaped projection 8 is connected to the circuit board in the same manner as the external terminal 4B of the terminal portion 4, so that the stress load per external terminal of the terminal portion 4 is reduced.

【0039】さらに、本発明の樹脂封止型半導体装置
は、パッケージの下面から端子をとるというエリアアレ
ータイプであるため、パッケージサイズと回路基板への
実装に必要な面積が同一であり、高密度の基板実装が可
能である。
Further, since the resin-sealed semiconductor device of the present invention is an area array type in which terminals are taken from the lower surface of the package, the package size and the area required for mounting on a circuit board are the same, Can be mounted on a substrate.

【0040】上記の樹脂封止型半導体装置51は、本発
明の回路部材1を用いた実施形態であるが、上述の本発
明の回路部材11,21,31を用いて、ダイパッド上
に半導体素子を搭載し、半導体素子の各端子と、端子部
の内部端子とをボンディングワイヤによって接続し、外
部端子の一部、および、外部端子形状凸部の一部を外部
に露出させるように端子部、ダイパッド、吊りリード、
半導体素子およびボンディングワイヤを封止部材により
封止して、本発明の樹脂封止型半導体装置とすることが
できる。特に、ダイパッド26,36の裏面に外部電極
形状凸部を備えた回路部材21,31では、上記のダミ
ー電極である外部端子形状凸部に設けた外部電極数が増
加するので、1個あたりの外部電極(半田ボール)への
応力負荷が軽減がより顕著となる。
The above-described resin-sealed semiconductor device 51 is an embodiment using the circuit member 1 of the present invention. However, by using the above-described circuit members 11, 21 and 31 of the present invention, a semiconductor element is mounted on a die pad. Is mounted, each terminal of the semiconductor element is connected to the internal terminal of the terminal portion by a bonding wire, a part of the external terminal, and a terminal portion such that a part of the external terminal shape convex portion is exposed to the outside, Die pad, suspension lead,
The semiconductor element and the bonding wire are sealed with the sealing member, whereby the resin-sealed semiconductor device of the present invention can be obtained. In particular, in the circuit members 21 and 31 having the external electrode-shaped protrusions on the back surfaces of the die pads 26 and 36, the number of external electrodes provided on the external terminal-shaped protrusions serving as the dummy electrodes described above increases. The stress load on the external electrodes (solder balls) is more remarkably reduced.

【0041】尚、上述の樹脂封止型半導体装置51にお
ける端子数、端子配列、吊りリード位置、外部端子形状
凸部の個数、配置等は例示であり、本発明の樹脂封止型
半導体装置がこれに限定されないことは勿論である。回路部材と樹脂封止型半導体装置の製造方法 ここで、本発明の回路部材と樹脂封止型半導体装置の製
造方法について、図1乃至図3に示される回路部材と、
図8乃至図10に示される樹脂封止型半導体装置を例に
して説明する。
The number of terminals, the arrangement of terminals, the positions of the suspension leads, the number and arrangement of the convex portions of the external terminal shape, and the like in the above-described resin-sealed semiconductor device 51 are merely examples. Of course, it is not limited to this. Circuit member and method of manufacturing resin-encapsulated semiconductor device Here, the circuit member of the present invention and the method of manufacturing a resin-encapsulated semiconductor device will be described with reference to the circuit member shown in FIGS.
The resin-sealed semiconductor device shown in FIGS. 8 to 10 will be described as an example.

【0042】図11と図12は、図1乃至図3に示され
る本発明の回路部材1と、この回路部材1を用いた樹脂
封止型半導体装置51の製造の一例を示す工程図であ
る。図11の各工程は、上記の図2に対応する回路部材
の縦断面図で示してあり、図12の各工程は、上記の図
3に対応する回路部材の縦断面図で示してある。
FIGS. 11 and 12 are process diagrams showing an example of manufacturing the circuit member 1 of the present invention shown in FIGS. 1 to 3 and the resin-sealed semiconductor device 51 using the circuit member 1. . Each step of FIG. 11 is shown in a longitudinal sectional view of the circuit member corresponding to FIG. 2 described above, and each step of FIG. 12 is shown in a longitudinal sectional view of the circuit member corresponding to FIG.

【0043】まず、回路部材1を製造する。図11およ
び図12において、導電性基板101の表裏に感光性レ
ジストを塗布、乾燥し、これを所望のフォトマスクを介
して露光した後、現像してレジストパターン102A,
102Bを形成する(図11(A)、図12(A))。
導電性基板101としては、上述のように42合金(N
i41%のFe合金)、銅、銅合金等の金属基板(厚み
100〜250μm)を使用することができ、この導電
性基板101は、両面を脱脂等を行い洗浄処理を施した
ものを使用することが好ましい。また、感光性レジスト
としては、従来公知のものを使用することができる。
First, the circuit member 1 is manufactured. 11 and 12, a photosensitive resist is applied to the front and back of the conductive substrate 101, dried, exposed through a desired photomask, and then developed to form a resist pattern 102A,
102B are formed (FIGS. 11A and 12A).
As described above, the conductive substrate 101 is made of 42 alloy (N
A metal substrate (thickness of 100% to 250 μm) of i41% Fe alloy), copper, copper alloy, or the like can be used. Is preferred. Further, as the photosensitive resist, conventionally known ones can be used.

【0044】次に、レジストパターン102A,102
Bを耐腐蝕膜として導電性基板101に腐蝕液でエッチ
ングを行う(図11(B)、図12(B))。腐蝕液
は、使用する導電性基板101の材質に応じて適宜選択
することができ、例えば、導電性基板101として42
合金を用いる場合、通常、塩化第二鉄水溶液を使用し、
導電性基板101の両面からスプレーエッチングにて行
う。
Next, the resist patterns 102A, 102
The conductive substrate 101 is etched with a corrosion liquid using B as a corrosion-resistant film (FIGS. 11B and 12B). The corrosion liquid can be appropriately selected depending on the material of the conductive substrate 101 to be used.
When using an alloy, usually, an aqueous solution of ferric chloride is used,
This is performed by spray etching from both sides of the conductive substrate 101.

【0045】次いで、レジストパターン102A,10
2Bを剥離して除去し、端子部4の内部端子4Aの位置
に銀めっき層5を形成することにより、端子部4が接続
リード3により外枠部材2に一体的に連結され、外枠部
材2の所定位置から吊りリード7(図示せず)により支
持されたダイパッド6を備え、吊りリード7の裏面に外
部端子形状凸部8を有した回路部材1が得られる(図1
1(C)、図12(C))。
Next, the resist patterns 102A, 102A
2B is peeled and removed, and a silver plating layer 5 is formed at the position of the internal terminal 4A of the terminal portion 4, whereby the terminal portion 4 is integrally connected to the outer frame member 2 by the connection lead 3, and the outer frame member 2 is provided with a die pad 6 supported by a suspension lead 7 (not shown) from a predetermined position, and a circuit member 1 having an external terminal-shaped projection 8 on the back surface of the suspension lead 7 is obtained (FIG. 1).
1 (C), FIG. 12 (C)).

【0046】次に、ダイパッド6の表面側6aに電気絶
縁性の両面接着テープ53を貼付し、この両面接着テー
プ53を介して半導体素子52の回路形成面の裏面側を
固着することにより、半導体素子52を搭載する(図1
1(D)、図12(D))。
Next, an electrically insulating double-sided adhesive tape 53 is attached to the front side 6 a of the die pad 6, and the back surface side of the circuit forming surface of the semiconductor element 52 is fixed via the double-sided adhesive tape 53, thereby forming a semiconductor. The element 52 is mounted (FIG. 1
1 (D), FIG. 12 (D)).

【0047】次いで、搭載した半導体素子52の端子5
2aと、回路部材1の内部端子4Aの銀めっき層5と
を、ボンディングワイヤ54で電気的に接続し、外部端
子4Bの一部と、外部端子形状凸部8の一部とを外部に
露出させるようにして、端子部4、ダイパッド6、吊り
リード7、半導体素子52およびボンディングワイヤ5
4を封止部材55で封止する(図11(E)、図12
(E))。
Next, the terminal 5 of the mounted semiconductor element 52
2a and the silver plating layer 5 of the internal terminal 4A of the circuit member 1 are electrically connected by a bonding wire 54, and a part of the external terminal 4B and a part of the external terminal-shaped projection 8 are exposed to the outside. The terminal portion 4, the die pad 6, the suspension lead 7, the semiconductor element 52, and the bonding wire 5
4 is sealed with a sealing member 55 (FIG. 11E, FIG. 12).
(E)).

【0048】次に、封止部材55から露出している回路
部材1の各接続リード3と各吊りリード7を切断し外枠
部材2を除去して、本発明の半導体装置51とする(図
11(F)、図12(F))。その後、外部に露出して
いる外部端子4Bに半田からなる外部電極56を形成
し、また、外部に露出している外部端子形状凸部8に半
田からなる外部電極57を形成する。
Next, the connection leads 3 and the suspension leads 7 of the circuit member 1 exposed from the sealing member 55 are cut, and the outer frame member 2 is removed to obtain a semiconductor device 51 of the present invention (FIG. 11 (F), FIG. 12 (F)). Thereafter, an external electrode 56 made of solder is formed on the external terminal 4B exposed to the outside, and an external electrode 57 made of solder is formed on the external terminal-shaped projection 8 exposed to the outside.

【0049】[0049]

【実施例】次に、具体的な実施例を挙げて本発明を更に
詳細に説明する。 (回路部材の作製)導電性基板として厚み0.15mm
の42合金を準備し、脱脂処理、洗浄処理を行った後、
この導電性基板の両面に紫外線硬化型レジスト(東京応
化工業(株)製OFPR1305)を掛け流し法により
塗布して乾燥した。次いで、表面側および裏面側のレジ
スト層をそれぞれ所定のフォトマスクを介して露光した
後、現像してレジストパターンを形成した。その後、導
電性基板の両面から塩化第二鉄水溶液を使用してスプレ
ーエッチングを行い、洗浄後、有機アルカリ溶液を用い
てレジストパターンを剥離除去した。
Next, the present invention will be described in more detail with reference to specific examples. (Production of a circuit member) 0.15 mm thick as a conductive substrate
After preparing the 42 alloy, and performing degreasing and cleaning,
An ultraviolet-curable resist (OFPR1305 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied to both sides of the conductive substrate by a pouring method and dried. Next, the resist layers on the front side and the back side were respectively exposed through a predetermined photomask, and then developed to form a resist pattern. Thereafter, spray etching was performed on both surfaces of the conductive substrate using an aqueous ferric chloride solution, and after cleaning, the resist pattern was peeled off using an organic alkali solution.

【0050】次に、内部端子面に銀めっき層(厚み約5
μm)を形成した後、ダイパッドの表面に電気絶縁性の
両面接着テープ(巴川製紙所(株)製UH1W)を貼合
して回路部材とした。この回路部材は、外枠部材から接
続リードを介して72個の端子部が設けられ、また、外
枠部材の四隅から吊りリードを介してダイパッドが設け
られ、上記の各吊りリードの裏面には、2個の外部端子
形状凸部が形成されたものである。 (半導体装置の作製)上記の回路部材の両面接着テープ
に半導体素子(寸法6mm四方、厚み約250μm)の
回路形成面の裏面側を圧着して加熱(180℃)するこ
とにより固着して半導体素子を搭載した。次いで、回路
部材の内部端子上の銀めっき層と搭載した半導体素子の
端子とを金線により結線した。その後、外部端子の一部
と、外部端子形状凸部の一部を外部に露出させるように
して、端子部、ダイパッド、吊りリード、半導体素子お
よび金線を樹脂材料(日東電工(株)製MP−740
0)で封止した。
Next, a silver plating layer (having a thickness of about 5
μm), an electrically insulating double-sided adhesive tape (UH1W manufactured by Tomagawa Paper Mills Co., Ltd.) was bonded to the surface of the die pad to obtain a circuit member. In this circuit member, 72 terminal portions are provided from the outer frame member via connection leads, and die pads are provided from the four corners of the outer frame member via hanging leads. And two external terminal-shaped projections. (Production of Semiconductor Device) The back surface side of the circuit forming surface of the semiconductor element (dimensions: 6 mm square, thickness: about 250 μm) is pressed against the double-sided adhesive tape of the above-mentioned circuit member and fixed by heating (180 ° C.). Equipped. Next, the silver plating layer on the internal terminal of the circuit member and the terminal of the mounted semiconductor element were connected by a gold wire. Then, by exposing a part of the external terminal and a part of the convex part of the external terminal shape to the outside, the terminal part, the die pad, the suspension lead, the semiconductor element and the gold wire are made of a resin material (MP manufactured by Nitto Denko Corporation). -740
0).

【0051】次に、露出している回路部材の各接続リー
ドと各吊りリードを切断して外枠部材を除去し、外部に
露出している外部端子と外部端子形状凸部に半田からな
るボールを接着して外部電極を形成した。
Next, each connection lead and each suspension lead of the exposed circuit member are cut to remove the outer frame member, and the external terminal exposed to the outside and the ball formed of solder on the external terminal shape convex portion are formed. Were bonded to form external electrodes.

【0052】このようにして作製した樹脂封止型半導体
装置は外部端子数が72ピンのBGAであり、その外形
寸法は10mm四方、厚みが0.8mmであり、非常に
小型で薄いものであった。また、半導体装置の下面から
端子を取るというエリアアレータイプであるために、パ
ッケージサイズと回路基板実装に必要な面積が同一とな
り、高密度の基板実装が可能となった。
The resin-encapsulated semiconductor device manufactured as described above is a BGA having 72 external pins, its external dimensions are 10 mm square and 0.8 mm thick, and it is very small and thin. Was. Further, since the area array type is such that terminals are taken from the lower surface of the semiconductor device, the package size and the area required for mounting the circuit board are the same, and high-density board mounting is possible.

【0053】また、上記の樹脂封止型半導体装置は、電
極として用いられる外部電極が72ピンであるが、他に
8ピンの外部電極が吊りリードの外部端子形状凸部に設
けられている。これらの合計80ピンの半田ボールから
なる外部電極を用いて回路基板に実装し、温度サイクル
試験(−25℃から+125℃までの温度変化を60分
サイクルで繰り返す)を実施した結果、650サイクル
経過しても半田ボールにクラック(チップ割れ)が発生
せず、実用レベルの安定性を有していることが確認され
た。
In the above resin-encapsulated semiconductor device, the external electrode used as an electrode has 72 pins, and an external electrode of 8 pins is additionally provided on the external terminal-shaped projection of the suspension lead. After mounting on a circuit board using the external electrodes composed of the solder balls having a total of 80 pins and performing a temperature cycle test (a temperature change from −25 ° C. to + 125 ° C. is repeated in 60 minute cycles), 650 cycles have elapsed. No cracks (chip breaks) occurred in the solder balls, and it was confirmed that the solder balls had a practical level of stability.

【0054】一方、比較として、吊りリードの外部端子
形状凸部に半田ボールからなる外部電極を設けない樹脂
封止型半導体装置を作製した。この樹脂封止型半導体装
置を、合計72ピンの半田ボールからなる外部電極を用
いて回路基板に実装し、上記と同様の温度サイクル試験
を実施した結果、330サイクル経過した時点で半田ボ
ールにクラック(チップ割れ)が発生した。
On the other hand, as a comparison, a resin-sealed semiconductor device in which an external electrode made of a solder ball was not provided on the external terminal-shaped protrusion of the suspension lead was manufactured. This resin-encapsulated semiconductor device was mounted on a circuit board using external electrodes consisting of a total of 72 pins of solder balls, and the same temperature cycle test was performed. (Chip cracking) occurred.

【0055】さらに、比較として、ポリイミド基板を用
いた従来のエリアアレー型の半導体装置(外部端子72
ピン)を、半田ボールを用いて回路基板上に実装し、上
記と同様の温度サイクル試験を実施した結果、650サ
イクル経過しても半田ボールにクラック(チップ割れ)
が発生せず、安定していることが確認された。
For comparison, a conventional area array type semiconductor device using a polyimide substrate (external terminals 72) was used.
Pins) were mounted on a circuit board using solder balls, and the same temperature cycle test was performed. As a result, even after 650 cycles, cracks (chip cracks) occurred in the solder balls.
No occurrence was observed and it was confirmed that it was stable.

【0056】以上のことから、本発明の樹脂封止型半導
体装置は、回路基板への実装信頼性が従来のポリイミド
基板を用いた半導体装置と同レベルに高いことが確認さ
れた。
From the above, it was confirmed that the resin-encapsulated semiconductor device of the present invention had the same high mounting reliability on a circuit board as a semiconductor device using a conventional polyimide substrate.

【0057】[0057]

【発明の効果】以上詳述したように、本発明によれば半
導体素子の占有率が高くなり小型化が可能となって回路
基板への実装密度を向上させることができ、また、ダイ
パッドから延びる吊りリードの裏面に設けられた外部端
子形状凸部やダイパッドの裏面に設けられた外部端子形
状凸部の存在によって、半田ボールを使わないLGA
(Land Grid Array)のような回路基板
への樹脂封止型半導体装置の搭載では、端子部の外部端
子と同様に回路基板へ接続されることにより、端子部の
外部端子1個あたりの応力負荷が軽減され、また、半田
ボールを用いたBGA(Ball Grid Arra
y)のような樹脂封止型半導体装置の回路基板への搭載
においては、端子部の外部端子と同様に半田ボールを介
して回路基板へ接続されることにより、1個あたりの半
田ボールへの応力負荷が軽減され、これにより回路基板
への高い実装信頼性をもち、さらに、従来のポリイミド
基板を用いた半導体装置に比べて製造コストの低減が可
能となる。
As described in detail above, according to the present invention, the occupancy of the semiconductor element is increased, the size of the semiconductor element can be reduced, the mounting density on the circuit board can be improved, and the semiconductor element extends from the die pad. An LGA that does not use solder balls due to the presence of external terminal-shaped protrusions provided on the back surface of the suspension leads and external terminal-shaped protrusions provided on the back surface of the die pad
In mounting a resin-encapsulated semiconductor device on a circuit board such as a (Land Grid Array), by connecting to the circuit board in the same manner as the external terminal of the terminal section, the stress load per external terminal of the terminal section is increased. And a ball grid array (BGA) using solder balls.
In mounting the resin-encapsulated semiconductor device on the circuit board as in y), the terminal is connected to the circuit board via a solder ball in the same manner as the external terminal of the terminal portion, so that each solder ball is connected to one of the solder balls. The stress load is reduced, thereby having high mounting reliability on a circuit board, and further reducing the manufacturing cost as compared with a conventional semiconductor device using a polyimide substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の回路部材の一実施形態を示す平面図で
ある。
FIG. 1 is a plan view showing one embodiment of a circuit member of the present invention.

【図2】図1に示される回路部材のA−A線矢視におけ
る縦断面図である。
FIG. 2 is a longitudinal sectional view of the circuit member shown in FIG. 1 taken along line AA.

【図3】図1に示される回路部材のB−B線矢視におけ
る縦断面図である。
FIG. 3 is a longitudinal sectional view of the circuit member shown in FIG. 1 taken along line BB.

【図4】本発明の回路部材の他の実施形態を示す図2相
当の縦断面図である。
FIG. 4 is a longitudinal sectional view corresponding to FIG. 2, showing another embodiment of the circuit member of the present invention.

【図5】本発明の回路部材の他の実施形態を示す図3相
当の縦断面図である。
5 is a longitudinal sectional view corresponding to FIG. 3, showing another embodiment of the circuit member of the present invention.

【図6】本発明の回路部材の他の実施形態を示す図2相
当の縦断面図である。
FIG. 6 is a longitudinal sectional view corresponding to FIG. 2, showing another embodiment of the circuit member of the present invention.

【図7】本発明の回路部材の他の実施形態を示す図2相
当の縦断面図である。
FIG. 7 is a longitudinal sectional view corresponding to FIG. 2, showing another embodiment of the circuit member of the present invention.

【図8】図1乃至図3に示される本発明の回路部材を使
用した本発明の樹脂封止型半導体装置の一実施形態を示
す平面図である。
FIG. 8 is a plan view showing an embodiment of the resin-sealed semiconductor device of the present invention using the circuit member of the present invention shown in FIGS. 1 to 3;

【図9】図8に示される樹脂封止型半導体装置のC−C
線矢視における縦断面図である。
9 is a cross-sectional view of the resin-encapsulated semiconductor device shown in FIG.
It is a longitudinal cross-sectional view in a line arrow.

【図10】図8に示される樹脂封止型半導体装置のD−
D線矢視における縦断面図である。
10 is a cross-sectional view of the resin-encapsulated semiconductor device shown in FIG.
It is a longitudinal cross-sectional view in the direction of arrow D.

【図11】図1乃至図3に示される本発明の回路部材
と、この回路部材を用いた樹脂封止型半導体装置の製造
の一例を示す工程図であり、図2に対応する縦断面図で
示してある。
11 is a process diagram showing an example of manufacturing the circuit member of the present invention shown in FIGS. 1 to 3 and a resin-sealed semiconductor device using the circuit member, and is a longitudinal sectional view corresponding to FIG. 2; Indicated by

【図12】図1乃至図3に示される本発明の回路部材
と、この回路部材を用いた樹脂封止型半導体装置の製造
の一例を示す工程図であり、図3に対応する縦断面図で
示してある。
12 is a process chart showing an example of the production of the circuit member of the present invention shown in FIGS. 1 to 3 and a resin-sealed semiconductor device using the circuit member, and is a longitudinal sectional view corresponding to FIG. 3; Indicated by

【符号の説明】[Explanation of symbols]

1,11,21,31…回路部材 2,12,22,32…外枠部材 3,13,23,33…接続リード 4,14,24,34…端子部 4A,14A,24A,34A…内部端子 4B,14B,24B,34B…外部端子 5,15,25,35…銀めっき層 6,16,26,36…ダイパッド 7,17…吊りリード 8,18,29,39…外部端子形状凸部 51…樹脂封止型半導体装置 52…半導体素子 52a…端子 54…ボンディングワイヤ 55…封止部材 56…外部電極 57…外部電極 1, 11, 21, 31 ... circuit member 2, 12, 22, 32 ... outer frame member 3, 13, 23, 33 ... connection lead 4, 14, 24, 34 ... terminal portion 4A, 14A, 24A, 34A ... inside Terminals 4B, 14B, 24B, 34B: external terminals 5, 15, 25, 35: silver plating layers 6, 16, 26, 36: die pads 7, 17: suspension leads 8, 18, 29, 39: external terminal shape convex portions 51: Resin-sealed semiconductor device 52: Semiconductor element 52a: Terminal 54: Bonding wire 55: Sealing member 56: External electrode 57: External electrode

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 表面側に内部端子を裏面側に外部端子を
表裏一体的に有する複数の端子部を略一平面内に二次元
的に互いに電気的に独立して配置し、端子部の内部端子
と半導体素子の端子とをワイヤにて電気的に接続し、各
端子部の外部端子の一部を外部に露出させるように全体
を樹脂封止した樹脂封止型半導体装置において、 複数個の前記端子部を二次元的に配置する平面の略中央
部に、複数の吊りリードを備えたダイパッドが電気的に
独立して配置され、前記複数の吊りリードは前記端子部
が二次元的に配置された平面内に延びるとともに、裏面
に外部端子形状凸部を備え、かつ、該外部端子形状凸部
の一部が外部に露出し、前記半導体素子が前記ダイパッ
ドの表面に電気的に絶縁して搭載されたことを特徴とす
る樹脂封止型半導体装置。
A plurality of terminal portions having an internal terminal on a front surface side and an external terminal on a back surface integrated front and back are two-dimensionally and electrically independent from each other in a substantially one plane. In the resin-encapsulated semiconductor device in which the terminals and the terminals of the semiconductor element are electrically connected by wires, and the entirety of the external terminals of each terminal portion is resin-encapsulated so as to expose a part of the external terminals, A die pad having a plurality of suspension leads is electrically independently arranged at a substantially central portion of a plane where the terminal portions are two-dimensionally arranged, and the terminal portions are two-dimensionally arranged with the plurality of suspension leads. Extending in the plane provided, and provided with an external terminal-shaped convex portion on the back surface, and a part of the external terminal-shaped convex portion is exposed to the outside, and the semiconductor element is electrically insulated from the surface of the die pad. Resin-sealed semiconductor device characterized by being mounted
【請求項2】 前記ダイパッドの表面は、前記端子部の
内部端子の表面と略一平面をなすことを特徴とする請求
項1に記載の樹脂封止型半導体装置。
2. The resin-encapsulated semiconductor device according to claim 1, wherein a surface of the die pad is substantially flush with a surface of an internal terminal of the terminal portion.
【請求項3】 前記ダイパッドは、裏面に1個以上の外
部端子形状凸部を備え、該外部端子形状凸部の一部が外
部に露出していることを特徴とする請求項1または請求
項2に記載の樹脂封止型半導体装置。
3. The die pad according to claim 1, wherein the back surface of the die pad has one or more external terminal-shaped protrusions, and a part of the external terminal-shaped protrusions is exposed to the outside. 3. The resin-sealed semiconductor device according to 2.
【請求項4】 外部に露出している外部端子および外部
端子形状凸部に半田からなる外部電極を設けたことを特
徴とする請求項1乃至請求項3のいずれかに記載の樹脂
封止型半導体装置。
4. The resin-sealed mold according to claim 1, wherein an external electrode made of solder is provided on the external terminal exposed to the outside and the external terminal shape convex portion. Semiconductor device.
【請求項5】 樹脂封止型半導体装置用の回路部材にお
いて、外枠部材と、該外枠部材から各々接続リードを介
して相互に独立して突設された複数の端子部と、前記外
枠部材から複数の吊りリードを介して保持されたダイパ
ッドとを備え、各端子部は表面側に内部端子を裏面側に
外部端子を表裏一体的に有し、前記吊りリードは裏面に
外部端子形状凸部を備え、前記外部端子面と前記外部端
子形状凸部面は略一平面上に位置していることを特徴と
する回路部材。
5. A circuit member for a resin-encapsulated semiconductor device, comprising: an outer frame member; a plurality of terminal portions projecting from the outer frame member independently of each other via connection leads; A die pad held from the frame member via a plurality of suspension leads, each terminal portion integrally having an internal terminal on the front side and an external terminal on the back side, and the suspension lead has an external terminal shape on the back side. A circuit member comprising a convex portion, wherein the external terminal surface and the external terminal shape convex surface are located on substantially one plane.
【請求項6】 前記ダイパッドの表面は、前記端子部の
内部端子の表面と略一平面をなすことを特徴とする請求
項5に記載の回路部材。
6. The circuit member according to claim 5, wherein a surface of the die pad is substantially flush with a surface of an internal terminal of the terminal portion.
【請求項7】 前記ダイパッドは、裏面に1個以上の外
部端子形状凸部を備え、該外部端子形状凸部面と前記外
部端子面は略一平面上に位置していることを特徴とする
請求項5または請求項6に記載の回路部材。
7. The die pad is provided with one or more external terminal-shaped convex portions on the back surface, and the external terminal-shaped convex portion surface and the external terminal surface are located on substantially one plane. The circuit member according to claim 5.
【請求項8】 ダイパッドの表面に電気絶縁性の両面接
着テープが一体的に設けられていることを特徴とする請
求項5乃至請求項7のいずれかに記載の回路部材。
8. The circuit member according to claim 5, wherein an electrically insulating double-sided adhesive tape is integrally provided on a surface of the die pad.
JP27061798A 1998-09-08 1998-09-08 Resin-sealed semiconductor device and circuit member used therein Pending JP2000091488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27061798A JP2000091488A (en) 1998-09-08 1998-09-08 Resin-sealed semiconductor device and circuit member used therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27061798A JP2000091488A (en) 1998-09-08 1998-09-08 Resin-sealed semiconductor device and circuit member used therein

Publications (1)

Publication Number Publication Date
JP2000091488A true JP2000091488A (en) 2000-03-31

Family

ID=17488590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27061798A Pending JP2000091488A (en) 1998-09-08 1998-09-08 Resin-sealed semiconductor device and circuit member used therein

Country Status (1)

Country Link
JP (1) JP2000091488A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001320007A (en) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd Frame for resin sealed semiconductor device
JP2001326295A (en) * 2000-05-15 2001-11-22 Rohm Co Ltd Semiconductor device and frame for manufacturing the same
JP2003046053A (en) * 2001-07-27 2003-02-14 Sanyo Electric Co Ltd Semiconductor device and manufacturing method therefor
US6809409B2 (en) 2001-12-27 2004-10-26 Mitsui High-Tec, Inc. Lead frame and semiconductor device made using the lead frame
JP2005197604A (en) * 2004-01-09 2005-07-21 Matsushita Electric Ind Co Ltd Semiconductor device
US7170149B2 (en) 2001-04-13 2007-01-30 Yamaha Corporation Semiconductor device and package, and method of manufacture therefor
JP2008141222A (en) * 2008-02-04 2008-06-19 Matsushita Electric Ind Co Ltd Lead frame and semiconductor device using the same and method of manufacturing the same
JP2008258652A (en) * 2001-12-14 2008-10-23 Renesas Technology Corp Manufacturing method of semiconductor device
JP2009302591A (en) * 2009-09-30 2009-12-24 Renesas Technology Corp Semiconductor device
WO2010035499A1 (en) * 2008-09-29 2010-04-01 凸版印刷株式会社 Leadframe substrate, method for manufacturing same, and semiconductor device
JP2010103577A (en) * 2010-02-09 2010-05-06 Rohm Co Ltd Semiconductor device
US7833833B2 (en) 2003-11-27 2010-11-16 Renesas Electronics Corporation Method of manufacturing a semiconductor device
JP2014112714A (en) * 2014-02-10 2014-06-19 Renesas Electronics Corp Semiconductor device
JP2019012854A (en) * 2018-10-16 2019-01-24 大日本印刷株式会社 Semiconductor device and manufacturing method of the same, and light device

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001320007A (en) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd Frame for resin sealed semiconductor device
JP2001326295A (en) * 2000-05-15 2001-11-22 Rohm Co Ltd Semiconductor device and frame for manufacturing the same
US7554182B2 (en) 2001-04-13 2009-06-30 Yamaha Corporation Semiconductor device and package, and method of manufacturer therefor
US7170149B2 (en) 2001-04-13 2007-01-30 Yamaha Corporation Semiconductor device and package, and method of manufacture therefor
JP2003046053A (en) * 2001-07-27 2003-02-14 Sanyo Electric Co Ltd Semiconductor device and manufacturing method therefor
JP2011155293A (en) * 2001-12-14 2011-08-11 Renesas Electronics Corp Method of manufacturing semiconductor device
JP2008258652A (en) * 2001-12-14 2008-10-23 Renesas Technology Corp Manufacturing method of semiconductor device
US6809409B2 (en) 2001-12-27 2004-10-26 Mitsui High-Tec, Inc. Lead frame and semiconductor device made using the lead frame
US7833833B2 (en) 2003-11-27 2010-11-16 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US9425165B2 (en) 2003-11-27 2016-08-23 Renesas Electronics Corporation Method of manufacturing semiconductor device
US10998288B2 (en) 2003-11-27 2021-05-04 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US10249595B2 (en) 2003-11-27 2019-04-02 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US9806035B2 (en) 2003-11-27 2017-10-31 Renesas Electronics Corporation Semiconductor device
US9024419B2 (en) 2003-11-27 2015-05-05 Renesas Electronics Corporation Method of manufacturing semiconductor device
US8592961B2 (en) 2003-11-27 2013-11-26 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US8513785B2 (en) 2003-11-27 2013-08-20 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US8053875B2 (en) 2003-11-27 2011-11-08 Renesas Electronics Corporation Method of manufacturing a semiconductor device
JP2005197604A (en) * 2004-01-09 2005-07-21 Matsushita Electric Ind Co Ltd Semiconductor device
JP2008141222A (en) * 2008-02-04 2008-06-19 Matsushita Electric Ind Co Ltd Lead frame and semiconductor device using the same and method of manufacturing the same
CN102165582A (en) * 2008-09-29 2011-08-24 凸版印刷株式会社 Leadframe substrate, method for manufacturing same, and semiconductor device
US8390105B2 (en) 2008-09-29 2013-03-05 Toppan Printing Co., Ltd. Lead frame substrate, manufacturing method thereof, and semiconductor apparatus
KR101604154B1 (en) 2008-09-29 2016-03-25 도판 인사츠 가부시키가이샤 Lead frame substrate, manufacturing method thereof, and semiconductor apparatus
JP2010080895A (en) * 2008-09-29 2010-04-08 Toppan Printing Co Ltd Lead frame type substrate and method for manufacturing the same, and semiconductor substrate
WO2010035499A1 (en) * 2008-09-29 2010-04-01 凸版印刷株式会社 Leadframe substrate, method for manufacturing same, and semiconductor device
JP4535513B2 (en) * 2009-09-30 2010-09-01 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2009302591A (en) * 2009-09-30 2009-12-24 Renesas Technology Corp Semiconductor device
JP2010103577A (en) * 2010-02-09 2010-05-06 Rohm Co Ltd Semiconductor device
JP2014112714A (en) * 2014-02-10 2014-06-19 Renesas Electronics Corp Semiconductor device
JP2019012854A (en) * 2018-10-16 2019-01-24 大日本印刷株式会社 Semiconductor device and manufacturing method of the same, and light device

Similar Documents

Publication Publication Date Title
JP3780122B2 (en) Manufacturing method of semiconductor device
JP3947292B2 (en) Manufacturing method of resin-encapsulated semiconductor device
JP3947750B2 (en) Semiconductor device manufacturing method and semiconductor device
JP4091050B2 (en) Manufacturing method of semiconductor device
US7045906B2 (en) Resin-encapsulated package, lead member for the same and method of fabricating the lead member
JPH098206A (en) Lead frame and bga resin sealed semiconductor device
KR19980081036A (en) Resin-sealed semiconductor device, circuit member and resin manufacturing method thereof
JPH08125066A (en) Resin-sealed semiconductor device and lead frame used for it, and manufacture of resin-sealed semiconductor device
JP2005317998A5 (en)
JP2000091488A (en) Resin-sealed semiconductor device and circuit member used therein
JP3072291B1 (en) Lead frame, resin-encapsulated semiconductor device using the same and method of manufacturing the same
JP3983930B2 (en) Circuit member manufacturing method
JP2000332162A (en) Resin-sealed semiconductor device
JPH11163024A (en) Semiconductor device and lead frame for assembling the same, and manufacture of the device
JP5850347B2 (en) Resin-sealed semiconductor device
JP3529915B2 (en) Lead frame member and method of manufacturing the same
JP3992877B2 (en) Manufacturing method of resin-encapsulated semiconductor device
JP3884552B2 (en) Semiconductor device, circuit member used therefor, and method for manufacturing semiconductor device
JP4137981B2 (en) Manufacturing method of semiconductor device
JP2001007274A (en) Resin-sealed semiconductor device, circuit member used thereof, and its manufacturer
JPH1154663A (en) Resin-sealed semiconductor device and circuit member used therein, and manufacture of circuit member
JPH08148526A (en) Semiconductor device
JP3699573B2 (en) Semiconductor device, circuit member used therefor, and manufacturing method thereof
JP2001230345A (en) Semiconductor device, its manufacturing method and lead frame for use in manufacture thereof
JPH1041432A (en) Lead frame member and surface mount semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050831

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060306

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081104

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081120

A131 Notification of reasons for refusal

Effective date: 20090915

Free format text: JAPANESE INTERMEDIATE CODE: A131

A02 Decision of refusal

Effective date: 20100126

Free format text: JAPANESE INTERMEDIATE CODE: A02