JP3780122B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP3780122B2
JP3780122B2 JP19322599A JP19322599A JP3780122B2 JP 3780122 B2 JP3780122 B2 JP 3780122B2 JP 19322599 A JP19322599 A JP 19322599A JP 19322599 A JP19322599 A JP 19322599A JP 3780122 B2 JP3780122 B2 JP 3780122B2
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lead frame
frame material
surface side
semiconductor device
metal plating
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JP2001024135A (en
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高士 中島
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Mitsui High Tech Inc
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Mitsui High Tech Inc
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/481—Disposition
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/92—Specific sequence of method steps
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    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
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Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device at a relatively low cost. SOLUTION: Noble metal plating layers 22 and 23 are formed on the wire bonding parts 12, parts of or all of an outer frame 17 and outer connection terminal parts 13 on both the front and rear surface sides of a lead frame material 21 and, after an etching resist film 24 is formed on the rear surface side of the lead frame material 21, half-etching is applied to the front surface side of the lead frame material 21 to obtain a predetermined etching depth. After a semiconductor chip 11 is mounted on the front side of the lead frame material 21, the chip 11 is electrically connected to the lead frame material 21 by wire bonding and the front side is sealed with resin. Then, the etching resist film 24 on the rear surface side of the lead frame material 21 is removed and the rear surface side of the lead frame material 21 is etched to make the outer connection terminal parts 13 protrude independently.

Description

【０００１】
【発明の属する技術分野】
本発明は、ＣＳＰ（チップサイズドパッケージ）の半導体装置の製造方法に係り、特に、外部接続端子部が封止樹脂の底面側に突出した半導体装置の製造方法に関する。
【０００２】
【従来の技術】
半導体装置の小型の要請から、ポリイミド樹脂テープと半田ボールを用いたテープ−ＣＳＰ型の半導体装置や、ベースメタルを使用したＢＣＣ（バンプチップキャリア）型の半導体装置が知られている。
【０００３】
【発明が解決しようとする課題】
しかしながら、テープ−ＣＳＰ型の半導体装置においては、ポリイミド樹脂テープが高価であり、軟質のためにストリップ搬送に適していないという問題がある。
また、ＢＣＣ型の半導体装置においては、ベースメタルをエッチングによってリムーブすると固片になってしまうので、モールド面を粘着テープで固定する必要があり、コスト高となるという問題がある。
本発明はかかる事情に鑑みてなされたもので、比較的安価に製造可能な半導体装置の製造方法を提供することを目的とする。
【０００４】
【課題を解決するための手段】
前記目的に沿う本発明に係る半導体装置の製造方法は、中央に半導体素子を、その周辺にエリアアレー状に、表面側がワイヤボンディング部となって裏面側が外部接続端子部となった導体端子を配置した半導体装置の製造方法であって、
リードフレーム材の表面側に搭載予定の前記半導体素子を囲んで形成される前記ワイヤボンディング部及びこれを囲む外枠の一部又は全部と、前記ワイヤボンディング部に対応して前記リードフレーム材の裏面側に形成される前記外部接続端子部とにＡｕからなる貴金属めっき層を形成する第１工程と、
前記リードフレーム材の裏面側に耐エッチングレジスト膜を形成した後、表面側に形成された前記貴金属めっき層をレジストマスクとして表面側から該リードフレーム材に所定深さのハーフエッチング加工を行い、前記外枠の一部又は全部と前記ワイヤボンディング部とを突出させる第２工程と、
前記リードフレーム材に前記半導体素子を接着剤を介して搭載した後、該半導体素子の電極パッド部とそれぞれ対応する前記ワイヤボンディング部との間をボンディングワイヤによって接続し電気的導通回路を形成する第３工程と、
前記半導体素子、前記ボンディングワイヤ、及び前記突出した外枠を含む前記リードフレーム材の表面側を樹脂封止する第４工程と、
前記耐エッチングレジスト膜が除去された前記リードフレーム材の裏面側に、裏面側に形成された前記貴金属めっき層をレジストマスクとしてエッチング加工を行って、前記外部接続端子部を突出させて独立させる第５工程とを有し、
しかも、前記耐エッチングレジスト膜の除去は、前記第２工程が完了した後に行う。
なお、個別の製品となる半導体装置は最終的には、外枠の一部を残して外枠から分離されることになる。
【０００５】
ここで、本発明に係る半導体装置の製造方法おいて、前記貴金属めっき層は、前記リードフレーム材の表面及び裏面を耐めっき性のフォトレジスト膜で覆った後、該貴金属めっき層が形成される部分の露光処理及びこれに続く現像処理を行って該リードフレーム材の露出を行った後に、貴金属めっきを行って形成するのが好ましい。
本発明に係る半導体装置の製造方法において、前記ワイヤボンディング部及びこれに符合する前記外部接続端子部はエリアアレー状、即ち、外部接続端子部を全体として格子点状、又は中央部に空間部を形成して周囲が格子点状に形成するのが好ましい。
そして、本発明に係る半導体装置の製造方法において、前記接着剤には導電性接着剤又は絶縁性接着剤のいずれも適用可能であるが、導電性接着剤を使用する場合には、Ａｇ・エポキシ系樹脂からなる接着剤を使用するのが好ましい。
【０００６】
【発明の実施の形態】
続いて、添付した図面を参照しつつ、本発明を具体化した実施の形態につき説明し、本発明の理解に供する。
ここに、図１は本発明の一実施の形態に係る半導体装置の製造方法の製造工程図、図２（Ａ）、（Ｂ）はそれぞれ同方法で製造された半導体装置の説明図、図３は同方法で製造された半導体装置の使用状態を示す断面図である。
【０００７】
図１〜図３に示すように、本発明の一実施の形態に係る半導体装置の製造方法によって製造された半導体装置１０は、中央に半導体素子１１を、その周辺にエリアアレー状（図２参照）に、上面側（表面側）がワイヤボンディング部１２となって下面側（裏面側）が外部接続端子部１３となった導体端子１４を配置している。ワイヤボンディング部１２と半導体素子１１の各電極パッド１５はボンディングワイヤ１６で電気的に連結されている。周囲にある導体からなる外枠１７を含めて、半導体素子１１、ボンディングワイヤ１６、及び導体端子１４の上半分は封止樹脂１８で樹脂封止されている。外部接続端子部１３には半田濡れ性の良いめっきが下部に設けられ、他の基板１９上に設けられたクリーム半田の溶融によって、図３に示すように、他の基板１９との電気的な接続が行われている。
半導体素子１１の底面側には導電性接着剤２０が塗布され、これによって、半導体素子１１からの熱放散を促進している。
【０００８】
続いて、図１（Ａ）〜（Ｅ）を参照しながら、この半導体装置１０の製造方法について説明する。
図１（Ａ）に示すように、板状のリードフレーム材２１の表面側に、中央に搭載予定の半導体素子１１を囲んで形成されるワイヤボンディング部１２及びこれを囲む外枠１７と、ワイヤボンディング部１２に対応して裏面側に形成される外部接続端子部１３とに貴金属めっき層２２、２３を形成する（第１工程）。
この貴金属めっき層２２、２３の形成は、リードフレーム材２１の表面及び裏面を耐めっき性のフォトレジスト膜で覆った後、貴金属めっき層２２、２３が形成される部分に関する露光処理及びこれに続く現像処理を行って該リードフレーム材２１の部分露出を行った後に、最初にニッケル等の下地めっき層を形成し、次に貴金属めっきを行う。このように、下地めっき層を介してＡｇ、Ａｕ、Ｐｄから選択された一種類の貴金属で貴金属めっき層２２、２３を形成することによって、リードフレーム材２１に銅等を使用する場合のボンダビリティの確保と半田濡れ性の確保を維持している。
【０００９】
次に、図１（Ｂ）に示すように、リードフレーム材２１の裏面側に耐エッチングレジスト膜２４を形成した後、表面側に形成された貴金属めっき層２２をレジストマスクとして表面側から該リードフレーム材２１に所定深さのエッチング加工（ハーフエッチング）を行う。これによって、外枠１７とワイヤボンディング部１２とを突出させることができる（第２工程）。
【００１０】
そして、図１（Ｃ）に示すように、ハーフエッチングされたリードフレーム材２１の表面側中央に半導体素子１１をＡｇ・エポキシ系樹脂からなる接着剤２０を介して搭載した後、半導体素子１１の電極パッド部１５とそれぞれ対応するワイヤボンディング部１２との間をボンディングワイヤ１６によって接続し、電気的導通回路を形成する（第３工程）。
この後、図１（Ｄ）に示すように、半導体素子１１、ボンディングワイヤ１６、及び突出した外枠１７を含むリードフレーム材２１の表面側を封止樹脂１８で樹脂封止する（第４工程）。
【００１１】
以上の処理が終わった後、リードフレーム材２１の裏面側に貼着していた耐エッチングレジスト膜２４を除去するが、これは組み立て工程の前に行ってもよい。更に、図１（Ｅ）に示すように、リードフレーム材２１の裏面側に、裏面側に形成された貴金属めっき層２３をレジストマスクとしてエッチング加工を行って、外部接続端子部１３を突出させると共に、隣り合う外部接続端子部１３を電気的に独立させる（第５工程）。この後、外枠１７の分離を行って、独立した半導体装置１０が製造される。
【００１２】
前記実施の形態においては、半導体素子１１の接着剤２０としてＡｇ・エポキシ系の接着剤を用いたが、その他の導電性の接着剤又は絶縁性の接着剤であっても本発明は適用される。
半導体装置の製造過程にあっては、半導体装置に残る外枠は周囲の外枠本体に実質的に連結されている必要があるので、外枠全体の全部の表面に貴金属めっき層を形成する必要はなく、外枠の一部（即ち、連結部分のみ）に貴金属めっき層を形成するのが好ましい。
また、前記実施の形態においては、耐エッチングレジスト膜の除去は、第５工程によって行ったが、第２工程が完了した後、裏面側のハーフエッチングを行う前であれば、何時行ってもよく、この場合も本発明は適用される。
【００１３】
【発明の効果】
請求項１〜３記載の半導体装置の製造方法においては、従来のように、ポリイミド樹脂テープや粘着テープを使用することなく、半導体装置を製造できる。従って、ポリイミド樹脂テープや粘着テープを使用することによる半導体装置の製造上の問題を避けて、比較的安価に半導体装置の製造が可能となる。
また、貴金属めっき層をレジストマスクとしているので、更にレジスト膜を形成する必要がなく、更に、貴金属めっき層はそのままワイヤボンディング部又は外部接続端子部として使用できる。
そして、外部接続端子部がエリアアレー状に配置されているので、他の基板との接合が容易となる。
特に、請求項２記載の半導体装置の製造方法においては、貴金属めっき層の形成が容易となり、同時に多数のリードフレーム材に同一の処理を行うことが可能となる。
そして、請求項３記載の半導体装置の製造方法においては、半導体素子をＡｇ・エポキシ系の樹脂で接合しているので、より有効な放熱性を確保できる。
【図面の簡単な説明】
【図１】本発明の一実施の形態に係る半導体装置の製造方法の製造工程図である。
【図２】（Ａ）、（Ｂ）はそれぞれ同方法で製造された半導体装置の説明図である。
【図３】同方法で製造された半導体装置の使用状態を示す断面図である。
【符号の説明】
１０：半導体装置、１１：半導体素子、１２：ワイヤボンディング部、１３：外部接続端子部、１４：導体端子、１５：電極パッド、１６：ボンディングワイヤ、１７：外枠、１８：封止樹脂、１９：他の基板、２０：Ａｇ・エポキシ系の接着剤、２１：リードフレーム材、２２、２３：貴金属めっき層、２４：耐エッチングレジスト膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a CSP (chip-sized package) semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which an external connection terminal portion protrudes toward the bottom surface side of a sealing resin.
[0002]
[Prior art]
Due to the demand for a small semiconductor device, a tape-CSP type semiconductor device using a polyimide resin tape and a solder ball and a BCC (bump chip carrier) type semiconductor device using a base metal are known.
[0003]
[Problems to be solved by the invention]
However, in a tape-CSP type semiconductor device, there is a problem that a polyimide resin tape is expensive and is not suitable for strip conveyance due to its softness.
Further, in the BCC type semiconductor device, when the base metal is removed by etching, it becomes a solid piece, so that there is a problem that it is necessary to fix the mold surface with an adhesive tape and the cost is increased.
The present invention has been made in view of such circumstances, and an object thereof is to provide a method of manufacturing a semiconductor device that can be manufactured at a relatively low cost.
[0004]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device according to the present invention in accordance with the above object includes arranging a semiconductor element in the center, an area array in the periphery thereof, and a conductor terminal having a wire bonding portion on the front side and an external connection terminal portion on the back side. A method for manufacturing a semiconductor device, comprising:
A part or all of the outer frame surrounding the wire bonding portion and which is formed to surround the semiconductor element mounting scheduled on the surface side of the lead frame material, the back surface of said lead frame material corresponding to the wire bonding portion a first step of forming a noble metal plating layer made of Au on said external connection terminal portion formed on the side,
After forming an etching resistant resist film on the back side of the lead frame material, the lead frame material is subjected to half etching processing of a predetermined depth from the surface side using the noble metal plating layer formed on the front side as a resist mask, a second step of projecting a portion of the outer frame or the whole and the wire bonding portion,
After the semiconductor element is mounted on the lead frame material via an adhesive, the electrode pad portions of the semiconductor element and the corresponding wire bonding portions are connected by bonding wires to form an electrical conduction circuit. 3 steps,
A fourth step of resin sealing the surface side of the lead frame material including the semiconductor element, the bonding wire, and the protruding outer frame;
Etching is performed on the back surface side of the lead frame material from which the etching resistant resist film has been removed, using the noble metal plating layer formed on the back surface side as a resist mask, and the external connection terminal portions are protruded to be independent. 5 steps ,
Moreover, the etching resistant resist film is removed after the second step is completed.
Note that the semiconductor device as an individual product is finally separated from the outer frame, leaving a part of the outer frame.
[0005]
Here, in the method of manufacturing a semiconductor device according to the present invention, the noble metal plating layer is formed after the front and back surfaces of the lead frame material are covered with a plating-resistant photoresist film. It is preferable that the lead frame material is exposed by performing a partial exposure process and a subsequent development process, followed by precious metal plating.
In the method of manufacturing a semiconductor device according to the present invention, the wire bonding portion and the external connection terminal portion corresponding to the wire bonding portion are in an area array shape, that is, the external connection terminal portion as a whole is a lattice point shape, or a space portion in the central portion. Preferably, the periphery is formed in a lattice point shape.
In the method for manufacturing a semiconductor device according to the present invention, either a conductive adhesive or an insulating adhesive can be applied to the adhesive. However, when a conductive adhesive is used, Ag / epoxy is used. It is preferable to use an adhesive made of a resin.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the accompanying drawings for understanding of the present invention.
1 is a manufacturing process diagram of a semiconductor device manufacturing method according to an embodiment of the present invention, FIGS. 2A and 2B are explanatory diagrams of the semiconductor device manufactured by the same method, and FIG. FIG. 6 is a cross-sectional view showing a usage state of the semiconductor device manufactured by the same method.
[0007]
As shown in FIGS. 1 to 3, a semiconductor device 10 manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention has a semiconductor element 11 in the center and an area array shape in the periphery (see FIG. 2). ), The conductor terminal 14 having the upper surface side (front surface side) as the wire bonding portion 12 and the lower surface side (back surface side) as the external connection terminal portion 13 is disposed. The wire bonding portion 12 and each electrode pad 15 of the semiconductor element 11 are electrically connected by a bonding wire 16. The upper half of the semiconductor element 11, the bonding wire 16, and the conductor terminal 14 including the outer frame 17 made of the surrounding conductor is sealed with a sealing resin 18. The external connection terminal portion 13 is provided with a plating with good solder wettability at the bottom, and by melting the cream solder provided on the other substrate 19, as shown in FIG. A connection is being made.
A conductive adhesive 20 is applied to the bottom surface side of the semiconductor element 11, thereby promoting heat dissipation from the semiconductor element 11.
[0008]
Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS.
As shown in FIG. 1A, on the surface side of a plate-like lead frame member 21, a wire bonding portion 12 formed to surround a semiconductor element 11 to be mounted in the center, an outer frame 17 surrounding the wire bonding portion 12, and a wire Precious metal plating layers 22 and 23 are formed on the external connection terminal portion 13 formed on the back surface side corresponding to the bonding portion 12 (first step).
The noble metal plating layers 22 and 23 are formed after the front and back surfaces of the lead frame material 21 are covered with a plating-resistant photoresist film, followed by an exposure process for a portion where the noble metal plating layers 22 and 23 are formed, and the following. After the development processing is performed and the lead frame material 21 is partially exposed, a base plating layer such as nickel is first formed, and then noble metal plating is performed. Thus, bondability in the case of using copper or the like for the lead frame material 21 by forming the noble metal plating layers 22 and 23 with one kind of noble metal selected from Ag, Au, and Pd through the base plating layer. And solder wettability are maintained.
[0009]
Next, as shown in FIG. 1B, after forming an etching resistant resist film 24 on the back side of the lead frame material 21, the lead is formed from the front side using the noble metal plating layer 22 formed on the front side as a resist mask. The frame material 21 is etched to a predetermined depth (half etching). Thereby, the outer frame 17 and the wire bonding part 12 can be protruded (2nd process).
[0010]
Then, as shown in FIG. 1C, after the semiconductor element 11 is mounted on the surface side center of the half-etched lead frame material 21 via the adhesive 20 made of Ag / epoxy resin, The electrode pad portions 15 and the corresponding wire bonding portions 12 are connected by bonding wires 16 to form an electrical conduction circuit (third step).
Thereafter, as shown in FIG. 1D, the surface side of the lead frame material 21 including the semiconductor element 11, the bonding wire 16, and the protruding outer frame 17 is resin-sealed with a sealing resin 18 (fourth step). ).
[0011]
After the above processing is completed, the etching resistant resist film 24 adhered to the back side of the lead frame material 21 is removed, but this may be performed before the assembly process. Further, as shown in FIG. 1E, etching is performed on the back surface side of the lead frame material 21 using the noble metal plating layer 23 formed on the back surface side as a resist mask to project the external connection terminal portion 13. The adjacent external connection terminal portions 13 are electrically independent (fifth step). Thereafter, the outer frame 17 is separated, and the independent semiconductor device 10 is manufactured.
[0012]
In the above-described embodiment, an Ag / epoxy adhesive is used as the adhesive 20 of the semiconductor element 11. However, the present invention can be applied to other conductive adhesives or insulating adhesives. .
In the manufacturing process of a semiconductor device, the outer frame remaining in the semiconductor device needs to be substantially connected to the surrounding outer frame main body, so it is necessary to form a noble metal plating layer on the entire surface of the entire outer frame. Rather, it is preferable to form a noble metal plating layer on a part of the outer frame (that is, only the connecting part).
In the above embodiment, the etching-resistant resist film is removed by the fifth step. However, it may be performed at any time after the second step is completed and before half etching on the back side. In this case, the present invention is also applied.
[0013]
【The invention's effect】
In the method for manufacturing a semiconductor device according to any one of claims 1 to 3 , the semiconductor device can be manufactured without using a polyimide resin tape or an adhesive tape as in the prior art. Therefore, it is possible to manufacture the semiconductor device at a relatively low cost while avoiding problems in manufacturing the semiconductor device due to the use of the polyimide resin tape or the adhesive tape.
Further, since the noble metal plating layer is used as a resist mask, it is not necessary to form a resist film, and the noble metal plating layer can be used as it is as a wire bonding portion or an external connection terminal portion.
And since the external connection terminal part is arrange | positioned at area array shape, joining with another board | substrate becomes easy.
In particular, in the method for manufacturing a semiconductor device according to the second aspect, it becomes easy to form a noble metal plating layer, and at the same time, it is possible to perform the same processing on a number of lead frame materials.
In the method for manufacturing a semiconductor device according to the third aspect , since the semiconductor elements are joined with the Ag / epoxy resin, more effective heat dissipation can be secured.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 2A and 2B are explanatory diagrams of a semiconductor device manufactured by the same method. FIG.
FIG. 3 is a cross-sectional view showing a use state of the semiconductor device manufactured by the same method.
[Explanation of symbols]
10: Semiconductor device, 11: Semiconductor element, 12: Wire bonding part, 13: External connection terminal part, 14: Conductor terminal, 15: Electrode pad, 16: Bonding wire, 17: Outer frame, 18: Sealing resin, 19 : Other substrate, 20: Ag / epoxy adhesive, 21: lead frame material, 22, 23: noble metal plating layer, 24: etching resist film

Claims (3)

中央に半導体素子を、その周辺にエリアアレー状に、表面側がワイヤボンディング部となって裏面側が外部接続端子部となった導体端子を配置した半導体装置の製造方法であって、
リードフレーム材の表面側に搭載予定の前記半導体素子を囲んで形成される前記ワイヤボンディング部及びこれを囲む外枠の一部又は全部と、前記ワイヤボンディング部に対応して前記リードフレーム材の裏面側に形成される前記外部接続端子部とにＡｕからなる貴金属めっき層を形成する第１工程と、
前記リードフレーム材の裏面側に耐エッチングレジスト膜を形成した後、表面側に形成された前記貴金属めっき層をレジストマスクとして表面側から該リードフレーム材に所定深さのハーフエッチング加工を行い、前記外枠の一部又は全部と前記ワイヤボンディング部とを突出させる第２工程と、
前記リードフレーム材に前記半導体素子を接着剤を介して搭載した後、該半導体素子の電極パッド部とそれぞれ対応する前記ワイヤボンディング部との間をボンディングワイヤによって接続し電気的導通回路を形成する第３工程と、
前記半導体素子、前記ボンディングワイヤ、及び前記突出した外枠を含む前記リードフレーム材の表面側を樹脂封止する第４工程と、
前記耐エッチングレジスト膜が除去された前記リードフレーム材の裏面側に、裏面側に形成された前記貴金属めっき層をレジストマスクとしてエッチング加工を行って、前記外部接続端子部を突出させて独立させる第５工程とを有し、
しかも、前記耐エッチングレジスト膜の除去は、前記第２工程が完了した後に行うことを特徴とする半導体装置の製造方法。 A semiconductor device manufacturing method in which a semiconductor element is arranged in the center, an area array is formed around the semiconductor element, and a conductor terminal in which the front surface side is a wire bonding portion and the back surface side is an external connection terminal portion,
A part or all of the outer frame surrounding the wire bonding portion and which is formed to surround the semiconductor element mounting scheduled on the surface side of the lead frame material, the back surface of said lead frame material corresponding to the wire bonding portion a first step of forming a noble metal plating layer made of Au on said external connection terminal portion formed on the side,
After forming an etching resistant resist film on the back side of the lead frame material, the lead frame material is subjected to half etching processing of a predetermined depth from the surface side using the noble metal plating layer formed on the front side as a resist mask, a second step of projecting a portion of the outer frame or the whole and the wire bonding portion,
After the semiconductor element is mounted on the lead frame material via an adhesive, the electrode pad portions of the semiconductor element and the corresponding wire bonding portions are connected by bonding wires to form an electrical conduction circuit. 3 steps,
A fourth step of resin sealing the surface side of the lead frame material including the semiconductor element, the bonding wire, and the protruding outer frame;
Etching is performed on the back surface side of the lead frame material from which the etching resistant resist film has been removed, using the noble metal plating layer formed on the back surface side as a resist mask, and the external connection terminal portions are protruded to be independent. 5 steps ,
In addition, the removal of the etching resistant resist film is performed after the second step is completed . 請求項１記載の半導体装置の製造方法において、前記貴金属めっき層は、前記リードフレーム材の表面及び裏面を耐めっき性のフォトレジスト膜で覆った後、該貴金属めっき層が形成される部分の露光処理及びこれに続く現像処理を行って該リードフレーム材の露出を行った後に、貴金属めっきを行って形成されていることを特徴とする半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, wherein the noble metal plating layer is formed by exposing the surface and the back surface of the lead frame material with a plating-resistant photoresist film, and then exposing a portion where the noble metal plating layer is formed. A method of manufacturing a semiconductor device, wherein the lead frame material is exposed by performing processing and subsequent development processing, and then performing precious metal plating. 請求項１及び２のいずれか１項に記載の半導体装置の製造方法において、前記接着剤は、Ａｇ・エポキシ系樹脂からなる導電性接着剤であることを特徴とする半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the adhesive is a conductive adhesive made of an Ag / epoxy resin. 4.
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